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31#include <linux/clk.h>
32#include <linux/clk-provider.h>
33#include <linux/debugfs.h>
34#include <linux/device.h>
35#include <linux/err.h>
36#include <linux/i2c.h>
37#include <linux/io.h>
38#include <linux/kernel.h>
39#include <linux/module.h>
40#include <linux/of.h>
41#include <linux/pinctrl/consumer.h>
42#include <linux/pm_opp.h>
43#include <linux/pm_runtime.h>
44#include <linux/regmap.h>
45#include <linux/regulator/consumer.h>
46#include <linux/reset.h>
47#include <linux/seq_file.h>
48
49#include "clk-dfll.h"
50#include "cvb.h"
51
52
53
54
55
56
57#define DFLL_CTRL 0x00
58#define DFLL_CTRL_MODE_MASK 0x03
59
60
61#define DFLL_CONFIG 0x04
62#define DFLL_CONFIG_DIV_MASK 0xff
63#define DFLL_CONFIG_DIV_PRESCALE 32
64
65
66#define DFLL_PARAMS 0x08
67#define DFLL_PARAMS_CG_SCALE (0x1 << 24)
68#define DFLL_PARAMS_FORCE_MODE_SHIFT 22
69#define DFLL_PARAMS_FORCE_MODE_MASK (0x3 << DFLL_PARAMS_FORCE_MODE_SHIFT)
70#define DFLL_PARAMS_CF_PARAM_SHIFT 16
71#define DFLL_PARAMS_CF_PARAM_MASK (0x3f << DFLL_PARAMS_CF_PARAM_SHIFT)
72#define DFLL_PARAMS_CI_PARAM_SHIFT 8
73#define DFLL_PARAMS_CI_PARAM_MASK (0x7 << DFLL_PARAMS_CI_PARAM_SHIFT)
74#define DFLL_PARAMS_CG_PARAM_SHIFT 0
75#define DFLL_PARAMS_CG_PARAM_MASK (0xff << DFLL_PARAMS_CG_PARAM_SHIFT)
76
77
78#define DFLL_TUNE0 0x0c
79
80
81#define DFLL_TUNE1 0x10
82
83
84#define DFLL_FREQ_REQ 0x14
85#define DFLL_FREQ_REQ_FORCE_ENABLE (0x1 << 28)
86#define DFLL_FREQ_REQ_FORCE_SHIFT 16
87#define DFLL_FREQ_REQ_FORCE_MASK (0xfff << DFLL_FREQ_REQ_FORCE_SHIFT)
88#define FORCE_MAX 2047
89#define FORCE_MIN -2048
90#define DFLL_FREQ_REQ_SCALE_SHIFT 8
91#define DFLL_FREQ_REQ_SCALE_MASK (0xff << DFLL_FREQ_REQ_SCALE_SHIFT)
92#define DFLL_FREQ_REQ_SCALE_MAX 256
93#define DFLL_FREQ_REQ_FREQ_VALID (0x1 << 7)
94#define DFLL_FREQ_REQ_MULT_SHIFT 0
95#define DFLL_FREQ_REG_MULT_MASK (0x7f << DFLL_FREQ_REQ_MULT_SHIFT)
96#define FREQ_MAX 127
97
98
99#define DFLL_DROOP_CTRL 0x1c
100
101
102
103#define DFLL_OUTPUT_CFG 0x20
104#define DFLL_OUTPUT_CFG_I2C_ENABLE (0x1 << 30)
105#define OUT_MASK 0x3f
106#define DFLL_OUTPUT_CFG_SAFE_SHIFT 24
107#define DFLL_OUTPUT_CFG_SAFE_MASK \
108 (OUT_MASK << DFLL_OUTPUT_CFG_SAFE_SHIFT)
109#define DFLL_OUTPUT_CFG_MAX_SHIFT 16
110#define DFLL_OUTPUT_CFG_MAX_MASK \
111 (OUT_MASK << DFLL_OUTPUT_CFG_MAX_SHIFT)
112#define DFLL_OUTPUT_CFG_MIN_SHIFT 8
113#define DFLL_OUTPUT_CFG_MIN_MASK \
114 (OUT_MASK << DFLL_OUTPUT_CFG_MIN_SHIFT)
115#define DFLL_OUTPUT_CFG_PWM_DELTA (0x1 << 7)
116#define DFLL_OUTPUT_CFG_PWM_ENABLE (0x1 << 6)
117#define DFLL_OUTPUT_CFG_PWM_DIV_SHIFT 0
118#define DFLL_OUTPUT_CFG_PWM_DIV_MASK \
119 (OUT_MASK << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)
120
121
122#define DFLL_OUTPUT_FORCE 0x24
123#define DFLL_OUTPUT_FORCE_ENABLE (0x1 << 6)
124#define DFLL_OUTPUT_FORCE_VALUE_SHIFT 0
125#define DFLL_OUTPUT_FORCE_VALUE_MASK \
126 (OUT_MASK << DFLL_OUTPUT_FORCE_VALUE_SHIFT)
127
128
129#define DFLL_MONITOR_CTRL 0x28
130#define DFLL_MONITOR_CTRL_FREQ 6
131
132
133#define DFLL_MONITOR_DATA 0x2c
134#define DFLL_MONITOR_DATA_NEW_MASK (0x1 << 16)
135#define DFLL_MONITOR_DATA_VAL_SHIFT 0
136#define DFLL_MONITOR_DATA_VAL_MASK (0xFFFF << DFLL_MONITOR_DATA_VAL_SHIFT)
137
138
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140
141
142
143#define DFLL_I2C_CFG 0x40
144#define DFLL_I2C_CFG_ARB_ENABLE (0x1 << 20)
145#define DFLL_I2C_CFG_HS_CODE_SHIFT 16
146#define DFLL_I2C_CFG_HS_CODE_MASK (0x7 << DFLL_I2C_CFG_HS_CODE_SHIFT)
147#define DFLL_I2C_CFG_PACKET_ENABLE (0x1 << 15)
148#define DFLL_I2C_CFG_SIZE_SHIFT 12
149#define DFLL_I2C_CFG_SIZE_MASK (0x7 << DFLL_I2C_CFG_SIZE_SHIFT)
150#define DFLL_I2C_CFG_SLAVE_ADDR_10 (0x1 << 10)
151#define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT 1
152#define DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT 0
153
154
155#define DFLL_I2C_VDD_REG_ADDR 0x44
156
157
158#define DFLL_I2C_STS 0x48
159#define DFLL_I2C_STS_I2C_LAST_SHIFT 1
160#define DFLL_I2C_STS_I2C_REQ_PENDING 0x1
161
162
163#define DFLL_INTR_STS 0x5c
164
165
166#define DFLL_INTR_EN 0x60
167#define DFLL_INTR_MIN_MASK 0x1
168#define DFLL_INTR_MAX_MASK 0x2
169
170
171
172
173
174
175#define DFLL_I2C_CLK_DIVISOR 0x6c
176#define DFLL_I2C_CLK_DIVISOR_MASK 0xffff
177#define DFLL_I2C_CLK_DIVISOR_FS_SHIFT 16
178#define DFLL_I2C_CLK_DIVISOR_HS_SHIFT 0
179#define DFLL_I2C_CLK_DIVISOR_PREDIV 8
180#define DFLL_I2C_CLK_DIVISOR_HSMODE_PREDIV 12
181
182
183
184
185
186
187#define MAX_DFLL_VOLTAGES 33
188
189
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192
193
194#define REF_CLK_CYC_PER_DVCO_SAMPLE 4
195
196
197
198
199
200#define REF_CLOCK_RATE 51000000UL
201
202#define DVCO_RATE_TO_MULT(rate, ref_rate) ((rate) / ((ref_rate) / 2))
203#define MULT_TO_DVCO_RATE(mult, ref_rate) ((mult) * ((ref_rate) / 2))
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215
216enum dfll_ctrl_mode {
217 DFLL_UNINITIALIZED = 0,
218 DFLL_DISABLED = 1,
219 DFLL_OPEN_LOOP = 2,
220 DFLL_CLOSED_LOOP = 3,
221};
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232
233enum dfll_tune_range {
234 DFLL_TUNE_UNINITIALIZED = 0,
235 DFLL_TUNE_LOW = 1,
236};
237
238
239enum tegra_dfll_pmu_if {
240 TEGRA_DFLL_PMU_I2C = 0,
241 TEGRA_DFLL_PMU_PWM = 1,
242};
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251
252struct dfll_rate_req {
253 unsigned long rate;
254 unsigned long dvco_target_rate;
255 int lut_index;
256 u8 mult_bits;
257 u8 scale_bits;
258};
259
260struct tegra_dfll {
261 struct device *dev;
262 struct tegra_dfll_soc_data *soc;
263
264 void __iomem *base;
265 void __iomem *i2c_base;
266 void __iomem *i2c_controller_base;
267 void __iomem *lut_base;
268
269 struct regulator *vdd_reg;
270 struct clk *soc_clk;
271 struct clk *ref_clk;
272 struct clk *i2c_clk;
273 struct clk *dfll_clk;
274 struct reset_control *dvco_rst;
275 unsigned long ref_rate;
276 unsigned long i2c_clk_rate;
277 unsigned long dvco_rate_min;
278
279 enum dfll_ctrl_mode mode;
280 enum dfll_tune_range tune_range;
281 struct dentry *debugfs_dir;
282 struct clk_hw dfll_clk_hw;
283 const char *output_clock_name;
284 struct dfll_rate_req last_req;
285 unsigned long last_unrounded_rate;
286
287
288 u32 droop_ctrl;
289 u32 sample_rate;
290 u32 force_mode;
291 u32 cf;
292 u32 ci;
293 u32 cg;
294 bool cg_scale;
295
296
297 u32 i2c_fs_rate;
298 u32 i2c_reg;
299 u32 i2c_slave_addr;
300
301
302 unsigned lut[MAX_DFLL_VOLTAGES];
303 unsigned long lut_uv[MAX_DFLL_VOLTAGES];
304 int lut_size;
305 u8 lut_bottom, lut_min, lut_max, lut_safe;
306
307
308 enum tegra_dfll_pmu_if pmu_if;
309 unsigned long pwm_rate;
310 struct pinctrl *pwm_pin;
311 struct pinctrl_state *pwm_enable_state;
312 struct pinctrl_state *pwm_disable_state;
313 u32 reg_init_uV;
314};
315
316#define clk_hw_to_dfll(_hw) container_of(_hw, struct tegra_dfll, dfll_clk_hw)
317
318
319static const char * const mode_name[] = {
320 [DFLL_UNINITIALIZED] = "uninitialized",
321 [DFLL_DISABLED] = "disabled",
322 [DFLL_OPEN_LOOP] = "open_loop",
323 [DFLL_CLOSED_LOOP] = "closed_loop",
324};
325
326
327
328
329
330static inline u32 dfll_readl(struct tegra_dfll *td, u32 offs)
331{
332 return __raw_readl(td->base + offs);
333}
334
335static inline void dfll_writel(struct tegra_dfll *td, u32 val, u32 offs)
336{
337 WARN_ON(offs >= DFLL_I2C_CFG);
338 __raw_writel(val, td->base + offs);
339}
340
341static inline void dfll_wmb(struct tegra_dfll *td)
342{
343 dfll_readl(td, DFLL_CTRL);
344}
345
346
347
348static inline u32 dfll_i2c_readl(struct tegra_dfll *td, u32 offs)
349{
350 return __raw_readl(td->i2c_base + offs);
351}
352
353static inline void dfll_i2c_writel(struct tegra_dfll *td, u32 val, u32 offs)
354{
355 __raw_writel(val, td->i2c_base + offs);
356}
357
358static inline void dfll_i2c_wmb(struct tegra_dfll *td)
359{
360 dfll_i2c_readl(td, DFLL_I2C_CFG);
361}
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369
370static bool dfll_is_running(struct tegra_dfll *td)
371{
372 return td->mode >= DFLL_OPEN_LOOP;
373}
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388int tegra_dfll_runtime_resume(struct device *dev)
389{
390 struct tegra_dfll *td = dev_get_drvdata(dev);
391 int ret;
392
393 ret = clk_enable(td->ref_clk);
394 if (ret) {
395 dev_err(dev, "could not enable ref clock: %d\n", ret);
396 return ret;
397 }
398
399 ret = clk_enable(td->soc_clk);
400 if (ret) {
401 dev_err(dev, "could not enable register clock: %d\n", ret);
402 clk_disable(td->ref_clk);
403 return ret;
404 }
405
406 ret = clk_enable(td->i2c_clk);
407 if (ret) {
408 dev_err(dev, "could not enable i2c clock: %d\n", ret);
409 clk_disable(td->soc_clk);
410 clk_disable(td->ref_clk);
411 return ret;
412 }
413
414 return 0;
415}
416EXPORT_SYMBOL(tegra_dfll_runtime_resume);
417
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423
424
425int tegra_dfll_runtime_suspend(struct device *dev)
426{
427 struct tegra_dfll *td = dev_get_drvdata(dev);
428
429 clk_disable(td->ref_clk);
430 clk_disable(td->soc_clk);
431 clk_disable(td->i2c_clk);
432
433 return 0;
434}
435EXPORT_SYMBOL(tegra_dfll_runtime_suspend);
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448
449static void dfll_tune_low(struct tegra_dfll *td)
450{
451 td->tune_range = DFLL_TUNE_LOW;
452
453 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune0_low, DFLL_TUNE0);
454 dfll_writel(td, td->soc->cvb->cpu_dfll_data.tune1, DFLL_TUNE1);
455 dfll_wmb(td);
456
457 if (td->soc->set_clock_trimmers_low)
458 td->soc->set_clock_trimmers_low();
459}
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472
473static unsigned long dfll_scale_dvco_rate(int scale_bits,
474 unsigned long dvco_rate)
475{
476 return (u64)dvco_rate * (scale_bits + 1) / DFLL_FREQ_REQ_SCALE_MAX;
477}
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491static void dfll_set_mode(struct tegra_dfll *td,
492 enum dfll_ctrl_mode mode)
493{
494 td->mode = mode;
495 dfll_writel(td, mode - 1, DFLL_CTRL);
496 dfll_wmb(td);
497}
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502
503static unsigned long get_dvco_rate_below(struct tegra_dfll *td, u8 out_min)
504{
505 struct dev_pm_opp *opp;
506 unsigned long rate, prev_rate;
507 unsigned long uv, min_uv;
508
509 min_uv = td->lut_uv[out_min];
510 for (rate = 0, prev_rate = 0; ; rate++) {
511 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
512 if (IS_ERR(opp))
513 break;
514
515 uv = dev_pm_opp_get_voltage(opp);
516 dev_pm_opp_put(opp);
517
518 if (uv && uv > min_uv)
519 return prev_rate;
520
521 prev_rate = rate;
522 }
523
524 return prev_rate;
525}
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539static int dfll_i2c_set_output_enabled(struct tegra_dfll *td, bool enable)
540{
541 u32 val;
542
543 val = dfll_i2c_readl(td, DFLL_OUTPUT_CFG);
544
545 if (enable)
546 val |= DFLL_OUTPUT_CFG_I2C_ENABLE;
547 else
548 val &= ~DFLL_OUTPUT_CFG_I2C_ENABLE;
549
550 dfll_i2c_writel(td, val, DFLL_OUTPUT_CFG);
551 dfll_i2c_wmb(td);
552
553 return 0;
554}
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569
570static int dfll_pwm_set_output_enabled(struct tegra_dfll *td, bool enable)
571{
572 int ret;
573 u32 val, div;
574
575 if (enable) {
576 ret = pinctrl_select_state(td->pwm_pin, td->pwm_enable_state);
577 if (ret < 0) {
578 dev_err(td->dev, "setting enable state failed\n");
579 return -EINVAL;
580 }
581 val = dfll_readl(td, DFLL_OUTPUT_CFG);
582 val &= ~DFLL_OUTPUT_CFG_PWM_DIV_MASK;
583 div = DIV_ROUND_UP(td->ref_rate, td->pwm_rate);
584 val |= (div << DFLL_OUTPUT_CFG_PWM_DIV_SHIFT)
585 & DFLL_OUTPUT_CFG_PWM_DIV_MASK;
586 dfll_writel(td, val, DFLL_OUTPUT_CFG);
587 dfll_wmb(td);
588
589 val |= DFLL_OUTPUT_CFG_PWM_ENABLE;
590 dfll_writel(td, val, DFLL_OUTPUT_CFG);
591 dfll_wmb(td);
592 } else {
593 ret = pinctrl_select_state(td->pwm_pin, td->pwm_disable_state);
594 if (ret < 0)
595 dev_warn(td->dev, "setting disable state failed\n");
596
597 val = dfll_readl(td, DFLL_OUTPUT_CFG);
598 val &= ~DFLL_OUTPUT_CFG_PWM_ENABLE;
599 dfll_writel(td, val, DFLL_OUTPUT_CFG);
600 dfll_wmb(td);
601 }
602
603 return 0;
604}
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613
614static u32 dfll_set_force_output_value(struct tegra_dfll *td, u8 out_val)
615{
616 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
617
618 val = (val & DFLL_OUTPUT_FORCE_ENABLE) | (out_val & OUT_MASK);
619 dfll_writel(td, val, DFLL_OUTPUT_FORCE);
620 dfll_wmb(td);
621
622 return dfll_readl(td, DFLL_OUTPUT_FORCE);
623}
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631
632static void dfll_set_force_output_enabled(struct tegra_dfll *td, bool enable)
633{
634 u32 val = dfll_readl(td, DFLL_OUTPUT_FORCE);
635
636 if (enable)
637 val |= DFLL_OUTPUT_FORCE_ENABLE;
638 else
639 val &= ~DFLL_OUTPUT_FORCE_ENABLE;
640
641 dfll_writel(td, val, DFLL_OUTPUT_FORCE);
642 dfll_wmb(td);
643}
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651
652static int dfll_force_output(struct tegra_dfll *td, unsigned int out_sel)
653{
654 u32 val;
655
656 if (out_sel > OUT_MASK)
657 return -EINVAL;
658
659 val = dfll_set_force_output_value(td, out_sel);
660 if ((td->mode < DFLL_CLOSED_LOOP) &&
661 !(val & DFLL_OUTPUT_FORCE_ENABLE)) {
662 dfll_set_force_output_enabled(td, true);
663 }
664
665 return 0;
666}
667
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673
674
675static void dfll_load_i2c_lut(struct tegra_dfll *td)
676{
677 int i, lut_index;
678 u32 val;
679
680 for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
681 if (i < td->lut_min)
682 lut_index = td->lut_min;
683 else if (i > td->lut_max)
684 lut_index = td->lut_max;
685 else
686 lut_index = i;
687
688 val = regulator_list_hardware_vsel(td->vdd_reg,
689 td->lut[lut_index]);
690 __raw_writel(val, td->lut_base + i * 4);
691 }
692
693 dfll_i2c_wmb(td);
694}
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705
706static void dfll_init_i2c_if(struct tegra_dfll *td)
707{
708 u32 val;
709
710 if (td->i2c_slave_addr > 0x7f) {
711 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_10BIT;
712 val |= DFLL_I2C_CFG_SLAVE_ADDR_10;
713 } else {
714 val = td->i2c_slave_addr << DFLL_I2C_CFG_SLAVE_ADDR_SHIFT_7BIT;
715 }
716 val |= DFLL_I2C_CFG_SIZE_MASK;
717 val |= DFLL_I2C_CFG_ARB_ENABLE;
718 dfll_i2c_writel(td, val, DFLL_I2C_CFG);
719
720 dfll_i2c_writel(td, td->i2c_reg, DFLL_I2C_VDD_REG_ADDR);
721
722 val = DIV_ROUND_UP(td->i2c_clk_rate, td->i2c_fs_rate * 8);
723 BUG_ON(!val || (val > DFLL_I2C_CLK_DIVISOR_MASK));
724 val = (val - 1) << DFLL_I2C_CLK_DIVISOR_FS_SHIFT;
725
726
727 val |= 1 << DFLL_I2C_CLK_DIVISOR_HS_SHIFT;
728 __raw_writel(val, td->i2c_controller_base + DFLL_I2C_CLK_DIVISOR);
729 dfll_i2c_wmb(td);
730}
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738
739
740static void dfll_init_out_if(struct tegra_dfll *td)
741{
742 u32 val;
743
744 td->lut_min = td->lut_bottom;
745 td->lut_max = td->lut_size - 1;
746 td->lut_safe = td->lut_min + (td->lut_min < td->lut_max ? 1 : 0);
747
748
749 dfll_writel(td, 0, DFLL_OUTPUT_CFG);
750 dfll_wmb(td);
751
752 val = (td->lut_safe << DFLL_OUTPUT_CFG_SAFE_SHIFT) |
753 (td->lut_max << DFLL_OUTPUT_CFG_MAX_SHIFT) |
754 (td->lut_min << DFLL_OUTPUT_CFG_MIN_SHIFT);
755 dfll_writel(td, val, DFLL_OUTPUT_CFG);
756 dfll_wmb(td);
757
758 dfll_writel(td, 0, DFLL_OUTPUT_FORCE);
759 dfll_i2c_writel(td, 0, DFLL_INTR_EN);
760 dfll_i2c_writel(td, DFLL_INTR_MAX_MASK | DFLL_INTR_MIN_MASK,
761 DFLL_INTR_STS);
762
763 if (td->pmu_if == TEGRA_DFLL_PMU_PWM) {
764 u32 vinit = td->reg_init_uV;
765 int vstep = td->soc->alignment.step_uv;
766 unsigned long vmin = td->lut_uv[0];
767
768
769 if ((vinit >= vmin) && vstep) {
770 unsigned int vsel;
771
772 vsel = DIV_ROUND_UP((vinit - vmin), vstep);
773 dfll_force_output(td, vsel);
774 }
775 } else {
776 dfll_load_i2c_lut(td);
777 dfll_init_i2c_if(td);
778 }
779}
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794
795static int find_lut_index_for_rate(struct tegra_dfll *td, unsigned long rate)
796{
797 struct dev_pm_opp *opp;
798 int i, align_step;
799
800 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
801 if (IS_ERR(opp))
802 return PTR_ERR(opp);
803
804 align_step = dev_pm_opp_get_voltage(opp) / td->soc->alignment.step_uv;
805 dev_pm_opp_put(opp);
806
807 for (i = td->lut_bottom; i < td->lut_size; i++) {
808 if ((td->lut_uv[i] / td->soc->alignment.step_uv) >= align_step)
809 return i;
810 }
811
812 return -ENOENT;
813}
814
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824
825
826static int dfll_calculate_rate_request(struct tegra_dfll *td,
827 struct dfll_rate_req *req,
828 unsigned long rate)
829{
830 u32 val;
831
832
833
834
835
836
837
838 req->scale_bits = DFLL_FREQ_REQ_SCALE_MAX - 1;
839 if (rate < td->dvco_rate_min) {
840 int scale;
841
842 scale = DIV_ROUND_CLOSEST(rate / 1000 * DFLL_FREQ_REQ_SCALE_MAX,
843 td->dvco_rate_min / 1000);
844 if (!scale) {
845 dev_err(td->dev, "%s: Rate %lu is too low\n",
846 __func__, rate);
847 return -EINVAL;
848 }
849 req->scale_bits = scale - 1;
850 rate = td->dvco_rate_min;
851 }
852
853
854 val = DVCO_RATE_TO_MULT(rate, td->ref_rate);
855 if (val > FREQ_MAX) {
856 dev_err(td->dev, "%s: Rate %lu is above dfll range\n",
857 __func__, rate);
858 return -EINVAL;
859 }
860 req->mult_bits = val;
861 req->dvco_target_rate = MULT_TO_DVCO_RATE(req->mult_bits, td->ref_rate);
862 req->rate = dfll_scale_dvco_rate(req->scale_bits,
863 req->dvco_target_rate);
864 req->lut_index = find_lut_index_for_rate(td, req->dvco_target_rate);
865 if (req->lut_index < 0)
866 return req->lut_index;
867
868 return 0;
869}
870
871
872
873
874
875
876
877
878
879static void dfll_set_frequency_request(struct tegra_dfll *td,
880 struct dfll_rate_req *req)
881{
882 u32 val = 0;
883 int force_val;
884 int coef = 128; ;
885
886 force_val = (req->lut_index - td->lut_safe) * coef / td->cg;
887 force_val = clamp(force_val, FORCE_MIN, FORCE_MAX);
888
889 val |= req->mult_bits << DFLL_FREQ_REQ_MULT_SHIFT;
890 val |= req->scale_bits << DFLL_FREQ_REQ_SCALE_SHIFT;
891 val |= ((u32)force_val << DFLL_FREQ_REQ_FORCE_SHIFT) &
892 DFLL_FREQ_REQ_FORCE_MASK;
893 val |= DFLL_FREQ_REQ_FREQ_VALID | DFLL_FREQ_REQ_FORCE_ENABLE;
894
895 dfll_writel(td, val, DFLL_FREQ_REQ);
896 dfll_wmb(td);
897}
898
899
900
901
902
903
904
905
906
907
908
909
910
911static int dfll_request_rate(struct tegra_dfll *td, unsigned long rate)
912{
913 int ret;
914 struct dfll_rate_req req;
915
916 if (td->mode == DFLL_UNINITIALIZED) {
917 dev_err(td->dev, "%s: Cannot set DFLL rate in %s mode\n",
918 __func__, mode_name[td->mode]);
919 return -EPERM;
920 }
921
922 ret = dfll_calculate_rate_request(td, &req, rate);
923 if (ret)
924 return ret;
925
926 td->last_unrounded_rate = rate;
927 td->last_req = req;
928
929 if (td->mode == DFLL_CLOSED_LOOP)
930 dfll_set_frequency_request(td, &td->last_req);
931
932 return 0;
933}
934
935
936
937
938
939
940
941
942
943
944
945
946static int dfll_disable(struct tegra_dfll *td)
947{
948 if (td->mode != DFLL_OPEN_LOOP) {
949 dev_err(td->dev, "cannot disable DFLL in %s mode\n",
950 mode_name[td->mode]);
951 return -EINVAL;
952 }
953
954 dfll_set_mode(td, DFLL_DISABLED);
955 pm_runtime_put_sync(td->dev);
956
957 return 0;
958}
959
960
961
962
963
964
965
966
967static int dfll_enable(struct tegra_dfll *td)
968{
969 if (td->mode != DFLL_DISABLED) {
970 dev_err(td->dev, "cannot enable DFLL in %s mode\n",
971 mode_name[td->mode]);
972 return -EPERM;
973 }
974
975 pm_runtime_get_sync(td->dev);
976 dfll_set_mode(td, DFLL_OPEN_LOOP);
977
978 return 0;
979}
980
981
982
983
984
985
986
987
988
989
990
991
992static void dfll_set_open_loop_config(struct tegra_dfll *td)
993{
994 u32 val;
995
996
997 if (td->tune_range != DFLL_TUNE_LOW)
998 dfll_tune_low(td);
999
1000 val = dfll_readl(td, DFLL_FREQ_REQ);
1001 val |= DFLL_FREQ_REQ_SCALE_MASK;
1002 val &= ~DFLL_FREQ_REQ_FORCE_ENABLE;
1003 dfll_writel(td, val, DFLL_FREQ_REQ);
1004 dfll_wmb(td);
1005}
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015static int dfll_lock(struct tegra_dfll *td)
1016{
1017 struct dfll_rate_req *req = &td->last_req;
1018
1019 switch (td->mode) {
1020 case DFLL_CLOSED_LOOP:
1021 return 0;
1022
1023 case DFLL_OPEN_LOOP:
1024 if (req->rate == 0) {
1025 dev_err(td->dev, "%s: Cannot lock DFLL at rate 0\n",
1026 __func__);
1027 return -EINVAL;
1028 }
1029
1030 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1031 dfll_pwm_set_output_enabled(td, true);
1032 else
1033 dfll_i2c_set_output_enabled(td, true);
1034
1035 dfll_set_mode(td, DFLL_CLOSED_LOOP);
1036 dfll_set_frequency_request(td, req);
1037 dfll_set_force_output_enabled(td, false);
1038 return 0;
1039
1040 default:
1041 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
1042 dev_err(td->dev, "%s: Cannot lock DFLL in %s mode\n",
1043 __func__, mode_name[td->mode]);
1044 return -EPERM;
1045 }
1046}
1047
1048
1049
1050
1051
1052
1053
1054
1055static int dfll_unlock(struct tegra_dfll *td)
1056{
1057 switch (td->mode) {
1058 case DFLL_CLOSED_LOOP:
1059 dfll_set_open_loop_config(td);
1060 dfll_set_mode(td, DFLL_OPEN_LOOP);
1061 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1062 dfll_pwm_set_output_enabled(td, false);
1063 else
1064 dfll_i2c_set_output_enabled(td, false);
1065 return 0;
1066
1067 case DFLL_OPEN_LOOP:
1068 return 0;
1069
1070 default:
1071 BUG_ON(td->mode > DFLL_CLOSED_LOOP);
1072 dev_err(td->dev, "%s: Cannot unlock DFLL in %s mode\n",
1073 __func__, mode_name[td->mode]);
1074 return -EPERM;
1075 }
1076}
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087static int dfll_clk_is_enabled(struct clk_hw *hw)
1088{
1089 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1090
1091 return dfll_is_running(td);
1092}
1093
1094static int dfll_clk_enable(struct clk_hw *hw)
1095{
1096 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1097 int ret;
1098
1099 ret = dfll_enable(td);
1100 if (ret)
1101 return ret;
1102
1103 ret = dfll_lock(td);
1104 if (ret)
1105 dfll_disable(td);
1106
1107 return ret;
1108}
1109
1110static void dfll_clk_disable(struct clk_hw *hw)
1111{
1112 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1113 int ret;
1114
1115 ret = dfll_unlock(td);
1116 if (!ret)
1117 dfll_disable(td);
1118}
1119
1120static unsigned long dfll_clk_recalc_rate(struct clk_hw *hw,
1121 unsigned long parent_rate)
1122{
1123 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1124
1125 return td->last_unrounded_rate;
1126}
1127
1128
1129static int dfll_clk_determine_rate(struct clk_hw *hw,
1130 struct clk_rate_request *clk_req)
1131{
1132 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1133 struct dfll_rate_req req;
1134 int ret;
1135
1136 ret = dfll_calculate_rate_request(td, &req, clk_req->rate);
1137 if (ret)
1138 return ret;
1139
1140
1141
1142
1143
1144
1145
1146 return 0;
1147}
1148
1149static int dfll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
1150 unsigned long parent_rate)
1151{
1152 struct tegra_dfll *td = clk_hw_to_dfll(hw);
1153
1154 return dfll_request_rate(td, rate);
1155}
1156
1157static const struct clk_ops dfll_clk_ops = {
1158 .is_enabled = dfll_clk_is_enabled,
1159 .enable = dfll_clk_enable,
1160 .disable = dfll_clk_disable,
1161 .recalc_rate = dfll_clk_recalc_rate,
1162 .determine_rate = dfll_clk_determine_rate,
1163 .set_rate = dfll_clk_set_rate,
1164};
1165
1166static struct clk_init_data dfll_clk_init_data = {
1167 .ops = &dfll_clk_ops,
1168 .num_parents = 0,
1169};
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179static int dfll_register_clk(struct tegra_dfll *td)
1180{
1181 int ret;
1182
1183 dfll_clk_init_data.name = td->output_clock_name;
1184 td->dfll_clk_hw.init = &dfll_clk_init_data;
1185
1186 td->dfll_clk = clk_register(td->dev, &td->dfll_clk_hw);
1187 if (IS_ERR(td->dfll_clk)) {
1188 dev_err(td->dev, "DFLL clock registration error\n");
1189 return -EINVAL;
1190 }
1191
1192 ret = of_clk_add_provider(td->dev->of_node, of_clk_src_simple_get,
1193 td->dfll_clk);
1194 if (ret) {
1195 dev_err(td->dev, "of_clk_add_provider() failed\n");
1196
1197 clk_unregister(td->dfll_clk);
1198 return ret;
1199 }
1200
1201 return 0;
1202}
1203
1204
1205
1206
1207
1208
1209
1210
1211static void dfll_unregister_clk(struct tegra_dfll *td)
1212{
1213 of_clk_del_provider(td->dev->of_node);
1214 clk_unregister(td->dfll_clk);
1215 td->dfll_clk = NULL;
1216}
1217
1218
1219
1220
1221
1222#ifdef CONFIG_DEBUG_FS
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235static u64 dfll_calc_monitored_rate(u32 monitor_data,
1236 unsigned long ref_rate)
1237{
1238 return monitor_data * (ref_rate / REF_CLK_CYC_PER_DVCO_SAMPLE);
1239}
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254static u64 dfll_read_monitor_rate(struct tegra_dfll *td)
1255{
1256 u32 v, s;
1257 u64 pre_scaler_rate, post_scaler_rate;
1258
1259 if (!dfll_is_running(td))
1260 return 0;
1261
1262 v = dfll_readl(td, DFLL_MONITOR_DATA);
1263 v = (v & DFLL_MONITOR_DATA_VAL_MASK) >> DFLL_MONITOR_DATA_VAL_SHIFT;
1264 pre_scaler_rate = dfll_calc_monitored_rate(v, td->ref_rate);
1265
1266 s = dfll_readl(td, DFLL_FREQ_REQ);
1267 s = (s & DFLL_FREQ_REQ_SCALE_MASK) >> DFLL_FREQ_REQ_SCALE_SHIFT;
1268 post_scaler_rate = dfll_scale_dvco_rate(s, pre_scaler_rate);
1269
1270 return post_scaler_rate;
1271}
1272
1273static int attr_enable_get(void *data, u64 *val)
1274{
1275 struct tegra_dfll *td = data;
1276
1277 *val = dfll_is_running(td);
1278
1279 return 0;
1280}
1281static int attr_enable_set(void *data, u64 val)
1282{
1283 struct tegra_dfll *td = data;
1284
1285 return val ? dfll_enable(td) : dfll_disable(td);
1286}
1287DEFINE_DEBUGFS_ATTRIBUTE(enable_fops, attr_enable_get, attr_enable_set,
1288 "%llu\n");
1289
1290static int attr_lock_get(void *data, u64 *val)
1291{
1292 struct tegra_dfll *td = data;
1293
1294 *val = (td->mode == DFLL_CLOSED_LOOP);
1295
1296 return 0;
1297}
1298static int attr_lock_set(void *data, u64 val)
1299{
1300 struct tegra_dfll *td = data;
1301
1302 return val ? dfll_lock(td) : dfll_unlock(td);
1303}
1304DEFINE_DEBUGFS_ATTRIBUTE(lock_fops, attr_lock_get, attr_lock_set, "%llu\n");
1305
1306static int attr_rate_get(void *data, u64 *val)
1307{
1308 struct tegra_dfll *td = data;
1309
1310 *val = dfll_read_monitor_rate(td);
1311
1312 return 0;
1313}
1314
1315static int attr_rate_set(void *data, u64 val)
1316{
1317 struct tegra_dfll *td = data;
1318
1319 return dfll_request_rate(td, val);
1320}
1321DEFINE_DEBUGFS_ATTRIBUTE(rate_fops, attr_rate_get, attr_rate_set, "%llu\n");
1322
1323static int attr_registers_show(struct seq_file *s, void *data)
1324{
1325 u32 val, offs;
1326 struct tegra_dfll *td = s->private;
1327
1328 seq_puts(s, "CONTROL REGISTERS:\n");
1329 for (offs = 0; offs <= DFLL_MONITOR_DATA; offs += 4) {
1330 if (offs == DFLL_OUTPUT_CFG)
1331 val = dfll_i2c_readl(td, offs);
1332 else
1333 val = dfll_readl(td, offs);
1334 seq_printf(s, "[0x%02x] = 0x%08x\n", offs, val);
1335 }
1336
1337 seq_puts(s, "\nI2C and INTR REGISTERS:\n");
1338 for (offs = DFLL_I2C_CFG; offs <= DFLL_I2C_STS; offs += 4)
1339 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1340 dfll_i2c_readl(td, offs));
1341 for (offs = DFLL_INTR_STS; offs <= DFLL_INTR_EN; offs += 4)
1342 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1343 dfll_i2c_readl(td, offs));
1344
1345 if (td->pmu_if == TEGRA_DFLL_PMU_I2C) {
1346 seq_puts(s, "\nINTEGRATED I2C CONTROLLER REGISTERS:\n");
1347 offs = DFLL_I2C_CLK_DIVISOR;
1348 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1349 __raw_readl(td->i2c_controller_base + offs));
1350
1351 seq_puts(s, "\nLUT:\n");
1352 for (offs = 0; offs < 4 * MAX_DFLL_VOLTAGES; offs += 4)
1353 seq_printf(s, "[0x%02x] = 0x%08x\n", offs,
1354 __raw_readl(td->lut_base + offs));
1355 }
1356
1357 return 0;
1358}
1359
1360DEFINE_SHOW_ATTRIBUTE(attr_registers);
1361
1362static void dfll_debug_init(struct tegra_dfll *td)
1363{
1364 struct dentry *root;
1365
1366 if (!td || (td->mode == DFLL_UNINITIALIZED))
1367 return;
1368
1369 root = debugfs_create_dir("tegra_dfll_fcpu", NULL);
1370 td->debugfs_dir = root;
1371
1372 debugfs_create_file_unsafe("enable", 0644, root, td,
1373 &enable_fops);
1374 debugfs_create_file_unsafe("lock", 0444, root, td, &lock_fops);
1375 debugfs_create_file_unsafe("rate", 0444, root, td, &rate_fops);
1376 debugfs_create_file("registers", 0444, root, td, &attr_registers_fops);
1377}
1378
1379#else
1380static inline void dfll_debug_init(struct tegra_dfll *td) { }
1381#endif
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395static void dfll_set_default_params(struct tegra_dfll *td)
1396{
1397 u32 val;
1398
1399 val = DIV_ROUND_UP(td->ref_rate, td->sample_rate * 32);
1400 BUG_ON(val > DFLL_CONFIG_DIV_MASK);
1401 dfll_writel(td, val, DFLL_CONFIG);
1402
1403 val = (td->force_mode << DFLL_PARAMS_FORCE_MODE_SHIFT) |
1404 (td->cf << DFLL_PARAMS_CF_PARAM_SHIFT) |
1405 (td->ci << DFLL_PARAMS_CI_PARAM_SHIFT) |
1406 (td->cg << DFLL_PARAMS_CG_PARAM_SHIFT) |
1407 (td->cg_scale ? DFLL_PARAMS_CG_SCALE : 0);
1408 dfll_writel(td, val, DFLL_PARAMS);
1409
1410 dfll_tune_low(td);
1411 dfll_writel(td, td->droop_ctrl, DFLL_DROOP_CTRL);
1412 dfll_writel(td, DFLL_MONITOR_CTRL_FREQ, DFLL_MONITOR_CTRL);
1413}
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423static int dfll_init_clks(struct tegra_dfll *td)
1424{
1425 td->ref_clk = devm_clk_get(td->dev, "ref");
1426 if (IS_ERR(td->ref_clk)) {
1427 dev_err(td->dev, "missing ref clock\n");
1428 return PTR_ERR(td->ref_clk);
1429 }
1430
1431 td->soc_clk = devm_clk_get(td->dev, "soc");
1432 if (IS_ERR(td->soc_clk)) {
1433 dev_err(td->dev, "missing soc clock\n");
1434 return PTR_ERR(td->soc_clk);
1435 }
1436
1437 td->i2c_clk = devm_clk_get(td->dev, "i2c");
1438 if (IS_ERR(td->i2c_clk)) {
1439 dev_err(td->dev, "missing i2c clock\n");
1440 return PTR_ERR(td->i2c_clk);
1441 }
1442 td->i2c_clk_rate = clk_get_rate(td->i2c_clk);
1443
1444 return 0;
1445}
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456static int dfll_init(struct tegra_dfll *td)
1457{
1458 int ret;
1459
1460 td->ref_rate = clk_get_rate(td->ref_clk);
1461 if (td->ref_rate != REF_CLOCK_RATE) {
1462 dev_err(td->dev, "unexpected ref clk rate %lu, expecting %lu",
1463 td->ref_rate, REF_CLOCK_RATE);
1464 return -EINVAL;
1465 }
1466
1467 reset_control_deassert(td->dvco_rst);
1468
1469 ret = clk_prepare(td->ref_clk);
1470 if (ret) {
1471 dev_err(td->dev, "failed to prepare ref_clk\n");
1472 return ret;
1473 }
1474
1475 ret = clk_prepare(td->soc_clk);
1476 if (ret) {
1477 dev_err(td->dev, "failed to prepare soc_clk\n");
1478 goto di_err1;
1479 }
1480
1481 ret = clk_prepare(td->i2c_clk);
1482 if (ret) {
1483 dev_err(td->dev, "failed to prepare i2c_clk\n");
1484 goto di_err2;
1485 }
1486
1487 td->last_unrounded_rate = 0;
1488
1489 pm_runtime_enable(td->dev);
1490 pm_runtime_get_sync(td->dev);
1491
1492 dfll_set_mode(td, DFLL_DISABLED);
1493 dfll_set_default_params(td);
1494
1495 if (td->soc->init_clock_trimmers)
1496 td->soc->init_clock_trimmers();
1497
1498 dfll_set_open_loop_config(td);
1499
1500 dfll_init_out_if(td);
1501
1502 pm_runtime_put_sync(td->dev);
1503
1504 return 0;
1505
1506di_err2:
1507 clk_unprepare(td->soc_clk);
1508di_err1:
1509 clk_unprepare(td->ref_clk);
1510
1511 reset_control_assert(td->dvco_rst);
1512
1513 return ret;
1514}
1515
1516
1517
1518
1519
1520
1521
1522
1523int tegra_dfll_suspend(struct device *dev)
1524{
1525 struct tegra_dfll *td = dev_get_drvdata(dev);
1526
1527 if (dfll_is_running(td)) {
1528 dev_err(td->dev, "DFLL still enabled while suspending\n");
1529 return -EBUSY;
1530 }
1531
1532 reset_control_assert(td->dvco_rst);
1533
1534 return 0;
1535}
1536EXPORT_SYMBOL(tegra_dfll_suspend);
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547int tegra_dfll_resume(struct device *dev)
1548{
1549 struct tegra_dfll *td = dev_get_drvdata(dev);
1550
1551 reset_control_deassert(td->dvco_rst);
1552
1553 pm_runtime_get_sync(td->dev);
1554
1555 dfll_set_mode(td, DFLL_DISABLED);
1556 dfll_set_default_params(td);
1557
1558 if (td->soc->init_clock_trimmers)
1559 td->soc->init_clock_trimmers();
1560
1561 dfll_set_open_loop_config(td);
1562
1563 dfll_init_out_if(td);
1564
1565 pm_runtime_put_sync(td->dev);
1566
1567 return 0;
1568}
1569EXPORT_SYMBOL(tegra_dfll_resume);
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579static int find_vdd_map_entry_exact(struct tegra_dfll *td, int uV)
1580{
1581 int i, n_voltages, reg_uV,reg_volt_id, align_step;
1582
1583 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
1584 return -EINVAL;
1585
1586 align_step = uV / td->soc->alignment.step_uv;
1587 n_voltages = regulator_count_voltages(td->vdd_reg);
1588 for (i = 0; i < n_voltages; i++) {
1589 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1590 if (reg_uV < 0)
1591 break;
1592
1593 reg_volt_id = reg_uV / td->soc->alignment.step_uv;
1594
1595 if (align_step == reg_volt_id)
1596 return i;
1597 }
1598
1599 dev_err(td->dev, "no voltage map entry for %d uV\n", uV);
1600 return -EINVAL;
1601}
1602
1603
1604
1605
1606
1607static int find_vdd_map_entry_min(struct tegra_dfll *td, int uV)
1608{
1609 int i, n_voltages, reg_uV, reg_volt_id, align_step;
1610
1611 if (WARN_ON(td->pmu_if == TEGRA_DFLL_PMU_PWM))
1612 return -EINVAL;
1613
1614 align_step = uV / td->soc->alignment.step_uv;
1615 n_voltages = regulator_count_voltages(td->vdd_reg);
1616 for (i = 0; i < n_voltages; i++) {
1617 reg_uV = regulator_list_voltage(td->vdd_reg, i);
1618 if (reg_uV < 0)
1619 break;
1620
1621 reg_volt_id = reg_uV / td->soc->alignment.step_uv;
1622
1623 if (align_step <= reg_volt_id)
1624 return i;
1625 }
1626
1627 dev_err(td->dev, "no voltage map entry rounding to %d uV\n", uV);
1628 return -EINVAL;
1629}
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640static int dfll_build_pwm_lut(struct tegra_dfll *td, unsigned long v_max)
1641{
1642 int i;
1643 unsigned long rate, reg_volt;
1644 u8 lut_bottom = MAX_DFLL_VOLTAGES;
1645 int v_min = td->soc->cvb->min_millivolts * 1000;
1646
1647 for (i = 0; i < MAX_DFLL_VOLTAGES; i++) {
1648 reg_volt = td->lut_uv[i];
1649
1650
1651 reg_volt = (reg_volt / 1000) * 1000;
1652 if (reg_volt > v_max)
1653 break;
1654
1655 td->lut[i] = i;
1656 if ((lut_bottom == MAX_DFLL_VOLTAGES) && (reg_volt >= v_min))
1657 lut_bottom = i;
1658 }
1659
1660
1661 td->lut_size = i;
1662 if ((lut_bottom == MAX_DFLL_VOLTAGES) ||
1663 (lut_bottom + 1 >= td->lut_size)) {
1664 dev_err(td->dev, "no voltage above DFLL minimum %d mV\n",
1665 td->soc->cvb->min_millivolts);
1666 return -EINVAL;
1667 }
1668 td->lut_bottom = lut_bottom;
1669
1670
1671 rate = get_dvco_rate_below(td, td->lut_bottom);
1672 if (!rate) {
1673 dev_err(td->dev, "no opp below DFLL minimum voltage %d mV\n",
1674 td->soc->cvb->min_millivolts);
1675 return -EINVAL;
1676 }
1677 td->dvco_rate_min = rate;
1678
1679 return 0;
1680}
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690
1691
1692
1693
1694
1695static int dfll_build_i2c_lut(struct tegra_dfll *td, unsigned long v_max)
1696{
1697 unsigned long rate, v, v_opp;
1698 int ret = -EINVAL;
1699 int j, selector, lut;
1700
1701 v = td->soc->cvb->min_millivolts * 1000;
1702 lut = find_vdd_map_entry_exact(td, v);
1703 if (lut < 0)
1704 goto out;
1705 td->lut[0] = lut;
1706 td->lut_bottom = 0;
1707
1708 for (j = 1, rate = 0; ; rate++) {
1709 struct dev_pm_opp *opp;
1710
1711 opp = dev_pm_opp_find_freq_ceil(td->soc->dev, &rate);
1712 if (IS_ERR(opp))
1713 break;
1714 v_opp = dev_pm_opp_get_voltage(opp);
1715
1716 if (v_opp <= td->soc->cvb->min_millivolts * 1000)
1717 td->dvco_rate_min = dev_pm_opp_get_freq(opp);
1718
1719 dev_pm_opp_put(opp);
1720
1721 for (;;) {
1722 v += max(1UL, (v_max - v) / (MAX_DFLL_VOLTAGES - j));
1723 if (v >= v_opp)
1724 break;
1725
1726 selector = find_vdd_map_entry_min(td, v);
1727 if (selector < 0)
1728 goto out;
1729 if (selector != td->lut[j - 1])
1730 td->lut[j++] = selector;
1731 }
1732
1733 v = (j == MAX_DFLL_VOLTAGES - 1) ? v_max : v_opp;
1734 selector = find_vdd_map_entry_exact(td, v);
1735 if (selector < 0)
1736 goto out;
1737 if (selector != td->lut[j - 1])
1738 td->lut[j++] = selector;
1739
1740 if (v >= v_max)
1741 break;
1742 }
1743 td->lut_size = j;
1744
1745 if (!td->dvco_rate_min)
1746 dev_err(td->dev, "no opp above DFLL minimum voltage %d mV\n",
1747 td->soc->cvb->min_millivolts);
1748 else {
1749 ret = 0;
1750 for (j = 0; j < td->lut_size; j++)
1751 td->lut_uv[j] =
1752 regulator_list_voltage(td->vdd_reg,
1753 td->lut[j]);
1754 }
1755
1756out:
1757 return ret;
1758}
1759
1760static int dfll_build_lut(struct tegra_dfll *td)
1761{
1762 unsigned long rate, v_max;
1763 struct dev_pm_opp *opp;
1764
1765 rate = ULONG_MAX;
1766 opp = dev_pm_opp_find_freq_floor(td->soc->dev, &rate);
1767 if (IS_ERR(opp)) {
1768 dev_err(td->dev, "couldn't get vmax opp, empty opp table?\n");
1769 return -EINVAL;
1770 }
1771 v_max = dev_pm_opp_get_voltage(opp);
1772 dev_pm_opp_put(opp);
1773
1774 if (td->pmu_if == TEGRA_DFLL_PMU_PWM)
1775 return dfll_build_pwm_lut(td, v_max);
1776 else
1777 return dfll_build_i2c_lut(td, v_max);
1778}
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790static bool read_dt_param(struct tegra_dfll *td, const char *param, u32 *dest)
1791{
1792 int err = of_property_read_u32(td->dev->of_node, param, dest);
1793
1794 if (err < 0) {
1795 dev_err(td->dev, "failed to read DT parameter %s: %d\n",
1796 param, err);
1797 return false;
1798 }
1799
1800 return true;
1801}
1802
1803
1804
1805
1806
1807
1808
1809
1810
1811static int dfll_fetch_i2c_params(struct tegra_dfll *td)
1812{
1813 struct regmap *regmap;
1814 struct device *i2c_dev;
1815 struct i2c_client *i2c_client;
1816 int vsel_reg, vsel_mask;
1817 int ret;
1818
1819 if (!read_dt_param(td, "nvidia,i2c-fs-rate", &td->i2c_fs_rate))
1820 return -EINVAL;
1821
1822 regmap = regulator_get_regmap(td->vdd_reg);
1823 i2c_dev = regmap_get_device(regmap);
1824 i2c_client = to_i2c_client(i2c_dev);
1825
1826 td->i2c_slave_addr = i2c_client->addr;
1827
1828 ret = regulator_get_hardware_vsel_register(td->vdd_reg,
1829 &vsel_reg,
1830 &vsel_mask);
1831 if (ret < 0) {
1832 dev_err(td->dev,
1833 "regulator unsuitable for DFLL I2C operation\n");
1834 return -EINVAL;
1835 }
1836 td->i2c_reg = vsel_reg;
1837
1838 return 0;
1839}
1840
1841static int dfll_fetch_pwm_params(struct tegra_dfll *td)
1842{
1843 int ret, i;
1844 u32 pwm_period;
1845
1846 if (!td->soc->alignment.step_uv || !td->soc->alignment.offset_uv) {
1847 dev_err(td->dev,
1848 "Missing step or alignment info for PWM regulator");
1849 return -EINVAL;
1850 }
1851 for (i = 0; i < MAX_DFLL_VOLTAGES; i++)
1852 td->lut_uv[i] = td->soc->alignment.offset_uv +
1853 i * td->soc->alignment.step_uv;
1854
1855 ret = read_dt_param(td, "nvidia,pwm-tristate-microvolts",
1856 &td->reg_init_uV);
1857 if (!ret) {
1858 dev_err(td->dev, "couldn't get initialized voltage\n");
1859 return -EINVAL;
1860 }
1861
1862 ret = read_dt_param(td, "nvidia,pwm-period-nanoseconds", &pwm_period);
1863 if (!ret) {
1864 dev_err(td->dev, "couldn't get PWM period\n");
1865 return -EINVAL;
1866 }
1867 td->pwm_rate = (NSEC_PER_SEC / pwm_period) * (MAX_DFLL_VOLTAGES - 1);
1868
1869 td->pwm_pin = devm_pinctrl_get(td->dev);
1870 if (IS_ERR(td->pwm_pin)) {
1871 dev_err(td->dev, "DT: missing pinctrl device\n");
1872 return PTR_ERR(td->pwm_pin);
1873 }
1874
1875 td->pwm_enable_state = pinctrl_lookup_state(td->pwm_pin,
1876 "dvfs_pwm_enable");
1877 if (IS_ERR(td->pwm_enable_state)) {
1878 dev_err(td->dev, "DT: missing pwm enabled state\n");
1879 return PTR_ERR(td->pwm_enable_state);
1880 }
1881
1882 td->pwm_disable_state = pinctrl_lookup_state(td->pwm_pin,
1883 "dvfs_pwm_disable");
1884 if (IS_ERR(td->pwm_disable_state)) {
1885 dev_err(td->dev, "DT: missing pwm disabled state\n");
1886 return PTR_ERR(td->pwm_disable_state);
1887 }
1888
1889 return 0;
1890}
1891
1892
1893
1894
1895
1896
1897
1898
1899static int dfll_fetch_common_params(struct tegra_dfll *td)
1900{
1901 bool ok = true;
1902
1903 ok &= read_dt_param(td, "nvidia,droop-ctrl", &td->droop_ctrl);
1904 ok &= read_dt_param(td, "nvidia,sample-rate", &td->sample_rate);
1905 ok &= read_dt_param(td, "nvidia,force-mode", &td->force_mode);
1906 ok &= read_dt_param(td, "nvidia,cf", &td->cf);
1907 ok &= read_dt_param(td, "nvidia,ci", &td->ci);
1908 ok &= read_dt_param(td, "nvidia,cg", &td->cg);
1909 td->cg_scale = of_property_read_bool(td->dev->of_node,
1910 "nvidia,cg-scale");
1911
1912 if (of_property_read_string(td->dev->of_node, "clock-output-names",
1913 &td->output_clock_name)) {
1914 dev_err(td->dev, "missing clock-output-names property\n");
1915 ok = false;
1916 }
1917
1918 return ok ? 0 : -EINVAL;
1919}
1920
1921
1922
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932
1933
1934int tegra_dfll_register(struct platform_device *pdev,
1935 struct tegra_dfll_soc_data *soc)
1936{
1937 struct resource *mem;
1938 struct tegra_dfll *td;
1939 int ret;
1940
1941 if (!soc) {
1942 dev_err(&pdev->dev, "no tegra_dfll_soc_data provided\n");
1943 return -EINVAL;
1944 }
1945
1946 td = devm_kzalloc(&pdev->dev, sizeof(*td), GFP_KERNEL);
1947 if (!td)
1948 return -ENOMEM;
1949 td->dev = &pdev->dev;
1950 platform_set_drvdata(pdev, td);
1951
1952 td->soc = soc;
1953
1954 td->dvco_rst = devm_reset_control_get(td->dev, "dvco");
1955 if (IS_ERR(td->dvco_rst)) {
1956 dev_err(td->dev, "couldn't get dvco reset\n");
1957 return PTR_ERR(td->dvco_rst);
1958 }
1959
1960 ret = dfll_fetch_common_params(td);
1961 if (ret) {
1962 dev_err(td->dev, "couldn't parse device tree parameters\n");
1963 return ret;
1964 }
1965
1966 if (of_property_read_bool(td->dev->of_node, "nvidia,pwm-to-pmic")) {
1967 td->pmu_if = TEGRA_DFLL_PMU_PWM;
1968 ret = dfll_fetch_pwm_params(td);
1969 } else {
1970 td->vdd_reg = devm_regulator_get(td->dev, "vdd-cpu");
1971 if (IS_ERR(td->vdd_reg)) {
1972 dev_err(td->dev, "couldn't get vdd_cpu regulator\n");
1973 return PTR_ERR(td->vdd_reg);
1974 }
1975 td->pmu_if = TEGRA_DFLL_PMU_I2C;
1976 ret = dfll_fetch_i2c_params(td);
1977 }
1978 if (ret)
1979 return ret;
1980
1981 ret = dfll_build_lut(td);
1982 if (ret) {
1983 dev_err(td->dev, "couldn't build LUT\n");
1984 return ret;
1985 }
1986
1987 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1988 if (!mem) {
1989 dev_err(td->dev, "no control register resource\n");
1990 return -ENODEV;
1991 }
1992
1993 td->base = devm_ioremap(td->dev, mem->start, resource_size(mem));
1994 if (!td->base) {
1995 dev_err(td->dev, "couldn't ioremap DFLL control registers\n");
1996 return -ENODEV;
1997 }
1998
1999 mem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2000 if (!mem) {
2001 dev_err(td->dev, "no i2c_base resource\n");
2002 return -ENODEV;
2003 }
2004
2005 td->i2c_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
2006 if (!td->i2c_base) {
2007 dev_err(td->dev, "couldn't ioremap i2c_base resource\n");
2008 return -ENODEV;
2009 }
2010
2011 mem = platform_get_resource(pdev, IORESOURCE_MEM, 2);
2012 if (!mem) {
2013 dev_err(td->dev, "no i2c_controller_base resource\n");
2014 return -ENODEV;
2015 }
2016
2017 td->i2c_controller_base = devm_ioremap(td->dev, mem->start,
2018 resource_size(mem));
2019 if (!td->i2c_controller_base) {
2020 dev_err(td->dev,
2021 "couldn't ioremap i2c_controller_base resource\n");
2022 return -ENODEV;
2023 }
2024
2025 mem = platform_get_resource(pdev, IORESOURCE_MEM, 3);
2026 if (!mem) {
2027 dev_err(td->dev, "no lut_base resource\n");
2028 return -ENODEV;
2029 }
2030
2031 td->lut_base = devm_ioremap(td->dev, mem->start, resource_size(mem));
2032 if (!td->lut_base) {
2033 dev_err(td->dev,
2034 "couldn't ioremap lut_base resource\n");
2035 return -ENODEV;
2036 }
2037
2038 ret = dfll_init_clks(td);
2039 if (ret) {
2040 dev_err(&pdev->dev, "DFLL clock init error\n");
2041 return ret;
2042 }
2043
2044
2045 ret = dfll_init(td);
2046 if (ret)
2047 return ret;
2048
2049 ret = dfll_register_clk(td);
2050 if (ret) {
2051 dev_err(&pdev->dev, "DFLL clk registration failed\n");
2052 return ret;
2053 }
2054
2055 dfll_debug_init(td);
2056
2057 return 0;
2058}
2059EXPORT_SYMBOL(tegra_dfll_register);
2060
2061
2062
2063
2064
2065
2066
2067
2068
2069struct tegra_dfll_soc_data *tegra_dfll_unregister(struct platform_device *pdev)
2070{
2071 struct tegra_dfll *td = platform_get_drvdata(pdev);
2072
2073
2074 if (td->mode != DFLL_DISABLED) {
2075 dev_err(&pdev->dev,
2076 "must disable DFLL before removing driver\n");
2077 return ERR_PTR(-EBUSY);
2078 }
2079
2080 debugfs_remove_recursive(td->debugfs_dir);
2081
2082 dfll_unregister_clk(td);
2083 pm_runtime_disable(&pdev->dev);
2084
2085 clk_unprepare(td->ref_clk);
2086 clk_unprepare(td->soc_clk);
2087 clk_unprepare(td->i2c_clk);
2088
2089 reset_control_assert(td->dvco_rst);
2090
2091 return td->soc;
2092}
2093EXPORT_SYMBOL(tegra_dfll_unregister);
2094