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11#define pr_fmt(fmt) "%s: " fmt, __func__
12
13#include <linux/clk.h>
14#include <linux/clocksource.h>
15#include <linux/clockchips.h>
16#include <linux/delay.h>
17#include <linux/err.h>
18#include <linux/init.h>
19#include <linux/spinlock.h>
20#include <linux/mfd/syscon.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/platform_device.h>
24#include <linux/regmap.h>
25#include <linux/sched_clock.h>
26#include <linux/time.h>
27
28
29#define CR_TIMER_CTRL_CFG 0x00
30#define TIMER_ME_GLOBAL BIT(0)
31#define CR_TIMER_REV 0x10
32
33
34#define TIMER_CFG 0x20
35#define TIMER_ME_LOCAL BIT(0)
36#define TIMER_RELOAD_VALUE 0x24
37#define TIMER_CURRENT_VALUE 0x28
38#define TIMER_CURRENT_OVERFLOW_VALUE 0x2C
39#define TIMER_IRQ_STATUS 0x30
40#define TIMER_IRQ_CLEAR 0x34
41#define TIMER_IRQ_MASK 0x38
42
43#define PERIP_TIMER_CONTROL 0x90
44
45
46#define RELOAD_VALUE 0xffffffff
47
48struct pistachio_clocksource {
49 void __iomem *base;
50 raw_spinlock_t lock;
51 struct clocksource cs;
52};
53
54static struct pistachio_clocksource pcs_gpt;
55
56#define to_pistachio_clocksource(cs) \
57 container_of(cs, struct pistachio_clocksource, cs)
58
59static inline u32 gpt_readl(void __iomem *base, u32 offset, u32 gpt_id)
60{
61 return readl(base + 0x20 * gpt_id + offset);
62}
63
64static inline void gpt_writel(void __iomem *base, u32 value, u32 offset,
65 u32 gpt_id)
66{
67 writel(value, base + 0x20 * gpt_id + offset);
68}
69
70static u64 notrace
71pistachio_clocksource_read_cycles(struct clocksource *cs)
72{
73 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
74 u32 counter, overflow;
75 unsigned long flags;
76
77
78
79
80
81
82 raw_spin_lock_irqsave(&pcs->lock, flags);
83 overflow = gpt_readl(pcs->base, TIMER_CURRENT_OVERFLOW_VALUE, 0);
84 counter = gpt_readl(pcs->base, TIMER_CURRENT_VALUE, 0);
85 raw_spin_unlock_irqrestore(&pcs->lock, flags);
86
87 return (u64)~counter;
88}
89
90static u64 notrace pistachio_read_sched_clock(void)
91{
92 return pistachio_clocksource_read_cycles(&pcs_gpt.cs);
93}
94
95static void pistachio_clksrc_set_mode(struct clocksource *cs, int timeridx,
96 int enable)
97{
98 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
99 u32 val;
100
101 val = gpt_readl(pcs->base, TIMER_CFG, timeridx);
102 if (enable)
103 val |= TIMER_ME_LOCAL;
104 else
105 val &= ~TIMER_ME_LOCAL;
106
107 gpt_writel(pcs->base, val, TIMER_CFG, timeridx);
108}
109
110static void pistachio_clksrc_enable(struct clocksource *cs, int timeridx)
111{
112 struct pistachio_clocksource *pcs = to_pistachio_clocksource(cs);
113
114
115 pistachio_clksrc_set_mode(cs, timeridx, false);
116 gpt_writel(pcs->base, RELOAD_VALUE, TIMER_RELOAD_VALUE, timeridx);
117 pistachio_clksrc_set_mode(cs, timeridx, true);
118}
119
120static void pistachio_clksrc_disable(struct clocksource *cs, int timeridx)
121{
122
123 pistachio_clksrc_set_mode(cs, timeridx, false);
124}
125
126static int pistachio_clocksource_enable(struct clocksource *cs)
127{
128 pistachio_clksrc_enable(cs, 0);
129 return 0;
130}
131
132static void pistachio_clocksource_disable(struct clocksource *cs)
133{
134 pistachio_clksrc_disable(cs, 0);
135}
136
137
138static struct pistachio_clocksource pcs_gpt = {
139 .cs = {
140 .name = "gptimer",
141 .rating = 300,
142 .enable = pistachio_clocksource_enable,
143 .disable = pistachio_clocksource_disable,
144 .read = pistachio_clocksource_read_cycles,
145 .mask = CLOCKSOURCE_MASK(32),
146 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
147 CLOCK_SOURCE_SUSPEND_NONSTOP,
148 },
149};
150
151static int __init pistachio_clksrc_of_init(struct device_node *node)
152{
153 struct clk *sys_clk, *fast_clk;
154 struct regmap *periph_regs;
155 unsigned long rate;
156 int ret;
157
158 pcs_gpt.base = of_iomap(node, 0);
159 if (!pcs_gpt.base) {
160 pr_err("cannot iomap\n");
161 return -ENXIO;
162 }
163
164 periph_regs = syscon_regmap_lookup_by_phandle(node, "img,cr-periph");
165 if (IS_ERR(periph_regs)) {
166 pr_err("cannot get peripheral regmap (%ld)\n",
167 PTR_ERR(periph_regs));
168 return PTR_ERR(periph_regs);
169 }
170
171
172 ret = regmap_update_bits(periph_regs, PERIP_TIMER_CONTROL,
173 0xf, 0x0);
174 if (ret)
175 return ret;
176
177 sys_clk = of_clk_get_by_name(node, "sys");
178 if (IS_ERR(sys_clk)) {
179 pr_err("clock get failed (%ld)\n", PTR_ERR(sys_clk));
180 return PTR_ERR(sys_clk);
181 }
182
183 fast_clk = of_clk_get_by_name(node, "fast");
184 if (IS_ERR(fast_clk)) {
185 pr_err("clock get failed (%lu)\n", PTR_ERR(fast_clk));
186 return PTR_ERR(fast_clk);
187 }
188
189 ret = clk_prepare_enable(sys_clk);
190 if (ret < 0) {
191 pr_err("failed to enable clock (%d)\n", ret);
192 return ret;
193 }
194
195 ret = clk_prepare_enable(fast_clk);
196 if (ret < 0) {
197 pr_err("failed to enable clock (%d)\n", ret);
198 clk_disable_unprepare(sys_clk);
199 return ret;
200 }
201
202 rate = clk_get_rate(fast_clk);
203
204
205 gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 0);
206 gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 1);
207 gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 2);
208 gpt_writel(pcs_gpt.base, 0, TIMER_IRQ_MASK, 3);
209
210
211 writel(TIMER_ME_GLOBAL, pcs_gpt.base);
212
213 raw_spin_lock_init(&pcs_gpt.lock);
214 sched_clock_register(pistachio_read_sched_clock, 32, rate);
215 return clocksource_register_hz(&pcs_gpt.cs, rate);
216}
217TIMER_OF_DECLARE(pistachio_gptimer, "img,pistachio-gptimer",
218 pistachio_clksrc_of_init);
219
