1
2
3
4
5
6
7
8
9
10
11
12
13#include <linux/bitfield.h>
14#include <linux/counter.h>
15#include <linux/mfd/stm32-lptimer.h>
16#include <linux/mod_devicetable.h>
17#include <linux/module.h>
18#include <linux/pinctrl/consumer.h>
19#include <linux/platform_device.h>
20
21struct stm32_lptim_cnt {
22 struct counter_device counter;
23 struct device *dev;
24 struct regmap *regmap;
25 struct clk *clk;
26 u32 ceiling;
27 u32 polarity;
28 u32 quadrature_mode;
29 bool enabled;
30};
31
32static int stm32_lptim_is_enabled(struct stm32_lptim_cnt *priv)
33{
34 u32 val;
35 int ret;
36
37 ret = regmap_read(priv->regmap, STM32_LPTIM_CR, &val);
38 if (ret)
39 return ret;
40
41 return FIELD_GET(STM32_LPTIM_ENABLE, val);
42}
43
44static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
45 int enable)
46{
47 int ret;
48 u32 val;
49
50 val = FIELD_PREP(STM32_LPTIM_ENABLE, enable);
51 ret = regmap_write(priv->regmap, STM32_LPTIM_CR, val);
52 if (ret)
53 return ret;
54
55 if (!enable) {
56 clk_disable(priv->clk);
57 priv->enabled = false;
58 return 0;
59 }
60
61
62 ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
63 if (ret)
64 return ret;
65
66 ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
67 if (ret)
68 return ret;
69
70
71 ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
72 (val & STM32_LPTIM_CMPOK_ARROK),
73 100, 1000);
74 if (ret)
75 return ret;
76
77 ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
78 STM32_LPTIM_CMPOKCF_ARROKCF);
79 if (ret)
80 return ret;
81
82 ret = clk_enable(priv->clk);
83 if (ret) {
84 regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
85 return ret;
86 }
87 priv->enabled = true;
88
89
90 return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
91 STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
92}
93
94static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)
95{
96 u32 mask = STM32_LPTIM_ENC | STM32_LPTIM_COUNTMODE |
97 STM32_LPTIM_CKPOL | STM32_LPTIM_PRESC;
98 u32 val;
99
100
101 if (priv->quadrature_mode)
102 val = enable ? STM32_LPTIM_ENC : 0;
103 else
104 val = enable ? STM32_LPTIM_COUNTMODE : 0;
105 val |= FIELD_PREP(STM32_LPTIM_CKPOL, enable ? priv->polarity : 0);
106
107 return regmap_update_bits(priv->regmap, STM32_LPTIM_CFGR, mask, val);
108}
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132enum stm32_lptim_cnt_function {
133 STM32_LPTIM_COUNTER_INCREASE,
134 STM32_LPTIM_ENCODER_BOTH_EDGE,
135};
136
137static const enum counter_function stm32_lptim_cnt_functions[] = {
138 [STM32_LPTIM_COUNTER_INCREASE] = COUNTER_FUNCTION_INCREASE,
139 [STM32_LPTIM_ENCODER_BOTH_EDGE] = COUNTER_FUNCTION_QUADRATURE_X4,
140};
141
142enum stm32_lptim_synapse_action {
143 STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE,
144 STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE,
145 STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES,
146 STM32_LPTIM_SYNAPSE_ACTION_NONE,
147};
148
149static const enum counter_synapse_action stm32_lptim_cnt_synapse_actions[] = {
150
151 [STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE] = COUNTER_SYNAPSE_ACTION_RISING_EDGE,
152 [STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE] = COUNTER_SYNAPSE_ACTION_FALLING_EDGE,
153 [STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES] = COUNTER_SYNAPSE_ACTION_BOTH_EDGES,
154 [STM32_LPTIM_SYNAPSE_ACTION_NONE] = COUNTER_SYNAPSE_ACTION_NONE,
155};
156
157static int stm32_lptim_cnt_read(struct counter_device *counter,
158 struct counter_count *count, unsigned long *val)
159{
160 struct stm32_lptim_cnt *const priv = counter->priv;
161 u32 cnt;
162 int ret;
163
164 ret = regmap_read(priv->regmap, STM32_LPTIM_CNT, &cnt);
165 if (ret)
166 return ret;
167
168 *val = cnt;
169
170 return 0;
171}
172
173static int stm32_lptim_cnt_function_get(struct counter_device *counter,
174 struct counter_count *count,
175 size_t *function)
176{
177 struct stm32_lptim_cnt *const priv = counter->priv;
178
179 if (!priv->quadrature_mode) {
180 *function = STM32_LPTIM_COUNTER_INCREASE;
181 return 0;
182 }
183
184 if (priv->polarity == STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES) {
185 *function = STM32_LPTIM_ENCODER_BOTH_EDGE;
186 return 0;
187 }
188
189 return -EINVAL;
190}
191
192static int stm32_lptim_cnt_function_set(struct counter_device *counter,
193 struct counter_count *count,
194 size_t function)
195{
196 struct stm32_lptim_cnt *const priv = counter->priv;
197
198 if (stm32_lptim_is_enabled(priv))
199 return -EBUSY;
200
201 switch (function) {
202 case STM32_LPTIM_COUNTER_INCREASE:
203 priv->quadrature_mode = 0;
204 return 0;
205 case STM32_LPTIM_ENCODER_BOTH_EDGE:
206 priv->quadrature_mode = 1;
207 priv->polarity = STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES;
208 return 0;
209 default:
210
211 return -EINVAL;
212 }
213}
214
215static ssize_t stm32_lptim_cnt_enable_read(struct counter_device *counter,
216 struct counter_count *count,
217 void *private, char *buf)
218{
219 struct stm32_lptim_cnt *const priv = counter->priv;
220 int ret;
221
222 ret = stm32_lptim_is_enabled(priv);
223 if (ret < 0)
224 return ret;
225
226 return scnprintf(buf, PAGE_SIZE, "%u\n", ret);
227}
228
229static ssize_t stm32_lptim_cnt_enable_write(struct counter_device *counter,
230 struct counter_count *count,
231 void *private,
232 const char *buf, size_t len)
233{
234 struct stm32_lptim_cnt *const priv = counter->priv;
235 bool enable;
236 int ret;
237
238 ret = kstrtobool(buf, &enable);
239 if (ret)
240 return ret;
241
242
243 ret = stm32_lptim_is_enabled(priv);
244 if ((ret < 0) || (!ret && !enable))
245 return ret;
246 if (enable && ret)
247 return -EBUSY;
248
249 ret = stm32_lptim_setup(priv, enable);
250 if (ret)
251 return ret;
252
253 ret = stm32_lptim_set_enable_state(priv, enable);
254 if (ret)
255 return ret;
256
257 return len;
258}
259
260static ssize_t stm32_lptim_cnt_ceiling_read(struct counter_device *counter,
261 struct counter_count *count,
262 void *private, char *buf)
263{
264 struct stm32_lptim_cnt *const priv = counter->priv;
265
266 return snprintf(buf, PAGE_SIZE, "%u\n", priv->ceiling);
267}
268
269static ssize_t stm32_lptim_cnt_ceiling_write(struct counter_device *counter,
270 struct counter_count *count,
271 void *private,
272 const char *buf, size_t len)
273{
274 struct stm32_lptim_cnt *const priv = counter->priv;
275 unsigned int ceiling;
276 int ret;
277
278 if (stm32_lptim_is_enabled(priv))
279 return -EBUSY;
280
281 ret = kstrtouint(buf, 0, &ceiling);
282 if (ret)
283 return ret;
284
285 if (ceiling > STM32_LPTIM_MAX_ARR)
286 return -ERANGE;
287
288 priv->ceiling = ceiling;
289
290 return len;
291}
292
293static const struct counter_count_ext stm32_lptim_cnt_ext[] = {
294 {
295 .name = "enable",
296 .read = stm32_lptim_cnt_enable_read,
297 .write = stm32_lptim_cnt_enable_write
298 },
299 {
300 .name = "ceiling",
301 .read = stm32_lptim_cnt_ceiling_read,
302 .write = stm32_lptim_cnt_ceiling_write
303 },
304};
305
306static int stm32_lptim_cnt_action_get(struct counter_device *counter,
307 struct counter_count *count,
308 struct counter_synapse *synapse,
309 size_t *action)
310{
311 struct stm32_lptim_cnt *const priv = counter->priv;
312 size_t function;
313 int err;
314
315 err = stm32_lptim_cnt_function_get(counter, count, &function);
316 if (err)
317 return err;
318
319 switch (function) {
320 case STM32_LPTIM_COUNTER_INCREASE:
321
322 if (synapse->signal->id == count->synapses[0].signal->id)
323 *action = priv->polarity;
324 else
325 *action = STM32_LPTIM_SYNAPSE_ACTION_NONE;
326 return 0;
327 case STM32_LPTIM_ENCODER_BOTH_EDGE:
328 *action = priv->polarity;
329 return 0;
330 default:
331
332 return -EINVAL;
333 }
334}
335
336static int stm32_lptim_cnt_action_set(struct counter_device *counter,
337 struct counter_count *count,
338 struct counter_synapse *synapse,
339 size_t action)
340{
341 struct stm32_lptim_cnt *const priv = counter->priv;
342 size_t function;
343 int err;
344
345 if (stm32_lptim_is_enabled(priv))
346 return -EBUSY;
347
348 err = stm32_lptim_cnt_function_get(counter, count, &function);
349 if (err)
350 return err;
351
352
353 if (function == STM32_LPTIM_COUNTER_INCREASE
354 && synapse->signal->id == count->synapses[0].signal->id) {
355 switch (action) {
356 case STM32_LPTIM_SYNAPSE_ACTION_RISING_EDGE:
357 case STM32_LPTIM_SYNAPSE_ACTION_FALLING_EDGE:
358 case STM32_LPTIM_SYNAPSE_ACTION_BOTH_EDGES:
359 priv->polarity = action;
360 return 0;
361 }
362 }
363
364 return -EINVAL;
365}
366
367static const struct counter_ops stm32_lptim_cnt_ops = {
368 .count_read = stm32_lptim_cnt_read,
369 .function_get = stm32_lptim_cnt_function_get,
370 .function_set = stm32_lptim_cnt_function_set,
371 .action_get = stm32_lptim_cnt_action_get,
372 .action_set = stm32_lptim_cnt_action_set,
373};
374
375static struct counter_signal stm32_lptim_cnt_signals[] = {
376 {
377 .id = 0,
378 .name = "Channel 1 Quadrature A"
379 },
380 {
381 .id = 1,
382 .name = "Channel 1 Quadrature B"
383 }
384};
385
386static struct counter_synapse stm32_lptim_cnt_synapses[] = {
387 {
388 .actions_list = stm32_lptim_cnt_synapse_actions,
389 .num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
390 .signal = &stm32_lptim_cnt_signals[0]
391 },
392 {
393 .actions_list = stm32_lptim_cnt_synapse_actions,
394 .num_actions = ARRAY_SIZE(stm32_lptim_cnt_synapse_actions),
395 .signal = &stm32_lptim_cnt_signals[1]
396 }
397};
398
399
400static struct counter_count stm32_lptim_enc_counts = {
401 .id = 0,
402 .name = "LPTimer Count",
403 .functions_list = stm32_lptim_cnt_functions,
404 .num_functions = ARRAY_SIZE(stm32_lptim_cnt_functions),
405 .synapses = stm32_lptim_cnt_synapses,
406 .num_synapses = ARRAY_SIZE(stm32_lptim_cnt_synapses),
407 .ext = stm32_lptim_cnt_ext,
408 .num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
409};
410
411
412static struct counter_count stm32_lptim_in1_counts = {
413 .id = 0,
414 .name = "LPTimer Count",
415 .functions_list = stm32_lptim_cnt_functions,
416 .num_functions = 1,
417 .synapses = stm32_lptim_cnt_synapses,
418 .num_synapses = 1,
419 .ext = stm32_lptim_cnt_ext,
420 .num_ext = ARRAY_SIZE(stm32_lptim_cnt_ext)
421};
422
423static int stm32_lptim_cnt_probe(struct platform_device *pdev)
424{
425 struct stm32_lptimer *ddata = dev_get_drvdata(pdev->dev.parent);
426 struct stm32_lptim_cnt *priv;
427
428 if (IS_ERR_OR_NULL(ddata))
429 return -EINVAL;
430
431 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
432 if (!priv)
433 return -ENOMEM;
434
435 priv->dev = &pdev->dev;
436 priv->regmap = ddata->regmap;
437 priv->clk = ddata->clk;
438 priv->ceiling = STM32_LPTIM_MAX_ARR;
439
440
441 priv->counter.name = dev_name(&pdev->dev);
442 priv->counter.parent = &pdev->dev;
443 priv->counter.ops = &stm32_lptim_cnt_ops;
444 if (ddata->has_encoder) {
445 priv->counter.counts = &stm32_lptim_enc_counts;
446 priv->counter.num_signals = ARRAY_SIZE(stm32_lptim_cnt_signals);
447 } else {
448 priv->counter.counts = &stm32_lptim_in1_counts;
449 priv->counter.num_signals = 1;
450 }
451 priv->counter.num_counts = 1;
452 priv->counter.signals = stm32_lptim_cnt_signals;
453 priv->counter.priv = priv;
454
455 platform_set_drvdata(pdev, priv);
456
457 return devm_counter_register(&pdev->dev, &priv->counter);
458}
459
460#ifdef CONFIG_PM_SLEEP
461static int stm32_lptim_cnt_suspend(struct device *dev)
462{
463 struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
464 int ret;
465
466
467 if (priv->enabled) {
468 ret = stm32_lptim_setup(priv, 0);
469 if (ret)
470 return ret;
471
472 ret = stm32_lptim_set_enable_state(priv, 0);
473 if (ret)
474 return ret;
475
476
477 priv->enabled = true;
478 }
479
480 return pinctrl_pm_select_sleep_state(dev);
481}
482
483static int stm32_lptim_cnt_resume(struct device *dev)
484{
485 struct stm32_lptim_cnt *priv = dev_get_drvdata(dev);
486 int ret;
487
488 ret = pinctrl_pm_select_default_state(dev);
489 if (ret)
490 return ret;
491
492 if (priv->enabled) {
493 priv->enabled = false;
494 ret = stm32_lptim_setup(priv, 1);
495 if (ret)
496 return ret;
497
498 ret = stm32_lptim_set_enable_state(priv, 1);
499 if (ret)
500 return ret;
501 }
502
503 return 0;
504}
505#endif
506
507static SIMPLE_DEV_PM_OPS(stm32_lptim_cnt_pm_ops, stm32_lptim_cnt_suspend,
508 stm32_lptim_cnt_resume);
509
510static const struct of_device_id stm32_lptim_cnt_of_match[] = {
511 { .compatible = "st,stm32-lptimer-counter", },
512 {},
513};
514MODULE_DEVICE_TABLE(of, stm32_lptim_cnt_of_match);
515
516static struct platform_driver stm32_lptim_cnt_driver = {
517 .probe = stm32_lptim_cnt_probe,
518 .driver = {
519 .name = "stm32-lptimer-counter",
520 .of_match_table = stm32_lptim_cnt_of_match,
521 .pm = &stm32_lptim_cnt_pm_ops,
522 },
523};
524module_platform_driver(stm32_lptim_cnt_driver);
525
526MODULE_AUTHOR("Fabrice Gasnier <fabrice.gasnier@st.com>");
527MODULE_ALIAS("platform:stm32-lptimer-counter");
528MODULE_DESCRIPTION("STMicroelectronics STM32 LPTIM counter driver");
529MODULE_LICENSE("GPL v2");
530
