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7
8
9#include <linux/device.h>
10#include <linux/of_address.h>
11#include <linux/of_irq.h>
12#include <linux/sys_soc.h>
13#include <linux/fsl/mc.h>
14
15#include "compat.h"
16#include "debugfs.h"
17#include "regs.h"
18#include "intern.h"
19#include "jr.h"
20#include "desc_constr.h"
21#include "ctrl.h"
22
23bool caam_dpaa2;
24EXPORT_SYMBOL(caam_dpaa2);
25
26#ifdef CONFIG_CAAM_QI
27#include "qi.h"
28#endif
29
30
31
32
33
34static void build_instantiation_desc(u32 *desc, int handle, int do_sk)
35{
36 u32 *jump_cmd, op_flags;
37
38 init_job_desc(desc, 0);
39
40 op_flags = OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
41 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INIT |
42 OP_ALG_PR_ON;
43
44
45 append_operation(desc, op_flags);
46
47 if (!handle && do_sk) {
48
49
50
51
52
53 jump_cmd = append_jump(desc, JUMP_CLASS_CLASS1);
54 set_jump_tgt_here(desc, jump_cmd);
55
56
57
58
59
60 append_load_imm_u32(desc, 1, LDST_SRCDST_WORD_CLRW);
61
62
63 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
64 OP_ALG_AAI_RNG4_SK);
65 }
66
67 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
68}
69
70
71static void build_deinstantiation_desc(u32 *desc, int handle)
72{
73 init_job_desc(desc, 0);
74
75
76 append_operation(desc, OP_TYPE_CLASS1_ALG | OP_ALG_ALGSEL_RNG |
77 (handle << OP_ALG_AAI_SHIFT) | OP_ALG_AS_INITFINAL);
78
79 append_jump(desc, JUMP_CLASS_CLASS1 | JUMP_TYPE_HALT);
80}
81
82
83
84
85
86
87
88
89
90
91
92static inline int run_descriptor_deco0(struct device *ctrldev, u32 *desc,
93 u32 *status)
94{
95 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
96 struct caam_ctrl __iomem *ctrl = ctrlpriv->ctrl;
97 struct caam_deco __iomem *deco = ctrlpriv->deco;
98 unsigned int timeout = 100000;
99 u32 deco_dbg_reg, deco_state, flags;
100 int i;
101
102
103 if (ctrlpriv->virt_en == 1 ||
104
105
106
107
108 of_machine_is_compatible("fsl,imx8mq") ||
109 of_machine_is_compatible("fsl,imx8mm") ||
110 of_machine_is_compatible("fsl,imx8mn") ||
111 of_machine_is_compatible("fsl,imx8mp")) {
112 clrsetbits_32(&ctrl->deco_rsr, 0, DECORSR_JR0);
113
114 while (!(rd_reg32(&ctrl->deco_rsr) & DECORSR_VALID) &&
115 --timeout)
116 cpu_relax();
117
118 timeout = 100000;
119 }
120
121 clrsetbits_32(&ctrl->deco_rq, 0, DECORR_RQD0ENABLE);
122
123 while (!(rd_reg32(&ctrl->deco_rq) & DECORR_DEN0) &&
124 --timeout)
125 cpu_relax();
126
127 if (!timeout) {
128 dev_err(ctrldev, "failed to acquire DECO 0\n");
129 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
130 return -ENODEV;
131 }
132
133 for (i = 0; i < desc_len(desc); i++)
134 wr_reg32(&deco->descbuf[i], caam32_to_cpu(*(desc + i)));
135
136 flags = DECO_JQCR_WHL;
137
138
139
140
141 if (desc_len(desc) >= 4)
142 flags |= DECO_JQCR_FOUR;
143
144
145 clrsetbits_32(&deco->jr_ctl_hi, 0, flags);
146
147 timeout = 10000000;
148 do {
149 deco_dbg_reg = rd_reg32(&deco->desc_dbg);
150
151 if (ctrlpriv->era < 10)
152 deco_state = (deco_dbg_reg & DESC_DBG_DECO_STAT_MASK) >>
153 DESC_DBG_DECO_STAT_SHIFT;
154 else
155 deco_state = (rd_reg32(&deco->dbg_exec) &
156 DESC_DER_DECO_STAT_MASK) >>
157 DESC_DER_DECO_STAT_SHIFT;
158
159
160
161
162
163 if (deco_state == DECO_STAT_HOST_ERR)
164 break;
165
166 cpu_relax();
167 } while ((deco_dbg_reg & DESC_DBG_DECO_STAT_VALID) && --timeout);
168
169 *status = rd_reg32(&deco->op_status_hi) &
170 DECO_OP_STATUS_HI_ERR_MASK;
171
172 if (ctrlpriv->virt_en == 1)
173 clrsetbits_32(&ctrl->deco_rsr, DECORSR_JR0, 0);
174
175
176 clrsetbits_32(&ctrl->deco_rq, DECORR_RQD0ENABLE, 0);
177
178 if (!timeout)
179 return -EAGAIN;
180
181 return 0;
182}
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197static int deinstantiate_rng(struct device *ctrldev, int state_handle_mask)
198{
199 u32 *desc, status;
200 int sh_idx, ret = 0;
201
202 desc = kmalloc(CAAM_CMD_SZ * 3, GFP_KERNEL | GFP_DMA);
203 if (!desc)
204 return -ENOMEM;
205
206 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
207
208
209
210
211
212 if ((1 << sh_idx) & state_handle_mask) {
213
214
215
216
217 build_deinstantiation_desc(desc, sh_idx);
218
219
220 ret = run_descriptor_deco0(ctrldev, desc, &status);
221
222 if (ret ||
223 (status && status != JRSTA_SSRC_JUMP_HALT_CC)) {
224 dev_err(ctrldev,
225 "Failed to deinstantiate RNG4 SH%d\n",
226 sh_idx);
227 break;
228 }
229 dev_info(ctrldev, "Deinstantiated RNG4 SH%d\n", sh_idx);
230 }
231 }
232
233 kfree(desc);
234
235 return ret;
236}
237
238static void devm_deinstantiate_rng(void *data)
239{
240 struct device *ctrldev = data;
241 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
242
243
244
245
246
247 if (ctrlpriv->rng4_sh_init)
248 deinstantiate_rng(ctrldev, ctrlpriv->rng4_sh_init);
249}
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270static int instantiate_rng(struct device *ctrldev, int state_handle_mask,
271 int gen_sk)
272{
273 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
274 struct caam_ctrl __iomem *ctrl;
275 u32 *desc, status = 0, rdsta_val;
276 int ret = 0, sh_idx;
277
278 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
279 desc = kmalloc(CAAM_CMD_SZ * 7, GFP_KERNEL | GFP_DMA);
280 if (!desc)
281 return -ENOMEM;
282
283 for (sh_idx = 0; sh_idx < RNG4_MAX_HANDLES; sh_idx++) {
284 const u32 rdsta_if = RDSTA_IF0 << sh_idx;
285 const u32 rdsta_pr = RDSTA_PR0 << sh_idx;
286 const u32 rdsta_mask = rdsta_if | rdsta_pr;
287
288
289
290
291 if (rdsta_if & state_handle_mask) {
292 if (rdsta_pr & state_handle_mask)
293 continue;
294
295 dev_info(ctrldev,
296 "RNG4 SH%d was previously instantiated without prediction resistance. Tearing it down\n",
297 sh_idx);
298
299 ret = deinstantiate_rng(ctrldev, rdsta_if);
300 if (ret)
301 break;
302 }
303
304
305 build_instantiation_desc(desc, sh_idx, gen_sk);
306
307
308 ret = run_descriptor_deco0(ctrldev, desc, &status);
309
310
311
312
313
314
315
316
317
318
319 if (ret)
320 break;
321
322 rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_MASK;
323 if ((status && status != JRSTA_SSRC_JUMP_HALT_CC) ||
324 (rdsta_val & rdsta_mask) != rdsta_mask) {
325 ret = -EAGAIN;
326 break;
327 }
328
329 dev_info(ctrldev, "Instantiated RNG4 SH%d\n", sh_idx);
330
331 memset(desc, 0x00, CAAM_CMD_SZ * 7);
332 }
333
334 kfree(desc);
335
336 if (ret)
337 return ret;
338
339 return devm_add_action_or_reset(ctrldev, devm_deinstantiate_rng, ctrldev);
340}
341
342
343
344
345
346
347
348static void kick_trng(struct platform_device *pdev, int ent_delay)
349{
350 struct device *ctrldev = &pdev->dev;
351 struct caam_drv_private *ctrlpriv = dev_get_drvdata(ctrldev);
352 struct caam_ctrl __iomem *ctrl;
353 struct rng4tst __iomem *r4tst;
354 u32 val;
355
356 ctrl = (struct caam_ctrl __iomem *)ctrlpriv->ctrl;
357 r4tst = &ctrl->r4tst[0];
358
359
360
361
362
363
364 clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM | RTMCTL_ACC);
365
366
367
368
369
370
371
372
373
374 val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK)
375 >> RTSDCTL_ENT_DLY_SHIFT;
376 if (ent_delay <= val)
377 goto start_rng;
378
379 val = rd_reg32(&r4tst->rtsdctl);
380 val = (val & ~RTSDCTL_ENT_DLY_MASK) |
381 (ent_delay << RTSDCTL_ENT_DLY_SHIFT);
382 wr_reg32(&r4tst->rtsdctl, val);
383
384 wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2);
385
386 wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE);
387
388 val = rd_reg32(&r4tst->rtmctl);
389start_rng:
390
391
392
393
394 clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM | RTMCTL_ACC,
395 RTMCTL_SAMP_MODE_RAW_ES_SC);
396}
397
398static int caam_get_era_from_hw(struct caam_ctrl __iomem *ctrl)
399{
400 static const struct {
401 u16 ip_id;
402 u8 maj_rev;
403 u8 era;
404 } id[] = {
405 {0x0A10, 1, 1},
406 {0x0A10, 2, 2},
407 {0x0A12, 1, 3},
408 {0x0A14, 1, 3},
409 {0x0A14, 2, 4},
410 {0x0A16, 1, 4},
411 {0x0A10, 3, 4},
412 {0x0A11, 1, 4},
413 {0x0A18, 1, 4},
414 {0x0A11, 2, 5},
415 {0x0A12, 2, 5},
416 {0x0A13, 1, 5},
417 {0x0A1C, 1, 5}
418 };
419 u32 ccbvid, id_ms;
420 u8 maj_rev, era;
421 u16 ip_id;
422 int i;
423
424 ccbvid = rd_reg32(&ctrl->perfmon.ccb_id);
425 era = (ccbvid & CCBVID_ERA_MASK) >> CCBVID_ERA_SHIFT;
426 if (era)
427 return era;
428
429 id_ms = rd_reg32(&ctrl->perfmon.caam_id_ms);
430 ip_id = (id_ms & SECVID_MS_IPID_MASK) >> SECVID_MS_IPID_SHIFT;
431 maj_rev = (id_ms & SECVID_MS_MAJ_REV_MASK) >> SECVID_MS_MAJ_REV_SHIFT;
432
433 for (i = 0; i < ARRAY_SIZE(id); i++)
434 if (id[i].ip_id == ip_id && id[i].maj_rev == maj_rev)
435 return id[i].era;
436
437 return -ENOTSUPP;
438}
439
440
441
442
443
444
445
446
447
448
449static int caam_get_era(struct caam_ctrl __iomem *ctrl)
450{
451 struct device_node *caam_node;
452 int ret;
453 u32 prop;
454
455 caam_node = of_find_compatible_node(NULL, NULL, "fsl,sec-v4.0");
456 ret = of_property_read_u32(caam_node, "fsl,sec-era", &prop);
457 of_node_put(caam_node);
458
459 if (!ret)
460 return prop;
461 else
462 return caam_get_era_from_hw(ctrl);
463}
464
465
466
467
468
469
470
471
472
473
474static void handle_imx6_err005766(u32 __iomem *mcr)
475{
476 if (of_machine_is_compatible("fsl,imx6q") ||
477 of_machine_is_compatible("fsl,imx6dl") ||
478 of_machine_is_compatible("fsl,imx6qp"))
479 clrsetbits_32(mcr, MCFGR_AXIPIPE_MASK,
480 1 << MCFGR_AXIPIPE_SHIFT);
481}
482
483static const struct of_device_id caam_match[] = {
484 {
485 .compatible = "fsl,sec-v4.0",
486 },
487 {
488 .compatible = "fsl,sec4.0",
489 },
490 {},
491};
492MODULE_DEVICE_TABLE(of, caam_match);
493
494struct caam_imx_data {
495 const struct clk_bulk_data *clks;
496 int num_clks;
497};
498
499static const struct clk_bulk_data caam_imx6_clks[] = {
500 { .id = "ipg" },
501 { .id = "mem" },
502 { .id = "aclk" },
503 { .id = "emi_slow" },
504};
505
506static const struct caam_imx_data caam_imx6_data = {
507 .clks = caam_imx6_clks,
508 .num_clks = ARRAY_SIZE(caam_imx6_clks),
509};
510
511static const struct clk_bulk_data caam_imx7_clks[] = {
512 { .id = "ipg" },
513 { .id = "aclk" },
514};
515
516static const struct caam_imx_data caam_imx7_data = {
517 .clks = caam_imx7_clks,
518 .num_clks = ARRAY_SIZE(caam_imx7_clks),
519};
520
521static const struct clk_bulk_data caam_imx6ul_clks[] = {
522 { .id = "ipg" },
523 { .id = "mem" },
524 { .id = "aclk" },
525};
526
527static const struct caam_imx_data caam_imx6ul_data = {
528 .clks = caam_imx6ul_clks,
529 .num_clks = ARRAY_SIZE(caam_imx6ul_clks),
530};
531
532static const struct clk_bulk_data caam_vf610_clks[] = {
533 { .id = "ipg" },
534};
535
536static const struct caam_imx_data caam_vf610_data = {
537 .clks = caam_vf610_clks,
538 .num_clks = ARRAY_SIZE(caam_vf610_clks),
539};
540
541static const struct soc_device_attribute caam_imx_soc_table[] = {
542 { .soc_id = "i.MX6UL", .data = &caam_imx6ul_data },
543 { .soc_id = "i.MX6*", .data = &caam_imx6_data },
544 { .soc_id = "i.MX7*", .data = &caam_imx7_data },
545 { .soc_id = "i.MX8M*", .data = &caam_imx7_data },
546 { .soc_id = "VF*", .data = &caam_vf610_data },
547 { .family = "Freescale i.MX" },
548 { }
549};
550
551static void disable_clocks(void *data)
552{
553 struct caam_drv_private *ctrlpriv = data;
554
555 clk_bulk_disable_unprepare(ctrlpriv->num_clks, ctrlpriv->clks);
556}
557
558static int init_clocks(struct device *dev, const struct caam_imx_data *data)
559{
560 struct caam_drv_private *ctrlpriv = dev_get_drvdata(dev);
561 int ret;
562
563 ctrlpriv->num_clks = data->num_clks;
564 ctrlpriv->clks = devm_kmemdup(dev, data->clks,
565 data->num_clks * sizeof(data->clks[0]),
566 GFP_KERNEL);
567 if (!ctrlpriv->clks)
568 return -ENOMEM;
569
570 ret = devm_clk_bulk_get(dev, ctrlpriv->num_clks, ctrlpriv->clks);
571 if (ret) {
572 dev_err(dev,
573 "Failed to request all necessary clocks\n");
574 return ret;
575 }
576
577 ret = clk_bulk_prepare_enable(ctrlpriv->num_clks, ctrlpriv->clks);
578 if (ret) {
579 dev_err(dev,
580 "Failed to prepare/enable all necessary clocks\n");
581 return ret;
582 }
583
584 return devm_add_action_or_reset(dev, disable_clocks, ctrlpriv);
585}
586
587static void caam_remove_debugfs(void *root)
588{
589 debugfs_remove_recursive(root);
590}
591
592#ifdef CONFIG_FSL_MC_BUS
593static bool check_version(struct fsl_mc_version *mc_version, u32 major,
594 u32 minor, u32 revision)
595{
596 if (mc_version->major > major)
597 return true;
598
599 if (mc_version->major == major) {
600 if (mc_version->minor > minor)
601 return true;
602
603 if (mc_version->minor == minor &&
604 mc_version->revision > revision)
605 return true;
606 }
607
608 return false;
609}
610#endif
611
612
613static int caam_probe(struct platform_device *pdev)
614{
615 int ret, ring, gen_sk, ent_delay = RTSDCTL_ENT_DLY_MIN;
616 u64 caam_id;
617 const struct soc_device_attribute *imx_soc_match;
618 struct device *dev;
619 struct device_node *nprop, *np;
620 struct caam_ctrl __iomem *ctrl;
621 struct caam_drv_private *ctrlpriv;
622 struct dentry *dfs_root;
623 u32 scfgr, comp_params;
624 u8 rng_vid;
625 int pg_size;
626 int BLOCK_OFFSET = 0;
627 bool pr_support = false;
628
629 ctrlpriv = devm_kzalloc(&pdev->dev, sizeof(*ctrlpriv), GFP_KERNEL);
630 if (!ctrlpriv)
631 return -ENOMEM;
632
633 dev = &pdev->dev;
634 dev_set_drvdata(dev, ctrlpriv);
635 nprop = pdev->dev.of_node;
636
637 imx_soc_match = soc_device_match(caam_imx_soc_table);
638 caam_imx = (bool)imx_soc_match;
639
640 if (imx_soc_match) {
641 if (!imx_soc_match->data) {
642 dev_err(dev, "No clock data provided for i.MX SoC");
643 return -EINVAL;
644 }
645
646 ret = init_clocks(dev, imx_soc_match->data);
647 if (ret)
648 return ret;
649 }
650
651
652
653
654 ctrl = devm_of_iomap(dev, nprop, 0, NULL);
655 ret = PTR_ERR_OR_ZERO(ctrl);
656 if (ret) {
657 dev_err(dev, "caam: of_iomap() failed\n");
658 return ret;
659 }
660
661 caam_little_end = !(bool)(rd_reg32(&ctrl->perfmon.status) &
662 (CSTA_PLEND | CSTA_ALT_PLEND));
663 comp_params = rd_reg32(&ctrl->perfmon.comp_parms_ms);
664 if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
665 caam_ptr_sz = sizeof(u64);
666 else
667 caam_ptr_sz = sizeof(u32);
668 caam_dpaa2 = !!(comp_params & CTPR_MS_DPAA2);
669 ctrlpriv->qi_present = !!(comp_params & CTPR_MS_QI_MASK);
670
671#ifdef CONFIG_CAAM_QI
672
673 if (ctrlpriv->qi_present && !caam_dpaa2) {
674 ret = qman_is_probed();
675 if (!ret) {
676 return -EPROBE_DEFER;
677 } else if (ret < 0) {
678 dev_err(dev, "failing probe due to qman probe error\n");
679 return -ENODEV;
680 }
681
682 ret = qman_portals_probed();
683 if (!ret) {
684 return -EPROBE_DEFER;
685 } else if (ret < 0) {
686 dev_err(dev, "failing probe due to qman portals probe error\n");
687 return -ENODEV;
688 }
689 }
690#endif
691
692
693
694
695 pg_size = (comp_params & CTPR_MS_PG_SZ_MASK) >> CTPR_MS_PG_SZ_SHIFT;
696 if (pg_size == 0)
697 BLOCK_OFFSET = PG_SIZE_4K;
698 else
699 BLOCK_OFFSET = PG_SIZE_64K;
700
701 ctrlpriv->ctrl = (struct caam_ctrl __iomem __force *)ctrl;
702 ctrlpriv->assure = (struct caam_assurance __iomem __force *)
703 ((__force uint8_t *)ctrl +
704 BLOCK_OFFSET * ASSURE_BLOCK_NUMBER
705 );
706 ctrlpriv->deco = (struct caam_deco __iomem __force *)
707 ((__force uint8_t *)ctrl +
708 BLOCK_OFFSET * DECO_BLOCK_NUMBER
709 );
710
711
712 ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
713 np = of_find_compatible_node(NULL, NULL, "fsl,qoriq-mc");
714 ctrlpriv->mc_en = !!np;
715 of_node_put(np);
716
717#ifdef CONFIG_FSL_MC_BUS
718 if (ctrlpriv->mc_en) {
719 struct fsl_mc_version *mc_version;
720
721 mc_version = fsl_mc_get_version();
722 if (mc_version)
723 pr_support = check_version(mc_version, 10, 20, 0);
724 else
725 return -EPROBE_DEFER;
726 }
727#endif
728
729
730
731
732
733
734
735 if (!ctrlpriv->mc_en)
736 clrsetbits_32(&ctrl->mcr, MCFGR_AWCACHE_MASK,
737 MCFGR_AWCACHE_CACH | MCFGR_AWCACHE_BUFF |
738 MCFGR_WDENABLE | MCFGR_LARGE_BURST);
739
740 handle_imx6_err005766(&ctrl->mcr);
741
742
743
744
745
746 scfgr = rd_reg32(&ctrl->scfgr);
747
748 ctrlpriv->virt_en = 0;
749 if (comp_params & CTPR_MS_VIRT_EN_INCL) {
750
751
752
753 if ((comp_params & CTPR_MS_VIRT_EN_POR) ||
754 (!(comp_params & CTPR_MS_VIRT_EN_POR) &&
755 (scfgr & SCFGR_VIRT_EN)))
756 ctrlpriv->virt_en = 1;
757 } else {
758
759 if (comp_params & CTPR_MS_VIRT_EN_POR)
760 ctrlpriv->virt_en = 1;
761 }
762
763 if (ctrlpriv->virt_en == 1)
764 clrsetbits_32(&ctrl->jrstart, 0, JRSTART_JR0_START |
765 JRSTART_JR1_START | JRSTART_JR2_START |
766 JRSTART_JR3_START);
767
768 ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
769 if (ret) {
770 dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
771 return ret;
772 }
773
774 ctrlpriv->era = caam_get_era(ctrl);
775 ctrlpriv->domain = iommu_get_domain_for_dev(dev);
776
777 dfs_root = debugfs_create_dir(dev_name(dev), NULL);
778 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
779 ret = devm_add_action_or_reset(dev, caam_remove_debugfs,
780 dfs_root);
781 if (ret)
782 return ret;
783 }
784
785 caam_debugfs_init(ctrlpriv, dfs_root);
786
787
788 if (ctrlpriv->qi_present && !caam_dpaa2) {
789 ctrlpriv->qi = (struct caam_queue_if __iomem __force *)
790 ((__force uint8_t *)ctrl +
791 BLOCK_OFFSET * QI_BLOCK_NUMBER
792 );
793
794 wr_reg32(&ctrlpriv->qi->qi_control_lo, QICTL_DQEN);
795
796
797#ifdef CONFIG_CAAM_QI
798 ret = caam_qi_init(pdev);
799 if (ret)
800 dev_err(dev, "caam qi i/f init failed: %d\n", ret);
801#endif
802 }
803
804 ring = 0;
805 for_each_available_child_of_node(nprop, np)
806 if (of_device_is_compatible(np, "fsl,sec-v4.0-job-ring") ||
807 of_device_is_compatible(np, "fsl,sec4.0-job-ring")) {
808 ctrlpriv->jr[ring] = (struct caam_job_ring __iomem __force *)
809 ((__force uint8_t *)ctrl +
810 (ring + JR_BLOCK_NUMBER) *
811 BLOCK_OFFSET
812 );
813 ctrlpriv->total_jobrs++;
814 ring++;
815 }
816
817
818 if ((!ctrlpriv->qi_present) && (!ctrlpriv->total_jobrs)) {
819 dev_err(dev, "no queues configured, terminating\n");
820 return -ENOMEM;
821 }
822
823 if (ctrlpriv->era < 10)
824 rng_vid = (rd_reg32(&ctrl->perfmon.cha_id_ls) &
825 CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
826 else
827 rng_vid = (rd_reg32(&ctrl->vreg.rng) & CHA_VER_VID_MASK) >>
828 CHA_VER_VID_SHIFT;
829
830
831
832
833
834
835 if (!(ctrlpriv->mc_en && pr_support) && rng_vid >= 4) {
836 ctrlpriv->rng4_sh_init =
837 rd_reg32(&ctrl->r4tst[0].rdsta);
838
839
840
841
842
843
844 gen_sk = ctrlpriv->rng4_sh_init & RDSTA_SKVN ? 0 : 1;
845 ctrlpriv->rng4_sh_init &= RDSTA_MASK;
846 do {
847 int inst_handles =
848 rd_reg32(&ctrl->r4tst[0].rdsta) &
849 RDSTA_MASK;
850
851
852
853
854
855
856
857
858 if (!(ctrlpriv->rng4_sh_init || inst_handles)) {
859 dev_info(dev,
860 "Entropy delay = %u\n",
861 ent_delay);
862 kick_trng(pdev, ent_delay);
863 ent_delay += 400;
864 }
865
866
867
868
869
870
871
872 ret = instantiate_rng(dev, inst_handles,
873 gen_sk);
874 if (ret == -EAGAIN)
875
876
877
878
879 cpu_relax();
880 } while ((ret == -EAGAIN) && (ent_delay < RTSDCTL_ENT_DLY_MAX));
881 if (ret) {
882 dev_err(dev, "failed to instantiate RNG");
883 return ret;
884 }
885
886
887
888
889 ctrlpriv->rng4_sh_init = ~ctrlpriv->rng4_sh_init & RDSTA_MASK;
890
891
892 clrsetbits_32(&ctrl->scfgr, 0, SCFGR_RDBENABLE);
893 }
894
895
896
897 caam_id = (u64)rd_reg32(&ctrl->perfmon.caam_id_ms) << 32 |
898 (u64)rd_reg32(&ctrl->perfmon.caam_id_ls);
899
900
901 dev_info(dev, "device ID = 0x%016llx (Era %d)\n", caam_id,
902 ctrlpriv->era);
903 dev_info(dev, "job rings = %d, qi = %d\n",
904 ctrlpriv->total_jobrs, ctrlpriv->qi_present);
905
906 ret = devm_of_platform_populate(dev);
907 if (ret)
908 dev_err(dev, "JR platform devices creation error\n");
909
910 return ret;
911}
912
913static struct platform_driver caam_driver = {
914 .driver = {
915 .name = "caam",
916 .of_match_table = caam_match,
917 },
918 .probe = caam_probe,
919};
920
921module_platform_driver(caam_driver);
922
923MODULE_LICENSE("GPL");
924MODULE_DESCRIPTION("FSL CAAM request backend");
925MODULE_AUTHOR("Freescale Semiconductor - NMG/STC");
926