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9#ifndef REGS_H
10#define REGS_H
11
12#include <linux/types.h>
13#include <linux/bitops.h>
14#include <linux/io.h>
15#include <linux/io-64-nonatomic-hi-lo.h>
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71
72extern bool caam_little_end;
73extern bool caam_imx;
74extern size_t caam_ptr_sz;
75
76#define caam_to_cpu(len) \
77static inline u##len caam##len ## _to_cpu(u##len val) \
78{ \
79 if (caam_little_end) \
80 return le##len ## _to_cpu((__force __le##len)val); \
81 else \
82 return be##len ## _to_cpu((__force __be##len)val); \
83}
84
85#define cpu_to_caam(len) \
86static inline u##len cpu_to_caam##len(u##len val) \
87{ \
88 if (caam_little_end) \
89 return (__force u##len)cpu_to_le##len(val); \
90 else \
91 return (__force u##len)cpu_to_be##len(val); \
92}
93
94caam_to_cpu(16)
95caam_to_cpu(32)
96caam_to_cpu(64)
97cpu_to_caam(16)
98cpu_to_caam(32)
99cpu_to_caam(64)
100
101static inline void wr_reg32(void __iomem *reg, u32 data)
102{
103 if (caam_little_end)
104 iowrite32(data, reg);
105 else
106 iowrite32be(data, reg);
107}
108
109static inline u32 rd_reg32(void __iomem *reg)
110{
111 if (caam_little_end)
112 return ioread32(reg);
113
114 return ioread32be(reg);
115}
116
117static inline void clrsetbits_32(void __iomem *reg, u32 clear, u32 set)
118{
119 if (caam_little_end)
120 iowrite32((ioread32(reg) & ~clear) | set, reg);
121 else
122 iowrite32be((ioread32be(reg) & ~clear) | set, reg);
123}
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141
142static inline void wr_reg64(void __iomem *reg, u64 data)
143{
144 if (caam_little_end) {
145 if (caam_imx) {
146 iowrite32(data >> 32, (u32 __iomem *)(reg));
147 iowrite32(data, (u32 __iomem *)(reg) + 1);
148 } else {
149 iowrite64(data, reg);
150 }
151 } else {
152 iowrite64be(data, reg);
153 }
154}
155
156static inline u64 rd_reg64(void __iomem *reg)
157{
158 if (caam_little_end) {
159 if (caam_imx) {
160 u32 low, high;
161
162 high = ioread32(reg);
163 low = ioread32(reg + sizeof(u32));
164
165 return low + ((u64)high << 32);
166 } else {
167 return ioread64(reg);
168 }
169 } else {
170 return ioread64be(reg);
171 }
172}
173
174static inline u64 cpu_to_caam_dma64(dma_addr_t value)
175{
176 if (caam_imx) {
177 u64 ret_val = (u64)cpu_to_caam32(lower_32_bits(value)) << 32;
178
179 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT))
180 ret_val |= (u64)cpu_to_caam32(upper_32_bits(value));
181
182 return ret_val;
183 }
184
185 return cpu_to_caam64(value);
186}
187
188static inline u64 caam_dma64_to_cpu(u64 value)
189{
190 if (caam_imx)
191 return (((u64)caam32_to_cpu(lower_32_bits(value)) << 32) |
192 (u64)caam32_to_cpu(upper_32_bits(value)));
193
194 return caam64_to_cpu(value);
195}
196
197static inline u64 cpu_to_caam_dma(u64 value)
198{
199 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
200 caam_ptr_sz == sizeof(u64))
201 return cpu_to_caam_dma64(value);
202 else
203 return cpu_to_caam32(value);
204}
205
206static inline u64 caam_dma_to_cpu(u64 value)
207{
208 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT) &&
209 caam_ptr_sz == sizeof(u64))
210 return caam_dma64_to_cpu(value);
211 else
212 return caam32_to_cpu(value);
213}
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219
220static inline void jr_outentry_get(void *outring, int hw_idx, dma_addr_t *desc,
221 u32 *jrstatus)
222{
223
224 if (caam_ptr_sz == sizeof(u32)) {
225 struct {
226 u32 desc;
227 u32 jrstatus;
228 } __packed *outentry = outring;
229
230 *desc = outentry[hw_idx].desc;
231 *jrstatus = outentry[hw_idx].jrstatus;
232 } else {
233 struct {
234 dma_addr_t desc;
235 u32 jrstatus;
236 } __packed *outentry = outring;
237
238 *desc = outentry[hw_idx].desc;
239 *jrstatus = outentry[hw_idx].jrstatus;
240 }
241}
242
243#define SIZEOF_JR_OUTENTRY (caam_ptr_sz + sizeof(u32))
244
245static inline dma_addr_t jr_outentry_desc(void *outring, int hw_idx)
246{
247 dma_addr_t desc;
248 u32 unused;
249
250 jr_outentry_get(outring, hw_idx, &desc, &unused);
251
252 return desc;
253}
254
255static inline u32 jr_outentry_jrstatus(void *outring, int hw_idx)
256{
257 dma_addr_t unused;
258 u32 jrstatus;
259
260 jr_outentry_get(outring, hw_idx, &unused, &jrstatus);
261
262 return jrstatus;
263}
264
265static inline void jr_inpentry_set(void *inpring, int hw_idx, dma_addr_t val)
266{
267 if (caam_ptr_sz == sizeof(u32)) {
268 u32 *inpentry = inpring;
269
270 inpentry[hw_idx] = val;
271 } else {
272 dma_addr_t *inpentry = inpring;
273
274 inpentry[hw_idx] = val;
275 }
276}
277
278#define SIZEOF_JR_INPENTRY caam_ptr_sz
279
280
281
282struct version_regs {
283 u32 crca;
284 u32 afha;
285 u32 kfha;
286 u32 pkha;
287 u32 aesa;
288 u32 mdha;
289 u32 desa;
290 u32 snw8a;
291 u32 snw9a;
292 u32 zuce;
293 u32 zuca;
294 u32 ccha;
295 u32 ptha;
296 u32 rng;
297 u32 trng;
298 u32 aaha;
299 u32 rsvd[10];
300 u32 sr;
301 u32 dma;
302 u32 ai;
303 u32 qi;
304 u32 jr;
305 u32 deco;
306};
307
308
309
310
311#define CHA_VER_NUM_MASK 0xffull
312
313#define CHA_VER_MISC_SHIFT 8
314#define CHA_VER_MISC_MASK (0xffull << CHA_VER_MISC_SHIFT)
315
316#define CHA_VER_REV_SHIFT 16
317#define CHA_VER_REV_MASK (0xffull << CHA_VER_REV_SHIFT)
318
319#define CHA_VER_VID_SHIFT 24
320#define CHA_VER_VID_MASK (0xffull << CHA_VER_VID_SHIFT)
321
322
323#define CHA_VER_MISC_AES_GCM BIT(1 + CHA_VER_MISC_SHIFT)
324
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331
332
333#define CHA_NUM_MS_DECONUM_SHIFT 24
334#define CHA_NUM_MS_DECONUM_MASK (0xfull << CHA_NUM_MS_DECONUM_SHIFT)
335
336
337
338
339
340
341
342#define CHA_ID_LS_AES_SHIFT 0
343#define CHA_ID_LS_AES_MASK (0xfull << CHA_ID_LS_AES_SHIFT)
344
345#define CHA_ID_LS_DES_SHIFT 4
346#define CHA_ID_LS_DES_MASK (0xfull << CHA_ID_LS_DES_SHIFT)
347
348#define CHA_ID_LS_ARC4_SHIFT 8
349#define CHA_ID_LS_ARC4_MASK (0xfull << CHA_ID_LS_ARC4_SHIFT)
350
351#define CHA_ID_LS_MD_SHIFT 12
352#define CHA_ID_LS_MD_MASK (0xfull << CHA_ID_LS_MD_SHIFT)
353
354#define CHA_ID_LS_RNG_SHIFT 16
355#define CHA_ID_LS_RNG_MASK (0xfull << CHA_ID_LS_RNG_SHIFT)
356
357#define CHA_ID_LS_SNW8_SHIFT 20
358#define CHA_ID_LS_SNW8_MASK (0xfull << CHA_ID_LS_SNW8_SHIFT)
359
360#define CHA_ID_LS_KAS_SHIFT 24
361#define CHA_ID_LS_KAS_MASK (0xfull << CHA_ID_LS_KAS_SHIFT)
362
363#define CHA_ID_LS_PK_SHIFT 28
364#define CHA_ID_LS_PK_MASK (0xfull << CHA_ID_LS_PK_SHIFT)
365
366#define CHA_ID_MS_CRC_SHIFT 0
367#define CHA_ID_MS_CRC_MASK (0xfull << CHA_ID_MS_CRC_SHIFT)
368
369#define CHA_ID_MS_SNW9_SHIFT 4
370#define CHA_ID_MS_SNW9_MASK (0xfull << CHA_ID_MS_SNW9_SHIFT)
371
372#define CHA_ID_MS_DECO_SHIFT 24
373#define CHA_ID_MS_DECO_MASK (0xfull << CHA_ID_MS_DECO_SHIFT)
374
375#define CHA_ID_MS_JR_SHIFT 28
376#define CHA_ID_MS_JR_MASK (0xfull << CHA_ID_MS_JR_SHIFT)
377
378
379#define CHA_VER_VID_AES_LP 0x3ull
380#define CHA_VER_VID_AES_HP 0x4ull
381#define CHA_VER_VID_MD_LP256 0x0ull
382#define CHA_VER_VID_MD_LP512 0x1ull
383#define CHA_VER_VID_MD_HP 0x2ull
384
385struct sec_vid {
386 u16 ip_id;
387 u8 maj_rev;
388 u8 min_rev;
389};
390
391struct caam_perfmon {
392
393 u64 req_dequeued;
394 u64 ob_enc_req;
395 u64 ib_dec_req;
396 u64 ob_enc_bytes;
397 u64 ob_prot_bytes;
398 u64 ib_dec_bytes;
399 u64 ib_valid_bytes;
400 u64 rsvd[13];
401
402
403 u32 cha_rev_ms;
404 u32 cha_rev_ls;
405#define CTPR_MS_QI_SHIFT 25
406#define CTPR_MS_QI_MASK (0x1ull << CTPR_MS_QI_SHIFT)
407#define CTPR_MS_PS BIT(17)
408#define CTPR_MS_DPAA2 BIT(13)
409#define CTPR_MS_VIRT_EN_INCL 0x00000001
410#define CTPR_MS_VIRT_EN_POR 0x00000002
411#define CTPR_MS_PG_SZ_MASK 0x10
412#define CTPR_MS_PG_SZ_SHIFT 4
413 u32 comp_parms_ms;
414 u32 comp_parms_ls;
415 u64 rsvd1[2];
416
417
418 u64 faultaddr;
419 u32 faultliodn;
420 u32 faultdetail;
421 u32 rsvd2;
422#define CSTA_PLEND BIT(10)
423#define CSTA_ALT_PLEND BIT(18)
424 u32 status;
425 u64 rsvd3;
426
427
428 u32 rtic_id;
429#define CCBVID_ERA_MASK 0xff000000
430#define CCBVID_ERA_SHIFT 24
431 u32 ccb_id;
432 u32 cha_id_ms;
433 u32 cha_id_ls;
434 u32 cha_num_ms;
435 u32 cha_num_ls;
436#define SECVID_MS_IPID_MASK 0xffff0000
437#define SECVID_MS_IPID_SHIFT 16
438#define SECVID_MS_MAJ_REV_MASK 0x0000ff00
439#define SECVID_MS_MAJ_REV_SHIFT 8
440 u32 caam_id_ms;
441 u32 caam_id_ls;
442};
443
444
445#define MSTRID_LOCK_LIODN 0x80000000
446#define MSTRID_LOCK_MAKETRUSTED 0x00010000
447
448#define MSTRID_LIODN_MASK 0x0fff
449struct masterid {
450 u32 liodn_ms;
451 u32 liodn_ls;
452};
453
454
455struct partid {
456 u32 rsvd1;
457 u32 pidr;
458};
459
460
461
462struct rngtst {
463 u32 mode;
464 u32 rsvd1[3];
465 u32 reset;
466 u32 rsvd2[3];
467 u32 status;
468 u32 rsvd3;
469 u32 errstat;
470 u32 rsvd4;
471 u32 errctl;
472 u32 rsvd5;
473 u32 entropy;
474 u32 rsvd6[15];
475 u32 verifctl;
476 u32 rsvd7;
477 u32 verifstat;
478 u32 rsvd8;
479 u32 verifdata;
480 u32 rsvd9;
481 u32 xkey;
482 u32 rsvd10;
483 u32 oscctctl;
484 u32 rsvd11;
485 u32 oscct;
486 u32 rsvd12;
487 u32 oscctstat;
488 u32 rsvd13[2];
489 u32 ofifo[4];
490 u32 rsvd14[15];
491};
492
493
494struct rng4tst {
495#define RTMCTL_ACC BIT(5)
496#define RTMCTL_PRGM BIT(16)
497#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_SC 0
498
499
500#define RTMCTL_SAMP_MODE_RAW_ES_SC 1
501
502
503#define RTMCTL_SAMP_MODE_VON_NEUMANN_ES_RAW_SC 2
504
505
506#define RTMCTL_SAMP_MODE_INVALID 3
507 u32 rtmctl;
508 u32 rtscmisc;
509 u32 rtpkrrng;
510 union {
511 u32 rtpkrmax;
512 u32 rtpkrsq;
513 };
514#define RTSDCTL_ENT_DLY_SHIFT 16
515#define RTSDCTL_ENT_DLY_MASK (0xffff << RTSDCTL_ENT_DLY_SHIFT)
516#define RTSDCTL_ENT_DLY_MIN 3200
517#define RTSDCTL_ENT_DLY_MAX 12800
518 u32 rtsdctl;
519 union {
520 u32 rtsblim;
521 u32 rttotsam;
522 };
523 u32 rtfrqmin;
524#define RTFRQMAX_DISABLE (1 << 20)
525 union {
526 u32 rtfrqmax;
527 u32 rtfrqcnt;
528 };
529 u32 rsvd1[40];
530#define RDSTA_SKVT 0x80000000
531#define RDSTA_SKVN 0x40000000
532#define RDSTA_PR0 BIT(4)
533#define RDSTA_PR1 BIT(5)
534#define RDSTA_IF0 0x00000001
535#define RDSTA_IF1 0x00000002
536#define RDSTA_MASK (RDSTA_PR1 | RDSTA_PR0 | RDSTA_IF1 | RDSTA_IF0)
537 u32 rdsta;
538 u32 rsvd2[15];
539};
540
541
542
543
544
545
546#define KEK_KEY_SIZE 8
547#define TKEK_KEY_SIZE 8
548#define TDSK_KEY_SIZE 8
549
550#define DECO_RESET 1
551#define DECO_RESET_0 (DECO_RESET << 0)
552#define DECO_RESET_1 (DECO_RESET << 1)
553#define DECO_RESET_2 (DECO_RESET << 2)
554#define DECO_RESET_3 (DECO_RESET << 3)
555#define DECO_RESET_4 (DECO_RESET << 4)
556
557struct caam_ctrl {
558
559
560 u32 rsvd1;
561 u32 mcr;
562 u32 rsvd2;
563 u32 scfgr;
564
565
566
567 struct masterid jr_mid[4];
568 u32 rsvd3[11];
569 u32 jrstart;
570 struct masterid rtic_mid[4];
571 u32 rsvd4[5];
572 u32 deco_rsr;
573 u32 rsvd11;
574 u32 deco_rq;
575 struct partid deco_mid[5];
576 u32 rsvd5[22];
577
578
579 u32 deco_avail;
580 u32 deco_reset;
581 u32 rsvd6[182];
582
583
584
585 u32 kek[KEK_KEY_SIZE];
586 u32 tkek[TKEK_KEY_SIZE];
587 u32 tdsk[TDSK_KEY_SIZE];
588 u32 rsvd7[32];
589 u64 sknonce;
590 u32 rsvd8[70];
591
592
593
594 union {
595 struct rngtst rtst[2];
596 struct rng4tst r4tst[2];
597 };
598
599 u32 rsvd9[416];
600
601
602 struct version_regs vreg;
603
604 struct caam_perfmon perfmon;
605};
606
607
608
609
610#define MCFGR_SWRESET 0x80000000
611#define MCFGR_WDENABLE 0x40000000
612#define MCFGR_WDFAIL 0x20000000
613#define MCFGR_DMA_RESET 0x10000000
614#define MCFGR_LONG_PTR 0x00010000
615#define SCFGR_RDBENABLE 0x00000400
616#define SCFGR_VIRT_EN 0x00008000
617#define DECORR_RQD0ENABLE 0x00000001
618#define DECORSR_JR0 0x00000001
619#define DECORSR_VALID 0x80000000
620#define DECORR_DEN0 0x00010000
621
622
623#define MCFGR_ARCACHE_SHIFT 12
624#define MCFGR_ARCACHE_MASK (0xf << MCFGR_ARCACHE_SHIFT)
625#define MCFGR_ARCACHE_BUFF (0x1 << MCFGR_ARCACHE_SHIFT)
626#define MCFGR_ARCACHE_CACH (0x2 << MCFGR_ARCACHE_SHIFT)
627#define MCFGR_ARCACHE_RALL (0x4 << MCFGR_ARCACHE_SHIFT)
628
629
630#define MCFGR_AWCACHE_SHIFT 8
631#define MCFGR_AWCACHE_MASK (0xf << MCFGR_AWCACHE_SHIFT)
632#define MCFGR_AWCACHE_BUFF (0x1 << MCFGR_AWCACHE_SHIFT)
633#define MCFGR_AWCACHE_CACH (0x2 << MCFGR_AWCACHE_SHIFT)
634#define MCFGR_AWCACHE_WALL (0x8 << MCFGR_AWCACHE_SHIFT)
635
636
637#define MCFGR_AXIPIPE_SHIFT 4
638#define MCFGR_AXIPIPE_MASK (0xf << MCFGR_AXIPIPE_SHIFT)
639
640#define MCFGR_AXIPRI 0x00000008
641#define MCFGR_LARGE_BURST 0x00000004
642#define MCFGR_BURST_64 0x00000001
643
644
645#define JRSTART_JR0_START 0x00000001
646#define JRSTART_JR1_START 0x00000002
647#define JRSTART_JR2_START 0x00000004
648#define JRSTART_JR3_START 0x00000008
649
650
651
652
653
654
655struct caam_job_ring {
656
657 u64 inpring_base;
658 u32 rsvd1;
659 u32 inpring_size;
660 u32 rsvd2;
661 u32 inpring_avail;
662 u32 rsvd3;
663 u32 inpring_jobadd;
664
665
666 u64 outring_base;
667 u32 rsvd4;
668 u32 outring_size;
669 u32 rsvd5;
670 u32 outring_rmvd;
671 u32 rsvd6;
672 u32 outring_used;
673
674
675 u32 rsvd7;
676 u32 jroutstatus;
677 u32 rsvd8;
678 u32 jrintstatus;
679 u32 rconfig_hi;
680 u32 rconfig_lo;
681
682
683 u32 rsvd9;
684 u32 inp_rdidx;
685 u32 rsvd10;
686 u32 out_wtidx;
687
688
689 u32 rsvd11;
690 u32 jrcommand;
691
692 u32 rsvd12[900];
693
694
695 struct version_regs vreg;
696
697 struct caam_perfmon perfmon;
698};
699
700#define JR_RINGSIZE_MASK 0x03ff
701
702
703
704
705
706
707#define JRSTA_SSRC_SHIFT 28
708#define JRSTA_SSRC_MASK 0xf0000000
709
710#define JRSTA_SSRC_NONE 0x00000000
711#define JRSTA_SSRC_CCB_ERROR 0x20000000
712#define JRSTA_SSRC_JUMP_HALT_USER 0x30000000
713#define JRSTA_SSRC_DECO 0x40000000
714#define JRSTA_SSRC_QI 0x50000000
715#define JRSTA_SSRC_JRERROR 0x60000000
716#define JRSTA_SSRC_JUMP_HALT_CC 0x70000000
717
718#define JRSTA_DECOERR_JUMP 0x08000000
719#define JRSTA_DECOERR_INDEX_SHIFT 8
720#define JRSTA_DECOERR_INDEX_MASK 0xff00
721#define JRSTA_DECOERR_ERROR_MASK 0x00ff
722
723#define JRSTA_DECOERR_NONE 0x00
724#define JRSTA_DECOERR_LINKLEN 0x01
725#define JRSTA_DECOERR_LINKPTR 0x02
726#define JRSTA_DECOERR_JRCTRL 0x03
727#define JRSTA_DECOERR_DESCCMD 0x04
728#define JRSTA_DECOERR_ORDER 0x05
729#define JRSTA_DECOERR_KEYCMD 0x06
730#define JRSTA_DECOERR_LOADCMD 0x07
731#define JRSTA_DECOERR_STORECMD 0x08
732#define JRSTA_DECOERR_OPCMD 0x09
733#define JRSTA_DECOERR_FIFOLDCMD 0x0a
734#define JRSTA_DECOERR_FIFOSTCMD 0x0b
735#define JRSTA_DECOERR_MOVECMD 0x0c
736#define JRSTA_DECOERR_JUMPCMD 0x0d
737#define JRSTA_DECOERR_MATHCMD 0x0e
738#define JRSTA_DECOERR_SHASHCMD 0x0f
739#define JRSTA_DECOERR_SEQCMD 0x10
740#define JRSTA_DECOERR_DECOINTERNAL 0x11
741#define JRSTA_DECOERR_SHDESCHDR 0x12
742#define JRSTA_DECOERR_HDRLEN 0x13
743#define JRSTA_DECOERR_BURSTER 0x14
744#define JRSTA_DECOERR_DESCSIGNATURE 0x15
745#define JRSTA_DECOERR_DMA 0x16
746#define JRSTA_DECOERR_BURSTFIFO 0x17
747#define JRSTA_DECOERR_JRRESET 0x1a
748#define JRSTA_DECOERR_JOBFAIL 0x1b
749#define JRSTA_DECOERR_DNRERR 0x80
750#define JRSTA_DECOERR_UNDEFPCL 0x81
751#define JRSTA_DECOERR_PDBERR 0x82
752#define JRSTA_DECOERR_ANRPLY_LATE 0x83
753#define JRSTA_DECOERR_ANRPLY_REPLAY 0x84
754#define JRSTA_DECOERR_SEQOVF 0x85
755#define JRSTA_DECOERR_INVSIGN 0x86
756#define JRSTA_DECOERR_DSASIGN 0x87
757
758#define JRSTA_QIERR_ERROR_MASK 0x00ff
759
760#define JRSTA_CCBERR_JUMP 0x08000000
761#define JRSTA_CCBERR_INDEX_MASK 0xff00
762#define JRSTA_CCBERR_INDEX_SHIFT 8
763#define JRSTA_CCBERR_CHAID_MASK 0x00f0
764#define JRSTA_CCBERR_CHAID_SHIFT 4
765#define JRSTA_CCBERR_ERRID_MASK 0x000f
766
767#define JRSTA_CCBERR_CHAID_AES (0x01 << JRSTA_CCBERR_CHAID_SHIFT)
768#define JRSTA_CCBERR_CHAID_DES (0x02 << JRSTA_CCBERR_CHAID_SHIFT)
769#define JRSTA_CCBERR_CHAID_ARC4 (0x03 << JRSTA_CCBERR_CHAID_SHIFT)
770#define JRSTA_CCBERR_CHAID_MD (0x04 << JRSTA_CCBERR_CHAID_SHIFT)
771#define JRSTA_CCBERR_CHAID_RNG (0x05 << JRSTA_CCBERR_CHAID_SHIFT)
772#define JRSTA_CCBERR_CHAID_SNOW (0x06 << JRSTA_CCBERR_CHAID_SHIFT)
773#define JRSTA_CCBERR_CHAID_KASUMI (0x07 << JRSTA_CCBERR_CHAID_SHIFT)
774#define JRSTA_CCBERR_CHAID_PK (0x08 << JRSTA_CCBERR_CHAID_SHIFT)
775#define JRSTA_CCBERR_CHAID_CRC (0x09 << JRSTA_CCBERR_CHAID_SHIFT)
776
777#define JRSTA_CCBERR_ERRID_NONE 0x00
778#define JRSTA_CCBERR_ERRID_MODE 0x01
779#define JRSTA_CCBERR_ERRID_DATASIZ 0x02
780#define JRSTA_CCBERR_ERRID_KEYSIZ 0x03
781#define JRSTA_CCBERR_ERRID_PKAMEMSZ 0x04
782#define JRSTA_CCBERR_ERRID_PKBMEMSZ 0x05
783#define JRSTA_CCBERR_ERRID_SEQUENCE 0x06
784#define JRSTA_CCBERR_ERRID_PKDIVZRO 0x07
785#define JRSTA_CCBERR_ERRID_PKMODEVN 0x08
786#define JRSTA_CCBERR_ERRID_KEYPARIT 0x09
787#define JRSTA_CCBERR_ERRID_ICVCHK 0x0a
788#define JRSTA_CCBERR_ERRID_HARDWARE 0x0b
789#define JRSTA_CCBERR_ERRID_CCMAAD 0x0c
790#define JRSTA_CCBERR_ERRID_INVCHA 0x0f
791
792#define JRINT_ERR_INDEX_MASK 0x3fff0000
793#define JRINT_ERR_INDEX_SHIFT 16
794#define JRINT_ERR_TYPE_MASK 0xf00
795#define JRINT_ERR_TYPE_SHIFT 8
796#define JRINT_ERR_HALT_MASK 0xc
797#define JRINT_ERR_HALT_SHIFT 2
798#define JRINT_ERR_HALT_INPROGRESS 0x4
799#define JRINT_ERR_HALT_COMPLETE 0x8
800#define JRINT_JR_ERROR 0x02
801#define JRINT_JR_INT 0x01
802
803#define JRINT_ERR_TYPE_WRITE 1
804#define JRINT_ERR_TYPE_BAD_INPADDR 3
805#define JRINT_ERR_TYPE_BAD_OUTADDR 4
806#define JRINT_ERR_TYPE_INV_INPWRT 5
807#define JRINT_ERR_TYPE_INV_OUTWRT 6
808#define JRINT_ERR_TYPE_RESET 7
809#define JRINT_ERR_TYPE_REMOVE_OFL 8
810#define JRINT_ERR_TYPE_ADD_OFL 9
811
812#define JRCFG_SOE 0x04
813#define JRCFG_ICEN 0x02
814#define JRCFG_IMSK 0x01
815#define JRCFG_ICDCT_SHIFT 8
816#define JRCFG_ICTT_SHIFT 16
817
818#define JRCR_RESET 0x01
819
820
821
822
823
824
825struct rtic_element {
826 u64 address;
827 u32 rsvd;
828 u32 length;
829};
830
831struct rtic_block {
832 struct rtic_element element[2];
833};
834
835struct rtic_memhash {
836 u32 memhash_be[32];
837 u32 memhash_le[32];
838};
839
840struct caam_assurance {
841
842 u32 rsvd1;
843 u32 status;
844 u32 rsvd2;
845 u32 cmd;
846 u32 rsvd3;
847 u32 ctrl;
848 u32 rsvd4;
849 u32 throttle;
850 u32 rsvd5[2];
851 u64 watchdog;
852 u32 rsvd6;
853 u32 rend;
854 u32 rsvd7[50];
855
856
857 struct rtic_block memblk[4];
858 u32 rsvd8[32];
859
860
861 struct rtic_memhash hash[4];
862 u32 rsvd_3[640];
863};
864
865
866
867
868
869
870struct caam_queue_if {
871 u32 qi_control_hi;
872 u32 qi_control_lo;
873 u32 rsvd1;
874 u32 qi_status;
875 u32 qi_deq_cfg_hi;
876 u32 qi_deq_cfg_lo;
877 u32 qi_enq_cfg_hi;
878 u32 qi_enq_cfg_lo;
879 u32 rsvd2[1016];
880};
881
882
883#define QICTL_DQEN 0x01
884#define QICTL_STOP 0x02
885#define QICTL_SOE 0x04
886
887
888#define QICTL_MBSI 0x01
889#define QICTL_MHWSI 0x02
890#define QICTL_MWSI 0x04
891#define QICTL_MDWSI 0x08
892#define QICTL_CBSI 0x10
893#define QICTL_CHWSI 0x20
894#define QICTL_CWSI 0x40
895#define QICTL_CDWSI 0x80
896#define QICTL_MBSO 0x0100
897#define QICTL_MHWSO 0x0200
898#define QICTL_MWSO 0x0400
899#define QICTL_MDWSO 0x0800
900#define QICTL_CBSO 0x1000
901#define QICTL_CHWSO 0x2000
902#define QICTL_CWSO 0x4000
903#define QICTL_CDWSO 0x8000
904#define QICTL_DMBS 0x010000
905#define QICTL_EPO 0x020000
906
907
908#define QISTA_PHRDERR 0x01
909#define QISTA_CFRDERR 0x02
910#define QISTA_OFWRERR 0x04
911#define QISTA_BPDERR 0x08
912#define QISTA_BTSERR 0x10
913#define QISTA_CFWRERR 0x20
914#define QISTA_STOPD 0x80000000
915
916
917struct deco_sg_table {
918 u64 addr;
919 u32 elen;
920 u32 bpid_offset;
921};
922
923
924
925
926
927
928
929
930
931
932struct caam_deco {
933 u32 rsvd1;
934 u32 cls1_mode;
935 u32 rsvd2;
936 u32 cls1_keysize;
937 u32 cls1_datasize_hi;
938 u32 cls1_datasize_lo;
939 u32 rsvd3;
940 u32 cls1_icvsize;
941 u32 rsvd4[5];
942 u32 cha_ctrl;
943 u32 rsvd5;
944 u32 irq_crtl;
945 u32 rsvd6;
946 u32 clr_written;
947 u32 ccb_status_hi;
948 u32 ccb_status_lo;
949 u32 rsvd7[3];
950 u32 aad_size;
951 u32 rsvd8;
952 u32 cls1_iv_size;
953 u32 rsvd9[7];
954 u32 pkha_a_size;
955 u32 rsvd10;
956 u32 pkha_b_size;
957 u32 rsvd11;
958 u32 pkha_n_size;
959 u32 rsvd12;
960 u32 pkha_e_size;
961 u32 rsvd13[24];
962 u32 cls1_ctx[16];
963 u32 rsvd14[48];
964 u32 cls1_key[8];
965 u32 rsvd15[121];
966 u32 cls2_mode;
967 u32 rsvd16;
968 u32 cls2_keysize;
969 u32 cls2_datasize_hi;
970 u32 cls2_datasize_lo;
971 u32 rsvd17;
972 u32 cls2_icvsize;
973 u32 rsvd18[56];
974 u32 cls2_ctx[18];
975 u32 rsvd19[46];
976 u32 cls2_key[32];
977 u32 rsvd20[84];
978 u32 inp_infofifo_hi;
979 u32 inp_infofifo_lo;
980 u32 rsvd21[2];
981 u64 inp_datafifo;
982 u32 rsvd22[2];
983 u64 out_datafifo;
984 u32 rsvd23[2];
985 u32 jr_ctl_hi;
986 u32 jr_ctl_lo;
987 u64 jr_descaddr;
988#define DECO_OP_STATUS_HI_ERR_MASK 0xF00000FF
989 u32 op_status_hi;
990 u32 op_status_lo;
991 u32 rsvd24[2];
992 u32 liodn;
993 u32 td_liodn;
994 u32 rsvd26[6];
995 u64 math[4];
996 u32 rsvd27[8];
997 struct deco_sg_table gthr_tbl[4];
998 u32 rsvd28[16];
999 struct deco_sg_table sctr_tbl[4];
1000 u32 rsvd29[48];
1001 u32 descbuf[64];
1002 u32 rscvd30[193];
1003#define DESC_DBG_DECO_STAT_VALID 0x80000000
1004#define DESC_DBG_DECO_STAT_MASK 0x00F00000
1005#define DESC_DBG_DECO_STAT_SHIFT 20
1006 u32 desc_dbg;
1007 u32 rsvd31[13];
1008#define DESC_DER_DECO_STAT_MASK 0x000F0000
1009#define DESC_DER_DECO_STAT_SHIFT 16
1010 u32 dbg_exec;
1011 u32 rsvd32[112];
1012};
1013
1014#define DECO_STAT_HOST_ERR 0xD
1015
1016#define DECO_JQCR_WHL 0x20000000
1017#define DECO_JQCR_FOUR 0x10000000
1018
1019#define JR_BLOCK_NUMBER 1
1020#define ASSURE_BLOCK_NUMBER 6
1021#define QI_BLOCK_NUMBER 7
1022#define DECO_BLOCK_NUMBER 8
1023#define PG_SIZE_4K 0x1000
1024#define PG_SIZE_64K 0x10000
1025#endif
1026