LXR linux/drivers/crypto/cavium/cpt/cptpf.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (C) 2016 Cavium, Inc.
   4 */
   5
   6#ifndef __CPTPF_H
   7#define __CPTPF_H
   8
   9#include "cpt_common.h"
  10
  11#define CSR_DELAY 30
  12#define CPT_MAX_CORE_GROUPS 8
  13#define CPT_MAX_SE_CORES 10
  14#define CPT_MAX_AE_CORES 6
  15#define CPT_MAX_TOTAL_CORES (CPT_MAX_SE_CORES + CPT_MAX_AE_CORES)
  16#define CPT_MAX_VF_NUM 16
  17#define CPT_PF_MSIX_VECTORS 3
  18#define CPT_PF_INT_VEC_E_MBOXX(a) (0x02 + (a))
  19#define CPT_UCODE_VERSION_SZ 32
  20struct cpt_device;
  21
  22struct microcode {
  23        u8 is_mc_valid;
  24        u8 is_ae;
  25        u8 group;
  26        u8 num_cores;
  27        u32 code_size;
  28        u64 core_mask;
  29        u8 version[CPT_UCODE_VERSION_SZ];
  30        /* Base info */
  31        dma_addr_t phys_base;
  32        void *code;
  33};
  34
  35struct cpt_vf_info {
  36        u8 state;
  37        u8 priority;
  38        u8 id;
  39        u32 qlen;
  40};
  41
  42/**
  43 * cpt device structure
  44 */
  45struct cpt_device {
  46        u16 flags;      /* Flags to hold device status bits */
  47        u8 num_vf_en; /* Number of VFs enabled (0...CPT_MAX_VF_NUM) */
  48        struct cpt_vf_info vfinfo[CPT_MAX_VF_NUM]; /* Per VF info */
  49
  50        void __iomem *reg_base; /* Register start address */
  51        struct pci_dev *pdev; /* pci device handle */
  52
  53        struct microcode mcode[CPT_MAX_CORE_GROUPS];
  54        u8 next_mc_idx; /* next microcode index */
  55        u8 next_group;
  56        u8 max_se_cores;
  57        u8 max_ae_cores;
  58};
  59
  60void cpt_mbox_intr_handler(struct cpt_device *cpt, int mbx);
  61#endif /* __CPTPF_H */
  62