LXR linux/drivers/crypto/marvell/octeontx2/otx2_cpt

   1/* SPDX-License-Identifier: GPL-2.0-only
   2 * Copyright (C) 2020 Marvell.
   3 */
   4
   5#ifndef __OTX2_CPT_COMMON_H
   6#define __OTX2_CPT_COMMON_H
   7
   8#include <linux/pci.h>
   9#include <linux/types.h>
  10#include <linux/module.h>
  11#include <linux/delay.h>
  12#include <linux/crypto.h>
  13#include "otx2_cpt_hw_types.h"
  14#include "rvu.h"
  15#include "mbox.h"
  16
  17#define OTX2_CPT_MAX_VFS_NUM 128
  18#define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \
  19                (((blk) << 20) | ((slot) << 12) | (offs))
  20#define OTX2_CPT_RVU_PFFUNC(pf, func)   \
  21                ((((pf) & RVU_PFVF_PF_MASK) << RVU_PFVF_PF_SHIFT) | \
  22                (((func) & RVU_PFVF_FUNC_MASK) << RVU_PFVF_FUNC_SHIFT))
  23
  24#define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF
  25#define OTX2_CPT_NAME_LENGTH 64
  26#define OTX2_CPT_DMA_MINALIGN 128
  27
  28/* HW capability flags */
  29#define CN10K_MBOX  0
  30#define CN10K_LMTST 1
  31
  32#define BAD_OTX2_CPT_ENG_TYPE OTX2_CPT_MAX_ENG_TYPES
  33
  34enum otx2_cpt_eng_type {
  35        OTX2_CPT_AE_TYPES = 1,
  36        OTX2_CPT_SE_TYPES = 2,
  37        OTX2_CPT_IE_TYPES = 3,
  38        OTX2_CPT_MAX_ENG_TYPES,
  39};
  40
  41/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
  42#define MBOX_MSG_GET_ENG_GRP_NUM        0xBFF
  43#define MBOX_MSG_GET_CAPS               0xBFD
  44#define MBOX_MSG_GET_KVF_LIMITS         0xBFC
  45
  46/*
  47 * Message request and response to get engine group number
  48 * which has attached a given type of engines (SE, AE, IE)
  49 * This messages are only used between CPT PF <=> CPT VF
  50 */
  51struct otx2_cpt_egrp_num_msg {
  52        struct mbox_msghdr hdr;
  53        u8 eng_type;
  54};
  55
  56struct otx2_cpt_egrp_num_rsp {
  57        struct mbox_msghdr hdr;
  58        u8 eng_type;
  59        u8 eng_grp_num;
  60};
  61
  62/*
  63 * Message request and response to get kernel crypto limits
  64 * This messages are only used between CPT PF <-> CPT VF
  65 */
  66struct otx2_cpt_kvf_limits_msg {
  67        struct mbox_msghdr hdr;
  68};
  69
  70struct otx2_cpt_kvf_limits_rsp {
  71        struct mbox_msghdr hdr;
  72        u8 kvf_limits;
  73};
  74
  75/* CPT HW capabilities */
  76union otx2_cpt_eng_caps {
  77        u64 u;
  78        struct {
  79                u64 reserved_0_4:5;
  80                u64 mul:1;
  81                u64 sha1_sha2:1;
  82                u64 chacha20:1;
  83                u64 zuc_snow3g:1;
  84                u64 sha3:1;
  85                u64 aes:1;
  86                u64 kasumi:1;
  87                u64 des:1;
  88                u64 crc:1;
  89                u64 reserved_14_63:50;
  90        };
  91};
  92
  93/*
  94 * Message request and response to get HW capabilities for each
  95 * engine type (SE, IE, AE).
  96 * This messages are only used between CPT PF <=> CPT VF
  97 */
  98struct otx2_cpt_caps_msg {
  99        struct mbox_msghdr hdr;
 100};
 101
 102struct otx2_cpt_caps_rsp {
 103        struct mbox_msghdr hdr;
 104        u16 cpt_pf_drv_version;
 105        u8 cpt_revision;
 106        union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
 107};
 108
 109static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot,
 110                                    u64 offs, u64 val)
 111{
 112        writeq_relaxed(val, reg_base +
 113                       OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs));
 114}
 115
 116static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot,
 117                                  u64 offs)
 118{
 119        return readq_relaxed(reg_base +
 120                             OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs));
 121}
 122
 123static inline bool is_dev_otx2(struct pci_dev *pdev)
 124{
 125        if (pdev->device == OTX2_CPT_PCI_PF_DEVICE_ID ||
 126            pdev->device == OTX2_CPT_PCI_VF_DEVICE_ID)
 127                return true;
 128
 129        return false;
 130}
 131
 132static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,
 133                                        unsigned long *cap_flag)
 134{
 135        if (!is_dev_otx2(pdev)) {
 136                __set_bit(CN10K_MBOX, cap_flag);
 137                __set_bit(CN10K_LMTST, cap_flag);
 138        }
 139}
 140
 141
 142int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
 143int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
 144
 145int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox,
 146                                  struct pci_dev *pdev);
 147int otx2_cpt_add_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
 148                             u64 reg, u64 *val, int blkaddr);
 149int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
 150                              u64 reg, u64 val, int blkaddr);
 151int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
 152                         u64 reg, u64 *val, int blkaddr);
 153int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
 154                          u64 reg, u64 val, int blkaddr);
 155struct otx2_cptlfs_info;
 156int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs);
 157int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);
 158int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);
 159
 160#endif /* __OTX2_CPT_COMMON_H */
 161