LXR linux/drivers/crypto/marvell/octeontx2/otx2_cptpf

   1/* SPDX-License-Identifier: GPL-2.0-only
   2 * Copyright (C) 2020 Marvell.
   3 */
   4
   5#ifndef __OTX2_CPTPF_UCODE_H
   6#define __OTX2_CPTPF_UCODE_H
   7
   8#include <linux/pci.h>
   9#include <linux/types.h>
  10#include <linux/module.h>
  11#include "otx2_cpt_hw_types.h"
  12#include "otx2_cpt_common.h"
  13
  14/*
  15 * On OcteonTX2 platform IPSec ucode can use both IE and SE engines therefore
  16 * IE and SE engines can be attached to the same engine group.
  17 */
  18#define OTX2_CPT_MAX_ETYPES_PER_GRP 2
  19
  20/* CPT ucode signature size */
  21#define OTX2_CPT_UCODE_SIGN_LEN     256
  22
  23/* Microcode version string length */
  24#define OTX2_CPT_UCODE_VER_STR_SZ   44
  25
  26/* Maximum number of supported engines/cores on OcteonTX2/CN10K platform */
  27#define OTX2_CPT_MAX_ENGINES        144
  28
  29#define OTX2_CPT_ENGS_BITMASK_LEN   BITS_TO_LONGS(OTX2_CPT_MAX_ENGINES)
  30
  31#define OTX2_CPT_UCODE_SZ           (64 * 1024)
  32
  33/* Microcode types */
  34enum otx2_cpt_ucode_type {
  35        OTX2_CPT_AE_UC_TYPE = 1,  /* AE-MAIN */
  36        OTX2_CPT_SE_UC_TYPE1 = 20,/* SE-MAIN - combination of 21 and 22 */
  37        OTX2_CPT_SE_UC_TYPE2 = 21,/* Fast Path IPSec + AirCrypto */
  38        OTX2_CPT_SE_UC_TYPE3 = 22,/*
  39                                   * Hash + HMAC + FlexiCrypto + RNG +
  40                                   * Full Feature IPSec + AirCrypto + Kasumi
  41                                   */
  42        OTX2_CPT_IE_UC_TYPE1 = 30, /* IE-MAIN - combination of 31 and 32 */
  43        OTX2_CPT_IE_UC_TYPE2 = 31, /* Fast Path IPSec */
  44        OTX2_CPT_IE_UC_TYPE3 = 32, /*
  45                                    * Hash + HMAC + FlexiCrypto + RNG +
  46                                    * Full Future IPSec
  47                                    */
  48};
  49
  50struct otx2_cpt_bitmap {
  51        unsigned long bits[OTX2_CPT_ENGS_BITMASK_LEN];
  52        int size;
  53};
  54
  55struct otx2_cpt_engines {
  56        int type;
  57        int count;
  58};
  59
  60/* Microcode version number */
  61struct otx2_cpt_ucode_ver_num {
  62        u8 nn;
  63        u8 xx;
  64        u8 yy;
  65        u8 zz;
  66};
  67
  68struct otx2_cpt_ucode_hdr {
  69        struct otx2_cpt_ucode_ver_num ver_num;
  70        u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];
  71        __be32 code_length;
  72        u32 padding[3];
  73};
  74
  75struct otx2_cpt_ucode {
  76        u8 ver_str[OTX2_CPT_UCODE_VER_STR_SZ];/*
  77                                               * ucode version in readable
  78                                               * format
  79                                               */
  80        struct otx2_cpt_ucode_ver_num ver_num;/* ucode version number */
  81        char filename[OTX2_CPT_NAME_LENGTH];/* ucode filename */
  82        dma_addr_t dma;         /* phys address of ucode image */
  83        void *va;               /* virt address of ucode image */
  84        u32 size;               /* ucode image size */
  85        int type;               /* ucode image type SE, IE, AE or SE+IE */
  86};
  87
  88struct otx2_cpt_uc_info_t {
  89        struct list_head list;
  90        struct otx2_cpt_ucode ucode;/* microcode information */
  91        const struct firmware *fw;
  92};
  93
  94/* Maximum and current number of engines available for all engine groups */
  95struct otx2_cpt_engs_available {
  96        int max_se_cnt;
  97        int max_ie_cnt;
  98        int max_ae_cnt;
  99        int se_cnt;
 100        int ie_cnt;
 101        int ae_cnt;
 102};
 103
 104/* Engines reserved to an engine group */
 105struct otx2_cpt_engs_rsvd {
 106        int type;       /* engine type */
 107        int count;      /* number of engines attached */
 108        int offset;     /* constant offset of engine type in the bitmap */
 109        unsigned long *bmap;            /* attached engines bitmap */
 110        struct otx2_cpt_ucode *ucode;   /* ucode used by these engines */
 111};
 112
 113struct otx2_cpt_mirror_info {
 114        int is_ena;     /*
 115                         * is mirroring enabled, it is set only for engine
 116                         * group which mirrors another engine group
 117                         */
 118        int idx;        /*
 119                         * index of engine group which is mirrored by this
 120                         * group, set only for engine group which mirrors
 121                         * another group
 122                         */
 123        int ref_count;  /*
 124                         * number of times this engine group is mirrored by
 125                         * other groups, this is set only for engine group
 126                         * which is mirrored by other group(s)
 127                         */
 128};
 129
 130struct otx2_cpt_eng_grp_info {
 131        struct otx2_cpt_eng_grps *g; /* pointer to engine_groups structure */
 132        /* engines attached */
 133        struct otx2_cpt_engs_rsvd engs[OTX2_CPT_MAX_ETYPES_PER_GRP];
 134        /* ucodes information */
 135        struct otx2_cpt_ucode ucode[OTX2_CPT_MAX_ETYPES_PER_GRP];
 136        /* engine group mirroring information */
 137        struct otx2_cpt_mirror_info mirror;
 138        int idx;         /* engine group index */
 139        bool is_enabled; /*
 140                          * is engine group enabled, engine group is enabled
 141                          * when it has engines attached and ucode loaded
 142                          */
 143};
 144
 145struct otx2_cpt_eng_grps {
 146        struct otx2_cpt_eng_grp_info grp[OTX2_CPT_MAX_ENGINE_GROUPS];
 147        struct otx2_cpt_engs_available avail;
 148        void *obj;                      /* device specific data */
 149        int engs_num;                   /* total number of engines supported */
 150        u8 eng_ref_cnt[OTX2_CPT_MAX_ENGINES];/* engines reference count */
 151        bool is_grps_created; /* Is the engine groups are already created */
 152};
 153struct otx2_cptpf_dev;
 154int otx2_cpt_init_eng_grps(struct pci_dev *pdev,
 155                           struct otx2_cpt_eng_grps *eng_grps);
 156void otx2_cpt_cleanup_eng_grps(struct pci_dev *pdev,
 157                               struct otx2_cpt_eng_grps *eng_grps);
 158int otx2_cpt_create_eng_grps(struct otx2_cptpf_dev *cptpf,
 159                             struct otx2_cpt_eng_grps *eng_grps);
 160int otx2_cpt_disable_all_cores(struct otx2_cptpf_dev *cptpf);
 161int otx2_cpt_get_eng_grp(struct otx2_cpt_eng_grps *eng_grps, int eng_type);
 162int otx2_cpt_discover_eng_capabilities(struct otx2_cptpf_dev *cptpf);
 163
 164#endif /* __OTX2_CPTPF_UCODE_H */
 165