linux/drivers/crypto/qat/qat_common/icp_qat_fw_init_admin.h
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   1/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
   2/* Copyright(c) 2014 - 2020 Intel Corporation */
   3#ifndef _ICP_QAT_FW_INIT_ADMIN_H_
   4#define _ICP_QAT_FW_INIT_ADMIN_H_
   5
   6#include "icp_qat_fw.h"
   7
   8enum icp_qat_fw_init_admin_cmd_id {
   9        ICP_QAT_FW_INIT_AE = 0,
  10        ICP_QAT_FW_TRNG_ENABLE = 1,
  11        ICP_QAT_FW_TRNG_DISABLE = 2,
  12        ICP_QAT_FW_CONSTANTS_CFG = 3,
  13        ICP_QAT_FW_STATUS_GET = 4,
  14        ICP_QAT_FW_COUNTERS_GET = 5,
  15        ICP_QAT_FW_LOOPBACK = 6,
  16        ICP_QAT_FW_HEARTBEAT_SYNC = 7,
  17        ICP_QAT_FW_HEARTBEAT_GET = 8
  18};
  19
  20enum icp_qat_fw_init_admin_resp_status {
  21        ICP_QAT_FW_INIT_RESP_STATUS_SUCCESS = 0,
  22        ICP_QAT_FW_INIT_RESP_STATUS_FAIL
  23};
  24
  25struct icp_qat_fw_init_admin_req {
  26        __u16 init_cfg_sz;
  27        __u8 resrvd1;
  28        __u8 cmd_id;
  29        __u32 resrvd2;
  30        __u64 opaque_data;
  31        __u64 init_cfg_ptr;
  32
  33        union {
  34                struct {
  35                        __u16 ibuf_size_in_kb;
  36                        __u16 resrvd3;
  37                };
  38                __u32 idle_filter;
  39        };
  40
  41        __u32 resrvd4;
  42} __packed;
  43
  44struct icp_qat_fw_init_admin_resp {
  45        __u8 flags;
  46        __u8 resrvd1;
  47        __u8 status;
  48        __u8 cmd_id;
  49        union {
  50                __u32 resrvd2;
  51                struct {
  52                        __u16 version_minor_num;
  53                        __u16 version_major_num;
  54                };
  55        };
  56        __u64 opaque_data;
  57        union {
  58                __u32 resrvd3[ICP_QAT_FW_NUM_LONGWORDS_4];
  59                struct {
  60                        __u32 version_patch_num;
  61                        __u8 context_id;
  62                        __u8 ae_id;
  63                        __u16 resrvd4;
  64                        __u64 resrvd5;
  65                };
  66                struct {
  67                        __u64 req_rec_count;
  68                        __u64 resp_sent_count;
  69                };
  70                struct {
  71                        __u16 compression_algos;
  72                        __u16 checksum_algos;
  73                        __u32 deflate_capabilities;
  74                        __u32 resrvd6;
  75                        __u32 lzs_capabilities;
  76                };
  77                struct {
  78                        __u32 cipher_algos;
  79                        __u32 hash_algos;
  80                        __u16 keygen_algos;
  81                        __u16 other;
  82                        __u16 public_key_algos;
  83                        __u16 prime_algos;
  84                };
  85                struct {
  86                        __u64 timestamp;
  87                        __u64 resrvd7;
  88                };
  89                struct {
  90                        __u32 successful_count;
  91                        __u32 unsuccessful_count;
  92                        __u64 resrvd8;
  93                };
  94        };
  95} __packed;
  96
  97#define ICP_QAT_FW_COMN_HEARTBEAT_OK 0
  98#define ICP_QAT_FW_COMN_HEARTBEAT_BLOCKED 1
  99#define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS 0
 100#define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK 0x1
 101#define ICP_QAT_FW_COMN_STATUS_RESRVD_FLD_MASK 0xFE
 102#define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_GET(hdr_t) \
 103        ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(hdr_t.flags)
 104
 105#define ICP_QAT_FW_COMN_HEARTBEAT_HDR_FLAG_SET(hdr_t, val) \
 106        ICP_QAT_FW_COMN_HEARTBEAT_FLAG_SET(hdr_t, val)
 107
 108#define ICP_QAT_FW_COMN_HEARTBEAT_FLAG_GET(flags) \
 109        QAT_FIELD_GET(flags, \
 110                 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_BITPOS, \
 111                 ICP_QAT_FW_COMN_HEARTBEAT_FLAG_MASK)
 112#endif
 113