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9#ifndef _DW_EDMA_V0_REGS_H
10#define _DW_EDMA_V0_REGS_H
11
12#include <linux/dmaengine.h>
13
14#define EDMA_V0_MAX_NR_CH 8
15#define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
16#define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
17#define EDMA_V0_ABORT_INT_MASK GENMASK(23, 16)
18#define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
19#define EDMA_V0_READ_CH_COUNT_MASK GENMASK(19, 16)
20#define EDMA_V0_CH_STATUS_MASK GENMASK(6, 5)
21#define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
22#define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
23
24#define EDMA_V0_CH_ODD_MSI_DATA_MASK GENMASK(31, 16)
25#define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
26
27struct dw_edma_v0_ch_regs {
28 u32 ch_control1;
29 u32 ch_control2;
30 u32 transfer_size;
31 union {
32 u64 reg;
33 struct {
34 u32 lsb;
35 u32 msb;
36 };
37 } sar;
38 union {
39 u64 reg;
40 struct {
41 u32 lsb;
42 u32 msb;
43 };
44 } dar;
45 union {
46 u64 reg;
47 struct {
48 u32 lsb;
49 u32 msb;
50 };
51 } llp;
52} __packed;
53
54struct dw_edma_v0_ch {
55 struct dw_edma_v0_ch_regs wr;
56 u32 padding_1[55];
57 struct dw_edma_v0_ch_regs rd;
58 u32 padding_2[55];
59} __packed;
60
61struct dw_edma_v0_unroll {
62 u32 padding_1;
63 u32 wr_engine_chgroup;
64 u32 rd_engine_chgroup;
65 union {
66 u64 reg;
67 struct {
68 u32 lsb;
69 u32 msb;
70 };
71 } wr_engine_hshake_cnt;
72 u32 padding_2[2];
73 union {
74 u64 reg;
75 struct {
76 u32 lsb;
77 u32 msb;
78 };
79 } rd_engine_hshake_cnt;
80 u32 padding_3[2];
81 u32 wr_ch0_pwr_en;
82 u32 wr_ch1_pwr_en;
83 u32 wr_ch2_pwr_en;
84 u32 wr_ch3_pwr_en;
85 u32 wr_ch4_pwr_en;
86 u32 wr_ch5_pwr_en;
87 u32 wr_ch6_pwr_en;
88 u32 wr_ch7_pwr_en;
89 u32 padding_4[8];
90 u32 rd_ch0_pwr_en;
91 u32 rd_ch1_pwr_en;
92 u32 rd_ch2_pwr_en;
93 u32 rd_ch3_pwr_en;
94 u32 rd_ch4_pwr_en;
95 u32 rd_ch5_pwr_en;
96 u32 rd_ch6_pwr_en;
97 u32 rd_ch7_pwr_en;
98 u32 padding_5[30];
99 struct dw_edma_v0_ch ch[EDMA_V0_MAX_NR_CH];
100} __packed;
101
102struct dw_edma_v0_legacy {
103 u32 viewport_sel;
104 struct dw_edma_v0_ch_regs ch;
105} __packed;
106
107struct dw_edma_v0_regs {
108
109 u32 ctrl_data_arb_prior;
110 u32 padding_1;
111 u32 ctrl;
112 u32 wr_engine_en;
113 u32 wr_doorbell;
114 u32 padding_2;
115 union {
116 u64 reg;
117 struct {
118 u32 lsb;
119 u32 msb;
120 };
121 } wr_ch_arb_weight;
122 u32 padding_3[3];
123 u32 rd_engine_en;
124 u32 rd_doorbell;
125 u32 padding_4;
126 union {
127 u64 reg;
128 struct {
129 u32 lsb;
130 u32 msb;
131 };
132 } rd_ch_arb_weight;
133 u32 padding_5[3];
134
135 u32 wr_int_status;
136 u32 padding_6;
137 u32 wr_int_mask;
138 u32 wr_int_clear;
139 u32 wr_err_status;
140 union {
141 u64 reg;
142 struct {
143 u32 lsb;
144 u32 msb;
145 };
146 } wr_done_imwr;
147 union {
148 u64 reg;
149 struct {
150 u32 lsb;
151 u32 msb;
152 };
153 } wr_abort_imwr;
154 u32 wr_ch01_imwr_data;
155 u32 wr_ch23_imwr_data;
156 u32 wr_ch45_imwr_data;
157 u32 wr_ch67_imwr_data;
158 u32 padding_7[4];
159 u32 wr_linked_list_err_en;
160 u32 padding_8[3];
161 u32 rd_int_status;
162 u32 padding_9;
163 u32 rd_int_mask;
164 u32 rd_int_clear;
165 u32 padding_10;
166 union {
167 u64 reg;
168 struct {
169 u32 lsb;
170 u32 msb;
171 };
172 } rd_err_status;
173 u32 padding_11[2];
174 u32 rd_linked_list_err_en;
175 u32 padding_12;
176 union {
177 u64 reg;
178 struct {
179 u32 lsb;
180 u32 msb;
181 };
182 } rd_done_imwr;
183 union {
184 u64 reg;
185 struct {
186 u32 lsb;
187 u32 msb;
188 };
189 } rd_abort_imwr;
190 u32 rd_ch01_imwr_data;
191 u32 rd_ch23_imwr_data;
192 u32 rd_ch45_imwr_data;
193 u32 rd_ch67_imwr_data;
194 u32 padding_13[4];
195
196 union dw_edma_v0_type {
197 struct dw_edma_v0_legacy legacy;
198 struct dw_edma_v0_unroll unroll;
199 } type;
200} __packed;
201
202struct dw_edma_v0_lli {
203 u32 control;
204 u32 transfer_size;
205 union {
206 u64 reg;
207 struct {
208 u32 lsb;
209 u32 msb;
210 };
211 } sar;
212 union {
213 u64 reg;
214 struct {
215 u32 lsb;
216 u32 msb;
217 };
218 } dar;
219} __packed;
220
221struct dw_edma_v0_llp {
222 u32 control;
223 u32 reserved;
224 union {
225 u64 reg;
226 struct {
227 u32 lsb;
228 u32 msb;
229 };
230 } llp;
231} __packed;
232
233#endif
234
