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12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/pci.h>
15#include <linux/pci_ids.h>
16#include <linux/edac.h>
17#include "edac_module.h"
18
19#define EDAC_MOD_STR "i3000_edac"
20
21#define I3000_RANKS 8
22#define I3000_RANKS_PER_CHANNEL 4
23#define I3000_CHANNELS 2
24
25
26
27#define I3000_MCHBAR 0x44
28#define I3000_MCHBAR_MASK 0xffffc000
29#define I3000_MMR_WINDOW_SIZE 16384
30
31#define I3000_EDEAP 0x70
32
33
34
35
36#define I3000_DEAP 0x58
37
38
39
40
41
42#define I3000_DEAP_GRAIN (1 << 7)
43
44
45
46
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49
50
51static inline unsigned long deap_pfn(u8 edeap, u32 deap)
52{
53 deap >>= PAGE_SHIFT;
54 deap |= (edeap & 1) << (32 - PAGE_SHIFT);
55 return deap;
56}
57
58static inline unsigned long deap_offset(u32 deap)
59{
60 return deap & ~(I3000_DEAP_GRAIN - 1) & ~PAGE_MASK;
61}
62
63static inline int deap_channel(u32 deap)
64{
65 return deap & 1;
66}
67
68#define I3000_DERRSYN 0x5c
69
70
71
72
73#define I3000_ERRSTS 0xc8
74
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84
85#define I3000_ERRSTS_BITS 0x0b03
86#define I3000_ERRSTS_UE 0x0002
87#define I3000_ERRSTS_CE 0x0001
88
89#define I3000_ERRCMD 0xca
90
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107
108#define I3000_DRB_SHIFT 25
109
110#define I3000_C0DRB 0x100
111
112
113
114#define I3000_C1DRB 0x180
115
116
117
118
119#define I3000_C0DRA 0x108
120
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133
134
135#define I3000_C1DRA 0x188
136
137static inline unsigned char odd_rank_attrib(unsigned char dra)
138{
139 return (dra & 0x70) >> 4;
140}
141
142static inline unsigned char even_rank_attrib(unsigned char dra)
143{
144 return dra & 0x07;
145}
146
147#define I3000_C0DRC0 0x120
148
149
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155
156
157
158
159#define I3000_C0DRC1 0x124
160
161
162
163
164
165enum i3000p_chips {
166 I3000 = 0,
167};
168
169struct i3000_dev_info {
170 const char *ctl_name;
171};
172
173struct i3000_error_info {
174 u16 errsts;
175 u8 derrsyn;
176 u8 edeap;
177 u32 deap;
178 u16 errsts2;
179};
180
181static const struct i3000_dev_info i3000_devs[] = {
182 [I3000] = {
183 .ctl_name = "i3000"},
184};
185
186static struct pci_dev *mci_pdev;
187static int i3000_registered = 1;
188static struct edac_pci_ctl_info *i3000_pci;
189
190static void i3000_get_error_info(struct mem_ctl_info *mci,
191 struct i3000_error_info *info)
192{
193 struct pci_dev *pdev;
194
195 pdev = to_pci_dev(mci->pdev);
196
197
198
199
200
201
202 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts);
203 if (!(info->errsts & I3000_ERRSTS_BITS))
204 return;
205 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
206 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
207 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
208 pci_read_config_word(pdev, I3000_ERRSTS, &info->errsts2);
209
210
211
212
213
214
215
216 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
217 pci_read_config_byte(pdev, I3000_EDEAP, &info->edeap);
218 pci_read_config_dword(pdev, I3000_DEAP, &info->deap);
219 pci_read_config_byte(pdev, I3000_DERRSYN, &info->derrsyn);
220 }
221
222
223
224
225
226 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
227 I3000_ERRSTS_BITS);
228}
229
230static int i3000_process_error_info(struct mem_ctl_info *mci,
231 struct i3000_error_info *info,
232 int handle_errors)
233{
234 int row, multi_chan, channel;
235 unsigned long pfn, offset;
236
237 multi_chan = mci->csrows[0]->nr_channels - 1;
238
239 if (!(info->errsts & I3000_ERRSTS_BITS))
240 return 0;
241
242 if (!handle_errors)
243 return 1;
244
245 if ((info->errsts ^ info->errsts2) & I3000_ERRSTS_BITS) {
246 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
247 -1, -1, -1,
248 "UE overwrote CE", "");
249 info->errsts = info->errsts2;
250 }
251
252 pfn = deap_pfn(info->edeap, info->deap);
253 offset = deap_offset(info->deap);
254 channel = deap_channel(info->deap);
255
256 row = edac_mc_find_csrow_by_page(mci, pfn);
257
258 if (info->errsts & I3000_ERRSTS_UE)
259 edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1,
260 pfn, offset, 0,
261 row, -1, -1,
262 "i3000 UE", "");
263 else
264 edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1,
265 pfn, offset, info->derrsyn,
266 row, multi_chan ? channel : 0, -1,
267 "i3000 CE", "");
268
269 return 1;
270}
271
272static void i3000_check(struct mem_ctl_info *mci)
273{
274 struct i3000_error_info info;
275
276 i3000_get_error_info(mci, &info);
277 i3000_process_error_info(mci, &info, 1);
278}
279
280static int i3000_is_interleaved(const unsigned char *c0dra,
281 const unsigned char *c1dra,
282 const unsigned char *c0drb,
283 const unsigned char *c1drb)
284{
285 int i;
286
287
288
289
290
291 for (i = 0; i < I3000_RANKS_PER_CHANNEL / 2; i++)
292 if (odd_rank_attrib(c0dra[i]) != odd_rank_attrib(c1dra[i]) ||
293 even_rank_attrib(c0dra[i]) !=
294 even_rank_attrib(c1dra[i]))
295 return 0;
296
297
298
299
300
301 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++)
302 if (c0drb[i] != c1drb[i])
303 return 0;
304
305 return 1;
306}
307
308static int i3000_probe1(struct pci_dev *pdev, int dev_idx)
309{
310 int rc;
311 int i, j;
312 struct mem_ctl_info *mci = NULL;
313 struct edac_mc_layer layers[2];
314 unsigned long last_cumul_size, nr_pages;
315 int interleaved, nr_channels;
316 unsigned char dra[I3000_RANKS / 2], drb[I3000_RANKS];
317 unsigned char *c0dra = dra, *c1dra = &dra[I3000_RANKS_PER_CHANNEL / 2];
318 unsigned char *c0drb = drb, *c1drb = &drb[I3000_RANKS_PER_CHANNEL];
319 unsigned long mchbar;
320 void __iomem *window;
321
322 edac_dbg(0, "MC:\n");
323
324 pci_read_config_dword(pdev, I3000_MCHBAR, (u32 *) & mchbar);
325 mchbar &= I3000_MCHBAR_MASK;
326 window = ioremap(mchbar, I3000_MMR_WINDOW_SIZE);
327 if (!window) {
328 printk(KERN_ERR "i3000: cannot map mmio space at 0x%lx\n",
329 mchbar);
330 return -ENODEV;
331 }
332
333 c0dra[0] = readb(window + I3000_C0DRA + 0);
334 c0dra[1] = readb(window + I3000_C0DRA + 1);
335 c1dra[0] = readb(window + I3000_C1DRA + 0);
336 c1dra[1] = readb(window + I3000_C1DRA + 1);
337
338 for (i = 0; i < I3000_RANKS_PER_CHANNEL; i++) {
339 c0drb[i] = readb(window + I3000_C0DRB + i);
340 c1drb[i] = readb(window + I3000_C1DRB + i);
341 }
342
343 iounmap(window);
344
345
346
347
348
349
350
351
352
353 interleaved = i3000_is_interleaved(c0dra, c1dra, c0drb, c1drb);
354 nr_channels = interleaved ? 2 : 1;
355
356 layers[0].type = EDAC_MC_LAYER_CHIP_SELECT;
357 layers[0].size = I3000_RANKS / nr_channels;
358 layers[0].is_virt_csrow = true;
359 layers[1].type = EDAC_MC_LAYER_CHANNEL;
360 layers[1].size = nr_channels;
361 layers[1].is_virt_csrow = false;
362 mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, 0);
363 if (!mci)
364 return -ENOMEM;
365
366 edac_dbg(3, "MC: init mci\n");
367
368 mci->pdev = &pdev->dev;
369 mci->mtype_cap = MEM_FLAG_DDR2;
370
371 mci->edac_ctl_cap = EDAC_FLAG_SECDED;
372 mci->edac_cap = EDAC_FLAG_SECDED;
373
374 mci->mod_name = EDAC_MOD_STR;
375 mci->ctl_name = i3000_devs[dev_idx].ctl_name;
376 mci->dev_name = pci_name(pdev);
377 mci->edac_check = i3000_check;
378 mci->ctl_page_to_phys = NULL;
379
380
381
382
383
384
385
386
387
388
389 for (last_cumul_size = i = 0; i < mci->nr_csrows; i++) {
390 u8 value;
391 u32 cumul_size;
392 struct csrow_info *csrow = mci->csrows[i];
393
394 value = drb[i];
395 cumul_size = value << (I3000_DRB_SHIFT - PAGE_SHIFT);
396 if (interleaved)
397 cumul_size <<= 1;
398 edac_dbg(3, "MC: (%d) cumul_size 0x%x\n", i, cumul_size);
399 if (cumul_size == last_cumul_size)
400 continue;
401
402 csrow->first_page = last_cumul_size;
403 csrow->last_page = cumul_size - 1;
404 nr_pages = cumul_size - last_cumul_size;
405 last_cumul_size = cumul_size;
406
407 for (j = 0; j < nr_channels; j++) {
408 struct dimm_info *dimm = csrow->channels[j]->dimm;
409
410 dimm->nr_pages = nr_pages / nr_channels;
411 dimm->grain = I3000_DEAP_GRAIN;
412 dimm->mtype = MEM_DDR2;
413 dimm->dtype = DEV_UNKNOWN;
414 dimm->edac_mode = EDAC_UNKNOWN;
415 }
416 }
417
418
419
420
421
422 pci_write_bits16(pdev, I3000_ERRSTS, I3000_ERRSTS_BITS,
423 I3000_ERRSTS_BITS);
424
425 rc = -ENODEV;
426 if (edac_mc_add_mc(mci)) {
427 edac_dbg(3, "MC: failed edac_mc_add_mc()\n");
428 goto fail;
429 }
430
431
432 i3000_pci = edac_pci_create_generic_ctl(&pdev->dev, EDAC_MOD_STR);
433 if (!i3000_pci) {
434 printk(KERN_WARNING
435 "%s(): Unable to create PCI control\n",
436 __func__);
437 printk(KERN_WARNING
438 "%s(): PCI error report via EDAC not setup\n",
439 __func__);
440 }
441
442
443 edac_dbg(3, "MC: success\n");
444 return 0;
445
446fail:
447 if (mci)
448 edac_mc_free(mci);
449
450 return rc;
451}
452
453
454static int i3000_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
455{
456 int rc;
457
458 edac_dbg(0, "MC:\n");
459
460 if (pci_enable_device(pdev) < 0)
461 return -EIO;
462
463 rc = i3000_probe1(pdev, ent->driver_data);
464 if (!mci_pdev)
465 mci_pdev = pci_dev_get(pdev);
466
467 return rc;
468}
469
470static void i3000_remove_one(struct pci_dev *pdev)
471{
472 struct mem_ctl_info *mci;
473
474 edac_dbg(0, "\n");
475
476 if (i3000_pci)
477 edac_pci_release_generic_ctl(i3000_pci);
478
479 mci = edac_mc_del_mc(&pdev->dev);
480 if (!mci)
481 return;
482
483 edac_mc_free(mci);
484}
485
486static const struct pci_device_id i3000_pci_tbl[] = {
487 {
488 PCI_VEND_DEV(INTEL, 3000_HB), PCI_ANY_ID, PCI_ANY_ID, 0, 0,
489 I3000},
490 {
491 0,
492 }
493};
494
495MODULE_DEVICE_TABLE(pci, i3000_pci_tbl);
496
497static struct pci_driver i3000_driver = {
498 .name = EDAC_MOD_STR,
499 .probe = i3000_init_one,
500 .remove = i3000_remove_one,
501 .id_table = i3000_pci_tbl,
502};
503
504static int __init i3000_init(void)
505{
506 int pci_rc;
507
508 edac_dbg(3, "MC:\n");
509
510
511 opstate_init();
512
513 pci_rc = pci_register_driver(&i3000_driver);
514 if (pci_rc < 0)
515 goto fail0;
516
517 if (!mci_pdev) {
518 i3000_registered = 0;
519 mci_pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
520 PCI_DEVICE_ID_INTEL_3000_HB, NULL);
521 if (!mci_pdev) {
522 edac_dbg(0, "i3000 pci_get_device fail\n");
523 pci_rc = -ENODEV;
524 goto fail1;
525 }
526
527 pci_rc = i3000_init_one(mci_pdev, i3000_pci_tbl);
528 if (pci_rc < 0) {
529 edac_dbg(0, "i3000 init fail\n");
530 pci_rc = -ENODEV;
531 goto fail1;
532 }
533 }
534
535 return 0;
536
537fail1:
538 pci_unregister_driver(&i3000_driver);
539
540fail0:
541 pci_dev_put(mci_pdev);
542
543 return pci_rc;
544}
545
546static void __exit i3000_exit(void)
547{
548 edac_dbg(3, "MC:\n");
549
550 pci_unregister_driver(&i3000_driver);
551 if (!i3000_registered) {
552 i3000_remove_one(mci_pdev);
553 pci_dev_put(mci_pdev);
554 }
555}
556
557module_init(i3000_init);
558module_exit(i3000_exit);
559
560MODULE_LICENSE("GPL");
561MODULE_AUTHOR("Akamai Technologies Arthur Ulfeldt/Jason Uhlenkott");
562MODULE_DESCRIPTION("MC support for Intel 3000 memory hub controllers");
563
564module_param(edac_op_state, int, 0444);
565MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
566