LXR linux/drivers/firmware/qcom

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/* Copyright (c) 2010-2015,2019 The Linux Foundation. All rights reserved.
   3 */
   4#ifndef __QCOM_SCM_INT_H
   5#define __QCOM_SCM_INT_H
   6
   7enum qcom_scm_convention {
   8        SMC_CONVENTION_UNKNOWN,
   9        SMC_CONVENTION_LEGACY,
  10        SMC_CONVENTION_ARM_32,
  11        SMC_CONVENTION_ARM_64,
  12};
  13
  14extern enum qcom_scm_convention qcom_scm_convention;
  15
  16#define MAX_QCOM_SCM_ARGS 10
  17#define MAX_QCOM_SCM_RETS 3
  18
  19enum qcom_scm_arg_types {
  20        QCOM_SCM_VAL,
  21        QCOM_SCM_RO,
  22        QCOM_SCM_RW,
  23        QCOM_SCM_BUFVAL,
  24};
  25
  26#define QCOM_SCM_ARGS_IMPL(num, a, b, c, d, e, f, g, h, i, j, ...) (\
  27                           (((a) & 0x3) << 4) | \
  28                           (((b) & 0x3) << 6) | \
  29                           (((c) & 0x3) << 8) | \
  30                           (((d) & 0x3) << 10) | \
  31                           (((e) & 0x3) << 12) | \
  32                           (((f) & 0x3) << 14) | \
  33                           (((g) & 0x3) << 16) | \
  34                           (((h) & 0x3) << 18) | \
  35                           (((i) & 0x3) << 20) | \
  36                           (((j) & 0x3) << 22) | \
  37                           ((num) & 0xf))
  38
  39#define QCOM_SCM_ARGS(...) QCOM_SCM_ARGS_IMPL(__VA_ARGS__, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
  40
  41
  42/**
  43 * struct qcom_scm_desc
  44 * @arginfo:    Metadata describing the arguments in args[]
  45 * @args:       The array of arguments for the secure syscall
  46 */
  47struct qcom_scm_desc {
  48        u32 svc;
  49        u32 cmd;
  50        u32 arginfo;
  51        u64 args[MAX_QCOM_SCM_ARGS];
  52        u32 owner;
  53};
  54
  55/**
  56 * struct qcom_scm_res
  57 * @result:     The values returned by the secure syscall
  58 */
  59struct qcom_scm_res {
  60        u64 result[MAX_QCOM_SCM_RETS];
  61};
  62
  63#define SCM_SMC_FNID(s, c)      ((((s) & 0xFF) << 8) | ((c) & 0xFF))
  64extern int __scm_smc_call(struct device *dev, const struct qcom_scm_desc *desc,
  65                          enum qcom_scm_convention qcom_convention,
  66                          struct qcom_scm_res *res, bool atomic);
  67#define scm_smc_call(dev, desc, res, atomic) \
  68        __scm_smc_call((dev), (desc), qcom_scm_convention, (res), (atomic))
  69
  70#define SCM_LEGACY_FNID(s, c)   (((s) << 10) | ((c) & 0x3ff))
  71extern int scm_legacy_call_atomic(struct device *dev,
  72                                  const struct qcom_scm_desc *desc,
  73                                  struct qcom_scm_res *res);
  74extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc,
  75                           struct qcom_scm_res *res);
  76
  77#define QCOM_SCM_SVC_BOOT               0x01
  78#define QCOM_SCM_BOOT_SET_ADDR          0x01
  79#define QCOM_SCM_BOOT_TERMINATE_PC      0x02
  80#define QCOM_SCM_BOOT_SET_DLOAD_MODE    0x10
  81#define QCOM_SCM_BOOT_SET_REMOTE_STATE  0x0a
  82#define QCOM_SCM_FLUSH_FLAG_MASK        0x3
  83
  84#define QCOM_SCM_SVC_PIL                0x02
  85#define QCOM_SCM_PIL_PAS_INIT_IMAGE     0x01
  86#define QCOM_SCM_PIL_PAS_MEM_SETUP      0x02
  87#define QCOM_SCM_PIL_PAS_AUTH_AND_RESET 0x05
  88#define QCOM_SCM_PIL_PAS_SHUTDOWN       0x06
  89#define QCOM_SCM_PIL_PAS_IS_SUPPORTED   0x07
  90#define QCOM_SCM_PIL_PAS_MSS_RESET      0x0a
  91
  92#define QCOM_SCM_SVC_IO                 0x05
  93#define QCOM_SCM_IO_READ                0x01
  94#define QCOM_SCM_IO_WRITE               0x02
  95
  96#define QCOM_SCM_SVC_INFO               0x06
  97#define QCOM_SCM_INFO_IS_CALL_AVAIL     0x01
  98
  99#define QCOM_SCM_SVC_MP                         0x0c
 100#define QCOM_SCM_MP_RESTORE_SEC_CFG             0x02
 101#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_SIZE      0x03
 102#define QCOM_SCM_MP_IOMMU_SECURE_PTBL_INIT      0x04
 103#define QCOM_SCM_MP_VIDEO_VAR                   0x08
 104#define QCOM_SCM_MP_ASSIGN                      0x16
 105
 106#define QCOM_SCM_SVC_OCMEM              0x0f
 107#define QCOM_SCM_OCMEM_LOCK_CMD         0x01
 108#define QCOM_SCM_OCMEM_UNLOCK_CMD       0x02
 109
 110#define QCOM_SCM_SVC_ES                 0x10    /* Enterprise Security */
 111#define QCOM_SCM_ES_INVALIDATE_ICE_KEY  0x03
 112#define QCOM_SCM_ES_CONFIG_SET_ICE_KEY  0x04
 113
 114#define QCOM_SCM_SVC_HDCP               0x11
 115#define QCOM_SCM_HDCP_INVOKE            0x01
 116
 117#define QCOM_SCM_SVC_LMH                        0x13
 118#define QCOM_SCM_LMH_LIMIT_PROFILE_CHANGE       0x01
 119#define QCOM_SCM_LMH_LIMIT_DCVSH                0x10
 120
 121#define QCOM_SCM_SVC_SMMU_PROGRAM               0x15
 122#define QCOM_SCM_SMMU_CONFIG_ERRATA1            0x03
 123#define QCOM_SCM_SMMU_CONFIG_ERRATA1_CLIENT_ALL 0x02
 124
 125extern void __qcom_scm_init(void);
 126
 127/* common error codes */
 128#define QCOM_SCM_V2_EBUSY       -12
 129#define QCOM_SCM_ENOMEM         -5
 130#define QCOM_SCM_EOPNOTSUPP     -4
 131#define QCOM_SCM_EINVAL_ADDR    -3
 132#define QCOM_SCM_EINVAL_ARG     -2
 133#define QCOM_SCM_ERROR          -1
 134#define QCOM_SCM_INTERRUPTED    1
 135
 136static inline int qcom_scm_remap_error(int err)
 137{
 138        switch (err) {
 139        case QCOM_SCM_ERROR:
 140                return -EIO;
 141        case QCOM_SCM_EINVAL_ADDR:
 142        case QCOM_SCM_EINVAL_ARG:
 143                return -EINVAL;
 144        case QCOM_SCM_EOPNOTSUPP:
 145                return -EOPNOTSUPP;
 146        case QCOM_SCM_ENOMEM:
 147                return -ENOMEM;
 148        case QCOM_SCM_V2_EBUSY:
 149                return -EBUSY;
 150        }
 151        return -EINVAL;
 152}
 153
 154#endif
 155