LXR linux/drivers/gpio/gpio-bcm-kona.c

   1/*
   2 * Broadcom Kona GPIO Driver
   3 *
   4 * Author: Broadcom Corporation <bcm-kernel-feedback-list@broadcom.com>
   5 * Copyright (C) 2012-2014 Broadcom Corporation
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation version 2.
  10 *
  11 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  12 * kind, whether express or implied; without even the implied warranty
  13 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 * GNU General Public License for more details.
  15 */
  16
  17#include <linux/bitops.h>
  18#include <linux/err.h>
  19#include <linux/io.h>
  20#include <linux/gpio/driver.h>
  21#include <linux/of_device.h>
  22#include <linux/init.h>
  23#include <linux/irqdomain.h>
  24#include <linux/irqchip/chained_irq.h>
  25
  26#define BCM_GPIO_PASSWD                         0x00a5a501
  27#define GPIO_PER_BANK                           32
  28#define GPIO_MAX_BANK_NUM                       8
  29
  30#define GPIO_BANK(gpio)                         ((gpio) >> 5)
  31#define GPIO_BIT(gpio)                          ((gpio) & (GPIO_PER_BANK - 1))
  32
  33/* There is a GPIO control register for each GPIO */
  34#define GPIO_CONTROL(gpio)                      (0x00000100 + ((gpio) << 2))
  35
  36/* The remaining registers are per GPIO bank */
  37#define GPIO_OUT_STATUS(bank)                   (0x00000000 + ((bank) << 2))
  38#define GPIO_IN_STATUS(bank)                    (0x00000020 + ((bank) << 2))
  39#define GPIO_OUT_SET(bank)                      (0x00000040 + ((bank) << 2))
  40#define GPIO_OUT_CLEAR(bank)                    (0x00000060 + ((bank) << 2))
  41#define GPIO_INT_STATUS(bank)                   (0x00000080 + ((bank) << 2))
  42#define GPIO_INT_MASK(bank)                     (0x000000a0 + ((bank) << 2))
  43#define GPIO_INT_MSKCLR(bank)                   (0x000000c0 + ((bank) << 2))
  44#define GPIO_PWD_STATUS(bank)                   (0x00000500 + ((bank) << 2))
  45
  46#define GPIO_GPPWR_OFFSET                       0x00000520
  47
  48#define GPIO_GPCTR0_DBR_SHIFT                   5
  49#define GPIO_GPCTR0_DBR_MASK                    0x000001e0
  50
  51#define GPIO_GPCTR0_ITR_SHIFT                   3
  52#define GPIO_GPCTR0_ITR_MASK                    0x00000018
  53#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE         0x00000001
  54#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE        0x00000002
  55#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE           0x00000003
  56
  57#define GPIO_GPCTR0_IOTR_MASK                   0x00000001
  58#define GPIO_GPCTR0_IOTR_CMD_0UTPUT             0x00000000
  59#define GPIO_GPCTR0_IOTR_CMD_INPUT              0x00000001
  60
  61#define GPIO_GPCTR0_DB_ENABLE_MASK              0x00000100
  62
  63#define LOCK_CODE                               0xffffffff
  64#define UNLOCK_CODE                             0x00000000
  65
  66struct bcm_kona_gpio {
  67        void __iomem *reg_base;
  68        int num_bank;
  69        raw_spinlock_t lock;
  70        struct gpio_chip gpio_chip;
  71        struct irq_domain *irq_domain;
  72        struct bcm_kona_gpio_bank *banks;
  73        struct platform_device *pdev;
  74};
  75
  76struct bcm_kona_gpio_bank {
  77        int id;
  78        int irq;
  79        /* Used in the interrupt handler */
  80        struct bcm_kona_gpio *kona_gpio;
  81};
  82
  83static inline void bcm_kona_gpio_write_lock_regs(void __iomem *reg_base,
  84                                                int bank_id, u32 lockcode)
  85{
  86        writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
  87        writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
  88}
  89
  90static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpio *kona_gpio,
  91                                        unsigned gpio)
  92{
  93        u32 val;
  94        unsigned long flags;
  95        int bank_id = GPIO_BANK(gpio);
  96
  97        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
  98
  99        val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
 100        val |= BIT(gpio);
 101        bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
 102
 103        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 104}
 105
 106static void bcm_kona_gpio_unlock_gpio(struct bcm_kona_gpio *kona_gpio,
 107                                        unsigned gpio)
 108{
 109        u32 val;
 110        unsigned long flags;
 111        int bank_id = GPIO_BANK(gpio);
 112
 113        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 114
 115        val = readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id));
 116        val &= ~BIT(gpio);
 117        bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val);
 118
 119        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 120}
 121
 122static int bcm_kona_gpio_get_dir(struct gpio_chip *chip, unsigned gpio)
 123{
 124        struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
 125        void __iomem *reg_base = kona_gpio->reg_base;
 126        u32 val;
 127
 128        val = readl(reg_base + GPIO_CONTROL(gpio)) & GPIO_GPCTR0_IOTR_MASK;
 129        return val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
 130}
 131
 132static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
 133{
 134        struct bcm_kona_gpio *kona_gpio;
 135        void __iomem *reg_base;
 136        int bank_id = GPIO_BANK(gpio);
 137        int bit = GPIO_BIT(gpio);
 138        u32 val, reg_offset;
 139        unsigned long flags;
 140
 141        kona_gpio = gpiochip_get_data(chip);
 142        reg_base = kona_gpio->reg_base;
 143        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 144
 145        /* this function only applies to output pin */
 146        if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
 147                goto out;
 148
 149        reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
 150
 151        val = readl(reg_base + reg_offset);
 152        val |= BIT(bit);
 153        writel(val, reg_base + reg_offset);
 154
 155out:
 156        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 157}
 158
 159static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
 160{
 161        struct bcm_kona_gpio *kona_gpio;
 162        void __iomem *reg_base;
 163        int bank_id = GPIO_BANK(gpio);
 164        int bit = GPIO_BIT(gpio);
 165        u32 val, reg_offset;
 166        unsigned long flags;
 167
 168        kona_gpio = gpiochip_get_data(chip);
 169        reg_base = kona_gpio->reg_base;
 170        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 171
 172        if (bcm_kona_gpio_get_dir(chip, gpio) == GPIO_LINE_DIRECTION_IN)
 173                reg_offset = GPIO_IN_STATUS(bank_id);
 174        else
 175                reg_offset = GPIO_OUT_STATUS(bank_id);
 176
 177        /* read the GPIO bank status */
 178        val = readl(reg_base + reg_offset);
 179
 180        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 181
 182        /* return the specified bit status */
 183        return !!(val & BIT(bit));
 184}
 185
 186static int bcm_kona_gpio_request(struct gpio_chip *chip, unsigned gpio)
 187{
 188        struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
 189
 190        bcm_kona_gpio_unlock_gpio(kona_gpio, gpio);
 191        return 0;
 192}
 193
 194static void bcm_kona_gpio_free(struct gpio_chip *chip, unsigned gpio)
 195{
 196        struct bcm_kona_gpio *kona_gpio = gpiochip_get_data(chip);
 197
 198        bcm_kona_gpio_lock_gpio(kona_gpio, gpio);
 199}
 200
 201static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
 202{
 203        struct bcm_kona_gpio *kona_gpio;
 204        void __iomem *reg_base;
 205        u32 val;
 206        unsigned long flags;
 207
 208        kona_gpio = gpiochip_get_data(chip);
 209        reg_base = kona_gpio->reg_base;
 210        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 211
 212        val = readl(reg_base + GPIO_CONTROL(gpio));
 213        val &= ~GPIO_GPCTR0_IOTR_MASK;
 214        val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
 215        writel(val, reg_base + GPIO_CONTROL(gpio));
 216
 217        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 218
 219        return 0;
 220}
 221
 222static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
 223                                          unsigned gpio, int value)
 224{
 225        struct bcm_kona_gpio *kona_gpio;
 226        void __iomem *reg_base;
 227        int bank_id = GPIO_BANK(gpio);
 228        int bit = GPIO_BIT(gpio);
 229        u32 val, reg_offset;
 230        unsigned long flags;
 231
 232        kona_gpio = gpiochip_get_data(chip);
 233        reg_base = kona_gpio->reg_base;
 234        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 235
 236        val = readl(reg_base + GPIO_CONTROL(gpio));
 237        val &= ~GPIO_GPCTR0_IOTR_MASK;
 238        val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
 239        writel(val, reg_base + GPIO_CONTROL(gpio));
 240        reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
 241
 242        val = readl(reg_base + reg_offset);
 243        val |= BIT(bit);
 244        writel(val, reg_base + reg_offset);
 245
 246        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 247
 248        return 0;
 249}
 250
 251static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
 252{
 253        struct bcm_kona_gpio *kona_gpio;
 254
 255        kona_gpio = gpiochip_get_data(chip);
 256        if (gpio >= kona_gpio->gpio_chip.ngpio)
 257                return -ENXIO;
 258        return irq_create_mapping(kona_gpio->irq_domain, gpio);
 259}
 260
 261static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
 262                                      unsigned debounce)
 263{
 264        struct bcm_kona_gpio *kona_gpio;
 265        void __iomem *reg_base;
 266        u32 val, res;
 267        unsigned long flags;
 268
 269        kona_gpio = gpiochip_get_data(chip);
 270        reg_base = kona_gpio->reg_base;
 271        /* debounce must be 1-128ms (or 0) */
 272        if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
 273                dev_err(chip->parent, "Debounce value %u not in range\n",
 274                        debounce);
 275                return -EINVAL;
 276        }
 277
 278        /* calculate debounce bit value */
 279        if (debounce != 0) {
 280                /* Convert to ms */
 281                debounce /= 1000;
 282                /* find the MSB */
 283                res = fls(debounce) - 1;
 284                /* Check if MSB-1 is set (round up or down) */
 285                if (res > 0 && (debounce & BIT(res - 1)))
 286                        res++;
 287        }
 288
 289        /* spin lock for read-modify-write of the GPIO register */
 290        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 291
 292        val = readl(reg_base + GPIO_CONTROL(gpio));
 293        val &= ~GPIO_GPCTR0_DBR_MASK;
 294
 295        if (debounce == 0) {
 296                /* disable debounce */
 297                val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
 298        } else {
 299                val |= GPIO_GPCTR0_DB_ENABLE_MASK |
 300                    (res << GPIO_GPCTR0_DBR_SHIFT);
 301        }
 302
 303        writel(val, reg_base + GPIO_CONTROL(gpio));
 304
 305        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 306
 307        return 0;
 308}
 309
 310static int bcm_kona_gpio_set_config(struct gpio_chip *chip, unsigned gpio,
 311                                    unsigned long config)
 312{
 313        u32 debounce;
 314
 315        if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
 316                return -ENOTSUPP;
 317
 318        debounce = pinconf_to_config_argument(config);
 319        return bcm_kona_gpio_set_debounce(chip, gpio, debounce);
 320}
 321
 322static const struct gpio_chip template_chip = {
 323        .label = "bcm-kona-gpio",
 324        .owner = THIS_MODULE,
 325        .request = bcm_kona_gpio_request,
 326        .free = bcm_kona_gpio_free,
 327        .get_direction = bcm_kona_gpio_get_dir,
 328        .direction_input = bcm_kona_gpio_direction_input,
 329        .get = bcm_kona_gpio_get,
 330        .direction_output = bcm_kona_gpio_direction_output,
 331        .set = bcm_kona_gpio_set,
 332        .set_config = bcm_kona_gpio_set_config,
 333        .to_irq = bcm_kona_gpio_to_irq,
 334        .base = 0,
 335};
 336
 337static void bcm_kona_gpio_irq_ack(struct irq_data *d)
 338{
 339        struct bcm_kona_gpio *kona_gpio;
 340        void __iomem *reg_base;
 341        unsigned gpio = d->hwirq;
 342        int bank_id = GPIO_BANK(gpio);
 343        int bit = GPIO_BIT(gpio);
 344        u32 val;
 345        unsigned long flags;
 346
 347        kona_gpio = irq_data_get_irq_chip_data(d);
 348        reg_base = kona_gpio->reg_base;
 349        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 350
 351        val = readl(reg_base + GPIO_INT_STATUS(bank_id));
 352        val |= BIT(bit);
 353        writel(val, reg_base + GPIO_INT_STATUS(bank_id));
 354
 355        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 356}
 357
 358static void bcm_kona_gpio_irq_mask(struct irq_data *d)
 359{
 360        struct bcm_kona_gpio *kona_gpio;
 361        void __iomem *reg_base;
 362        unsigned gpio = d->hwirq;
 363        int bank_id = GPIO_BANK(gpio);
 364        int bit = GPIO_BIT(gpio);
 365        u32 val;
 366        unsigned long flags;
 367
 368        kona_gpio = irq_data_get_irq_chip_data(d);
 369        reg_base = kona_gpio->reg_base;
 370        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 371
 372        val = readl(reg_base + GPIO_INT_MASK(bank_id));
 373        val |= BIT(bit);
 374        writel(val, reg_base + GPIO_INT_MASK(bank_id));
 375        gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio);
 376
 377        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 378}
 379
 380static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
 381{
 382        struct bcm_kona_gpio *kona_gpio;
 383        void __iomem *reg_base;
 384        unsigned gpio = d->hwirq;
 385        int bank_id = GPIO_BANK(gpio);
 386        int bit = GPIO_BIT(gpio);
 387        u32 val;
 388        unsigned long flags;
 389
 390        kona_gpio = irq_data_get_irq_chip_data(d);
 391        reg_base = kona_gpio->reg_base;
 392        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 393
 394        val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
 395        val |= BIT(bit);
 396        writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
 397        gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio);
 398
 399        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 400}
 401
 402static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 403{
 404        struct bcm_kona_gpio *kona_gpio;
 405        void __iomem *reg_base;
 406        unsigned gpio = d->hwirq;
 407        u32 lvl_type;
 408        u32 val;
 409        unsigned long flags;
 410
 411        kona_gpio = irq_data_get_irq_chip_data(d);
 412        reg_base = kona_gpio->reg_base;
 413        switch (type & IRQ_TYPE_SENSE_MASK) {
 414        case IRQ_TYPE_EDGE_RISING:
 415                lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
 416                break;
 417
 418        case IRQ_TYPE_EDGE_FALLING:
 419                lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
 420                break;
 421
 422        case IRQ_TYPE_EDGE_BOTH:
 423                lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
 424                break;
 425
 426        case IRQ_TYPE_LEVEL_HIGH:
 427        case IRQ_TYPE_LEVEL_LOW:
 428                /* BCM GPIO doesn't support level triggering */
 429        default:
 430                dev_err(kona_gpio->gpio_chip.parent,
 431                        "Invalid BCM GPIO irq type 0x%x\n", type);
 432                return -EINVAL;
 433        }
 434
 435        raw_spin_lock_irqsave(&kona_gpio->lock, flags);
 436
 437        val = readl(reg_base + GPIO_CONTROL(gpio));
 438        val &= ~GPIO_GPCTR0_ITR_MASK;
 439        val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
 440        writel(val, reg_base + GPIO_CONTROL(gpio));
 441
 442        raw_spin_unlock_irqrestore(&kona_gpio->lock, flags);
 443
 444        return 0;
 445}
 446
 447static void bcm_kona_gpio_irq_handler(struct irq_desc *desc)
 448{
 449        void __iomem *reg_base;
 450        int bit, bank_id;
 451        unsigned long sta;
 452        struct bcm_kona_gpio_bank *bank = irq_desc_get_handler_data(desc);
 453        struct irq_chip *chip = irq_desc_get_chip(desc);
 454
 455        chained_irq_enter(chip, desc);
 456
 457        /*
 458         * For bank interrupts, we can't use chip_data to store the kona_gpio
 459         * pointer, since GIC needs it for its own purposes. Therefore, we get
 460         * our pointer from the bank structure.
 461         */
 462        reg_base = bank->kona_gpio->reg_base;
 463        bank_id = bank->id;
 464
 465        while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
 466                    (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
 467                for_each_set_bit(bit, &sta, 32) {
 468                        int hwirq = GPIO_PER_BANK * bank_id + bit;
 469                        /*
 470                         * Clear interrupt before handler is called so we don't
 471                         * miss any interrupt occurred during executing them.
 472                         */
 473                        writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
 474                               BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
 475                        /* Invoke interrupt handler */
 476                        generic_handle_domain_irq(bank->kona_gpio->irq_domain,
 477                                                  hwirq);
 478                }
 479        }
 480
 481        chained_irq_exit(chip, desc);
 482}
 483
 484static int bcm_kona_gpio_irq_reqres(struct irq_data *d)
 485{
 486        struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
 487
 488        return gpiochip_reqres_irq(&kona_gpio->gpio_chip, d->hwirq);
 489}
 490
 491static void bcm_kona_gpio_irq_relres(struct irq_data *d)
 492{
 493        struct bcm_kona_gpio *kona_gpio = irq_data_get_irq_chip_data(d);
 494
 495        gpiochip_relres_irq(&kona_gpio->gpio_chip, d->hwirq);
 496}
 497
 498static struct irq_chip bcm_gpio_irq_chip = {
 499        .name = "bcm-kona-gpio",
 500        .irq_ack = bcm_kona_gpio_irq_ack,
 501        .irq_mask = bcm_kona_gpio_irq_mask,
 502        .irq_unmask = bcm_kona_gpio_irq_unmask,
 503        .irq_set_type = bcm_kona_gpio_irq_set_type,
 504        .irq_request_resources = bcm_kona_gpio_irq_reqres,
 505        .irq_release_resources = bcm_kona_gpio_irq_relres,
 506};
 507
 508static struct of_device_id const bcm_kona_gpio_of_match[] = {
 509        { .compatible = "brcm,kona-gpio" },
 510        {}
 511};
 512
 513/*
 514 * This lock class tells lockdep that GPIO irqs are in a different
 515 * category than their parents, so it won't report false recursion.
 516 */
 517static struct lock_class_key gpio_lock_class;
 518static struct lock_class_key gpio_request_class;
 519
 520static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
 521                                 irq_hw_number_t hwirq)
 522{
 523        int ret;
 524
 525        ret = irq_set_chip_data(irq, d->host_data);
 526        if (ret < 0)
 527                return ret;
 528        irq_set_lockdep_class(irq, &gpio_lock_class, &gpio_request_class);
 529        irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
 530        irq_set_noprobe(irq);
 531
 532        return 0;
 533}
 534
 535static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int irq)
 536{
 537        irq_set_chip_and_handler(irq, NULL, NULL);
 538        irq_set_chip_data(irq, NULL);
 539}
 540
 541static const struct irq_domain_ops bcm_kona_irq_ops = {
 542        .map = bcm_kona_gpio_irq_map,
 543        .unmap = bcm_kona_gpio_irq_unmap,
 544        .xlate = irq_domain_xlate_twocell,
 545};
 546
 547static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
 548{
 549        void __iomem *reg_base;
 550        int i;
 551
 552        reg_base = kona_gpio->reg_base;
 553        /* disable interrupts and clear status */
 554        for (i = 0; i < kona_gpio->num_bank; i++) {
 555                /* Unlock the entire bank first */
 556                bcm_kona_gpio_write_lock_regs(reg_base, i, UNLOCK_CODE);
 557                writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
 558                writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
 559                /* Now re-lock the bank */
 560                bcm_kona_gpio_write_lock_regs(reg_base, i, LOCK_CODE);
 561        }
 562}
 563
 564static int bcm_kona_gpio_probe(struct platform_device *pdev)
 565{
 566        struct device *dev = &pdev->dev;
 567        const struct of_device_id *match;
 568        struct bcm_kona_gpio_bank *bank;
 569        struct bcm_kona_gpio *kona_gpio;
 570        struct gpio_chip *chip;
 571        int ret;
 572        int i;
 573
 574        match = of_match_device(bcm_kona_gpio_of_match, dev);
 575        if (!match) {
 576                dev_err(dev, "Failed to find gpio controller\n");
 577                return -ENODEV;
 578        }
 579
 580        kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
 581        if (!kona_gpio)
 582                return -ENOMEM;
 583
 584        kona_gpio->gpio_chip = template_chip;
 585        chip = &kona_gpio->gpio_chip;
 586        ret = platform_irq_count(pdev);
 587        if (!ret) {
 588                dev_err(dev, "Couldn't determine # GPIO banks\n");
 589                return -ENOENT;
 590        } else if (ret < 0) {
 591                return dev_err_probe(dev, ret, "Couldn't determine GPIO banks\n");
 592        }
 593        kona_gpio->num_bank = ret;
 594
 595        if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
 596                dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
 597                        GPIO_MAX_BANK_NUM);
 598                return -ENXIO;
 599        }
 600        kona_gpio->banks = devm_kcalloc(dev,
 601                                        kona_gpio->num_bank,
 602                                        sizeof(*kona_gpio->banks),
 603                                        GFP_KERNEL);
 604        if (!kona_gpio->banks)
 605                return -ENOMEM;
 606
 607        kona_gpio->pdev = pdev;
 608        platform_set_drvdata(pdev, kona_gpio);
 609        chip->of_node = dev->of_node;
 610        chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
 611
 612        kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
 613                                                      chip->ngpio,
 614                                                      &bcm_kona_irq_ops,
 615                                                      kona_gpio);
 616        if (!kona_gpio->irq_domain) {
 617                dev_err(dev, "Couldn't allocate IRQ domain\n");
 618                return -ENXIO;
 619        }
 620
 621        kona_gpio->reg_base = devm_platform_ioremap_resource(pdev, 0);
 622        if (IS_ERR(kona_gpio->reg_base)) {
 623                ret = PTR_ERR(kona_gpio->reg_base);
 624                goto err_irq_domain;
 625        }
 626
 627        for (i = 0; i < kona_gpio->num_bank; i++) {
 628                bank = &kona_gpio->banks[i];
 629                bank->id = i;
 630                bank->irq = platform_get_irq(pdev, i);
 631                bank->kona_gpio = kona_gpio;
 632                if (bank->irq < 0) {
 633                        dev_err(dev, "Couldn't get IRQ for bank %d", i);
 634                        ret = -ENOENT;
 635                        goto err_irq_domain;
 636                }
 637        }
 638
 639        dev_info(&pdev->dev, "Setting up Kona GPIO\n");
 640
 641        bcm_kona_gpio_reset(kona_gpio);
 642
 643        ret = devm_gpiochip_add_data(dev, chip, kona_gpio);
 644        if (ret < 0) {
 645                dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
 646                goto err_irq_domain;
 647        }
 648        for (i = 0; i < kona_gpio->num_bank; i++) {
 649                bank = &kona_gpio->banks[i];
 650                irq_set_chained_handler_and_data(bank->irq,
 651                                                 bcm_kona_gpio_irq_handler,
 652                                                 bank);
 653        }
 654
 655        raw_spin_lock_init(&kona_gpio->lock);
 656
 657        return 0;
 658
 659err_irq_domain:
 660        irq_domain_remove(kona_gpio->irq_domain);
 661
 662        return ret;
 663}
 664
 665static struct platform_driver bcm_kona_gpio_driver = {
 666        .driver = {
 667                        .name = "bcm-kona-gpio",
 668                        .of_match_table = bcm_kona_gpio_of_match,
 669        },
 670        .probe = bcm_kona_gpio_probe,
 671};
 672builtin_platform_driver(bcm_kona_gpio_driver);
 673