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5#include <linux/module.h>
6#include <linux/kernel.h>
7#include <linux/slab.h>
8#include <linux/pci.h>
9#include <linux/gpio/driver.h>
10#include <linux/interrupt.h>
11#include <linux/irq.h>
12
13#define IOH_EDGE_FALLING 0
14#define IOH_EDGE_RISING BIT(0)
15#define IOH_LEVEL_L BIT(1)
16#define IOH_LEVEL_H (BIT(0) | BIT(1))
17#define IOH_EDGE_BOTH BIT(2)
18#define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
19
20#define IOH_IRQ_BASE 0
21
22struct ioh_reg_comn {
23 u32 ien;
24 u32 istatus;
25 u32 idisp;
26 u32 iclr;
27 u32 imask;
28 u32 imaskclr;
29 u32 po;
30 u32 pi;
31 u32 pm;
32 u32 im_0;
33 u32 im_1;
34 u32 reserved;
35};
36
37struct ioh_regs {
38 struct ioh_reg_comn regs[8];
39 u32 reserve1[16];
40 u32 ioh_sel_reg[4];
41 u32 reserve2[11];
42 u32 srst;
43};
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53
54
55struct ioh_gpio_reg_data {
56 u32 ien_reg;
57 u32 imask_reg;
58 u32 po_reg;
59 u32 pm_reg;
60 u32 im0_reg;
61 u32 im1_reg;
62 u32 use_sel_reg;
63};
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77
78struct ioh_gpio {
79 void __iomem *base;
80 struct ioh_regs __iomem *reg;
81 struct device *dev;
82 struct gpio_chip gpio;
83 struct ioh_gpio_reg_data ioh_gpio_reg;
84 u32 gpio_use_sel;
85 int ch;
86 int irq_base;
87 spinlock_t spinlock;
88};
89
90static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
91
92static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
93{
94 u32 reg_val;
95 struct ioh_gpio *chip = gpiochip_get_data(gpio);
96 unsigned long flags;
97
98 spin_lock_irqsave(&chip->spinlock, flags);
99 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
100 if (val)
101 reg_val |= (1 << nr);
102 else
103 reg_val &= ~(1 << nr);
104
105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
106 spin_unlock_irqrestore(&chip->spinlock, flags);
107}
108
109static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
110{
111 struct ioh_gpio *chip = gpiochip_get_data(gpio);
112
113 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr));
114}
115
116static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
117 int val)
118{
119 struct ioh_gpio *chip = gpiochip_get_data(gpio);
120 u32 pm;
121 u32 reg_val;
122 unsigned long flags;
123
124 spin_lock_irqsave(&chip->spinlock, flags);
125 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
126 ((1 << num_ports[chip->ch]) - 1);
127 pm |= (1 << nr);
128 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
129
130 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
131 if (val)
132 reg_val |= (1 << nr);
133 else
134 reg_val &= ~(1 << nr);
135 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
136
137 spin_unlock_irqrestore(&chip->spinlock, flags);
138
139 return 0;
140}
141
142static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
143{
144 struct ioh_gpio *chip = gpiochip_get_data(gpio);
145 u32 pm;
146 unsigned long flags;
147
148 spin_lock_irqsave(&chip->spinlock, flags);
149 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
150 ((1 << num_ports[chip->ch]) - 1);
151 pm &= ~(1 << nr);
152 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
153 spin_unlock_irqrestore(&chip->spinlock, flags);
154
155 return 0;
156}
157
158
159
160
161static void __maybe_unused ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
162{
163 int i;
164
165 for (i = 0; i < 8; i ++, chip++) {
166 chip->ioh_gpio_reg.po_reg =
167 ioread32(&chip->reg->regs[chip->ch].po);
168 chip->ioh_gpio_reg.pm_reg =
169 ioread32(&chip->reg->regs[chip->ch].pm);
170 chip->ioh_gpio_reg.ien_reg =
171 ioread32(&chip->reg->regs[chip->ch].ien);
172 chip->ioh_gpio_reg.imask_reg =
173 ioread32(&chip->reg->regs[chip->ch].imask);
174 chip->ioh_gpio_reg.im0_reg =
175 ioread32(&chip->reg->regs[chip->ch].im_0);
176 chip->ioh_gpio_reg.im1_reg =
177 ioread32(&chip->reg->regs[chip->ch].im_1);
178 if (i < 4)
179 chip->ioh_gpio_reg.use_sel_reg =
180 ioread32(&chip->reg->ioh_sel_reg[i]);
181 }
182}
183
184
185
186
187static void __maybe_unused ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
188{
189 int i;
190
191 for (i = 0; i < 8; i ++, chip++) {
192 iowrite32(chip->ioh_gpio_reg.po_reg,
193 &chip->reg->regs[chip->ch].po);
194 iowrite32(chip->ioh_gpio_reg.pm_reg,
195 &chip->reg->regs[chip->ch].pm);
196 iowrite32(chip->ioh_gpio_reg.ien_reg,
197 &chip->reg->regs[chip->ch].ien);
198 iowrite32(chip->ioh_gpio_reg.imask_reg,
199 &chip->reg->regs[chip->ch].imask);
200 iowrite32(chip->ioh_gpio_reg.im0_reg,
201 &chip->reg->regs[chip->ch].im_0);
202 iowrite32(chip->ioh_gpio_reg.im1_reg,
203 &chip->reg->regs[chip->ch].im_1);
204 if (i < 4)
205 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
206 &chip->reg->ioh_sel_reg[i]);
207 }
208}
209
210static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
211{
212 struct ioh_gpio *chip = gpiochip_get_data(gpio);
213 return chip->irq_base + offset;
214}
215
216static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
217{
218 struct gpio_chip *gpio = &chip->gpio;
219
220 gpio->label = dev_name(chip->dev);
221 gpio->owner = THIS_MODULE;
222 gpio->direction_input = ioh_gpio_direction_input;
223 gpio->get = ioh_gpio_get;
224 gpio->direction_output = ioh_gpio_direction_output;
225 gpio->set = ioh_gpio_set;
226 gpio->dbg_show = NULL;
227 gpio->base = -1;
228 gpio->ngpio = num_port;
229 gpio->can_sleep = false;
230 gpio->to_irq = ioh_gpio_to_irq;
231}
232
233static int ioh_irq_type(struct irq_data *d, unsigned int type)
234{
235 u32 im;
236 void __iomem *im_reg;
237 u32 ien;
238 u32 im_pos;
239 int ch;
240 unsigned long flags;
241 u32 val;
242 int irq = d->irq;
243 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
244 struct ioh_gpio *chip = gc->private;
245
246 ch = irq - chip->irq_base;
247 if (irq <= chip->irq_base + 7) {
248 im_reg = &chip->reg->regs[chip->ch].im_0;
249 im_pos = ch;
250 } else {
251 im_reg = &chip->reg->regs[chip->ch].im_1;
252 im_pos = ch - 8;
253 }
254 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
255 __func__, irq, type, ch, im_pos, type);
256
257 spin_lock_irqsave(&chip->spinlock, flags);
258
259 switch (type) {
260 case IRQ_TYPE_EDGE_RISING:
261 val = IOH_EDGE_RISING;
262 break;
263 case IRQ_TYPE_EDGE_FALLING:
264 val = IOH_EDGE_FALLING;
265 break;
266 case IRQ_TYPE_EDGE_BOTH:
267 val = IOH_EDGE_BOTH;
268 break;
269 case IRQ_TYPE_LEVEL_HIGH:
270 val = IOH_LEVEL_H;
271 break;
272 case IRQ_TYPE_LEVEL_LOW:
273 val = IOH_LEVEL_L;
274 break;
275 case IRQ_TYPE_PROBE:
276 goto end;
277 default:
278 dev_warn(chip->dev, "%s: unknown type(%dd)",
279 __func__, type);
280 goto end;
281 }
282
283
284 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
285 iowrite32(im | (val << (im_pos * 4)), im_reg);
286
287
288 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
289
290
291 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
292
293
294 ien = ioread32(&chip->reg->regs[chip->ch].ien);
295 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
296end:
297 spin_unlock_irqrestore(&chip->spinlock, flags);
298
299 return 0;
300}
301
302static void ioh_irq_unmask(struct irq_data *d)
303{
304 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
305 struct ioh_gpio *chip = gc->private;
306
307 iowrite32(1 << (d->irq - chip->irq_base),
308 &chip->reg->regs[chip->ch].imaskclr);
309}
310
311static void ioh_irq_mask(struct irq_data *d)
312{
313 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
314 struct ioh_gpio *chip = gc->private;
315
316 iowrite32(1 << (d->irq - chip->irq_base),
317 &chip->reg->regs[chip->ch].imask);
318}
319
320static void ioh_irq_disable(struct irq_data *d)
321{
322 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
323 struct ioh_gpio *chip = gc->private;
324 unsigned long flags;
325 u32 ien;
326
327 spin_lock_irqsave(&chip->spinlock, flags);
328 ien = ioread32(&chip->reg->regs[chip->ch].ien);
329 ien &= ~(1 << (d->irq - chip->irq_base));
330 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
331 spin_unlock_irqrestore(&chip->spinlock, flags);
332}
333
334static void ioh_irq_enable(struct irq_data *d)
335{
336 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
337 struct ioh_gpio *chip = gc->private;
338 unsigned long flags;
339 u32 ien;
340
341 spin_lock_irqsave(&chip->spinlock, flags);
342 ien = ioread32(&chip->reg->regs[chip->ch].ien);
343 ien |= 1 << (d->irq - chip->irq_base);
344 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
345 spin_unlock_irqrestore(&chip->spinlock, flags);
346}
347
348static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
349{
350 struct ioh_gpio *chip = dev_id;
351 u32 reg_val;
352 int i, j;
353 int ret = IRQ_NONE;
354
355 for (i = 0; i < 8; i++, chip++) {
356 reg_val = ioread32(&chip->reg->regs[i].istatus);
357 for (j = 0; j < num_ports[i]; j++) {
358 if (reg_val & BIT(j)) {
359 dev_dbg(chip->dev,
360 "%s:[%d]:irq=%d status=0x%x\n",
361 __func__, j, irq, reg_val);
362 iowrite32(BIT(j),
363 &chip->reg->regs[chip->ch].iclr);
364 generic_handle_irq(chip->irq_base + j);
365 ret = IRQ_HANDLED;
366 }
367 }
368 }
369 return ret;
370}
371
372static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
373 unsigned int irq_start,
374 unsigned int num)
375{
376 struct irq_chip_generic *gc;
377 struct irq_chip_type *ct;
378 int rv;
379
380 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start,
381 chip->base, handle_simple_irq);
382 if (!gc)
383 return -ENOMEM;
384
385 gc->private = chip;
386 ct = gc->chip_types;
387
388 ct->chip.irq_mask = ioh_irq_mask;
389 ct->chip.irq_unmask = ioh_irq_unmask;
390 ct->chip.irq_set_type = ioh_irq_type;
391 ct->chip.irq_disable = ioh_irq_disable;
392 ct->chip.irq_enable = ioh_irq_enable;
393
394 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num),
395 IRQ_GC_INIT_MASK_CACHE,
396 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
397
398 return rv;
399}
400
401static int ioh_gpio_probe(struct pci_dev *pdev,
402 const struct pci_device_id *id)
403{
404 int ret;
405 int i, j;
406 struct ioh_gpio *chip;
407 void __iomem *base;
408 void *chip_save;
409 int irq_base;
410
411 ret = pci_enable_device(pdev);
412 if (ret) {
413 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
414 goto err_pci_enable;
415 }
416
417 ret = pci_request_regions(pdev, KBUILD_MODNAME);
418 if (ret) {
419 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
420 goto err_request_regions;
421 }
422
423 base = pci_iomap(pdev, 1, 0);
424 if (!base) {
425 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
426 ret = -ENOMEM;
427 goto err_iomap;
428 }
429
430 chip_save = kcalloc(8, sizeof(*chip), GFP_KERNEL);
431 if (chip_save == NULL) {
432 ret = -ENOMEM;
433 goto err_kzalloc;
434 }
435
436 chip = chip_save;
437 for (i = 0; i < 8; i++, chip++) {
438 chip->dev = &pdev->dev;
439 chip->base = base;
440 chip->reg = chip->base;
441 chip->ch = i;
442 spin_lock_init(&chip->spinlock);
443 ioh_gpio_setup(chip, num_ports[i]);
444 ret = gpiochip_add_data(&chip->gpio, chip);
445 if (ret) {
446 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
447 goto err_gpiochip_add;
448 }
449 }
450
451 chip = chip_save;
452 for (j = 0; j < 8; j++, chip++) {
453 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, IOH_IRQ_BASE,
454 num_ports[j], NUMA_NO_NODE);
455 if (irq_base < 0) {
456 dev_warn(&pdev->dev,
457 "ml_ioh_gpio: Failed to get IRQ base num\n");
458 ret = irq_base;
459 goto err_gpiochip_add;
460 }
461 chip->irq_base = irq_base;
462
463 ret = ioh_gpio_alloc_generic_chip(chip,
464 irq_base, num_ports[j]);
465 if (ret)
466 goto err_gpiochip_add;
467 }
468
469 chip = chip_save;
470 ret = devm_request_irq(&pdev->dev, pdev->irq, ioh_gpio_handler,
471 IRQF_SHARED, KBUILD_MODNAME, chip);
472 if (ret != 0) {
473 dev_err(&pdev->dev,
474 "%s request_irq failed\n", __func__);
475 goto err_gpiochip_add;
476 }
477
478 pci_set_drvdata(pdev, chip);
479
480 return 0;
481
482err_gpiochip_add:
483 chip = chip_save;
484 while (--i >= 0) {
485 gpiochip_remove(&chip->gpio);
486 chip++;
487 }
488 kfree(chip_save);
489
490err_kzalloc:
491 pci_iounmap(pdev, base);
492
493err_iomap:
494 pci_release_regions(pdev);
495
496err_request_regions:
497 pci_disable_device(pdev);
498
499err_pci_enable:
500
501 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
502 return ret;
503}
504
505static void ioh_gpio_remove(struct pci_dev *pdev)
506{
507 int i;
508 struct ioh_gpio *chip = pci_get_drvdata(pdev);
509 void *chip_save;
510
511 chip_save = chip;
512
513 for (i = 0; i < 8; i++, chip++)
514 gpiochip_remove(&chip->gpio);
515
516 chip = chip_save;
517 pci_iounmap(pdev, chip->base);
518 pci_release_regions(pdev);
519 pci_disable_device(pdev);
520 kfree(chip);
521}
522
523static int __maybe_unused ioh_gpio_suspend(struct device *dev)
524{
525 struct ioh_gpio *chip = dev_get_drvdata(dev);
526 unsigned long flags;
527
528 spin_lock_irqsave(&chip->spinlock, flags);
529 ioh_gpio_save_reg_conf(chip);
530 spin_unlock_irqrestore(&chip->spinlock, flags);
531
532 return 0;
533}
534
535static int __maybe_unused ioh_gpio_resume(struct device *dev)
536{
537 struct ioh_gpio *chip = dev_get_drvdata(dev);
538 unsigned long flags;
539
540 spin_lock_irqsave(&chip->spinlock, flags);
541 iowrite32(0x01, &chip->reg->srst);
542 iowrite32(0x00, &chip->reg->srst);
543 ioh_gpio_restore_reg_conf(chip);
544 spin_unlock_irqrestore(&chip->spinlock, flags);
545
546 return 0;
547}
548
549static SIMPLE_DEV_PM_OPS(ioh_gpio_pm_ops, ioh_gpio_suspend, ioh_gpio_resume);
550
551static const struct pci_device_id ioh_gpio_pcidev_id[] = {
552 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
553 { 0, }
554};
555MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
556
557static struct pci_driver ioh_gpio_driver = {
558 .name = "ml_ioh_gpio",
559 .id_table = ioh_gpio_pcidev_id,
560 .probe = ioh_gpio_probe,
561 .remove = ioh_gpio_remove,
562 .driver = {
563 .pm = &ioh_gpio_pm_ops,
564 },
565};
566
567module_pci_driver(ioh_gpio_driver);
568
569MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
570MODULE_LICENSE("GPL");
571
