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7#include <linux/err.h>
8#include <linux/gpio/driver.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/of_irq.h>
13#include <linux/platform_device.h>
14#include <linux/spinlock.h>
15
16#define MTK_BANK_CNT 3
17#define MTK_BANK_WIDTH 32
18
19#define GPIO_BANK_STRIDE 0x04
20#define GPIO_REG_CTRL 0x00
21#define GPIO_REG_POL 0x10
22#define GPIO_REG_DATA 0x20
23#define GPIO_REG_DSET 0x30
24#define GPIO_REG_DCLR 0x40
25#define GPIO_REG_REDGE 0x50
26#define GPIO_REG_FEDGE 0x60
27#define GPIO_REG_HLVL 0x70
28#define GPIO_REG_LLVL 0x80
29#define GPIO_REG_STAT 0x90
30#define GPIO_REG_EDGE 0xA0
31
32struct mtk_gc {
33 struct irq_chip irq_chip;
34 struct gpio_chip chip;
35 spinlock_t lock;
36 int bank;
37 u32 rising;
38 u32 falling;
39 u32 hlevel;
40 u32 llevel;
41};
42
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50
51
52
53struct mtk {
54 struct device *dev;
55 void __iomem *base;
56 int gpio_irq;
57 struct mtk_gc gc_map[MTK_BANK_CNT];
58};
59
60static inline struct mtk_gc *
61to_mediatek_gpio(struct gpio_chip *chip)
62{
63 return container_of(chip, struct mtk_gc, chip);
64}
65
66static inline void
67mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val)
68{
69 struct gpio_chip *gc = &rg->chip;
70 struct mtk *mtk = gpiochip_get_data(gc);
71
72 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
73 gc->write_reg(mtk->base + offset, val);
74}
75
76static inline u32
77mtk_gpio_r32(struct mtk_gc *rg, u32 offset)
78{
79 struct gpio_chip *gc = &rg->chip;
80 struct mtk *mtk = gpiochip_get_data(gc);
81
82 offset = (rg->bank * GPIO_BANK_STRIDE) + offset;
83 return gc->read_reg(mtk->base + offset);
84}
85
86static irqreturn_t
87mediatek_gpio_irq_handler(int irq, void *data)
88{
89 struct gpio_chip *gc = data;
90 struct mtk_gc *rg = to_mediatek_gpio(gc);
91 irqreturn_t ret = IRQ_NONE;
92 unsigned long pending;
93 int bit;
94
95 pending = mtk_gpio_r32(rg, GPIO_REG_STAT);
96
97 for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) {
98 generic_handle_domain_irq(gc->irq.domain, bit);
99 mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit));
100 ret |= IRQ_HANDLED;
101 }
102
103 return ret;
104}
105
106static void
107mediatek_gpio_irq_unmask(struct irq_data *d)
108{
109 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
110 struct mtk_gc *rg = to_mediatek_gpio(gc);
111 int pin = d->hwirq;
112 unsigned long flags;
113 u32 rise, fall, high, low;
114
115 spin_lock_irqsave(&rg->lock, flags);
116 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
117 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
118 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
119 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
120 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising));
121 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling));
122 mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel));
123 mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel));
124 spin_unlock_irqrestore(&rg->lock, flags);
125}
126
127static void
128mediatek_gpio_irq_mask(struct irq_data *d)
129{
130 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
131 struct mtk_gc *rg = to_mediatek_gpio(gc);
132 int pin = d->hwirq;
133 unsigned long flags;
134 u32 rise, fall, high, low;
135
136 spin_lock_irqsave(&rg->lock, flags);
137 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE);
138 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE);
139 high = mtk_gpio_r32(rg, GPIO_REG_HLVL);
140 low = mtk_gpio_r32(rg, GPIO_REG_LLVL);
141 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin));
142 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin));
143 mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin));
144 mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin));
145 spin_unlock_irqrestore(&rg->lock, flags);
146}
147
148static int
149mediatek_gpio_irq_type(struct irq_data *d, unsigned int type)
150{
151 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
152 struct mtk_gc *rg = to_mediatek_gpio(gc);
153 int pin = d->hwirq;
154 u32 mask = BIT(pin);
155
156 if (type == IRQ_TYPE_PROBE) {
157 if ((rg->rising | rg->falling |
158 rg->hlevel | rg->llevel) & mask)
159 return 0;
160
161 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
162 }
163
164 rg->rising &= ~mask;
165 rg->falling &= ~mask;
166 rg->hlevel &= ~mask;
167 rg->llevel &= ~mask;
168
169 switch (type & IRQ_TYPE_SENSE_MASK) {
170 case IRQ_TYPE_EDGE_BOTH:
171 rg->rising |= mask;
172 rg->falling |= mask;
173 break;
174 case IRQ_TYPE_EDGE_RISING:
175 rg->rising |= mask;
176 break;
177 case IRQ_TYPE_EDGE_FALLING:
178 rg->falling |= mask;
179 break;
180 case IRQ_TYPE_LEVEL_HIGH:
181 rg->hlevel |= mask;
182 break;
183 case IRQ_TYPE_LEVEL_LOW:
184 rg->llevel |= mask;
185 break;
186 }
187
188 return 0;
189}
190
191static int
192mediatek_gpio_xlate(struct gpio_chip *chip,
193 const struct of_phandle_args *spec, u32 *flags)
194{
195 int gpio = spec->args[0];
196 struct mtk_gc *rg = to_mediatek_gpio(chip);
197
198 if (rg->bank != gpio / MTK_BANK_WIDTH)
199 return -EINVAL;
200
201 if (flags)
202 *flags = spec->args[1];
203
204 return gpio % MTK_BANK_WIDTH;
205}
206
207static int
208mediatek_gpio_bank_probe(struct device *dev,
209 struct device_node *node, int bank)
210{
211 struct mtk *mtk = dev_get_drvdata(dev);
212 struct mtk_gc *rg;
213 void __iomem *dat, *set, *ctrl, *diro;
214 int ret;
215
216 rg = &mtk->gc_map[bank];
217 memset(rg, 0, sizeof(*rg));
218
219 spin_lock_init(&rg->lock);
220 rg->chip.of_node = node;
221 rg->bank = bank;
222
223 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE);
224 set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE);
225 ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE);
226 diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE);
227
228 ret = bgpio_init(&rg->chip, dev, 4, dat, set, ctrl, diro, NULL,
229 BGPIOF_NO_SET_ON_INPUT);
230 if (ret) {
231 dev_err(dev, "bgpio_init() failed\n");
232 return ret;
233 }
234
235 rg->chip.of_gpio_n_cells = 2;
236 rg->chip.of_xlate = mediatek_gpio_xlate;
237 rg->chip.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d",
238 dev_name(dev), bank);
239 if (!rg->chip.label)
240 return -ENOMEM;
241
242 rg->chip.offset = bank * MTK_BANK_WIDTH;
243 rg->irq_chip.name = dev_name(dev);
244 rg->irq_chip.parent_device = dev;
245 rg->irq_chip.irq_unmask = mediatek_gpio_irq_unmask;
246 rg->irq_chip.irq_mask = mediatek_gpio_irq_mask;
247 rg->irq_chip.irq_mask_ack = mediatek_gpio_irq_mask;
248 rg->irq_chip.irq_set_type = mediatek_gpio_irq_type;
249
250 if (mtk->gpio_irq) {
251 struct gpio_irq_chip *girq;
252
253
254
255
256
257 ret = devm_request_irq(dev, mtk->gpio_irq,
258 mediatek_gpio_irq_handler, IRQF_SHARED,
259 rg->chip.label, &rg->chip);
260
261 if (ret) {
262 dev_err(dev, "Error requesting IRQ %d: %d\n",
263 mtk->gpio_irq, ret);
264 return ret;
265 }
266
267 girq = &rg->chip.irq;
268 girq->chip = &rg->irq_chip;
269
270 girq->parent_handler = NULL;
271 girq->num_parents = 0;
272 girq->parents = NULL;
273 girq->default_type = IRQ_TYPE_NONE;
274 girq->handler = handle_simple_irq;
275 }
276
277 ret = devm_gpiochip_add_data(dev, &rg->chip, mtk);
278 if (ret < 0) {
279 dev_err(dev, "Could not register gpio %d, ret=%d\n",
280 rg->chip.ngpio, ret);
281 return ret;
282 }
283
284
285 mtk_gpio_w32(rg, GPIO_REG_POL, 0);
286
287 dev_info(dev, "registering %d gpios\n", rg->chip.ngpio);
288
289 return 0;
290}
291
292static int
293mediatek_gpio_probe(struct platform_device *pdev)
294{
295 struct device *dev = &pdev->dev;
296 struct device_node *np = dev->of_node;
297 struct mtk *mtk;
298 int i;
299 int ret;
300
301 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL);
302 if (!mtk)
303 return -ENOMEM;
304
305 mtk->base = devm_platform_ioremap_resource(pdev, 0);
306 if (IS_ERR(mtk->base))
307 return PTR_ERR(mtk->base);
308
309 mtk->gpio_irq = irq_of_parse_and_map(np, 0);
310 mtk->dev = dev;
311 platform_set_drvdata(pdev, mtk);
312
313 for (i = 0; i < MTK_BANK_CNT; i++) {
314 ret = mediatek_gpio_bank_probe(dev, np, i);
315 if (ret)
316 return ret;
317 }
318
319 return 0;
320}
321
322static const struct of_device_id mediatek_gpio_match[] = {
323 { .compatible = "mediatek,mt7621-gpio" },
324 {},
325};
326MODULE_DEVICE_TABLE(of, mediatek_gpio_match);
327
328static struct platform_driver mediatek_gpio_driver = {
329 .probe = mediatek_gpio_probe,
330 .driver = {
331 .name = "mt7621_gpio",
332 .of_match_table = mediatek_gpio_match,
333 },
334};
335
336builtin_platform_driver(mediatek_gpio_driver);
337
