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12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/interrupt.h>
15#include <linux/syscore_ops.h>
16#include <linux/err.h>
17#include <linux/clk.h>
18#include <linux/io.h>
19#include <linux/cpu_pm.h>
20#include <linux/device.h>
21#include <linux/pm_runtime.h>
22#include <linux/pm.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/gpio/driver.h>
26#include <linux/bitops.h>
27#include <linux/platform_data/gpio-omap.h>
28
29#define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
30
31struct gpio_regs {
32 u32 sysconfig;
33 u32 irqenable1;
34 u32 irqenable2;
35 u32 wake_en;
36 u32 ctrl;
37 u32 oe;
38 u32 leveldetect0;
39 u32 leveldetect1;
40 u32 risingdetect;
41 u32 fallingdetect;
42 u32 dataout;
43 u32 debounce;
44 u32 debounce_en;
45};
46
47struct gpio_bank {
48 void __iomem *base;
49 const struct omap_gpio_reg_offs *regs;
50
51 int irq;
52 u32 non_wakeup_gpios;
53 u32 enabled_non_wakeup_gpios;
54 struct gpio_regs context;
55 u32 saved_datain;
56 u32 level_mask;
57 u32 toggle_mask;
58 raw_spinlock_t lock;
59 raw_spinlock_t wa_lock;
60 struct gpio_chip chip;
61 struct clk *dbck;
62 struct notifier_block nb;
63 unsigned int is_suspended:1;
64 unsigned int needs_resume:1;
65 u32 mod_usage;
66 u32 irq_usage;
67 u32 dbck_enable_mask;
68 bool dbck_enabled;
69 bool is_mpuio;
70 bool dbck_flag;
71 bool loses_context;
72 bool context_valid;
73 int stride;
74 u32 width;
75 int context_loss_count;
76
77 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
78 int (*get_context_loss_count)(struct device *dev);
79};
80
81#define GPIO_MOD_CTRL_BIT BIT(0)
82
83#define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
84#define LINE_USED(line, offset) (line & (BIT(offset)))
85
86static void omap_gpio_unmask_irq(struct irq_data *d);
87
88static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
89{
90 struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
91 return gpiochip_get_data(chip);
92}
93
94static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set)
95{
96 u32 val = readl_relaxed(reg);
97
98 if (set)
99 val |= mask;
100 else
101 val &= ~mask;
102
103 writel_relaxed(val, reg);
104
105 return val;
106}
107
108static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
109 int is_input)
110{
111 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction,
112 BIT(gpio), is_input);
113}
114
115
116
117static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
118 int enable)
119{
120 void __iomem *reg = bank->base;
121 u32 l = BIT(offset);
122
123 if (enable) {
124 reg += bank->regs->set_dataout;
125 bank->context.dataout |= l;
126 } else {
127 reg += bank->regs->clr_dataout;
128 bank->context.dataout &= ~l;
129 }
130
131 writel_relaxed(l, reg);
132}
133
134
135static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
136 int enable)
137{
138 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout,
139 BIT(offset), enable);
140}
141
142static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
143{
144 if (bank->dbck_enable_mask && !bank->dbck_enabled) {
145 clk_enable(bank->dbck);
146 bank->dbck_enabled = true;
147
148 writel_relaxed(bank->dbck_enable_mask,
149 bank->base + bank->regs->debounce_en);
150 }
151}
152
153static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
154{
155 if (bank->dbck_enable_mask && bank->dbck_enabled) {
156
157
158
159
160
161 writel_relaxed(0, bank->base + bank->regs->debounce_en);
162
163 clk_disable(bank->dbck);
164 bank->dbck_enabled = false;
165 }
166}
167
168
169
170
171
172
173
174
175
176
177
178
179
180static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
181 unsigned debounce)
182{
183 u32 val;
184 u32 l;
185 bool enable = !!debounce;
186
187 if (!bank->dbck_flag)
188 return -ENOTSUPP;
189
190 if (enable) {
191 debounce = DIV_ROUND_UP(debounce, 31) - 1;
192 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
193 return -EINVAL;
194 }
195
196 l = BIT(offset);
197
198 clk_enable(bank->dbck);
199 writel_relaxed(debounce, bank->base + bank->regs->debounce);
200
201 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable);
202 bank->dbck_enable_mask = val;
203
204 clk_disable(bank->dbck);
205
206
207
208
209
210
211
212
213 omap_gpio_dbck_enable(bank);
214 if (bank->dbck_enable_mask) {
215 bank->context.debounce = debounce;
216 bank->context.debounce_en = val;
217 }
218
219 return 0;
220}
221
222
223
224
225
226
227
228
229
230
231
232static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
233{
234 u32 gpio_bit = BIT(offset);
235
236 if (!bank->dbck_flag)
237 return;
238
239 if (!(bank->dbck_enable_mask & gpio_bit))
240 return;
241
242 bank->dbck_enable_mask &= ~gpio_bit;
243 bank->context.debounce_en &= ~gpio_bit;
244 writel_relaxed(bank->context.debounce_en,
245 bank->base + bank->regs->debounce_en);
246
247 if (!bank->dbck_enable_mask) {
248 bank->context.debounce = 0;
249 writel_relaxed(bank->context.debounce, bank->base +
250 bank->regs->debounce);
251 clk_disable(bank->dbck);
252 bank->dbck_enabled = false;
253 }
254}
255
256
257
258
259
260
261
262static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
263{
264 u32 no_wake = bank->non_wakeup_gpios;
265
266 if (no_wake)
267 return !!(~no_wake & gpio_mask);
268
269 return false;
270}
271
272static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
273 unsigned trigger)
274{
275 void __iomem *base = bank->base;
276 u32 gpio_bit = BIT(gpio);
277
278 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit,
279 trigger & IRQ_TYPE_LEVEL_LOW);
280 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit,
281 trigger & IRQ_TYPE_LEVEL_HIGH);
282
283
284
285
286
287
288 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit,
289 trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
290 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit,
291 trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
292
293 bank->context.leveldetect0 =
294 readl_relaxed(bank->base + bank->regs->leveldetect0);
295 bank->context.leveldetect1 =
296 readl_relaxed(bank->base + bank->regs->leveldetect1);
297 bank->context.risingdetect =
298 readl_relaxed(bank->base + bank->regs->risingdetect);
299 bank->context.fallingdetect =
300 readl_relaxed(bank->base + bank->regs->fallingdetect);
301
302 bank->level_mask = bank->context.leveldetect0 |
303 bank->context.leveldetect1;
304
305
306 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
307
308
309
310
311
312
313 if (trigger & IRQ_TYPE_EDGE_BOTH)
314 bank->enabled_non_wakeup_gpios |= gpio_bit;
315 else
316 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
317 }
318}
319
320
321
322
323
324static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
325{
326 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) {
327 void __iomem *reg = bank->base + bank->regs->irqctrl;
328
329 writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg);
330 }
331}
332
333static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
334 unsigned trigger)
335{
336 void __iomem *reg = bank->base;
337 u32 l = 0;
338
339 if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
340 omap_set_gpio_trigger(bank, gpio, trigger);
341 } else if (bank->regs->irqctrl) {
342 reg += bank->regs->irqctrl;
343
344 l = readl_relaxed(reg);
345 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
346 bank->toggle_mask |= BIT(gpio);
347 if (trigger & IRQ_TYPE_EDGE_RISING)
348 l |= BIT(gpio);
349 else if (trigger & IRQ_TYPE_EDGE_FALLING)
350 l &= ~(BIT(gpio));
351 else
352 return -EINVAL;
353
354 writel_relaxed(l, reg);
355 } else if (bank->regs->edgectrl1) {
356 if (gpio & 0x08)
357 reg += bank->regs->edgectrl2;
358 else
359 reg += bank->regs->edgectrl1;
360
361 gpio &= 0x07;
362 l = readl_relaxed(reg);
363 l &= ~(3 << (gpio << 1));
364 if (trigger & IRQ_TYPE_EDGE_RISING)
365 l |= 2 << (gpio << 1);
366 if (trigger & IRQ_TYPE_EDGE_FALLING)
367 l |= BIT(gpio << 1);
368 writel_relaxed(l, reg);
369 }
370 return 0;
371}
372
373static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
374{
375 if (bank->regs->pinctrl) {
376 void __iomem *reg = bank->base + bank->regs->pinctrl;
377
378
379 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
380 }
381
382 if (bank->regs->ctrl && !BANK_USED(bank)) {
383 void __iomem *reg = bank->base + bank->regs->ctrl;
384 u32 ctrl;
385
386 ctrl = readl_relaxed(reg);
387
388 ctrl &= ~GPIO_MOD_CTRL_BIT;
389 writel_relaxed(ctrl, reg);
390 bank->context.ctrl = ctrl;
391 }
392}
393
394static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
395{
396 if (bank->regs->ctrl && !BANK_USED(bank)) {
397 void __iomem *reg = bank->base + bank->regs->ctrl;
398 u32 ctrl;
399
400 ctrl = readl_relaxed(reg);
401
402 ctrl |= GPIO_MOD_CTRL_BIT;
403 writel_relaxed(ctrl, reg);
404 bank->context.ctrl = ctrl;
405 }
406}
407
408static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
409{
410 void __iomem *reg = bank->base + bank->regs->direction;
411
412 return readl_relaxed(reg) & BIT(offset);
413}
414
415static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
416{
417 if (!LINE_USED(bank->mod_usage, offset)) {
418 omap_enable_gpio_module(bank, offset);
419 omap_set_gpio_direction(bank, offset, 1);
420 }
421 bank->irq_usage |= BIT(offset);
422}
423
424static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
425{
426 struct gpio_bank *bank = omap_irq_data_get_bank(d);
427 int retval;
428 unsigned long flags;
429 unsigned offset = d->hwirq;
430
431 if (type & ~IRQ_TYPE_SENSE_MASK)
432 return -EINVAL;
433
434 if (!bank->regs->leveldetect0 &&
435 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
436 return -EINVAL;
437
438 raw_spin_lock_irqsave(&bank->lock, flags);
439 retval = omap_set_gpio_triggering(bank, offset, type);
440 if (retval) {
441 raw_spin_unlock_irqrestore(&bank->lock, flags);
442 goto error;
443 }
444 omap_gpio_init_irq(bank, offset);
445 if (!omap_gpio_is_input(bank, offset)) {
446 raw_spin_unlock_irqrestore(&bank->lock, flags);
447 retval = -EINVAL;
448 goto error;
449 }
450 raw_spin_unlock_irqrestore(&bank->lock, flags);
451
452 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
453 irq_set_handler_locked(d, handle_level_irq);
454 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
455
456
457
458
459
460
461 irq_set_handler_locked(d, handle_simple_irq);
462
463 return 0;
464
465error:
466 return retval;
467}
468
469static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
470{
471 void __iomem *reg = bank->base;
472
473 reg += bank->regs->irqstatus;
474 writel_relaxed(gpio_mask, reg);
475
476
477 if (bank->regs->irqstatus2) {
478 reg = bank->base + bank->regs->irqstatus2;
479 writel_relaxed(gpio_mask, reg);
480 }
481
482
483 readl_relaxed(reg);
484}
485
486static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
487 unsigned offset)
488{
489 omap_clear_gpio_irqbank(bank, BIT(offset));
490}
491
492static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
493{
494 void __iomem *reg = bank->base;
495 u32 l;
496 u32 mask = (BIT(bank->width)) - 1;
497
498 reg += bank->regs->irqenable;
499 l = readl_relaxed(reg);
500 if (bank->regs->irqenable_inv)
501 l = ~l;
502 l &= mask;
503 return l;
504}
505
506static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
507 unsigned offset, int enable)
508{
509 void __iomem *reg = bank->base;
510 u32 gpio_mask = BIT(offset);
511
512 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) {
513 if (enable) {
514 reg += bank->regs->set_irqenable;
515 bank->context.irqenable1 |= gpio_mask;
516 } else {
517 reg += bank->regs->clr_irqenable;
518 bank->context.irqenable1 &= ~gpio_mask;
519 }
520 writel_relaxed(gpio_mask, reg);
521 } else {
522 bank->context.irqenable1 =
523 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask,
524 enable ^ bank->regs->irqenable_inv);
525 }
526
527
528
529
530
531
532
533 if (bank->regs->wkup_en &&
534 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) {
535 bank->context.wake_en =
536 omap_gpio_rmw(bank->base + bank->regs->wkup_en,
537 gpio_mask, enable);
538 }
539}
540
541
542static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
543{
544 struct gpio_bank *bank = omap_irq_data_get_bank(d);
545
546 return irq_set_irq_wake(bank->irq, enable);
547}
548
549
550
551
552
553
554
555
556
557
558static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
559{
560 void __iomem *isr_reg = NULL;
561 u32 enabled, isr, edge;
562 unsigned int bit;
563 struct gpio_bank *bank = gpiobank;
564 unsigned long wa_lock_flags;
565 unsigned long lock_flags;
566
567 isr_reg = bank->base + bank->regs->irqstatus;
568 if (WARN_ON(!isr_reg))
569 goto exit;
570
571 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
572 "gpio irq%i while runtime suspended?\n", irq))
573 return IRQ_NONE;
574
575 while (1) {
576 raw_spin_lock_irqsave(&bank->lock, lock_flags);
577
578 enabled = omap_get_gpio_irqbank_mask(bank);
579 isr = readl_relaxed(isr_reg) & enabled;
580
581
582
583
584
585
586 edge = isr & ~bank->level_mask;
587 if (edge)
588 omap_clear_gpio_irqbank(bank, edge);
589
590 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
591
592 if (!isr)
593 break;
594
595 while (isr) {
596 bit = __ffs(isr);
597 isr &= ~(BIT(bit));
598
599 raw_spin_lock_irqsave(&bank->lock, lock_flags);
600
601
602
603
604
605
606
607 if (bank->toggle_mask & (BIT(bit)))
608 omap_toggle_gpio_edge_triggering(bank, bit);
609
610 raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
611
612 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
613
614 generic_handle_domain_irq(bank->chip.irq.domain, bit);
615
616 raw_spin_unlock_irqrestore(&bank->wa_lock,
617 wa_lock_flags);
618 }
619 }
620exit:
621 return IRQ_HANDLED;
622}
623
624static unsigned int omap_gpio_irq_startup(struct irq_data *d)
625{
626 struct gpio_bank *bank = omap_irq_data_get_bank(d);
627 unsigned long flags;
628 unsigned offset = d->hwirq;
629
630 raw_spin_lock_irqsave(&bank->lock, flags);
631
632 if (!LINE_USED(bank->mod_usage, offset))
633 omap_set_gpio_direction(bank, offset, 1);
634 omap_enable_gpio_module(bank, offset);
635 bank->irq_usage |= BIT(offset);
636
637 raw_spin_unlock_irqrestore(&bank->lock, flags);
638 omap_gpio_unmask_irq(d);
639
640 return 0;
641}
642
643static void omap_gpio_irq_shutdown(struct irq_data *d)
644{
645 struct gpio_bank *bank = omap_irq_data_get_bank(d);
646 unsigned long flags;
647 unsigned offset = d->hwirq;
648
649 raw_spin_lock_irqsave(&bank->lock, flags);
650 bank->irq_usage &= ~(BIT(offset));
651 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
652 omap_clear_gpio_irqstatus(bank, offset);
653 omap_set_gpio_irqenable(bank, offset, 0);
654 if (!LINE_USED(bank->mod_usage, offset))
655 omap_clear_gpio_debounce(bank, offset);
656 omap_disable_gpio_module(bank, offset);
657 raw_spin_unlock_irqrestore(&bank->lock, flags);
658}
659
660static void omap_gpio_irq_bus_lock(struct irq_data *data)
661{
662 struct gpio_bank *bank = omap_irq_data_get_bank(data);
663
664 pm_runtime_get_sync(bank->chip.parent);
665}
666
667static void gpio_irq_bus_sync_unlock(struct irq_data *data)
668{
669 struct gpio_bank *bank = omap_irq_data_get_bank(data);
670
671 pm_runtime_put(bank->chip.parent);
672}
673
674static void omap_gpio_mask_irq(struct irq_data *d)
675{
676 struct gpio_bank *bank = omap_irq_data_get_bank(d);
677 unsigned offset = d->hwirq;
678 unsigned long flags;
679
680 raw_spin_lock_irqsave(&bank->lock, flags);
681 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
682 omap_set_gpio_irqenable(bank, offset, 0);
683 raw_spin_unlock_irqrestore(&bank->lock, flags);
684}
685
686static void omap_gpio_unmask_irq(struct irq_data *d)
687{
688 struct gpio_bank *bank = omap_irq_data_get_bank(d);
689 unsigned offset = d->hwirq;
690 u32 trigger = irqd_get_trigger_type(d);
691 unsigned long flags;
692
693 raw_spin_lock_irqsave(&bank->lock, flags);
694 omap_set_gpio_irqenable(bank, offset, 1);
695
696
697
698
699
700
701 if (bank->regs->leveldetect0 && bank->regs->wkup_en &&
702 trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
703 omap_clear_gpio_irqstatus(bank, offset);
704
705 if (trigger)
706 omap_set_gpio_triggering(bank, offset, trigger);
707
708 raw_spin_unlock_irqrestore(&bank->lock, flags);
709}
710
711
712
713static int omap_mpuio_suspend_noirq(struct device *dev)
714{
715 struct gpio_bank *bank = dev_get_drvdata(dev);
716 void __iomem *mask_reg = bank->base +
717 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
718 unsigned long flags;
719
720 raw_spin_lock_irqsave(&bank->lock, flags);
721 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
722 raw_spin_unlock_irqrestore(&bank->lock, flags);
723
724 return 0;
725}
726
727static int omap_mpuio_resume_noirq(struct device *dev)
728{
729 struct gpio_bank *bank = dev_get_drvdata(dev);
730 void __iomem *mask_reg = bank->base +
731 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
732 unsigned long flags;
733
734 raw_spin_lock_irqsave(&bank->lock, flags);
735 writel_relaxed(bank->context.wake_en, mask_reg);
736 raw_spin_unlock_irqrestore(&bank->lock, flags);
737
738 return 0;
739}
740
741static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
742 .suspend_noirq = omap_mpuio_suspend_noirq,
743 .resume_noirq = omap_mpuio_resume_noirq,
744};
745
746
747static struct platform_driver omap_mpuio_driver = {
748 .driver = {
749 .name = "mpuio",
750 .pm = &omap_mpuio_dev_pm_ops,
751 },
752};
753
754static struct platform_device omap_mpuio_device = {
755 .name = "mpuio",
756 .id = -1,
757 .dev = {
758 .driver = &omap_mpuio_driver.driver,
759 }
760
761};
762
763static inline void omap_mpuio_init(struct gpio_bank *bank)
764{
765 platform_set_drvdata(&omap_mpuio_device, bank);
766
767 if (platform_driver_register(&omap_mpuio_driver) == 0)
768 (void) platform_device_register(&omap_mpuio_device);
769}
770
771
772
773static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
774{
775 struct gpio_bank *bank = gpiochip_get_data(chip);
776 unsigned long flags;
777
778 pm_runtime_get_sync(chip->parent);
779
780 raw_spin_lock_irqsave(&bank->lock, flags);
781 omap_enable_gpio_module(bank, offset);
782 bank->mod_usage |= BIT(offset);
783 raw_spin_unlock_irqrestore(&bank->lock, flags);
784
785 return 0;
786}
787
788static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
789{
790 struct gpio_bank *bank = gpiochip_get_data(chip);
791 unsigned long flags;
792
793 raw_spin_lock_irqsave(&bank->lock, flags);
794 bank->mod_usage &= ~(BIT(offset));
795 if (!LINE_USED(bank->irq_usage, offset)) {
796 omap_set_gpio_direction(bank, offset, 1);
797 omap_clear_gpio_debounce(bank, offset);
798 }
799 omap_disable_gpio_module(bank, offset);
800 raw_spin_unlock_irqrestore(&bank->lock, flags);
801
802 pm_runtime_put(chip->parent);
803}
804
805static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
806{
807 struct gpio_bank *bank = gpiochip_get_data(chip);
808
809 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset))
810 return GPIO_LINE_DIRECTION_IN;
811
812 return GPIO_LINE_DIRECTION_OUT;
813}
814
815static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
816{
817 struct gpio_bank *bank;
818 unsigned long flags;
819
820 bank = gpiochip_get_data(chip);
821 raw_spin_lock_irqsave(&bank->lock, flags);
822 omap_set_gpio_direction(bank, offset, 1);
823 raw_spin_unlock_irqrestore(&bank->lock, flags);
824 return 0;
825}
826
827static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
828{
829 struct gpio_bank *bank = gpiochip_get_data(chip);
830 void __iomem *reg;
831
832 if (omap_gpio_is_input(bank, offset))
833 reg = bank->base + bank->regs->datain;
834 else
835 reg = bank->base + bank->regs->dataout;
836
837 return (readl_relaxed(reg) & BIT(offset)) != 0;
838}
839
840static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
841{
842 struct gpio_bank *bank;
843 unsigned long flags;
844
845 bank = gpiochip_get_data(chip);
846 raw_spin_lock_irqsave(&bank->lock, flags);
847 bank->set_dataout(bank, offset, value);
848 omap_set_gpio_direction(bank, offset, 0);
849 raw_spin_unlock_irqrestore(&bank->lock, flags);
850 return 0;
851}
852
853static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
854 unsigned long *bits)
855{
856 struct gpio_bank *bank = gpiochip_get_data(chip);
857 void __iomem *base = bank->base;
858 u32 direction, m, val = 0;
859
860 direction = readl_relaxed(base + bank->regs->direction);
861
862 m = direction & *mask;
863 if (m)
864 val |= readl_relaxed(base + bank->regs->datain) & m;
865
866 m = ~direction & *mask;
867 if (m)
868 val |= readl_relaxed(base + bank->regs->dataout) & m;
869
870 *bits = val;
871
872 return 0;
873}
874
875static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
876 unsigned debounce)
877{
878 struct gpio_bank *bank;
879 unsigned long flags;
880 int ret;
881
882 bank = gpiochip_get_data(chip);
883
884 raw_spin_lock_irqsave(&bank->lock, flags);
885 ret = omap2_set_gpio_debounce(bank, offset, debounce);
886 raw_spin_unlock_irqrestore(&bank->lock, flags);
887
888 if (ret)
889 dev_info(chip->parent,
890 "Could not set line %u debounce to %u microseconds (%d)",
891 offset, debounce, ret);
892
893 return ret;
894}
895
896static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
897 unsigned long config)
898{
899 u32 debounce;
900 int ret = -ENOTSUPP;
901
902 switch (pinconf_to_config_param(config)) {
903 case PIN_CONFIG_BIAS_DISABLE:
904 case PIN_CONFIG_BIAS_PULL_UP:
905 case PIN_CONFIG_BIAS_PULL_DOWN:
906 ret = gpiochip_generic_config(chip, offset, config);
907 break;
908 case PIN_CONFIG_INPUT_DEBOUNCE:
909 debounce = pinconf_to_config_argument(config);
910 ret = omap_gpio_debounce(chip, offset, debounce);
911 break;
912 default:
913 break;
914 }
915
916 return ret;
917}
918
919static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
920{
921 struct gpio_bank *bank;
922 unsigned long flags;
923
924 bank = gpiochip_get_data(chip);
925 raw_spin_lock_irqsave(&bank->lock, flags);
926 bank->set_dataout(bank, offset, value);
927 raw_spin_unlock_irqrestore(&bank->lock, flags);
928}
929
930static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
931 unsigned long *bits)
932{
933 struct gpio_bank *bank = gpiochip_get_data(chip);
934 void __iomem *reg = bank->base + bank->regs->dataout;
935 unsigned long flags;
936 u32 l;
937
938 raw_spin_lock_irqsave(&bank->lock, flags);
939 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
940 writel_relaxed(l, reg);
941 bank->context.dataout = l;
942 raw_spin_unlock_irqrestore(&bank->lock, flags);
943}
944
945
946
947static void omap_gpio_show_rev(struct gpio_bank *bank)
948{
949 static bool called;
950 u32 rev;
951
952 if (called || bank->regs->revision == USHRT_MAX)
953 return;
954
955 rev = readw_relaxed(bank->base + bank->regs->revision);
956 pr_info("OMAP GPIO hardware version %d.%d\n",
957 (rev >> 4) & 0x0f, rev & 0x0f);
958
959 called = true;
960}
961
962static void omap_gpio_mod_init(struct gpio_bank *bank)
963{
964 void __iomem *base = bank->base;
965 u32 l = 0xffffffff;
966
967 if (bank->width == 16)
968 l = 0xffff;
969
970 if (bank->is_mpuio) {
971 writel_relaxed(l, bank->base + bank->regs->irqenable);
972 return;
973 }
974
975 omap_gpio_rmw(base + bank->regs->irqenable, l,
976 bank->regs->irqenable_inv);
977 omap_gpio_rmw(base + bank->regs->irqstatus, l,
978 !bank->regs->irqenable_inv);
979 if (bank->regs->debounce_en)
980 writel_relaxed(0, base + bank->regs->debounce_en);
981
982
983 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
984
985 if (bank->regs->ctrl)
986 writel_relaxed(0, base + bank->regs->ctrl);
987}
988
989static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
990{
991 struct gpio_irq_chip *irq;
992 static int gpio;
993 const char *label;
994 int irq_base = 0;
995 int ret;
996
997
998
999
1000
1001 bank->chip.request = omap_gpio_request;
1002 bank->chip.free = omap_gpio_free;
1003 bank->chip.get_direction = omap_gpio_get_direction;
1004 bank->chip.direction_input = omap_gpio_input;
1005 bank->chip.get = omap_gpio_get;
1006 bank->chip.get_multiple = omap_gpio_get_multiple;
1007 bank->chip.direction_output = omap_gpio_output;
1008 bank->chip.set_config = omap_gpio_set_config;
1009 bank->chip.set = omap_gpio_set;
1010 bank->chip.set_multiple = omap_gpio_set_multiple;
1011 if (bank->is_mpuio) {
1012 bank->chip.label = "mpuio";
1013 if (bank->regs->wkup_en)
1014 bank->chip.parent = &omap_mpuio_device.dev;
1015 bank->chip.base = OMAP_MPUIO(0);
1016 } else {
1017 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1018 gpio, gpio + bank->width - 1);
1019 if (!label)
1020 return -ENOMEM;
1021 bank->chip.label = label;
1022 bank->chip.base = gpio;
1023 }
1024 bank->chip.ngpio = bank->width;
1025
1026#ifdef CONFIG_ARCH_OMAP1
1027
1028
1029
1030
1031 irq_base = devm_irq_alloc_descs(bank->chip.parent,
1032 -1, 0, bank->width, 0);
1033 if (irq_base < 0) {
1034 dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1035 return -ENODEV;
1036 }
1037#endif
1038
1039
1040 if (bank->is_mpuio && !bank->regs->wkup_en)
1041 irqc->irq_set_wake = NULL;
1042
1043 irq = &bank->chip.irq;
1044 irq->chip = irqc;
1045 irq->handler = handle_bad_irq;
1046 irq->default_type = IRQ_TYPE_NONE;
1047 irq->num_parents = 1;
1048 irq->parents = &bank->irq;
1049 irq->first = irq_base;
1050
1051 ret = gpiochip_add_data(&bank->chip, bank);
1052 if (ret)
1053 return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n");
1054
1055 ret = devm_request_irq(bank->chip.parent, bank->irq,
1056 omap_gpio_irq_handler,
1057 0, dev_name(bank->chip.parent), bank);
1058 if (ret)
1059 gpiochip_remove(&bank->chip);
1060
1061 if (!bank->is_mpuio)
1062 gpio += bank->width;
1063
1064 return ret;
1065}
1066
1067static void omap_gpio_init_context(struct gpio_bank *p)
1068{
1069 const struct omap_gpio_reg_offs *regs = p->regs;
1070 void __iomem *base = p->base;
1071
1072 p->context.sysconfig = readl_relaxed(base + regs->sysconfig);
1073 p->context.ctrl = readl_relaxed(base + regs->ctrl);
1074 p->context.oe = readl_relaxed(base + regs->direction);
1075 p->context.wake_en = readl_relaxed(base + regs->wkup_en);
1076 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0);
1077 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1);
1078 p->context.risingdetect = readl_relaxed(base + regs->risingdetect);
1079 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1080 p->context.irqenable1 = readl_relaxed(base + regs->irqenable);
1081 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2);
1082 p->context.dataout = readl_relaxed(base + regs->dataout);
1083
1084 p->context_valid = true;
1085}
1086
1087static void omap_gpio_restore_context(struct gpio_bank *bank)
1088{
1089 const struct omap_gpio_reg_offs *regs = bank->regs;
1090 void __iomem *base = bank->base;
1091
1092 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig);
1093 writel_relaxed(bank->context.wake_en, base + regs->wkup_en);
1094 writel_relaxed(bank->context.ctrl, base + regs->ctrl);
1095 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0);
1096 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1);
1097 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect);
1098 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect);
1099 writel_relaxed(bank->context.dataout, base + regs->dataout);
1100 writel_relaxed(bank->context.oe, base + regs->direction);
1101
1102 if (bank->dbck_enable_mask) {
1103 writel_relaxed(bank->context.debounce, base + regs->debounce);
1104 writel_relaxed(bank->context.debounce_en,
1105 base + regs->debounce_en);
1106 }
1107
1108 writel_relaxed(bank->context.irqenable1, base + regs->irqenable);
1109 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2);
1110}
1111
1112static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1113{
1114 struct device *dev = bank->chip.parent;
1115 void __iomem *base = bank->base;
1116 u32 mask, nowake;
1117
1118 bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1119
1120
1121 if (bank->loses_context)
1122 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig);
1123
1124 if (!bank->enabled_non_wakeup_gpios)
1125 goto update_gpio_context_count;
1126
1127
1128 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect;
1129 mask &= ~bank->context.risingdetect;
1130 bank->saved_datain |= mask;
1131
1132
1133 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect;
1134 mask &= ~bank->context.fallingdetect;
1135 bank->saved_datain &= ~mask;
1136
1137 if (!may_lose_context)
1138 goto update_gpio_context_count;
1139
1140
1141
1142
1143
1144
1145 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1146 nowake = bank->enabled_non_wakeup_gpios;
1147 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake);
1148 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake);
1149 }
1150
1151update_gpio_context_count:
1152 if (bank->get_context_loss_count)
1153 bank->context_loss_count =
1154 bank->get_context_loss_count(dev);
1155
1156 omap_gpio_dbck_disable(bank);
1157}
1158
1159static void omap_gpio_unidle(struct gpio_bank *bank)
1160{
1161 struct device *dev = bank->chip.parent;
1162 u32 l = 0, gen, gen0, gen1;
1163 int c;
1164
1165
1166
1167
1168
1169
1170 if (bank->loses_context && !bank->context_valid) {
1171 omap_gpio_init_context(bank);
1172
1173 if (bank->get_context_loss_count)
1174 bank->context_loss_count =
1175 bank->get_context_loss_count(dev);
1176 }
1177
1178 omap_gpio_dbck_enable(bank);
1179
1180 if (bank->loses_context) {
1181 if (!bank->get_context_loss_count) {
1182 omap_gpio_restore_context(bank);
1183 } else {
1184 c = bank->get_context_loss_count(dev);
1185 if (c != bank->context_loss_count) {
1186 omap_gpio_restore_context(bank);
1187 } else {
1188 return;
1189 }
1190 }
1191 } else {
1192
1193 writel_relaxed(bank->context.fallingdetect,
1194 bank->base + bank->regs->fallingdetect);
1195 writel_relaxed(bank->context.risingdetect,
1196 bank->base + bank->regs->risingdetect);
1197 }
1198
1199 l = readl_relaxed(bank->base + bank->regs->datain);
1200
1201
1202
1203
1204
1205
1206
1207 l ^= bank->saved_datain;
1208 l &= bank->enabled_non_wakeup_gpios;
1209
1210
1211
1212
1213
1214 gen0 = l & bank->context.fallingdetect;
1215 gen0 &= bank->saved_datain;
1216
1217 gen1 = l & bank->context.risingdetect;
1218 gen1 &= ~(bank->saved_datain);
1219
1220
1221 gen = l & (~(bank->context.fallingdetect) &
1222 ~(bank->context.risingdetect));
1223
1224 gen |= gen0 | gen1;
1225
1226 if (gen) {
1227 u32 old0, old1;
1228
1229 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1230 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1231
1232 if (!bank->regs->irqstatus_raw0) {
1233 writel_relaxed(old0 | gen, bank->base +
1234 bank->regs->leveldetect0);
1235 writel_relaxed(old1 | gen, bank->base +
1236 bank->regs->leveldetect1);
1237 }
1238
1239 if (bank->regs->irqstatus_raw0) {
1240 writel_relaxed(old0 | l, bank->base +
1241 bank->regs->leveldetect0);
1242 writel_relaxed(old1 | l, bank->base +
1243 bank->regs->leveldetect1);
1244 }
1245 writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1246 writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1247 }
1248}
1249
1250static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1251 unsigned long cmd, void *v)
1252{
1253 struct gpio_bank *bank;
1254 unsigned long flags;
1255 int ret = NOTIFY_OK;
1256 u32 isr, mask;
1257
1258 bank = container_of(nb, struct gpio_bank, nb);
1259
1260 raw_spin_lock_irqsave(&bank->lock, flags);
1261 if (bank->is_suspended)
1262 goto out_unlock;
1263
1264 switch (cmd) {
1265 case CPU_CLUSTER_PM_ENTER:
1266 mask = omap_get_gpio_irqbank_mask(bank);
1267 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask;
1268 if (isr) {
1269 ret = NOTIFY_BAD;
1270 break;
1271 }
1272 omap_gpio_idle(bank, true);
1273 break;
1274 case CPU_CLUSTER_PM_ENTER_FAILED:
1275 case CPU_CLUSTER_PM_EXIT:
1276 omap_gpio_unidle(bank);
1277 break;
1278 }
1279
1280out_unlock:
1281 raw_spin_unlock_irqrestore(&bank->lock, flags);
1282
1283 return ret;
1284}
1285
1286static const struct omap_gpio_reg_offs omap2_gpio_regs = {
1287 .revision = OMAP24XX_GPIO_REVISION,
1288 .sysconfig = OMAP24XX_GPIO_SYSCONFIG,
1289 .direction = OMAP24XX_GPIO_OE,
1290 .datain = OMAP24XX_GPIO_DATAIN,
1291 .dataout = OMAP24XX_GPIO_DATAOUT,
1292 .set_dataout = OMAP24XX_GPIO_SETDATAOUT,
1293 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT,
1294 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1,
1295 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2,
1296 .irqenable = OMAP24XX_GPIO_IRQENABLE1,
1297 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2,
1298 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1,
1299 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1,
1300 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL,
1301 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN,
1302 .ctrl = OMAP24XX_GPIO_CTRL,
1303 .wkup_en = OMAP24XX_GPIO_WAKE_EN,
1304 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0,
1305 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1,
1306 .risingdetect = OMAP24XX_GPIO_RISINGDETECT,
1307 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT,
1308};
1309
1310static const struct omap_gpio_reg_offs omap4_gpio_regs = {
1311 .revision = OMAP4_GPIO_REVISION,
1312 .sysconfig = OMAP4_GPIO_SYSCONFIG,
1313 .direction = OMAP4_GPIO_OE,
1314 .datain = OMAP4_GPIO_DATAIN,
1315 .dataout = OMAP4_GPIO_DATAOUT,
1316 .set_dataout = OMAP4_GPIO_SETDATAOUT,
1317 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT,
1318 .irqstatus = OMAP4_GPIO_IRQSTATUS0,
1319 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1,
1320 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0,
1321 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1,
1322 .irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1323 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1,
1324 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0,
1325 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0,
1326 .debounce = OMAP4_GPIO_DEBOUNCINGTIME,
1327 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE,
1328 .ctrl = OMAP4_GPIO_CTRL,
1329 .wkup_en = OMAP4_GPIO_IRQWAKEN0,
1330 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0,
1331 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1,
1332 .risingdetect = OMAP4_GPIO_RISINGDETECT,
1333 .fallingdetect = OMAP4_GPIO_FALLINGDETECT,
1334};
1335
1336static const struct omap_gpio_platform_data omap2_pdata = {
1337 .regs = &omap2_gpio_regs,
1338 .bank_width = 32,
1339 .dbck_flag = false,
1340};
1341
1342static const struct omap_gpio_platform_data omap3_pdata = {
1343 .regs = &omap2_gpio_regs,
1344 .bank_width = 32,
1345 .dbck_flag = true,
1346};
1347
1348static const struct omap_gpio_platform_data omap4_pdata = {
1349 .regs = &omap4_gpio_regs,
1350 .bank_width = 32,
1351 .dbck_flag = true,
1352};
1353
1354static const struct of_device_id omap_gpio_match[] = {
1355 {
1356 .compatible = "ti,omap4-gpio",
1357 .data = &omap4_pdata,
1358 },
1359 {
1360 .compatible = "ti,omap3-gpio",
1361 .data = &omap3_pdata,
1362 },
1363 {
1364 .compatible = "ti,omap2-gpio",
1365 .data = &omap2_pdata,
1366 },
1367 { },
1368};
1369MODULE_DEVICE_TABLE(of, omap_gpio_match);
1370
1371static int omap_gpio_probe(struct platform_device *pdev)
1372{
1373 struct device *dev = &pdev->dev;
1374 struct device_node *node = dev->of_node;
1375 const struct omap_gpio_platform_data *pdata;
1376 struct gpio_bank *bank;
1377 struct irq_chip *irqc;
1378 int ret;
1379
1380 pdata = device_get_match_data(dev);
1381
1382 pdata = pdata ?: dev_get_platdata(dev);
1383 if (!pdata)
1384 return -EINVAL;
1385
1386 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1387 if (!bank)
1388 return -ENOMEM;
1389
1390 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1391 if (!irqc)
1392 return -ENOMEM;
1393
1394 irqc->irq_startup = omap_gpio_irq_startup,
1395 irqc->irq_shutdown = omap_gpio_irq_shutdown,
1396 irqc->irq_ack = dummy_irq_chip.irq_ack,
1397 irqc->irq_mask = omap_gpio_mask_irq,
1398 irqc->irq_unmask = omap_gpio_unmask_irq,
1399 irqc->irq_set_type = omap_gpio_irq_type,
1400 irqc->irq_set_wake = omap_gpio_wake_enable,
1401 irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1402 irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1403 irqc->name = dev_name(&pdev->dev);
1404 irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1405 irqc->parent_device = dev;
1406
1407 bank->irq = platform_get_irq(pdev, 0);
1408 if (bank->irq <= 0) {
1409 if (!bank->irq)
1410 bank->irq = -ENXIO;
1411 return dev_err_probe(dev, bank->irq, "can't get irq resource\n");
1412 }
1413
1414 bank->chip.parent = dev;
1415 bank->chip.owner = THIS_MODULE;
1416 bank->dbck_flag = pdata->dbck_flag;
1417 bank->stride = pdata->bank_stride;
1418 bank->width = pdata->bank_width;
1419 bank->is_mpuio = pdata->is_mpuio;
1420 bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1421 bank->regs = pdata->regs;
1422#ifdef CONFIG_OF_GPIO
1423 bank->chip.of_node = of_node_get(node);
1424#endif
1425
1426 if (node) {
1427 if (!of_property_read_bool(node, "ti,gpio-always-on"))
1428 bank->loses_context = true;
1429 } else {
1430 bank->loses_context = pdata->loses_context;
1431
1432 if (bank->loses_context)
1433 bank->get_context_loss_count =
1434 pdata->get_context_loss_count;
1435 }
1436
1437 if (bank->regs->set_dataout && bank->regs->clr_dataout)
1438 bank->set_dataout = omap_set_gpio_dataout_reg;
1439 else
1440 bank->set_dataout = omap_set_gpio_dataout_mask;
1441
1442 raw_spin_lock_init(&bank->lock);
1443 raw_spin_lock_init(&bank->wa_lock);
1444
1445
1446 bank->base = devm_platform_ioremap_resource(pdev, 0);
1447 if (IS_ERR(bank->base)) {
1448 return PTR_ERR(bank->base);
1449 }
1450
1451 if (bank->dbck_flag) {
1452 bank->dbck = devm_clk_get(dev, "dbclk");
1453 if (IS_ERR(bank->dbck)) {
1454 dev_err(dev,
1455 "Could not get gpio dbck. Disable debounce\n");
1456 bank->dbck_flag = false;
1457 } else {
1458 clk_prepare(bank->dbck);
1459 }
1460 }
1461
1462 platform_set_drvdata(pdev, bank);
1463
1464 pm_runtime_enable(dev);
1465 pm_runtime_get_sync(dev);
1466
1467 if (bank->is_mpuio)
1468 omap_mpuio_init(bank);
1469
1470 omap_gpio_mod_init(bank);
1471
1472 ret = omap_gpio_chip_init(bank, irqc);
1473 if (ret) {
1474 pm_runtime_put_sync(dev);
1475 pm_runtime_disable(dev);
1476 if (bank->dbck_flag)
1477 clk_unprepare(bank->dbck);
1478 return ret;
1479 }
1480
1481 omap_gpio_show_rev(bank);
1482
1483 bank->nb.notifier_call = gpio_omap_cpu_notifier;
1484 cpu_pm_register_notifier(&bank->nb);
1485
1486 pm_runtime_put(dev);
1487
1488 return 0;
1489}
1490
1491static int omap_gpio_remove(struct platform_device *pdev)
1492{
1493 struct gpio_bank *bank = platform_get_drvdata(pdev);
1494
1495 cpu_pm_unregister_notifier(&bank->nb);
1496 gpiochip_remove(&bank->chip);
1497 pm_runtime_disable(&pdev->dev);
1498 if (bank->dbck_flag)
1499 clk_unprepare(bank->dbck);
1500
1501 return 0;
1502}
1503
1504static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
1505{
1506 struct gpio_bank *bank = dev_get_drvdata(dev);
1507 unsigned long flags;
1508
1509 raw_spin_lock_irqsave(&bank->lock, flags);
1510 omap_gpio_idle(bank, true);
1511 bank->is_suspended = true;
1512 raw_spin_unlock_irqrestore(&bank->lock, flags);
1513
1514 return 0;
1515}
1516
1517static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
1518{
1519 struct gpio_bank *bank = dev_get_drvdata(dev);
1520 unsigned long flags;
1521
1522 raw_spin_lock_irqsave(&bank->lock, flags);
1523 omap_gpio_unidle(bank);
1524 bank->is_suspended = false;
1525 raw_spin_unlock_irqrestore(&bank->lock, flags);
1526
1527 return 0;
1528}
1529
1530static int __maybe_unused omap_gpio_suspend(struct device *dev)
1531{
1532 struct gpio_bank *bank = dev_get_drvdata(dev);
1533
1534 if (bank->is_suspended)
1535 return 0;
1536
1537 bank->needs_resume = 1;
1538
1539 return omap_gpio_runtime_suspend(dev);
1540}
1541
1542static int __maybe_unused omap_gpio_resume(struct device *dev)
1543{
1544 struct gpio_bank *bank = dev_get_drvdata(dev);
1545
1546 if (!bank->needs_resume)
1547 return 0;
1548
1549 bank->needs_resume = 0;
1550
1551 return omap_gpio_runtime_resume(dev);
1552}
1553
1554static const struct dev_pm_ops gpio_pm_ops = {
1555 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1556 NULL)
1557 SET_LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume)
1558};
1559
1560static struct platform_driver omap_gpio_driver = {
1561 .probe = omap_gpio_probe,
1562 .remove = omap_gpio_remove,
1563 .driver = {
1564 .name = "omap_gpio",
1565 .pm = &gpio_pm_ops,
1566 .of_match_table = omap_gpio_match,
1567 },
1568};
1569
1570
1571
1572
1573
1574
1575static int __init omap_gpio_drv_reg(void)
1576{
1577 return platform_driver_register(&omap_gpio_driver);
1578}
1579postcore_initcall(omap_gpio_drv_reg);
1580
1581static void __exit omap_gpio_exit(void)
1582{
1583 platform_driver_unregister(&omap_gpio_driver);
1584}
1585module_exit(omap_gpio_exit);
1586
1587MODULE_DESCRIPTION("omap gpio driver");
1588MODULE_ALIAS("platform:gpio-omap");
1589MODULE_LICENSE("GPL v2");
1590