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25#include <drm/amdgpu_drm.h>
26#include <drm/drm_aperture.h>
27#include <drm/drm_drv.h>
28#include <drm/drm_gem.h>
29#include <drm/drm_vblank.h>
30#include <drm/drm_managed.h>
31#include "amdgpu_drv.h"
32
33#include <drm/drm_pciids.h>
34#include <linux/console.h>
35#include <linux/module.h>
36#include <linux/pm_runtime.h>
37#include <linux/vga_switcheroo.h>
38#include <drm/drm_probe_helper.h>
39#include <linux/mmu_notifier.h>
40#include <linux/suspend.h>
41
42#include "amdgpu.h"
43#include "amdgpu_irq.h"
44#include "amdgpu_dma_buf.h"
45#include "amdgpu_sched.h"
46#include "amdgpu_fdinfo.h"
47#include "amdgpu_amdkfd.h"
48
49#include "amdgpu_ras.h"
50#include "amdgpu_xgmi.h"
51#include "amdgpu_reset.h"
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99
100#define KMS_DRIVER_MAJOR 3
101#define KMS_DRIVER_MINOR 42
102#define KMS_DRIVER_PATCHLEVEL 0
103
104int amdgpu_vram_limit;
105int amdgpu_vis_vram_limit;
106int amdgpu_gart_size = -1;
107int amdgpu_gtt_size = -1;
108int amdgpu_moverate = -1;
109int amdgpu_benchmarking;
110int amdgpu_testing;
111int amdgpu_audio = -1;
112int amdgpu_disp_priority;
113int amdgpu_hw_i2c;
114int amdgpu_pcie_gen2 = -1;
115int amdgpu_msi = -1;
116char amdgpu_lockup_timeout[AMDGPU_MAX_TIMEOUT_PARAM_LENGTH];
117int amdgpu_dpm = -1;
118int amdgpu_fw_load_type = -1;
119int amdgpu_aspm = -1;
120int amdgpu_runtime_pm = -1;
121uint amdgpu_ip_block_mask = 0xffffffff;
122int amdgpu_bapm = -1;
123int amdgpu_deep_color;
124int amdgpu_vm_size = -1;
125int amdgpu_vm_fragment_size = -1;
126int amdgpu_vm_block_size = -1;
127int amdgpu_vm_fault_stop;
128int amdgpu_vm_debug;
129int amdgpu_vm_update_mode = -1;
130int amdgpu_exp_hw_support;
131int amdgpu_dc = -1;
132int amdgpu_sched_jobs = 32;
133int amdgpu_sched_hw_submission = 2;
134uint amdgpu_pcie_gen_cap;
135uint amdgpu_pcie_lane_cap;
136uint amdgpu_cg_mask = 0xffffffff;
137uint amdgpu_pg_mask = 0xffffffff;
138uint amdgpu_sdma_phase_quantum = 32;
139char *amdgpu_disable_cu = NULL;
140char *amdgpu_virtual_display = NULL;
141
142
143
144
145
146uint amdgpu_pp_feature_mask = 0xfff7bfff;
147uint amdgpu_force_long_training;
148int amdgpu_job_hang_limit;
149int amdgpu_lbpw = -1;
150int amdgpu_compute_multipipe = -1;
151int amdgpu_gpu_recovery = -1;
152int amdgpu_emu_mode;
153uint amdgpu_smu_memory_pool_size;
154int amdgpu_smu_pptable_id = -1;
155
156
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161
162
163
164
165uint amdgpu_dc_feature_mask = 2;
166uint amdgpu_dc_debug_mask;
167int amdgpu_async_gfx_ring = 1;
168int amdgpu_mcbp;
169int amdgpu_discovery = -1;
170int amdgpu_mes;
171int amdgpu_noretry = -1;
172int amdgpu_force_asic_type = -1;
173int amdgpu_tmz = -1;
174uint amdgpu_freesync_vid_mode;
175int amdgpu_reset_method = -1;
176int amdgpu_num_kcq = -1;
177int amdgpu_smartshift_bias;
178
179static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work);
180
181struct amdgpu_mgpu_info mgpu_info = {
182 .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex),
183 .delayed_reset_work = __DELAYED_WORK_INITIALIZER(
184 mgpu_info.delayed_reset_work,
185 amdgpu_drv_delayed_reset_work_handler, 0),
186};
187int amdgpu_ras_enable = -1;
188uint amdgpu_ras_mask = 0xffffffff;
189int amdgpu_bad_page_threshold = -1;
190struct amdgpu_watchdog_timer amdgpu_watchdog_timer = {
191 .timeout_fatal_disable = false,
192 .period = 0x0,
193};
194
195
196
197
198
199MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
200module_param_named(vramlimit, amdgpu_vram_limit, int, 0600);
201
202
203
204
205
206MODULE_PARM_DESC(vis_vramlimit, "Restrict visible VRAM for testing, in megabytes");
207module_param_named(vis_vramlimit, amdgpu_vis_vram_limit, int, 0444);
208
209
210
211
212
213MODULE_PARM_DESC(gartsize, "Size of GART to setup in megabytes (32, 64, etc., -1=auto)");
214module_param_named(gartsize, amdgpu_gart_size, uint, 0600);
215
216
217
218
219
220
221MODULE_PARM_DESC(gttsize, "Size of the GTT domain in megabytes (-1 = auto)");
222module_param_named(gttsize, amdgpu_gtt_size, int, 0600);
223
224
225
226
227
228MODULE_PARM_DESC(moverate, "Maximum buffer migration rate in MB/s. (32, 64, etc., -1=auto, 0=1=disabled)");
229module_param_named(moverate, amdgpu_moverate, int, 0600);
230
231
232
233
234
235MODULE_PARM_DESC(benchmark, "Run benchmark");
236module_param_named(benchmark, amdgpu_benchmarking, int, 0444);
237
238
239
240
241
242MODULE_PARM_DESC(test, "Run tests");
243module_param_named(test, amdgpu_testing, int, 0444);
244
245
246
247
248
249MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
250module_param_named(audio, amdgpu_audio, int, 0444);
251
252
253
254
255
256MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
257module_param_named(disp_priority, amdgpu_disp_priority, int, 0444);
258
259
260
261
262
263MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
264module_param_named(hw_i2c, amdgpu_hw_i2c, int, 0444);
265
266
267
268
269
270MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
271module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444);
272
273
274
275
276
277MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
278module_param_named(msi, amdgpu_msi, int, 0444);
279
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295
296MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default: for bare metal 10000 for non-compute jobs and 60000 for compute jobs; "
297 "for passthrough or sriov, 10000 for all jobs."
298 " 0: keep default value. negative: infinity timeout), "
299 "format: for bare metal [Non-Compute] or [GFX,Compute,SDMA,Video]; "
300 "for passthrough or sriov [all jobs] or [GFX,Compute,SDMA,Video].");
301module_param_string(lockup_timeout, amdgpu_lockup_timeout, sizeof(amdgpu_lockup_timeout), 0444);
302
303
304
305
306
307
308
309MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
310module_param_named(dpm, amdgpu_dpm, int, 0444);
311
312
313
314
315
316MODULE_PARM_DESC(fw_load_type, "firmware loading type (0 = direct, 1 = SMU, 2 = PSP, -1 = auto)");
317module_param_named(fw_load_type, amdgpu_fw_load_type, int, 0444);
318
319
320
321
322
323MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
324module_param_named(aspm, amdgpu_aspm, int, 0444);
325
326
327
328
329
330
331MODULE_PARM_DESC(runpm, "PX runtime pm (2 = force enable with BAMACO, 1 = force enable with BACO, 0 = disable, -1 = PX only default)");
332module_param_named(runpm, amdgpu_runtime_pm, int, 0444);
333
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338
339
340
341MODULE_PARM_DESC(ip_block_mask, "IP Block Mask (all blocks enabled (default))");
342module_param_named(ip_block_mask, amdgpu_ip_block_mask, uint, 0444);
343
344
345
346
347
348
349MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
350module_param_named(bapm, amdgpu_bapm, int, 0444);
351
352
353
354
355
356MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
357module_param_named(deep_color, amdgpu_deep_color, int, 0444);
358
359
360
361
362
363MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 64GB)");
364module_param_named(vm_size, amdgpu_vm_size, int, 0444);
365
366
367
368
369
370MODULE_PARM_DESC(vm_fragment_size, "VM fragment size in bits (4, 5, etc. 4 = 64K (default), Max 9 = 2M)");
371module_param_named(vm_fragment_size, amdgpu_vm_fragment_size, int, 0444);
372
373
374
375
376
377MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
378module_param_named(vm_block_size, amdgpu_vm_block_size, int, 0444);
379
380
381
382
383
384MODULE_PARM_DESC(vm_fault_stop, "Stop on VM fault (0 = never (default), 1 = print first, 2 = always)");
385module_param_named(vm_fault_stop, amdgpu_vm_fault_stop, int, 0444);
386
387
388
389
390
391MODULE_PARM_DESC(vm_debug, "Debug VM handling (0 = disabled (default), 1 = enabled)");
392module_param_named(vm_debug, amdgpu_vm_debug, int, 0644);
393
394
395
396
397
398
399MODULE_PARM_DESC(vm_update_mode, "VM update using CPU (0 = never (default except for large BAR(LB)), 1 = Graphics only, 2 = Compute only (default for LB), 3 = Both");
400module_param_named(vm_update_mode, amdgpu_vm_update_mode, int, 0444);
401
402
403
404
405
406MODULE_PARM_DESC(exp_hw_support, "experimental hw support (1 = enable, 0 = disable (default))");
407module_param_named(exp_hw_support, amdgpu_exp_hw_support, int, 0444);
408
409
410
411
412
413MODULE_PARM_DESC(dc, "Display Core driver (1 = enable, 0 = disable, -1 = auto (default))");
414module_param_named(dc, amdgpu_dc, int, 0444);
415
416
417
418
419
420MODULE_PARM_DESC(sched_jobs, "the max number of jobs supported in the sw queue (default 32)");
421module_param_named(sched_jobs, amdgpu_sched_jobs, int, 0444);
422
423
424
425
426
427MODULE_PARM_DESC(sched_hw_submission, "the max number of HW submissions (default 2)");
428module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444);
429
430
431
432
433
434
435MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))");
436module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444);
437
438
439
440
441
442
443MODULE_PARM_DESC(forcelongtraining, "force memory long training");
444module_param_named(forcelongtraining, amdgpu_force_long_training, uint, 0444);
445
446
447
448
449
450
451MODULE_PARM_DESC(pcie_gen_cap, "PCIE Gen Caps (0: autodetect (default))");
452module_param_named(pcie_gen_cap, amdgpu_pcie_gen_cap, uint, 0444);
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454
455
456
457
458
459MODULE_PARM_DESC(pcie_lane_cap, "PCIE Lane Caps (0: autodetect (default))");
460module_param_named(pcie_lane_cap, amdgpu_pcie_lane_cap, uint, 0444);
461
462
463
464
465
466
467MODULE_PARM_DESC(cg_mask, "Clockgating flags mask (0 = disable clock gating)");
468module_param_named(cg_mask, amdgpu_cg_mask, uint, 0444);
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472
473
474
475MODULE_PARM_DESC(pg_mask, "Powergating flags mask (0 = disable power gating)");
476module_param_named(pg_mask, amdgpu_pg_mask, uint, 0444);
477
478
479
480
481
482MODULE_PARM_DESC(sdma_phase_quantum, "SDMA context switch phase quantum (x 1K GPU clock cycles, 0 = no change (default 32))");
483module_param_named(sdma_phase_quantum, amdgpu_sdma_phase_quantum, uint, 0444);
484
485
486
487
488
489MODULE_PARM_DESC(disable_cu, "Disable CUs (se.sh.cu,...)");
490module_param_named(disable_cu, amdgpu_disable_cu, charp, 0444);
491
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493
494
495
496
497
498
499MODULE_PARM_DESC(virtual_display,
500 "Enable virtual display feature (the virtual_display will be set like xxxx:xx:xx.x,x;xxxx:xx:xx.x,x)");
501module_param_named(virtual_display, amdgpu_virtual_display, charp, 0444);
502
503
504
505
506
507MODULE_PARM_DESC(job_hang_limit, "how much time allow a job hang and not drop it (default 0)");
508module_param_named(job_hang_limit, amdgpu_job_hang_limit, int ,0444);
509
510
511
512
513
514MODULE_PARM_DESC(lbpw, "Load Balancing Per Watt (LBPW) support (1 = enable, 0 = disable, -1 = auto)");
515module_param_named(lbpw, amdgpu_lbpw, int, 0444);
516
517MODULE_PARM_DESC(compute_multipipe, "Force compute queues to be spread across pipes (1 = enable, 0 = disable, -1 = auto)");
518module_param_named(compute_multipipe, amdgpu_compute_multipipe, int, 0444);
519
520
521
522
523
524MODULE_PARM_DESC(gpu_recovery, "Enable GPU recovery mechanism, (2 = advanced tdr mode, 1 = enable, 0 = disable, -1 = auto)");
525module_param_named(gpu_recovery, amdgpu_gpu_recovery, int, 0444);
526
527
528
529
530
531MODULE_PARM_DESC(emu_mode, "Emulation mode, (1 = enable, 0 = disable)");
532module_param_named(emu_mode, amdgpu_emu_mode, int, 0444);
533
534
535
536
537
538MODULE_PARM_DESC(ras_enable, "Enable RAS features on the GPU (0 = disable, 1 = enable, -1 = auto (default))");
539module_param_named(ras_enable, amdgpu_ras_enable, int, 0444);
540
541
542
543
544
545
546MODULE_PARM_DESC(ras_mask, "Mask of RAS features to enable (default 0xffffffff), only valid when ras_enable == 1");
547module_param_named(ras_mask, amdgpu_ras_mask, uint, 0444);
548
549
550
551
552
553MODULE_PARM_DESC(timeout_fatal_disable, "disable watchdog timeout fatal error (false = default)");
554module_param_named(timeout_fatal_disable, amdgpu_watchdog_timer.timeout_fatal_disable, bool, 0644);
555
556
557
558
559
560MODULE_PARM_DESC(timeout_period, "watchdog timeout period (0 = timeout disabled, 1 ~ 0x23 = timeout maxcycles = (1 << period)");
561module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644);
562
563
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566
567
568
569#ifdef CONFIG_DRM_AMDGPU_SI
570
571#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
572int amdgpu_si_support = 0;
573MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))");
574#else
575int amdgpu_si_support = 1;
576MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)");
577#endif
578
579module_param_named(si_support, amdgpu_si_support, int, 0444);
580#endif
581
582
583
584
585
586
587
588#ifdef CONFIG_DRM_AMDGPU_CIK
589
590#if defined(CONFIG_DRM_RADEON) || defined(CONFIG_DRM_RADEON_MODULE)
591int amdgpu_cik_support = 0;
592MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))");
593#else
594int amdgpu_cik_support = 1;
595MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)");
596#endif
597
598module_param_named(cik_support, amdgpu_cik_support, int, 0444);
599#endif
600
601
602
603
604
605
606MODULE_PARM_DESC(smu_memory_pool_size,
607 "reserve gtt for smu debug usage, 0 = disable,"
608 "0x1 = 256Mbyte, 0x2 = 512Mbyte, 0x4 = 1 Gbyte, 0x8 = 2GByte");
609module_param_named(smu_memory_pool_size, amdgpu_smu_memory_pool_size, uint, 0444);
610
611
612
613
614
615MODULE_PARM_DESC(async_gfx_ring,
616 "Asynchronous GFX rings that could be configured with either different priorities (HP3D ring and LP3D ring), or equal priorities (0 = disabled, 1 = enabled (default))");
617module_param_named(async_gfx_ring, amdgpu_async_gfx_ring, int, 0444);
618
619
620
621
622
623MODULE_PARM_DESC(mcbp,
624 "Enable Mid-command buffer preemption (0 = disabled (default), 1 = enabled)");
625module_param_named(mcbp, amdgpu_mcbp, int, 0444);
626
627
628
629
630
631
632MODULE_PARM_DESC(discovery,
633 "Allow driver to discover hardware IPs from IP Discovery table at the top of VRAM");
634module_param_named(discovery, amdgpu_discovery, int, 0444);
635
636
637
638
639
640
641MODULE_PARM_DESC(mes,
642 "Enable Micro Engine Scheduler (0 = disabled (default), 1 = enabled)");
643module_param_named(mes, amdgpu_mes, int, 0444);
644
645
646
647
648
649
650
651MODULE_PARM_DESC(noretry,
652 "Disable retry faults (0 = retry enabled, 1 = retry disabled, -1 auto (default))");
653module_param_named(noretry, amdgpu_noretry, int, 0644);
654
655
656
657
658
659MODULE_PARM_DESC(force_asic_type,
660 "A non negative value used to specify the asic type for all supported GPUs");
661module_param_named(force_asic_type, amdgpu_force_asic_type, int, 0444);
662
663
664
665#ifdef CONFIG_HSA_AMD
666
667
668
669
670
671
672int sched_policy = KFD_SCHED_POLICY_HWS;
673module_param(sched_policy, int, 0444);
674MODULE_PARM_DESC(sched_policy,
675 "Scheduling policy (0 = HWS (Default), 1 = HWS without over-subscription, 2 = Non-HWS (Used for debugging only)");
676
677
678
679
680
681
682int hws_max_conc_proc = 8;
683module_param(hws_max_conc_proc, int, 0444);
684MODULE_PARM_DESC(hws_max_conc_proc,
685 "Max # processes HWS can execute concurrently when sched_policy=0 (0 = no concurrency, #VMIDs for KFD = Maximum(default))");
686
687
688
689
690
691
692
693int cwsr_enable = 1;
694module_param(cwsr_enable, int, 0444);
695MODULE_PARM_DESC(cwsr_enable, "CWSR enable (0 = Off, 1 = On (Default))");
696
697
698
699
700
701
702int max_num_of_queues_per_device = KFD_MAX_NUM_OF_QUEUES_PER_DEVICE_DEFAULT;
703module_param(max_num_of_queues_per_device, int, 0444);
704MODULE_PARM_DESC(max_num_of_queues_per_device,
705 "Maximum number of supported queues per device (1 = Minimum, 4096 = default)");
706
707
708
709
710
711
712int send_sigterm;
713module_param(send_sigterm, int, 0444);
714MODULE_PARM_DESC(send_sigterm,
715 "Send sigterm to HSA process on unhandled exception (0 = disable, 1 = enable)");
716
717
718
719
720
721
722
723
724int debug_largebar;
725module_param(debug_largebar, int, 0444);
726MODULE_PARM_DESC(debug_largebar,
727 "Debug large-bar flag used to simulate large-bar capability on non-large bar machine (0 = disable, 1 = enable)");
728
729
730
731
732
733
734
735
736
737
738int ignore_crat;
739module_param(ignore_crat, int, 0444);
740MODULE_PARM_DESC(ignore_crat,
741 "Ignore CRAT table during KFD initialization (0 = auto (default), 1 = ignore CRAT)");
742
743
744
745
746
747
748int halt_if_hws_hang;
749module_param(halt_if_hws_hang, int, 0644);
750MODULE_PARM_DESC(halt_if_hws_hang, "Halt if HWS hang is detected (0 = off (default), 1 = on)");
751
752
753
754
755
756
757bool hws_gws_support;
758module_param(hws_gws_support, bool, 0444);
759MODULE_PARM_DESC(hws_gws_support, "Assume MEC2 FW supports GWS barriers (false = rely on FW version check (Default), true = force supported)");
760
761
762
763
764
765int queue_preemption_timeout_ms = 9000;
766module_param(queue_preemption_timeout_ms, int, 0644);
767MODULE_PARM_DESC(queue_preemption_timeout_ms, "queue preemption timeout in ms (1 = Minimum, 9000 = default)");
768
769
770
771
772
773bool debug_evictions;
774module_param(debug_evictions, bool, 0644);
775MODULE_PARM_DESC(debug_evictions, "enable eviction debug messages (false = default)");
776
777
778
779
780
781bool no_system_mem_limit;
782module_param(no_system_mem_limit, bool, 0644);
783MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = default)");
784
785
786
787
788
789int amdgpu_no_queue_eviction_on_vm_fault = 0;
790MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)");
791module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444);
792#endif
793
794
795
796
797
798
799MODULE_PARM_DESC(dcfeaturemask, "all stable DC features enabled (default))");
800module_param_named(dcfeaturemask, amdgpu_dc_feature_mask, uint, 0444);
801
802
803
804
805
806MODULE_PARM_DESC(dcdebugmask, "all debug options disabled (default))");
807module_param_named(dcdebugmask, amdgpu_dc_debug_mask, uint, 0444);
808
809
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811
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820
821uint amdgpu_dm_abm_level;
822MODULE_PARM_DESC(abmlevel, "ABM level (0 = off (default), 1-4 = backlight reduction level) ");
823module_param_named(abmlevel, amdgpu_dm_abm_level, uint, 0444);
824
825int amdgpu_backlight = -1;
826MODULE_PARM_DESC(backlight, "Backlight control (0 = pwm, 1 = aux, -1 auto (default))");
827module_param_named(backlight, amdgpu_backlight, bint, 0444);
828
829
830
831
832
833
834
835
836MODULE_PARM_DESC(tmz, "Enable TMZ feature (-1 = auto (default), 0 = off, 1 = on)");
837module_param_named(tmz, amdgpu_tmz, int, 0444);
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860MODULE_PARM_DESC(
861 freesync_video,
862 "Enable freesync modesetting optimization feature (0 = off (default), 1 = on)");
863module_param_named(freesync_video, amdgpu_freesync_vid_mode, uint, 0444);
864
865
866
867
868
869MODULE_PARM_DESC(reset_method, "GPU reset method (-1 = auto (default), 0 = legacy, 1 = mode0, 2 = mode1, 3 = mode2, 4 = baco/bamaco, 5 = pci)");
870module_param_named(reset_method, amdgpu_reset_method, int, 0444);
871
872
873
874
875
876
877
878MODULE_PARM_DESC(bad_page_threshold, "Bad page threshold(-1 = auto(default value), 0 = disable bad page retirement)");
879module_param_named(bad_page_threshold, amdgpu_bad_page_threshold, int, 0444);
880
881MODULE_PARM_DESC(num_kcq, "number of kernel compute queue user want to setup (8 if set to greater than 8 or less than 0, only affect gfx 8+)");
882module_param_named(num_kcq, amdgpu_num_kcq, int, 0444);
883
884
885
886
887
888
889MODULE_PARM_DESC(smu_pptable_id,
890 "specify pptable id to be used (-1 = auto(default) value, 0 = use pptable from vbios, > 0 = soft pptable id)");
891module_param_named(smu_pptable_id, amdgpu_smu_pptable_id, int, 0444);
892
893static const struct pci_device_id pciidlist[] = {
894#ifdef CONFIG_DRM_AMDGPU_SI
895 {0x1002, 0x6780, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
896 {0x1002, 0x6784, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
897 {0x1002, 0x6788, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
898 {0x1002, 0x678A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
899 {0x1002, 0x6790, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
900 {0x1002, 0x6791, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
901 {0x1002, 0x6792, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
902 {0x1002, 0x6798, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
903 {0x1002, 0x6799, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
904 {0x1002, 0x679A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
905 {0x1002, 0x679B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
906 {0x1002, 0x679E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
907 {0x1002, 0x679F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TAHITI},
908 {0x1002, 0x6800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
909 {0x1002, 0x6801, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
910 {0x1002, 0x6802, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN|AMD_IS_MOBILITY},
911 {0x1002, 0x6806, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
912 {0x1002, 0x6808, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
913 {0x1002, 0x6809, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
914 {0x1002, 0x6810, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
915 {0x1002, 0x6811, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
916 {0x1002, 0x6816, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
917 {0x1002, 0x6817, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
918 {0x1002, 0x6818, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
919 {0x1002, 0x6819, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PITCAIRN},
920 {0x1002, 0x6600, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
921 {0x1002, 0x6601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
922 {0x1002, 0x6602, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
923 {0x1002, 0x6603, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
924 {0x1002, 0x6604, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
925 {0x1002, 0x6605, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
926 {0x1002, 0x6606, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
927 {0x1002, 0x6607, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
928 {0x1002, 0x6608, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
929 {0x1002, 0x6610, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
930 {0x1002, 0x6611, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
931 {0x1002, 0x6613, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
932 {0x1002, 0x6617, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
933 {0x1002, 0x6620, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
934 {0x1002, 0x6621, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
935 {0x1002, 0x6623, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND|AMD_IS_MOBILITY},
936 {0x1002, 0x6631, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_OLAND},
937 {0x1002, 0x6820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
938 {0x1002, 0x6821, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
939 {0x1002, 0x6822, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
940 {0x1002, 0x6823, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
941 {0x1002, 0x6824, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
942 {0x1002, 0x6825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
943 {0x1002, 0x6826, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
944 {0x1002, 0x6827, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
945 {0x1002, 0x6828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
946 {0x1002, 0x6829, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
947 {0x1002, 0x682A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
948 {0x1002, 0x682B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
949 {0x1002, 0x682C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
950 {0x1002, 0x682D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
951 {0x1002, 0x682F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
952 {0x1002, 0x6830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
953 {0x1002, 0x6831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE|AMD_IS_MOBILITY},
954 {0x1002, 0x6835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
955 {0x1002, 0x6837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
956 {0x1002, 0x6838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
957 {0x1002, 0x6839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
958 {0x1002, 0x683B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
959 {0x1002, 0x683D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
960 {0x1002, 0x683F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VERDE},
961 {0x1002, 0x6660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
962 {0x1002, 0x6663, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
963 {0x1002, 0x6664, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
964 {0x1002, 0x6665, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
965 {0x1002, 0x6667, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
966 {0x1002, 0x666F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAINAN|AMD_IS_MOBILITY},
967#endif
968#ifdef CONFIG_DRM_AMDGPU_CIK
969
970 {0x1002, 0x1304, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
971 {0x1002, 0x1305, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
972 {0x1002, 0x1306, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
973 {0x1002, 0x1307, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
974 {0x1002, 0x1309, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
975 {0x1002, 0x130A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
976 {0x1002, 0x130B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
977 {0x1002, 0x130C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
978 {0x1002, 0x130D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
979 {0x1002, 0x130E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
980 {0x1002, 0x130F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
981 {0x1002, 0x1310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
982 {0x1002, 0x1311, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
983 {0x1002, 0x1312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
984 {0x1002, 0x1313, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
985 {0x1002, 0x1315, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
986 {0x1002, 0x1316, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
987 {0x1002, 0x1317, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
988 {0x1002, 0x1318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_MOBILITY|AMD_IS_APU},
989 {0x1002, 0x131B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
990 {0x1002, 0x131C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
991 {0x1002, 0x131D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KAVERI|AMD_IS_APU},
992
993 {0x1002, 0x6640, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
994 {0x1002, 0x6641, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
995 {0x1002, 0x6646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
996 {0x1002, 0x6647, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE|AMD_IS_MOBILITY},
997 {0x1002, 0x6649, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
998 {0x1002, 0x6650, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
999 {0x1002, 0x6651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1000 {0x1002, 0x6658, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1001 {0x1002, 0x665c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1002 {0x1002, 0x665d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1003 {0x1002, 0x665f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BONAIRE},
1004
1005 {0x1002, 0x67A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1006 {0x1002, 0x67A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1007 {0x1002, 0x67A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1008 {0x1002, 0x67A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1009 {0x1002, 0x67A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1010 {0x1002, 0x67AA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1011 {0x1002, 0x67B0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1012 {0x1002, 0x67B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1013 {0x1002, 0x67B8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1014 {0x1002, 0x67B9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1015 {0x1002, 0x67BA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1016 {0x1002, 0x67BE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_HAWAII},
1017
1018 {0x1002, 0x9830, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1019 {0x1002, 0x9831, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1020 {0x1002, 0x9832, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1021 {0x1002, 0x9833, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1022 {0x1002, 0x9834, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1023 {0x1002, 0x9835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1024 {0x1002, 0x9836, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1025 {0x1002, 0x9837, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1026 {0x1002, 0x9838, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1027 {0x1002, 0x9839, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1028 {0x1002, 0x983a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1029 {0x1002, 0x983b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_MOBILITY|AMD_IS_APU},
1030 {0x1002, 0x983c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1031 {0x1002, 0x983d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1032 {0x1002, 0x983e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1033 {0x1002, 0x983f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_KABINI|AMD_IS_APU},
1034
1035 {0x1002, 0x9850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1036 {0x1002, 0x9851, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1037 {0x1002, 0x9852, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1038 {0x1002, 0x9853, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1039 {0x1002, 0x9854, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1040 {0x1002, 0x9855, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1041 {0x1002, 0x9856, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1042 {0x1002, 0x9857, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1043 {0x1002, 0x9858, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1044 {0x1002, 0x9859, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1045 {0x1002, 0x985A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1046 {0x1002, 0x985B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1047 {0x1002, 0x985C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1048 {0x1002, 0x985D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1049 {0x1002, 0x985E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1050 {0x1002, 0x985F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MULLINS|AMD_IS_MOBILITY|AMD_IS_APU},
1051#endif
1052
1053 {0x1002, 0x6900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1054 {0x1002, 0x6901, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1055 {0x1002, 0x6902, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1056 {0x1002, 0x6903, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1057 {0x1002, 0x6907, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TOPAZ},
1058
1059 {0x1002, 0x6920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1060 {0x1002, 0x6921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1061 {0x1002, 0x6928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1062 {0x1002, 0x6929, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1063 {0x1002, 0x692B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1064 {0x1002, 0x692F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1065 {0x1002, 0x6930, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1066 {0x1002, 0x6938, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1067 {0x1002, 0x6939, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_TONGA},
1068
1069 {0x1002, 0x7300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1070 {0x1002, 0x730F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_FIJI},
1071
1072 {0x1002, 0x9870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1073 {0x1002, 0x9874, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1074 {0x1002, 0x9875, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1075 {0x1002, 0x9876, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1076 {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU},
1077
1078 {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU},
1079
1080 {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1081 {0x1002, 0x67E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1082 {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1083 {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1084 {0x1002, 0x67EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1085 {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1086 {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1087 {0x1002, 0x67E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1088 {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11},
1089
1090 {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1091 {0x1002, 0x67C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1092 {0x1002, 0x67C2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1093 {0x1002, 0x67C4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1094 {0x1002, 0x67C7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1095 {0x1002, 0x67D0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1096 {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1097 {0x1002, 0x67C8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1098 {0x1002, 0x67C9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1099 {0x1002, 0x67CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1100 {0x1002, 0x67CC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1101 {0x1002, 0x67CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1102 {0x1002, 0x6FDF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10},
1103
1104 {0x1002, 0x6980, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1105 {0x1002, 0x6981, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1106 {0x1002, 0x6985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1107 {0x1002, 0x6986, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1108 {0x1002, 0x6987, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1109 {0x1002, 0x6995, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1110 {0x1002, 0x6997, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1111 {0x1002, 0x699F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS12},
1112
1113 {0x1002, 0x694C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1114 {0x1002, 0x694E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1115 {0x1002, 0x694F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGAM},
1116
1117 {0x1002, 0x6860, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1118 {0x1002, 0x6861, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1119 {0x1002, 0x6862, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1120 {0x1002, 0x6863, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1121 {0x1002, 0x6864, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1122 {0x1002, 0x6867, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1123 {0x1002, 0x6868, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1124 {0x1002, 0x6869, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1125 {0x1002, 0x686a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1126 {0x1002, 0x686b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1127 {0x1002, 0x686c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1128 {0x1002, 0x686d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1129 {0x1002, 0x686e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1130 {0x1002, 0x686f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1131 {0x1002, 0x687f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA10},
1132
1133 {0x1002, 0x69A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1134 {0x1002, 0x69A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1135 {0x1002, 0x69A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1136 {0x1002, 0x69A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1137 {0x1002, 0x69AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA12},
1138
1139 {0x1002, 0x66A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1140 {0x1002, 0x66A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1141 {0x1002, 0x66A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1142 {0x1002, 0x66A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1143 {0x1002, 0x66A4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1144 {0x1002, 0x66A7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1145 {0x1002, 0x66AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VEGA20},
1146
1147 {0x1002, 0x15dd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1148 {0x1002, 0x15d8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RAVEN|AMD_IS_APU},
1149
1150 {0x1002, 0x738C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1151 {0x1002, 0x7388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1152 {0x1002, 0x738E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1153 {0x1002, 0x7390, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ARCTURUS},
1154
1155 {0x1002, 0x7310, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1156 {0x1002, 0x7312, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1157 {0x1002, 0x7318, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1158 {0x1002, 0x7319, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1159 {0x1002, 0x731A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1160 {0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1161 {0x1002, 0x731E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1162 {0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
1163
1164 {0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1165 {0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1166 {0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1167 {0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1168
1169
1170 {0x1002, 0x15E7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1171 {0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1172 {0x1002, 0x1638, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1173 {0x1002, 0x164C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU},
1174
1175
1176 {0x1002, 0x7360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1177 {0x1002, 0x7362, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI12},
1178
1179
1180 {0x1002, 0x73A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1181 {0x1002, 0x73A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1182 {0x1002, 0x73A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1183 {0x1002, 0x73A3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1184 {0x1002, 0x73A5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1185 {0x1002, 0x73A8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1186 {0x1002, 0x73A9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1187 {0x1002, 0x73AB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1188 {0x1002, 0x73AC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1189 {0x1002, 0x73AD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1190 {0x1002, 0x73AE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1191 {0x1002, 0x73AF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1192 {0x1002, 0x73BF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_SIENNA_CICHLID},
1193
1194
1195 {0x1002, 0x163F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_VANGOGH|AMD_IS_APU},
1196
1197
1198 {0x1002, 0x164D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1199 {0x1002, 0x1681, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_YELLOW_CARP|AMD_IS_APU},
1200
1201
1202 {0x1002, 0x73C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1203 {0x1002, 0x73C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1204 {0x1002, 0x73C3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1205 {0x1002, 0x73DA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1206 {0x1002, 0x73DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1207 {0x1002, 0x73DC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1208 {0x1002, 0x73DD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1209 {0x1002, 0x73DE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1210 {0x1002, 0x73DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVY_FLOUNDER},
1211
1212
1213 {0x1002, 0x73E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1214 {0x1002, 0x73E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1215 {0x1002, 0x73E2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1216 {0x1002, 0x73E3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1217 {0x1002, 0x73E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1218 {0x1002, 0x73E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1219 {0x1002, 0x73EA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1220 {0x1002, 0x73EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1221 {0x1002, 0x73EC, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1222 {0x1002, 0x73ED, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1223 {0x1002, 0x73EF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1224 {0x1002, 0x73FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_DIMGREY_CAVEFISH},
1225
1226
1227 {0x1002, 0x7408, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1228 {0x1002, 0x740C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1229 {0x1002, 0x740F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1230 {0x1002, 0x7410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ALDEBARAN|AMD_EXP_HW_SUPPORT},
1231
1232
1233 {0x1002, 0x13FE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CYAN_SKILLFISH|AMD_IS_APU},
1234
1235
1236 {0x1002, 0x7420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1237 {0x1002, 0x7421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1238 {0x1002, 0x7422, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1239 {0x1002, 0x7423, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1240 {0x1002, 0x743F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BEIGE_GOBY},
1241
1242 {0, 0, 0}
1243};
1244
1245MODULE_DEVICE_TABLE(pci, pciidlist);
1246
1247static const struct drm_driver amdgpu_kms_driver;
1248
1249static int amdgpu_pci_probe(struct pci_dev *pdev,
1250 const struct pci_device_id *ent)
1251{
1252 struct drm_device *ddev;
1253 struct amdgpu_device *adev;
1254 unsigned long flags = ent->driver_data;
1255 int ret, retry = 0;
1256 bool supports_atomic = false;
1257
1258 if (amdgpu_virtual_display ||
1259 amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK))
1260 supports_atomic = true;
1261
1262 if ((flags & AMD_EXP_HW_SUPPORT) && !amdgpu_exp_hw_support) {
1263 DRM_INFO("This hardware requires experimental hardware support.\n"
1264 "See modparam exp_hw_support\n");
1265 return -ENODEV;
1266 }
1267
1268
1269
1270
1271
1272 if (mem_encrypt_active() && ((flags & AMD_ASIC_MASK) == CHIP_RAVEN)) {
1273 dev_info(&pdev->dev,
1274 "SME is not compatible with RAVEN\n");
1275 return -ENOTSUPP;
1276 }
1277
1278#ifdef CONFIG_DRM_AMDGPU_SI
1279 if (!amdgpu_si_support) {
1280 switch (flags & AMD_ASIC_MASK) {
1281 case CHIP_TAHITI:
1282 case CHIP_PITCAIRN:
1283 case CHIP_VERDE:
1284 case CHIP_OLAND:
1285 case CHIP_HAINAN:
1286 dev_info(&pdev->dev,
1287 "SI support provided by radeon.\n");
1288 dev_info(&pdev->dev,
1289 "Use radeon.si_support=0 amdgpu.si_support=1 to override.\n"
1290 );
1291 return -ENODEV;
1292 }
1293 }
1294#endif
1295#ifdef CONFIG_DRM_AMDGPU_CIK
1296 if (!amdgpu_cik_support) {
1297 switch (flags & AMD_ASIC_MASK) {
1298 case CHIP_KAVERI:
1299 case CHIP_BONAIRE:
1300 case CHIP_HAWAII:
1301 case CHIP_KABINI:
1302 case CHIP_MULLINS:
1303 dev_info(&pdev->dev,
1304 "CIK support provided by radeon.\n");
1305 dev_info(&pdev->dev,
1306 "Use radeon.cik_support=0 amdgpu.cik_support=1 to override.\n"
1307 );
1308 return -ENODEV;
1309 }
1310 }
1311#endif
1312
1313
1314 ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &amdgpu_kms_driver);
1315 if (ret)
1316 return ret;
1317
1318 adev = devm_drm_dev_alloc(&pdev->dev, &amdgpu_kms_driver, typeof(*adev), ddev);
1319 if (IS_ERR(adev))
1320 return PTR_ERR(adev);
1321
1322 adev->dev = &pdev->dev;
1323 adev->pdev = pdev;
1324 ddev = adev_to_drm(adev);
1325
1326 if (!supports_atomic)
1327 ddev->driver_features &= ~DRIVER_ATOMIC;
1328
1329 ret = pci_enable_device(pdev);
1330 if (ret)
1331 return ret;
1332
1333 pci_set_drvdata(pdev, ddev);
1334
1335 ret = amdgpu_driver_load_kms(adev, ent->driver_data);
1336 if (ret)
1337 goto err_pci;
1338
1339retry_init:
1340 ret = drm_dev_register(ddev, ent->driver_data);
1341 if (ret == -EAGAIN && ++retry <= 3) {
1342 DRM_INFO("retry init %d\n", retry);
1343
1344 msleep(5000);
1345 goto retry_init;
1346 } else if (ret) {
1347 goto err_pci;
1348 }
1349
1350 ret = amdgpu_debugfs_init(adev);
1351 if (ret)
1352 DRM_ERROR("Creating debugfs files failed (%d).\n", ret);
1353
1354 return 0;
1355
1356err_pci:
1357 pci_disable_device(pdev);
1358 return ret;
1359}
1360
1361static void
1362amdgpu_pci_remove(struct pci_dev *pdev)
1363{
1364 struct drm_device *dev = pci_get_drvdata(pdev);
1365
1366 drm_dev_unplug(dev);
1367 amdgpu_driver_unload_kms(dev);
1368
1369
1370
1371
1372
1373
1374 pci_disable_device(pdev);
1375 pci_wait_for_pending_transaction(pdev);
1376}
1377
1378static void
1379amdgpu_pci_shutdown(struct pci_dev *pdev)
1380{
1381 struct drm_device *dev = pci_get_drvdata(pdev);
1382 struct amdgpu_device *adev = drm_to_adev(dev);
1383
1384 if (amdgpu_ras_intr_triggered())
1385 return;
1386
1387
1388
1389
1390
1391
1392 if (!amdgpu_passthrough(adev))
1393 adev->mp1_state = PP_MP1_STATE_UNLOAD;
1394 amdgpu_device_ip_suspend(adev);
1395 adev->mp1_state = PP_MP1_STATE_NONE;
1396}
1397
1398
1399
1400
1401
1402
1403static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work)
1404{
1405 struct list_head device_list;
1406 struct amdgpu_device *adev;
1407 int i, r;
1408 struct amdgpu_reset_context reset_context;
1409
1410 memset(&reset_context, 0, sizeof(reset_context));
1411
1412 mutex_lock(&mgpu_info.mutex);
1413 if (mgpu_info.pending_reset == true) {
1414 mutex_unlock(&mgpu_info.mutex);
1415 return;
1416 }
1417 mgpu_info.pending_reset = true;
1418 mutex_unlock(&mgpu_info.mutex);
1419
1420
1421 reset_context.method = AMD_RESET_METHOD_NONE;
1422 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
1423
1424 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1425 adev = mgpu_info.gpu_ins[i].adev;
1426 reset_context.reset_req_dev = adev;
1427 r = amdgpu_device_pre_asic_reset(adev, &reset_context);
1428 if (r) {
1429 dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ",
1430 r, adev_to_drm(adev)->unique);
1431 }
1432 if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work))
1433 r = -EALREADY;
1434 }
1435 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1436 adev = mgpu_info.gpu_ins[i].adev;
1437 flush_work(&adev->xgmi_reset_work);
1438 adev->gmc.xgmi.pending_reset = false;
1439 }
1440
1441
1442 for (i = 0; i < mgpu_info.num_dgpu; i++)
1443 amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev);
1444
1445 INIT_LIST_HEAD(&device_list);
1446
1447 for (i = 0; i < mgpu_info.num_dgpu; i++)
1448 list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list);
1449
1450
1451 list_for_each_entry(adev, &device_list, reset_list)
1452 amdgpu_unregister_gpu_instance(adev);
1453
1454
1455 set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags);
1456 r = amdgpu_do_asic_reset(&device_list, &reset_context);
1457
1458 if (r) {
1459 DRM_ERROR("reinit gpus failure");
1460 return;
1461 }
1462 for (i = 0; i < mgpu_info.num_dgpu; i++) {
1463 adev = mgpu_info.gpu_ins[i].adev;
1464 if (!adev->kfd.init_complete)
1465 amdgpu_amdkfd_device_init(adev);
1466 amdgpu_ttm_set_buffer_funcs_status(adev, true);
1467 }
1468 return;
1469}
1470
1471static int amdgpu_pmops_prepare(struct device *dev)
1472{
1473 struct drm_device *drm_dev = dev_get_drvdata(dev);
1474
1475
1476
1477
1478 if (amdgpu_device_supports_boco(drm_dev))
1479 return pm_runtime_suspended(dev) &&
1480 pm_suspend_via_firmware();
1481
1482 return 0;
1483}
1484
1485static void amdgpu_pmops_complete(struct device *dev)
1486{
1487
1488}
1489
1490static int amdgpu_pmops_suspend(struct device *dev)
1491{
1492 struct drm_device *drm_dev = dev_get_drvdata(dev);
1493 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1494 int r;
1495
1496 if (amdgpu_acpi_is_s0ix_active(adev))
1497 adev->in_s0ix = true;
1498 adev->in_s3 = true;
1499 r = amdgpu_device_suspend(drm_dev, true);
1500 adev->in_s3 = false;
1501
1502 return r;
1503}
1504
1505static int amdgpu_pmops_resume(struct device *dev)
1506{
1507 struct drm_device *drm_dev = dev_get_drvdata(dev);
1508 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1509 int r;
1510
1511 r = amdgpu_device_resume(drm_dev, true);
1512 if (amdgpu_acpi_is_s0ix_active(adev))
1513 adev->in_s0ix = false;
1514 return r;
1515}
1516
1517static int amdgpu_pmops_freeze(struct device *dev)
1518{
1519 struct drm_device *drm_dev = dev_get_drvdata(dev);
1520 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1521 int r;
1522
1523 adev->in_s4 = true;
1524 r = amdgpu_device_suspend(drm_dev, true);
1525 adev->in_s4 = false;
1526 if (r)
1527 return r;
1528 return amdgpu_asic_reset(adev);
1529}
1530
1531static int amdgpu_pmops_thaw(struct device *dev)
1532{
1533 struct drm_device *drm_dev = dev_get_drvdata(dev);
1534
1535 return amdgpu_device_resume(drm_dev, true);
1536}
1537
1538static int amdgpu_pmops_poweroff(struct device *dev)
1539{
1540 struct drm_device *drm_dev = dev_get_drvdata(dev);
1541
1542 return amdgpu_device_suspend(drm_dev, true);
1543}
1544
1545static int amdgpu_pmops_restore(struct device *dev)
1546{
1547 struct drm_device *drm_dev = dev_get_drvdata(dev);
1548
1549 return amdgpu_device_resume(drm_dev, true);
1550}
1551
1552static int amdgpu_pmops_runtime_suspend(struct device *dev)
1553{
1554 struct pci_dev *pdev = to_pci_dev(dev);
1555 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1556 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1557 int ret, i;
1558
1559 if (!adev->runpm) {
1560 pm_runtime_forbid(dev);
1561 return -EBUSY;
1562 }
1563
1564
1565 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
1566 struct amdgpu_ring *ring = adev->rings[i];
1567 if (ring && ring->sched.ready) {
1568 ret = amdgpu_fence_wait_empty(ring);
1569 if (ret)
1570 return -EBUSY;
1571 }
1572 }
1573
1574 adev->in_runpm = true;
1575 if (amdgpu_device_supports_px(drm_dev))
1576 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1577
1578 ret = amdgpu_device_suspend(drm_dev, false);
1579 if (ret) {
1580 adev->in_runpm = false;
1581 return ret;
1582 }
1583
1584 if (amdgpu_device_supports_px(drm_dev)) {
1585
1586
1587
1588 amdgpu_device_cache_pci_state(pdev);
1589 pci_disable_device(pdev);
1590 pci_ignore_hotplug(pdev);
1591 pci_set_power_state(pdev, PCI_D3cold);
1592 drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
1593 } else if (amdgpu_device_supports_boco(drm_dev)) {
1594
1595 } else if (amdgpu_device_supports_baco(drm_dev)) {
1596 amdgpu_device_baco_enter(drm_dev);
1597 }
1598
1599 return 0;
1600}
1601
1602static int amdgpu_pmops_runtime_resume(struct device *dev)
1603{
1604 struct pci_dev *pdev = to_pci_dev(dev);
1605 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1606 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1607 int ret;
1608
1609 if (!adev->runpm)
1610 return -EINVAL;
1611
1612
1613 if (!pci_device_is_present(adev->pdev))
1614 adev->no_hw_access = true;
1615
1616 if (amdgpu_device_supports_px(drm_dev)) {
1617 drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1618
1619
1620
1621
1622 pci_set_power_state(pdev, PCI_D0);
1623 amdgpu_device_load_pci_state(pdev);
1624 ret = pci_enable_device(pdev);
1625 if (ret)
1626 return ret;
1627 pci_set_master(pdev);
1628 } else if (amdgpu_device_supports_boco(drm_dev)) {
1629
1630
1631
1632 pci_set_master(pdev);
1633 } else if (amdgpu_device_supports_baco(drm_dev)) {
1634 amdgpu_device_baco_exit(drm_dev);
1635 }
1636 ret = amdgpu_device_resume(drm_dev, false);
1637 if (ret)
1638 return ret;
1639
1640 if (amdgpu_device_supports_px(drm_dev))
1641 drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
1642 adev->in_runpm = false;
1643 return 0;
1644}
1645
1646static int amdgpu_pmops_runtime_idle(struct device *dev)
1647{
1648 struct drm_device *drm_dev = dev_get_drvdata(dev);
1649 struct amdgpu_device *adev = drm_to_adev(drm_dev);
1650
1651 int ret = 1;
1652
1653 if (!adev->runpm) {
1654 pm_runtime_forbid(dev);
1655 return -EBUSY;
1656 }
1657
1658 if (amdgpu_device_has_dc_support(adev)) {
1659 struct drm_crtc *crtc;
1660
1661 drm_for_each_crtc(crtc, drm_dev) {
1662 drm_modeset_lock(&crtc->mutex, NULL);
1663 if (crtc->state->active)
1664 ret = -EBUSY;
1665 drm_modeset_unlock(&crtc->mutex);
1666 if (ret < 0)
1667 break;
1668 }
1669
1670 } else {
1671 struct drm_connector *list_connector;
1672 struct drm_connector_list_iter iter;
1673
1674 mutex_lock(&drm_dev->mode_config.mutex);
1675 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL);
1676
1677 drm_connector_list_iter_begin(drm_dev, &iter);
1678 drm_for_each_connector_iter(list_connector, &iter) {
1679 if (list_connector->dpms == DRM_MODE_DPMS_ON) {
1680 ret = -EBUSY;
1681 break;
1682 }
1683 }
1684
1685 drm_connector_list_iter_end(&iter);
1686
1687 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex);
1688 mutex_unlock(&drm_dev->mode_config.mutex);
1689 }
1690
1691 if (ret == -EBUSY)
1692 DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
1693
1694 pm_runtime_mark_last_busy(dev);
1695 pm_runtime_autosuspend(dev);
1696 return ret;
1697}
1698
1699long amdgpu_drm_ioctl(struct file *filp,
1700 unsigned int cmd, unsigned long arg)
1701{
1702 struct drm_file *file_priv = filp->private_data;
1703 struct drm_device *dev;
1704 long ret;
1705 dev = file_priv->minor->dev;
1706 ret = pm_runtime_get_sync(dev->dev);
1707 if (ret < 0)
1708 goto out;
1709
1710 ret = drm_ioctl(filp, cmd, arg);
1711
1712 pm_runtime_mark_last_busy(dev->dev);
1713out:
1714 pm_runtime_put_autosuspend(dev->dev);
1715 return ret;
1716}
1717
1718static const struct dev_pm_ops amdgpu_pm_ops = {
1719 .prepare = amdgpu_pmops_prepare,
1720 .complete = amdgpu_pmops_complete,
1721 .suspend = amdgpu_pmops_suspend,
1722 .resume = amdgpu_pmops_resume,
1723 .freeze = amdgpu_pmops_freeze,
1724 .thaw = amdgpu_pmops_thaw,
1725 .poweroff = amdgpu_pmops_poweroff,
1726 .restore = amdgpu_pmops_restore,
1727 .runtime_suspend = amdgpu_pmops_runtime_suspend,
1728 .runtime_resume = amdgpu_pmops_runtime_resume,
1729 .runtime_idle = amdgpu_pmops_runtime_idle,
1730};
1731
1732static int amdgpu_flush(struct file *f, fl_owner_t id)
1733{
1734 struct drm_file *file_priv = f->private_data;
1735 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1736 long timeout = MAX_WAIT_SCHED_ENTITY_Q_EMPTY;
1737
1738 timeout = amdgpu_ctx_mgr_entity_flush(&fpriv->ctx_mgr, timeout);
1739 timeout = amdgpu_vm_wait_idle(&fpriv->vm, timeout);
1740
1741 return timeout >= 0 ? 0 : timeout;
1742}
1743
1744static const struct file_operations amdgpu_driver_kms_fops = {
1745 .owner = THIS_MODULE,
1746 .open = drm_open,
1747 .flush = amdgpu_flush,
1748 .release = drm_release,
1749 .unlocked_ioctl = amdgpu_drm_ioctl,
1750 .mmap = drm_gem_mmap,
1751 .poll = drm_poll,
1752 .read = drm_read,
1753#ifdef CONFIG_COMPAT
1754 .compat_ioctl = amdgpu_kms_compat_ioctl,
1755#endif
1756#ifdef CONFIG_PROC_FS
1757 .show_fdinfo = amdgpu_show_fdinfo
1758#endif
1759};
1760
1761int amdgpu_file_to_fpriv(struct file *filp, struct amdgpu_fpriv **fpriv)
1762{
1763 struct drm_file *file;
1764
1765 if (!filp)
1766 return -EINVAL;
1767
1768 if (filp->f_op != &amdgpu_driver_kms_fops) {
1769 return -EINVAL;
1770 }
1771
1772 file = filp->private_data;
1773 *fpriv = file->driver_priv;
1774 return 0;
1775}
1776
1777const struct drm_ioctl_desc amdgpu_ioctls_kms[] = {
1778 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_CREATE, amdgpu_gem_create_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1779 DRM_IOCTL_DEF_DRV(AMDGPU_CTX, amdgpu_ctx_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1780 DRM_IOCTL_DEF_DRV(AMDGPU_VM, amdgpu_vm_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1781 DRM_IOCTL_DEF_DRV(AMDGPU_SCHED, amdgpu_sched_ioctl, DRM_MASTER),
1782 DRM_IOCTL_DEF_DRV(AMDGPU_BO_LIST, amdgpu_bo_list_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1783 DRM_IOCTL_DEF_DRV(AMDGPU_FENCE_TO_HANDLE, amdgpu_cs_fence_to_handle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1784
1785 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_MMAP, amdgpu_gem_mmap_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1786 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_WAIT_IDLE, amdgpu_gem_wait_idle_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1787 DRM_IOCTL_DEF_DRV(AMDGPU_CS, amdgpu_cs_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1788 DRM_IOCTL_DEF_DRV(AMDGPU_INFO, amdgpu_info_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1789 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_CS, amdgpu_cs_wait_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1790 DRM_IOCTL_DEF_DRV(AMDGPU_WAIT_FENCES, amdgpu_cs_wait_fences_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1791 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_METADATA, amdgpu_gem_metadata_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1792 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1793 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1794 DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW),
1795};
1796
1797static const struct drm_driver amdgpu_kms_driver = {
1798 .driver_features =
1799 DRIVER_ATOMIC |
1800 DRIVER_GEM |
1801 DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ |
1802 DRIVER_SYNCOBJ_TIMELINE,
1803 .open = amdgpu_driver_open_kms,
1804 .postclose = amdgpu_driver_postclose_kms,
1805 .lastclose = amdgpu_driver_lastclose_kms,
1806 .ioctls = amdgpu_ioctls_kms,
1807 .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms),
1808 .dumb_create = amdgpu_mode_dumb_create,
1809 .dumb_map_offset = amdgpu_mode_dumb_mmap,
1810 .fops = &amdgpu_driver_kms_fops,
1811 .release = &amdgpu_driver_release_kms,
1812
1813 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1814 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1815 .gem_prime_import = amdgpu_gem_prime_import,
1816 .gem_prime_mmap = drm_gem_prime_mmap,
1817
1818 .name = DRIVER_NAME,
1819 .desc = DRIVER_DESC,
1820 .date = DRIVER_DATE,
1821 .major = KMS_DRIVER_MAJOR,
1822 .minor = KMS_DRIVER_MINOR,
1823 .patchlevel = KMS_DRIVER_PATCHLEVEL,
1824};
1825
1826static struct pci_error_handlers amdgpu_pci_err_handler = {
1827 .error_detected = amdgpu_pci_error_detected,
1828 .mmio_enabled = amdgpu_pci_mmio_enabled,
1829 .slot_reset = amdgpu_pci_slot_reset,
1830 .resume = amdgpu_pci_resume,
1831};
1832
1833extern const struct attribute_group amdgpu_vram_mgr_attr_group;
1834extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
1835extern const struct attribute_group amdgpu_vbios_version_attr_group;
1836
1837static const struct attribute_group *amdgpu_sysfs_groups[] = {
1838 &amdgpu_vram_mgr_attr_group,
1839 &amdgpu_gtt_mgr_attr_group,
1840 &amdgpu_vbios_version_attr_group,
1841 NULL,
1842};
1843
1844
1845static struct pci_driver amdgpu_kms_pci_driver = {
1846 .name = DRIVER_NAME,
1847 .id_table = pciidlist,
1848 .probe = amdgpu_pci_probe,
1849 .remove = amdgpu_pci_remove,
1850 .shutdown = amdgpu_pci_shutdown,
1851 .driver.pm = &amdgpu_pm_ops,
1852 .err_handler = &amdgpu_pci_err_handler,
1853 .dev_groups = amdgpu_sysfs_groups,
1854};
1855
1856static int __init amdgpu_init(void)
1857{
1858 int r;
1859
1860 if (vgacon_text_force()) {
1861 DRM_ERROR("VGACON disables amdgpu kernel modesetting.\n");
1862 return -EINVAL;
1863 }
1864
1865 r = amdgpu_sync_init();
1866 if (r)
1867 goto error_sync;
1868
1869 r = amdgpu_fence_slab_init();
1870 if (r)
1871 goto error_fence;
1872
1873 DRM_INFO("amdgpu kernel modesetting enabled.\n");
1874 amdgpu_register_atpx_handler();
1875 amdgpu_acpi_detect();
1876
1877
1878 amdgpu_amdkfd_init();
1879
1880
1881 return pci_register_driver(&amdgpu_kms_pci_driver);
1882
1883error_fence:
1884 amdgpu_sync_fini();
1885
1886error_sync:
1887 return r;
1888}
1889
1890static void __exit amdgpu_exit(void)
1891{
1892 amdgpu_amdkfd_fini();
1893 pci_unregister_driver(&amdgpu_kms_pci_driver);
1894 amdgpu_unregister_atpx_handler();
1895 amdgpu_sync_fini();
1896 amdgpu_fence_slab_fini();
1897 mmu_notifier_synchronize();
1898}
1899
1900module_init(amdgpu_init);
1901module_exit(amdgpu_exit);
1902
1903MODULE_AUTHOR(DRIVER_AUTHOR);
1904MODULE_DESCRIPTION(DRIVER_DESC);
1905MODULE_LICENSE("GPL and additional rights");
1906