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29#include "amdgpu.h"
30#include <drm/amdgpu_drm.h>
31#include <drm/drm_drv.h>
32#include "amdgpu_uvd.h"
33#include "amdgpu_vce.h"
34#include "atom.h"
35
36#include <linux/vga_switcheroo.h>
37#include <linux/slab.h>
38#include <linux/uaccess.h>
39#include <linux/pci.h>
40#include <linux/pm_runtime.h>
41#include "amdgpu_amdkfd.h"
42#include "amdgpu_gem.h"
43#include "amdgpu_display.h"
44#include "amdgpu_ras.h"
45
46void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev)
47{
48 struct amdgpu_gpu_instance *gpu_instance;
49 int i;
50
51 mutex_lock(&mgpu_info.mutex);
52
53 for (i = 0; i < mgpu_info.num_gpu; i++) {
54 gpu_instance = &(mgpu_info.gpu_ins[i]);
55 if (gpu_instance->adev == adev) {
56 mgpu_info.gpu_ins[i] =
57 mgpu_info.gpu_ins[mgpu_info.num_gpu - 1];
58 mgpu_info.num_gpu--;
59 if (adev->flags & AMD_IS_APU)
60 mgpu_info.num_apu--;
61 else
62 mgpu_info.num_dgpu--;
63 break;
64 }
65 }
66
67 mutex_unlock(&mgpu_info.mutex);
68}
69
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76
77
78void amdgpu_driver_unload_kms(struct drm_device *dev)
79{
80 struct amdgpu_device *adev = drm_to_adev(dev);
81
82 if (adev == NULL)
83 return;
84
85 amdgpu_unregister_gpu_instance(adev);
86
87 if (adev->rmmio == NULL)
88 return;
89
90 if (adev->runpm) {
91 pm_runtime_get_sync(dev->dev);
92 pm_runtime_forbid(dev->dev);
93 }
94
95 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_UNLOAD))
96 DRM_WARN("smart shift update failed\n");
97
98 amdgpu_acpi_fini(adev);
99 amdgpu_device_fini_hw(adev);
100}
101
102void amdgpu_register_gpu_instance(struct amdgpu_device *adev)
103{
104 struct amdgpu_gpu_instance *gpu_instance;
105
106 mutex_lock(&mgpu_info.mutex);
107
108 if (mgpu_info.num_gpu >= MAX_GPU_INSTANCE) {
109 DRM_ERROR("Cannot register more gpu instance\n");
110 mutex_unlock(&mgpu_info.mutex);
111 return;
112 }
113
114 gpu_instance = &(mgpu_info.gpu_ins[mgpu_info.num_gpu]);
115 gpu_instance->adev = adev;
116 gpu_instance->mgpu_fan_enabled = 0;
117
118 mgpu_info.num_gpu++;
119 if (adev->flags & AMD_IS_APU)
120 mgpu_info.num_apu++;
121 else
122 mgpu_info.num_dgpu++;
123
124 mutex_unlock(&mgpu_info.mutex);
125}
126
127static void amdgpu_get_audio_func(struct amdgpu_device *adev)
128{
129 struct pci_dev *p = NULL;
130
131 p = pci_get_domain_bus_and_slot(pci_domain_nr(adev->pdev->bus),
132 adev->pdev->bus->number, 1);
133 if (p) {
134 pm_runtime_get_sync(&p->dev);
135
136 pm_runtime_mark_last_busy(&p->dev);
137 pm_runtime_put_autosuspend(&p->dev);
138
139 pci_dev_put(p);
140 }
141}
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151
152int amdgpu_driver_load_kms(struct amdgpu_device *adev, unsigned long flags)
153{
154 struct drm_device *dev;
155 struct pci_dev *parent;
156 int r, acpi_status;
157
158 dev = adev_to_drm(adev);
159
160 if (amdgpu_has_atpx() &&
161 (amdgpu_is_atpx_hybrid() ||
162 amdgpu_has_atpx_dgpu_power_cntl()) &&
163 ((flags & AMD_IS_APU) == 0) &&
164 !pci_is_thunderbolt_attached(to_pci_dev(dev->dev)))
165 flags |= AMD_IS_PX;
166
167 parent = pci_upstream_bridge(adev->pdev);
168 adev->has_pr3 = parent ? pci_pr3_present(parent) : false;
169
170
171
172
173
174
175
176 r = amdgpu_device_init(adev, flags);
177 if (r) {
178 dev_err(dev->dev, "Fatal error during GPU init\n");
179 goto out;
180 }
181
182 if (amdgpu_device_supports_px(dev) &&
183 (amdgpu_runtime_pm != 0)) {
184 adev->runpm = true;
185 dev_info(adev->dev, "Using ATPX for runtime pm\n");
186 } else if (amdgpu_device_supports_boco(dev) &&
187 (amdgpu_runtime_pm != 0)) {
188 adev->runpm = true;
189 dev_info(adev->dev, "Using BOCO for runtime pm\n");
190 } else if (amdgpu_device_supports_baco(dev) &&
191 (amdgpu_runtime_pm != 0)) {
192 switch (adev->asic_type) {
193 case CHIP_VEGA20:
194 case CHIP_ARCTURUS:
195
196 if (amdgpu_runtime_pm > 0)
197 adev->runpm = true;
198 break;
199 case CHIP_VEGA10:
200
201 if (!adev->gmc.noretry)
202 adev->runpm = true;
203 break;
204 default:
205
206 adev->runpm = true;
207 break;
208 }
209 if (adev->runpm)
210 dev_info(adev->dev, "Using BACO for runtime pm\n");
211 }
212
213
214
215
216
217 acpi_status = amdgpu_acpi_init(adev);
218 if (acpi_status)
219 dev_dbg(dev->dev, "Error during ACPI methods call\n");
220
221 if (adev->runpm) {
222
223 if (amdgpu_device_supports_px(dev))
224 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_NO_DIRECT_COMPLETE);
225
226 if (amdgpu_device_supports_boco(dev))
227 dev_pm_set_driver_flags(dev->dev, DPM_FLAG_SMART_PREPARE |
228 DPM_FLAG_SMART_SUSPEND |
229 DPM_FLAG_MAY_SKIP_RESUME);
230 pm_runtime_use_autosuspend(dev->dev);
231 pm_runtime_set_autosuspend_delay(dev->dev, 5000);
232
233 pm_runtime_allow(dev->dev);
234
235 pm_runtime_mark_last_busy(dev->dev);
236 pm_runtime_put_autosuspend(dev->dev);
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256
257 if (amdgpu_device_supports_baco(dev) &&
258 !(adev->flags & AMD_IS_APU) &&
259 (adev->asic_type >= CHIP_NAVI10))
260 amdgpu_get_audio_func(adev);
261 }
262
263 if (amdgpu_acpi_smart_shift_update(dev, AMDGPU_SS_DRV_LOAD))
264 DRM_WARN("smart shift update failed\n");
265
266out:
267 if (r) {
268
269 if (adev->rmmio && adev->runpm)
270 pm_runtime_put_noidle(dev->dev);
271 amdgpu_driver_unload_kms(dev);
272 }
273
274 return r;
275}
276
277static int amdgpu_firmware_info(struct drm_amdgpu_info_firmware *fw_info,
278 struct drm_amdgpu_query_fw *query_fw,
279 struct amdgpu_device *adev)
280{
281 switch (query_fw->fw_type) {
282 case AMDGPU_INFO_FW_VCE:
283 fw_info->ver = adev->vce.fw_version;
284 fw_info->feature = adev->vce.fb_version;
285 break;
286 case AMDGPU_INFO_FW_UVD:
287 fw_info->ver = adev->uvd.fw_version;
288 fw_info->feature = 0;
289 break;
290 case AMDGPU_INFO_FW_VCN:
291 fw_info->ver = adev->vcn.fw_version;
292 fw_info->feature = 0;
293 break;
294 case AMDGPU_INFO_FW_GMC:
295 fw_info->ver = adev->gmc.fw_version;
296 fw_info->feature = 0;
297 break;
298 case AMDGPU_INFO_FW_GFX_ME:
299 fw_info->ver = adev->gfx.me_fw_version;
300 fw_info->feature = adev->gfx.me_feature_version;
301 break;
302 case AMDGPU_INFO_FW_GFX_PFP:
303 fw_info->ver = adev->gfx.pfp_fw_version;
304 fw_info->feature = adev->gfx.pfp_feature_version;
305 break;
306 case AMDGPU_INFO_FW_GFX_CE:
307 fw_info->ver = adev->gfx.ce_fw_version;
308 fw_info->feature = adev->gfx.ce_feature_version;
309 break;
310 case AMDGPU_INFO_FW_GFX_RLC:
311 fw_info->ver = adev->gfx.rlc_fw_version;
312 fw_info->feature = adev->gfx.rlc_feature_version;
313 break;
314 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL:
315 fw_info->ver = adev->gfx.rlc_srlc_fw_version;
316 fw_info->feature = adev->gfx.rlc_srlc_feature_version;
317 break;
318 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM:
319 fw_info->ver = adev->gfx.rlc_srlg_fw_version;
320 fw_info->feature = adev->gfx.rlc_srlg_feature_version;
321 break;
322 case AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM:
323 fw_info->ver = adev->gfx.rlc_srls_fw_version;
324 fw_info->feature = adev->gfx.rlc_srls_feature_version;
325 break;
326 case AMDGPU_INFO_FW_GFX_MEC:
327 if (query_fw->index == 0) {
328 fw_info->ver = adev->gfx.mec_fw_version;
329 fw_info->feature = adev->gfx.mec_feature_version;
330 } else if (query_fw->index == 1) {
331 fw_info->ver = adev->gfx.mec2_fw_version;
332 fw_info->feature = adev->gfx.mec2_feature_version;
333 } else
334 return -EINVAL;
335 break;
336 case AMDGPU_INFO_FW_SMC:
337 fw_info->ver = adev->pm.fw_version;
338 fw_info->feature = 0;
339 break;
340 case AMDGPU_INFO_FW_TA:
341 switch (query_fw->index) {
342 case TA_FW_TYPE_PSP_XGMI:
343 fw_info->ver = adev->psp.ta_fw_version;
344 fw_info->feature = adev->psp.xgmi.feature_version;
345 break;
346 case TA_FW_TYPE_PSP_RAS:
347 fw_info->ver = adev->psp.ta_fw_version;
348 fw_info->feature = adev->psp.ras.feature_version;
349 break;
350 case TA_FW_TYPE_PSP_HDCP:
351 fw_info->ver = adev->psp.ta_fw_version;
352 fw_info->feature = adev->psp.hdcp.feature_version;
353 break;
354 case TA_FW_TYPE_PSP_DTM:
355 fw_info->ver = adev->psp.ta_fw_version;
356 fw_info->feature = adev->psp.dtm.feature_version;
357 break;
358 case TA_FW_TYPE_PSP_RAP:
359 fw_info->ver = adev->psp.ta_fw_version;
360 fw_info->feature = adev->psp.rap.feature_version;
361 break;
362 case TA_FW_TYPE_PSP_SECUREDISPLAY:
363 fw_info->ver = adev->psp.ta_fw_version;
364 fw_info->feature = adev->psp.securedisplay.feature_version;
365 break;
366 default:
367 return -EINVAL;
368 }
369 break;
370 case AMDGPU_INFO_FW_SDMA:
371 if (query_fw->index >= adev->sdma.num_instances)
372 return -EINVAL;
373 fw_info->ver = adev->sdma.instance[query_fw->index].fw_version;
374 fw_info->feature = adev->sdma.instance[query_fw->index].feature_version;
375 break;
376 case AMDGPU_INFO_FW_SOS:
377 fw_info->ver = adev->psp.sos.fw_version;
378 fw_info->feature = adev->psp.sos.feature_version;
379 break;
380 case AMDGPU_INFO_FW_ASD:
381 fw_info->ver = adev->psp.asd.fw_version;
382 fw_info->feature = adev->psp.asd.feature_version;
383 break;
384 case AMDGPU_INFO_FW_DMCU:
385 fw_info->ver = adev->dm.dmcu_fw_version;
386 fw_info->feature = 0;
387 break;
388 case AMDGPU_INFO_FW_DMCUB:
389 fw_info->ver = adev->dm.dmcub_fw_version;
390 fw_info->feature = 0;
391 break;
392 case AMDGPU_INFO_FW_TOC:
393 fw_info->ver = adev->psp.toc.fw_version;
394 fw_info->feature = adev->psp.toc.feature_version;
395 break;
396 default:
397 return -EINVAL;
398 }
399 return 0;
400}
401
402static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
403 struct drm_amdgpu_info *info,
404 struct drm_amdgpu_info_hw_ip *result)
405{
406 uint32_t ib_start_alignment = 0;
407 uint32_t ib_size_alignment = 0;
408 enum amd_ip_block_type type;
409 unsigned int num_rings = 0;
410 unsigned int i, j;
411
412 if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
413 return -EINVAL;
414
415 switch (info->query_hw_ip.type) {
416 case AMDGPU_HW_IP_GFX:
417 type = AMD_IP_BLOCK_TYPE_GFX;
418 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
419 if (adev->gfx.gfx_ring[i].sched.ready)
420 ++num_rings;
421 ib_start_alignment = 32;
422 ib_size_alignment = 32;
423 break;
424 case AMDGPU_HW_IP_COMPUTE:
425 type = AMD_IP_BLOCK_TYPE_GFX;
426 for (i = 0; i < adev->gfx.num_compute_rings; i++)
427 if (adev->gfx.compute_ring[i].sched.ready)
428 ++num_rings;
429 ib_start_alignment = 32;
430 ib_size_alignment = 32;
431 break;
432 case AMDGPU_HW_IP_DMA:
433 type = AMD_IP_BLOCK_TYPE_SDMA;
434 for (i = 0; i < adev->sdma.num_instances; i++)
435 if (adev->sdma.instance[i].ring.sched.ready)
436 ++num_rings;
437 ib_start_alignment = 256;
438 ib_size_alignment = 4;
439 break;
440 case AMDGPU_HW_IP_UVD:
441 type = AMD_IP_BLOCK_TYPE_UVD;
442 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
443 if (adev->uvd.harvest_config & (1 << i))
444 continue;
445
446 if (adev->uvd.inst[i].ring.sched.ready)
447 ++num_rings;
448 }
449 ib_start_alignment = 64;
450 ib_size_alignment = 64;
451 break;
452 case AMDGPU_HW_IP_VCE:
453 type = AMD_IP_BLOCK_TYPE_VCE;
454 for (i = 0; i < adev->vce.num_rings; i++)
455 if (adev->vce.ring[i].sched.ready)
456 ++num_rings;
457 ib_start_alignment = 4;
458 ib_size_alignment = 1;
459 break;
460 case AMDGPU_HW_IP_UVD_ENC:
461 type = AMD_IP_BLOCK_TYPE_UVD;
462 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
463 if (adev->uvd.harvest_config & (1 << i))
464 continue;
465
466 for (j = 0; j < adev->uvd.num_enc_rings; j++)
467 if (adev->uvd.inst[i].ring_enc[j].sched.ready)
468 ++num_rings;
469 }
470 ib_start_alignment = 64;
471 ib_size_alignment = 64;
472 break;
473 case AMDGPU_HW_IP_VCN_DEC:
474 type = AMD_IP_BLOCK_TYPE_VCN;
475 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
476 if (adev->uvd.harvest_config & (1 << i))
477 continue;
478
479 if (adev->vcn.inst[i].ring_dec.sched.ready)
480 ++num_rings;
481 }
482 ib_start_alignment = 16;
483 ib_size_alignment = 16;
484 break;
485 case AMDGPU_HW_IP_VCN_ENC:
486 type = AMD_IP_BLOCK_TYPE_VCN;
487 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
488 if (adev->uvd.harvest_config & (1 << i))
489 continue;
490
491 for (j = 0; j < adev->vcn.num_enc_rings; j++)
492 if (adev->vcn.inst[i].ring_enc[j].sched.ready)
493 ++num_rings;
494 }
495 ib_start_alignment = 64;
496 ib_size_alignment = 1;
497 break;
498 case AMDGPU_HW_IP_VCN_JPEG:
499 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
500 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
501
502 for (i = 0; i < adev->jpeg.num_jpeg_inst; i++) {
503 if (adev->jpeg.harvest_config & (1 << i))
504 continue;
505
506 if (adev->jpeg.inst[i].ring_dec.sched.ready)
507 ++num_rings;
508 }
509 ib_start_alignment = 16;
510 ib_size_alignment = 16;
511 break;
512 default:
513 return -EINVAL;
514 }
515
516 for (i = 0; i < adev->num_ip_blocks; i++)
517 if (adev->ip_blocks[i].version->type == type &&
518 adev->ip_blocks[i].status.valid)
519 break;
520
521 if (i == adev->num_ip_blocks)
522 return 0;
523
524 num_rings = min(amdgpu_ctx_num_entities[info->query_hw_ip.type],
525 num_rings);
526
527 result->hw_ip_version_major = adev->ip_blocks[i].version->major;
528 result->hw_ip_version_minor = adev->ip_blocks[i].version->minor;
529 result->capabilities_flags = 0;
530 result->available_rings = (1 << num_rings) - 1;
531 result->ib_start_alignment = ib_start_alignment;
532 result->ib_size_alignment = ib_size_alignment;
533 return 0;
534}
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551int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
552{
553 struct amdgpu_device *adev = drm_to_adev(dev);
554 struct drm_amdgpu_info *info = data;
555 struct amdgpu_mode_info *minfo = &adev->mode_info;
556 void __user *out = (void __user *)(uintptr_t)info->return_pointer;
557 uint32_t size = info->return_size;
558 struct drm_crtc *crtc;
559 uint32_t ui32 = 0;
560 uint64_t ui64 = 0;
561 int i, found;
562 int ui32_size = sizeof(ui32);
563
564 if (!info->return_size || !info->return_pointer)
565 return -EINVAL;
566
567 switch (info->query) {
568 case AMDGPU_INFO_ACCEL_WORKING:
569 ui32 = adev->accel_working;
570 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
571 case AMDGPU_INFO_CRTC_FROM_ID:
572 for (i = 0, found = 0; i < adev->mode_info.num_crtc; i++) {
573 crtc = (struct drm_crtc *)minfo->crtcs[i];
574 if (crtc && crtc->base.id == info->mode_crtc.id) {
575 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
576 ui32 = amdgpu_crtc->crtc_id;
577 found = 1;
578 break;
579 }
580 }
581 if (!found) {
582 DRM_DEBUG_KMS("unknown crtc id %d\n", info->mode_crtc.id);
583 return -EINVAL;
584 }
585 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
586 case AMDGPU_INFO_HW_IP_INFO: {
587 struct drm_amdgpu_info_hw_ip ip = {};
588 int ret;
589
590 ret = amdgpu_hw_ip_info(adev, info, &ip);
591 if (ret)
592 return ret;
593
594 ret = copy_to_user(out, &ip, min((size_t)size, sizeof(ip)));
595 return ret ? -EFAULT : 0;
596 }
597 case AMDGPU_INFO_HW_IP_COUNT: {
598 enum amd_ip_block_type type;
599 uint32_t count = 0;
600
601 switch (info->query_hw_ip.type) {
602 case AMDGPU_HW_IP_GFX:
603 type = AMD_IP_BLOCK_TYPE_GFX;
604 break;
605 case AMDGPU_HW_IP_COMPUTE:
606 type = AMD_IP_BLOCK_TYPE_GFX;
607 break;
608 case AMDGPU_HW_IP_DMA:
609 type = AMD_IP_BLOCK_TYPE_SDMA;
610 break;
611 case AMDGPU_HW_IP_UVD:
612 type = AMD_IP_BLOCK_TYPE_UVD;
613 break;
614 case AMDGPU_HW_IP_VCE:
615 type = AMD_IP_BLOCK_TYPE_VCE;
616 break;
617 case AMDGPU_HW_IP_UVD_ENC:
618 type = AMD_IP_BLOCK_TYPE_UVD;
619 break;
620 case AMDGPU_HW_IP_VCN_DEC:
621 case AMDGPU_HW_IP_VCN_ENC:
622 type = AMD_IP_BLOCK_TYPE_VCN;
623 break;
624 case AMDGPU_HW_IP_VCN_JPEG:
625 type = (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_JPEG)) ?
626 AMD_IP_BLOCK_TYPE_JPEG : AMD_IP_BLOCK_TYPE_VCN;
627 break;
628 default:
629 return -EINVAL;
630 }
631
632 for (i = 0; i < adev->num_ip_blocks; i++)
633 if (adev->ip_blocks[i].version->type == type &&
634 adev->ip_blocks[i].status.valid &&
635 count < AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
636 count++;
637
638 return copy_to_user(out, &count, min(size, 4u)) ? -EFAULT : 0;
639 }
640 case AMDGPU_INFO_TIMESTAMP:
641 ui64 = amdgpu_gfx_get_gpu_clock_counter(adev);
642 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
643 case AMDGPU_INFO_FW_VERSION: {
644 struct drm_amdgpu_info_firmware fw_info;
645 int ret;
646
647
648 if (info->query_fw.ip_instance != 0)
649 return -EINVAL;
650
651 ret = amdgpu_firmware_info(&fw_info, &info->query_fw, adev);
652 if (ret)
653 return ret;
654
655 return copy_to_user(out, &fw_info,
656 min((size_t)size, sizeof(fw_info))) ? -EFAULT : 0;
657 }
658 case AMDGPU_INFO_NUM_BYTES_MOVED:
659 ui64 = atomic64_read(&adev->num_bytes_moved);
660 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
661 case AMDGPU_INFO_NUM_EVICTIONS:
662 ui64 = atomic64_read(&adev->num_evictions);
663 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
664 case AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS:
665 ui64 = atomic64_read(&adev->num_vram_cpu_page_faults);
666 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
667 case AMDGPU_INFO_VRAM_USAGE:
668 ui64 = amdgpu_vram_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
669 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
670 case AMDGPU_INFO_VIS_VRAM_USAGE:
671 ui64 = amdgpu_vram_mgr_vis_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM));
672 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
673 case AMDGPU_INFO_GTT_USAGE:
674 ui64 = amdgpu_gtt_mgr_usage(ttm_manager_type(&adev->mman.bdev, TTM_PL_TT));
675 return copy_to_user(out, &ui64, min(size, 8u)) ? -EFAULT : 0;
676 case AMDGPU_INFO_GDS_CONFIG: {
677 struct drm_amdgpu_info_gds gds_info;
678
679 memset(&gds_info, 0, sizeof(gds_info));
680 gds_info.compute_partition_size = adev->gds.gds_size;
681 gds_info.gds_total_size = adev->gds.gds_size;
682 gds_info.gws_per_compute_partition = adev->gds.gws_size;
683 gds_info.oa_per_compute_partition = adev->gds.oa_size;
684 return copy_to_user(out, &gds_info,
685 min((size_t)size, sizeof(gds_info))) ? -EFAULT : 0;
686 }
687 case AMDGPU_INFO_VRAM_GTT: {
688 struct drm_amdgpu_info_vram_gtt vram_gtt;
689
690 vram_gtt.vram_size = adev->gmc.real_vram_size -
691 atomic64_read(&adev->vram_pin_size) -
692 AMDGPU_VM_RESERVED_VRAM;
693 vram_gtt.vram_cpu_accessible_size =
694 min(adev->gmc.visible_vram_size -
695 atomic64_read(&adev->visible_pin_size),
696 vram_gtt.vram_size);
697 vram_gtt.gtt_size = ttm_manager_type(&adev->mman.bdev, TTM_PL_TT)->size;
698 vram_gtt.gtt_size *= PAGE_SIZE;
699 vram_gtt.gtt_size -= atomic64_read(&adev->gart_pin_size);
700 return copy_to_user(out, &vram_gtt,
701 min((size_t)size, sizeof(vram_gtt))) ? -EFAULT : 0;
702 }
703 case AMDGPU_INFO_MEMORY: {
704 struct drm_amdgpu_memory_info mem;
705 struct ttm_resource_manager *vram_man =
706 ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
707 struct ttm_resource_manager *gtt_man =
708 ttm_manager_type(&adev->mman.bdev, TTM_PL_TT);
709 memset(&mem, 0, sizeof(mem));
710 mem.vram.total_heap_size = adev->gmc.real_vram_size;
711 mem.vram.usable_heap_size = adev->gmc.real_vram_size -
712 atomic64_read(&adev->vram_pin_size) -
713 AMDGPU_VM_RESERVED_VRAM;
714 mem.vram.heap_usage =
715 amdgpu_vram_mgr_usage(vram_man);
716 mem.vram.max_allocation = mem.vram.usable_heap_size * 3 / 4;
717
718 mem.cpu_accessible_vram.total_heap_size =
719 adev->gmc.visible_vram_size;
720 mem.cpu_accessible_vram.usable_heap_size =
721 min(adev->gmc.visible_vram_size -
722 atomic64_read(&adev->visible_pin_size),
723 mem.vram.usable_heap_size);
724 mem.cpu_accessible_vram.heap_usage =
725 amdgpu_vram_mgr_vis_usage(vram_man);
726 mem.cpu_accessible_vram.max_allocation =
727 mem.cpu_accessible_vram.usable_heap_size * 3 / 4;
728
729 mem.gtt.total_heap_size = gtt_man->size;
730 mem.gtt.total_heap_size *= PAGE_SIZE;
731 mem.gtt.usable_heap_size = mem.gtt.total_heap_size -
732 atomic64_read(&adev->gart_pin_size);
733 mem.gtt.heap_usage =
734 amdgpu_gtt_mgr_usage(gtt_man);
735 mem.gtt.max_allocation = mem.gtt.usable_heap_size * 3 / 4;
736
737 return copy_to_user(out, &mem,
738 min((size_t)size, sizeof(mem)))
739 ? -EFAULT : 0;
740 }
741 case AMDGPU_INFO_READ_MMR_REG: {
742 unsigned n, alloc_size;
743 uint32_t *regs;
744 unsigned se_num = (info->read_mmr_reg.instance >>
745 AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
746 AMDGPU_INFO_MMR_SE_INDEX_MASK;
747 unsigned sh_num = (info->read_mmr_reg.instance >>
748 AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
749 AMDGPU_INFO_MMR_SH_INDEX_MASK;
750
751
752
753 if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
754 se_num = 0xffffffff;
755 else if (se_num >= AMDGPU_GFX_MAX_SE)
756 return -EINVAL;
757 if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
758 sh_num = 0xffffffff;
759 else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
760 return -EINVAL;
761
762 if (info->read_mmr_reg.count > 128)
763 return -EINVAL;
764
765 regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
766 if (!regs)
767 return -ENOMEM;
768 alloc_size = info->read_mmr_reg.count * sizeof(*regs);
769
770 amdgpu_gfx_off_ctrl(adev, false);
771 for (i = 0; i < info->read_mmr_reg.count; i++) {
772 if (amdgpu_asic_read_register(adev, se_num, sh_num,
773 info->read_mmr_reg.dword_offset + i,
774 ®s[i])) {
775 DRM_DEBUG_KMS("unallowed offset %#x\n",
776 info->read_mmr_reg.dword_offset + i);
777 kfree(regs);
778 amdgpu_gfx_off_ctrl(adev, true);
779 return -EFAULT;
780 }
781 }
782 amdgpu_gfx_off_ctrl(adev, true);
783 n = copy_to_user(out, regs, min(size, alloc_size));
784 kfree(regs);
785 return n ? -EFAULT : 0;
786 }
787 case AMDGPU_INFO_DEV_INFO: {
788 struct drm_amdgpu_info_device *dev_info;
789 uint64_t vm_size;
790 int ret;
791
792 dev_info = kzalloc(sizeof(*dev_info), GFP_KERNEL);
793 if (!dev_info)
794 return -ENOMEM;
795
796 dev_info->device_id = adev->pdev->device;
797 dev_info->chip_rev = adev->rev_id;
798 dev_info->external_rev = adev->external_rev_id;
799 dev_info->pci_rev = adev->pdev->revision;
800 dev_info->family = adev->family;
801 dev_info->num_shader_engines = adev->gfx.config.max_shader_engines;
802 dev_info->num_shader_arrays_per_engine = adev->gfx.config.max_sh_per_se;
803
804 dev_info->gpu_counter_freq = amdgpu_asic_get_xclk(adev) * 10;
805 if (adev->pm.dpm_enabled) {
806 dev_info->max_engine_clock = amdgpu_dpm_get_sclk(adev, false) * 10;
807 dev_info->max_memory_clock = amdgpu_dpm_get_mclk(adev, false) * 10;
808 } else {
809 dev_info->max_engine_clock = adev->clock.default_sclk * 10;
810 dev_info->max_memory_clock = adev->clock.default_mclk * 10;
811 }
812 dev_info->enabled_rb_pipes_mask = adev->gfx.config.backend_enable_mask;
813 dev_info->num_rb_pipes = adev->gfx.config.max_backends_per_se *
814 adev->gfx.config.max_shader_engines;
815 dev_info->num_hw_gfx_contexts = adev->gfx.config.max_hw_contexts;
816 dev_info->_pad = 0;
817 dev_info->ids_flags = 0;
818 if (adev->flags & AMD_IS_APU)
819 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_FUSION;
820 if (amdgpu_mcbp || amdgpu_sriov_vf(adev))
821 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_PREEMPTION;
822 if (amdgpu_is_tmz(adev))
823 dev_info->ids_flags |= AMDGPU_IDS_FLAGS_TMZ;
824
825 vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE;
826 vm_size -= AMDGPU_VA_RESERVED_SIZE;
827
828
829 if (adev->vce.fw_version &&
830 adev->vce.fw_version < AMDGPU_VCE_FW_53_45)
831 vm_size = min(vm_size, 1ULL << 40);
832
833 dev_info->virtual_address_offset = AMDGPU_VA_RESERVED_SIZE;
834 dev_info->virtual_address_max =
835 min(vm_size, AMDGPU_GMC_HOLE_START);
836
837 if (vm_size > AMDGPU_GMC_HOLE_START) {
838 dev_info->high_va_offset = AMDGPU_GMC_HOLE_END;
839 dev_info->high_va_max = AMDGPU_GMC_HOLE_END | vm_size;
840 }
841 dev_info->virtual_address_alignment = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
842 dev_info->pte_fragment_size = (1 << adev->vm_manager.fragment_size) * AMDGPU_GPU_PAGE_SIZE;
843 dev_info->gart_page_size = max_t(u32, PAGE_SIZE, AMDGPU_GPU_PAGE_SIZE);
844 dev_info->cu_active_number = adev->gfx.cu_info.number;
845 dev_info->cu_ao_mask = adev->gfx.cu_info.ao_cu_mask;
846 dev_info->ce_ram_size = adev->gfx.ce_ram_size;
847 memcpy(&dev_info->cu_ao_bitmap[0], &adev->gfx.cu_info.ao_cu_bitmap[0],
848 sizeof(adev->gfx.cu_info.ao_cu_bitmap));
849 memcpy(&dev_info->cu_bitmap[0], &adev->gfx.cu_info.bitmap[0],
850 sizeof(adev->gfx.cu_info.bitmap));
851 dev_info->vram_type = adev->gmc.vram_type;
852 dev_info->vram_bit_width = adev->gmc.vram_width;
853 dev_info->vce_harvest_config = adev->vce.harvest_config;
854 dev_info->gc_double_offchip_lds_buf =
855 adev->gfx.config.double_offchip_lds_buf;
856 dev_info->wave_front_size = adev->gfx.cu_info.wave_front_size;
857 dev_info->num_shader_visible_vgprs = adev->gfx.config.max_gprs;
858 dev_info->num_cu_per_sh = adev->gfx.config.max_cu_per_sh;
859 dev_info->num_tcc_blocks = adev->gfx.config.max_texture_channel_caches;
860 dev_info->gs_vgt_table_depth = adev->gfx.config.gs_vgt_table_depth;
861 dev_info->gs_prim_buffer_depth = adev->gfx.config.gs_prim_buffer_depth;
862 dev_info->max_gs_waves_per_vgt = adev->gfx.config.max_gs_threads;
863
864 if (adev->family >= AMDGPU_FAMILY_NV)
865 dev_info->pa_sc_tile_steering_override =
866 adev->gfx.config.pa_sc_tile_steering_override;
867
868 dev_info->tcc_disabled_mask = adev->gfx.config.tcc_disabled_mask;
869
870 ret = copy_to_user(out, dev_info,
871 min((size_t)size, sizeof(*dev_info))) ? -EFAULT : 0;
872 kfree(dev_info);
873 return ret;
874 }
875 case AMDGPU_INFO_VCE_CLOCK_TABLE: {
876 unsigned i;
877 struct drm_amdgpu_info_vce_clock_table vce_clk_table = {};
878 struct amd_vce_state *vce_state;
879
880 for (i = 0; i < AMDGPU_VCE_CLOCK_TABLE_ENTRIES; i++) {
881 vce_state = amdgpu_dpm_get_vce_clock_state(adev, i);
882 if (vce_state) {
883 vce_clk_table.entries[i].sclk = vce_state->sclk;
884 vce_clk_table.entries[i].mclk = vce_state->mclk;
885 vce_clk_table.entries[i].eclk = vce_state->evclk;
886 vce_clk_table.num_valid_entries++;
887 }
888 }
889
890 return copy_to_user(out, &vce_clk_table,
891 min((size_t)size, sizeof(vce_clk_table))) ? -EFAULT : 0;
892 }
893 case AMDGPU_INFO_VBIOS: {
894 uint32_t bios_size = adev->bios_size;
895
896 switch (info->vbios_info.type) {
897 case AMDGPU_INFO_VBIOS_SIZE:
898 return copy_to_user(out, &bios_size,
899 min((size_t)size, sizeof(bios_size)))
900 ? -EFAULT : 0;
901 case AMDGPU_INFO_VBIOS_IMAGE: {
902 uint8_t *bios;
903 uint32_t bios_offset = info->vbios_info.offset;
904
905 if (bios_offset >= bios_size)
906 return -EINVAL;
907
908 bios = adev->bios + bios_offset;
909 return copy_to_user(out, bios,
910 min((size_t)size, (size_t)(bios_size - bios_offset)))
911 ? -EFAULT : 0;
912 }
913 case AMDGPU_INFO_VBIOS_INFO: {
914 struct drm_amdgpu_info_vbios vbios_info = {};
915 struct atom_context *atom_context;
916
917 atom_context = adev->mode_info.atom_context;
918 memcpy(vbios_info.name, atom_context->name, sizeof(atom_context->name));
919 memcpy(vbios_info.vbios_pn, atom_context->vbios_pn, sizeof(atom_context->vbios_pn));
920 vbios_info.version = atom_context->version;
921 memcpy(vbios_info.vbios_ver_str, atom_context->vbios_ver_str,
922 sizeof(atom_context->vbios_ver_str));
923 memcpy(vbios_info.date, atom_context->date, sizeof(atom_context->date));
924
925 return copy_to_user(out, &vbios_info,
926 min((size_t)size, sizeof(vbios_info))) ? -EFAULT : 0;
927 }
928 default:
929 DRM_DEBUG_KMS("Invalid request %d\n",
930 info->vbios_info.type);
931 return -EINVAL;
932 }
933 }
934 case AMDGPU_INFO_NUM_HANDLES: {
935 struct drm_amdgpu_info_num_handles handle;
936
937 switch (info->query_hw_ip.type) {
938 case AMDGPU_HW_IP_UVD:
939
940 if (adev->asic_type < CHIP_POLARIS10) {
941 handle.uvd_max_handles = adev->uvd.max_handles;
942 handle.uvd_used_handles = amdgpu_uvd_used_handles(adev);
943
944 return copy_to_user(out, &handle,
945 min((size_t)size, sizeof(handle))) ? -EFAULT : 0;
946 } else {
947 return -ENODATA;
948 }
949
950 break;
951 default:
952 return -EINVAL;
953 }
954 }
955 case AMDGPU_INFO_SENSOR: {
956 if (!adev->pm.dpm_enabled)
957 return -ENOENT;
958
959 switch (info->sensor_info.type) {
960 case AMDGPU_INFO_SENSOR_GFX_SCLK:
961
962 if (amdgpu_dpm_read_sensor(adev,
963 AMDGPU_PP_SENSOR_GFX_SCLK,
964 (void *)&ui32, &ui32_size)) {
965 return -EINVAL;
966 }
967 ui32 /= 100;
968 break;
969 case AMDGPU_INFO_SENSOR_GFX_MCLK:
970
971 if (amdgpu_dpm_read_sensor(adev,
972 AMDGPU_PP_SENSOR_GFX_MCLK,
973 (void *)&ui32, &ui32_size)) {
974 return -EINVAL;
975 }
976 ui32 /= 100;
977 break;
978 case AMDGPU_INFO_SENSOR_GPU_TEMP:
979
980 if (amdgpu_dpm_read_sensor(adev,
981 AMDGPU_PP_SENSOR_GPU_TEMP,
982 (void *)&ui32, &ui32_size)) {
983 return -EINVAL;
984 }
985 break;
986 case AMDGPU_INFO_SENSOR_GPU_LOAD:
987
988 if (amdgpu_dpm_read_sensor(adev,
989 AMDGPU_PP_SENSOR_GPU_LOAD,
990 (void *)&ui32, &ui32_size)) {
991 return -EINVAL;
992 }
993 break;
994 case AMDGPU_INFO_SENSOR_GPU_AVG_POWER:
995
996 if (amdgpu_dpm_read_sensor(adev,
997 AMDGPU_PP_SENSOR_GPU_POWER,
998 (void *)&ui32, &ui32_size)) {
999 return -EINVAL;
1000 }
1001 ui32 >>= 8;
1002 break;
1003 case AMDGPU_INFO_SENSOR_VDDNB:
1004
1005 if (amdgpu_dpm_read_sensor(adev,
1006 AMDGPU_PP_SENSOR_VDDNB,
1007 (void *)&ui32, &ui32_size)) {
1008 return -EINVAL;
1009 }
1010 break;
1011 case AMDGPU_INFO_SENSOR_VDDGFX:
1012
1013 if (amdgpu_dpm_read_sensor(adev,
1014 AMDGPU_PP_SENSOR_VDDGFX,
1015 (void *)&ui32, &ui32_size)) {
1016 return -EINVAL;
1017 }
1018 break;
1019 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK:
1020
1021 if (amdgpu_dpm_read_sensor(adev,
1022 AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK,
1023 (void *)&ui32, &ui32_size)) {
1024 return -EINVAL;
1025 }
1026 ui32 /= 100;
1027 break;
1028 case AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK:
1029
1030 if (amdgpu_dpm_read_sensor(adev,
1031 AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK,
1032 (void *)&ui32, &ui32_size)) {
1033 return -EINVAL;
1034 }
1035 ui32 /= 100;
1036 break;
1037 default:
1038 DRM_DEBUG_KMS("Invalid request %d\n",
1039 info->sensor_info.type);
1040 return -EINVAL;
1041 }
1042 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1043 }
1044 case AMDGPU_INFO_VRAM_LOST_COUNTER:
1045 ui32 = atomic_read(&adev->vram_lost_counter);
1046 return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0;
1047 case AMDGPU_INFO_RAS_ENABLED_FEATURES: {
1048 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
1049 uint64_t ras_mask;
1050
1051 if (!ras)
1052 return -EINVAL;
1053 ras_mask = (uint64_t)adev->ras_enabled << 32 | ras->features;
1054
1055 return copy_to_user(out, &ras_mask,
1056 min_t(u64, size, sizeof(ras_mask))) ?
1057 -EFAULT : 0;
1058 }
1059 case AMDGPU_INFO_VIDEO_CAPS: {
1060 const struct amdgpu_video_codecs *codecs;
1061 struct drm_amdgpu_info_video_caps *caps;
1062 int r;
1063
1064 switch (info->video_cap.type) {
1065 case AMDGPU_INFO_VIDEO_CAPS_DECODE:
1066 r = amdgpu_asic_query_video_codecs(adev, false, &codecs);
1067 if (r)
1068 return -EINVAL;
1069 break;
1070 case AMDGPU_INFO_VIDEO_CAPS_ENCODE:
1071 r = amdgpu_asic_query_video_codecs(adev, true, &codecs);
1072 if (r)
1073 return -EINVAL;
1074 break;
1075 default:
1076 DRM_DEBUG_KMS("Invalid request %d\n",
1077 info->video_cap.type);
1078 return -EINVAL;
1079 }
1080
1081 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
1082 if (!caps)
1083 return -ENOMEM;
1084
1085 for (i = 0; i < codecs->codec_count; i++) {
1086 int idx = codecs->codec_array[i].codec_type;
1087
1088 switch (idx) {
1089 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2:
1090 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4:
1091 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1:
1092 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC:
1093 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC:
1094 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG:
1095 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9:
1096 case AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1:
1097 caps->codec_info[idx].valid = 1;
1098 caps->codec_info[idx].max_width =
1099 codecs->codec_array[i].max_width;
1100 caps->codec_info[idx].max_height =
1101 codecs->codec_array[i].max_height;
1102 caps->codec_info[idx].max_pixels_per_frame =
1103 codecs->codec_array[i].max_pixels_per_frame;
1104 caps->codec_info[idx].max_level =
1105 codecs->codec_array[i].max_level;
1106 break;
1107 default:
1108 break;
1109 }
1110 }
1111 r = copy_to_user(out, caps,
1112 min((size_t)size, sizeof(*caps))) ? -EFAULT : 0;
1113 kfree(caps);
1114 return r;
1115 }
1116 default:
1117 DRM_DEBUG_KMS("Invalid request %d\n", info->query);
1118 return -EINVAL;
1119 }
1120 return 0;
1121}
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134void amdgpu_driver_lastclose_kms(struct drm_device *dev)
1135{
1136 drm_fb_helper_lastclose(dev);
1137 vga_switcheroo_process_delayed_switch();
1138}
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
1150{
1151 struct amdgpu_device *adev = drm_to_adev(dev);
1152 struct amdgpu_fpriv *fpriv;
1153 int r, pasid;
1154
1155
1156 flush_delayed_work(&adev->delayed_init_work);
1157
1158
1159 if (amdgpu_ras_intr_triggered()) {
1160 DRM_ERROR("RAS Intr triggered, device disabled!!");
1161 return -EHWPOISON;
1162 }
1163
1164 file_priv->driver_priv = NULL;
1165
1166 r = pm_runtime_get_sync(dev->dev);
1167 if (r < 0)
1168 goto pm_put;
1169
1170 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
1171 if (unlikely(!fpriv)) {
1172 r = -ENOMEM;
1173 goto out_suspend;
1174 }
1175
1176 pasid = amdgpu_pasid_alloc(16);
1177 if (pasid < 0) {
1178 dev_warn(adev->dev, "No more PASIDs available!");
1179 pasid = 0;
1180 }
1181
1182 r = amdgpu_vm_init(adev, &fpriv->vm);
1183 if (r)
1184 goto error_pasid;
1185
1186 r = amdgpu_vm_set_pasid(adev, &fpriv->vm, pasid);
1187 if (r)
1188 goto error_vm;
1189
1190 fpriv->prt_va = amdgpu_vm_bo_add(adev, &fpriv->vm, NULL);
1191 if (!fpriv->prt_va) {
1192 r = -ENOMEM;
1193 goto error_vm;
1194 }
1195
1196 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1197 uint64_t csa_addr = amdgpu_csa_vaddr(adev) & AMDGPU_GMC_HOLE_MASK;
1198
1199 r = amdgpu_map_static_csa(adev, &fpriv->vm, adev->virt.csa_obj,
1200 &fpriv->csa_va, csa_addr, AMDGPU_CSA_SIZE);
1201 if (r)
1202 goto error_vm;
1203 }
1204
1205 mutex_init(&fpriv->bo_list_lock);
1206 idr_init(&fpriv->bo_list_handles);
1207
1208 amdgpu_ctx_mgr_init(&fpriv->ctx_mgr);
1209
1210 file_priv->driver_priv = fpriv;
1211 goto out_suspend;
1212
1213error_vm:
1214 amdgpu_vm_fini(adev, &fpriv->vm);
1215
1216error_pasid:
1217 if (pasid) {
1218 amdgpu_pasid_free(pasid);
1219 amdgpu_vm_set_pasid(adev, &fpriv->vm, 0);
1220 }
1221
1222 kfree(fpriv);
1223
1224out_suspend:
1225 pm_runtime_mark_last_busy(dev->dev);
1226pm_put:
1227 pm_runtime_put_autosuspend(dev->dev);
1228
1229 return r;
1230}
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240void amdgpu_driver_postclose_kms(struct drm_device *dev,
1241 struct drm_file *file_priv)
1242{
1243 struct amdgpu_device *adev = drm_to_adev(dev);
1244 struct amdgpu_fpriv *fpriv = file_priv->driver_priv;
1245 struct amdgpu_bo_list *list;
1246 struct amdgpu_bo *pd;
1247 u32 pasid;
1248 int handle;
1249
1250 if (!fpriv)
1251 return;
1252
1253 pm_runtime_get_sync(dev->dev);
1254
1255 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD) != NULL)
1256 amdgpu_uvd_free_handles(adev, file_priv);
1257 if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE) != NULL)
1258 amdgpu_vce_free_handles(adev, file_priv);
1259
1260 amdgpu_vm_bo_rmv(adev, fpriv->prt_va);
1261
1262 if (amdgpu_mcbp || amdgpu_sriov_vf(adev)) {
1263
1264 BUG_ON(amdgpu_bo_reserve(adev->virt.csa_obj, true));
1265 amdgpu_vm_bo_rmv(adev, fpriv->csa_va);
1266 fpriv->csa_va = NULL;
1267 amdgpu_bo_unreserve(adev->virt.csa_obj);
1268 }
1269
1270 pasid = fpriv->vm.pasid;
1271 pd = amdgpu_bo_ref(fpriv->vm.root.bo);
1272
1273 amdgpu_ctx_mgr_fini(&fpriv->ctx_mgr);
1274 amdgpu_vm_fini(adev, &fpriv->vm);
1275
1276 if (pasid)
1277 amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid);
1278 amdgpu_bo_unref(&pd);
1279
1280 idr_for_each_entry(&fpriv->bo_list_handles, list, handle)
1281 amdgpu_bo_list_put(list);
1282
1283 idr_destroy(&fpriv->bo_list_handles);
1284 mutex_destroy(&fpriv->bo_list_lock);
1285
1286 kfree(fpriv);
1287 file_priv->driver_priv = NULL;
1288
1289 pm_runtime_mark_last_busy(dev->dev);
1290 pm_runtime_put_autosuspend(dev->dev);
1291}
1292
1293
1294void amdgpu_driver_release_kms(struct drm_device *dev)
1295{
1296 struct amdgpu_device *adev = drm_to_adev(dev);
1297
1298 amdgpu_device_fini_sw(adev);
1299 pci_set_drvdata(adev->pdev, NULL);
1300}
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc)
1314{
1315 struct drm_device *dev = crtc->dev;
1316 unsigned int pipe = crtc->index;
1317 struct amdgpu_device *adev = drm_to_adev(dev);
1318 int vpos, hpos, stat;
1319 u32 count;
1320
1321 if (pipe >= adev->mode_info.num_crtc) {
1322 DRM_ERROR("Invalid crtc %u\n", pipe);
1323 return -EINVAL;
1324 }
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334 if (adev->mode_info.crtcs[pipe]) {
1335
1336
1337
1338 do {
1339 count = amdgpu_display_vblank_get_counter(adev, pipe);
1340
1341
1342
1343
1344 stat = amdgpu_display_get_crtc_scanoutpos(
1345 dev, pipe, GET_DISTANCE_TO_VBLANKSTART,
1346 &vpos, &hpos, NULL, NULL,
1347 &adev->mode_info.crtcs[pipe]->base.hwmode);
1348 } while (count != amdgpu_display_vblank_get_counter(adev, pipe));
1349
1350 if (((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) !=
1351 (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE))) {
1352 DRM_DEBUG_VBL("Query failed! stat %d\n", stat);
1353 } else {
1354 DRM_DEBUG_VBL("crtc %d: dist from vblank start %d\n",
1355 pipe, vpos);
1356
1357
1358
1359
1360
1361 if (vpos >= 0)
1362 count++;
1363 }
1364 } else {
1365
1366 count = amdgpu_display_vblank_get_counter(adev, pipe);
1367 DRM_DEBUG_VBL("NULL mode info! Returned count may be wrong.\n");
1368 }
1369
1370 return count;
1371}
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381int amdgpu_enable_vblank_kms(struct drm_crtc *crtc)
1382{
1383 struct drm_device *dev = crtc->dev;
1384 unsigned int pipe = crtc->index;
1385 struct amdgpu_device *adev = drm_to_adev(dev);
1386 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1387
1388 return amdgpu_irq_get(adev, &adev->crtc_irq, idx);
1389}
1390
1391
1392
1393
1394
1395
1396
1397
1398void amdgpu_disable_vblank_kms(struct drm_crtc *crtc)
1399{
1400 struct drm_device *dev = crtc->dev;
1401 unsigned int pipe = crtc->index;
1402 struct amdgpu_device *adev = drm_to_adev(dev);
1403 int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe);
1404
1405 amdgpu_irq_put(adev, &adev->crtc_irq, idx);
1406}
1407
1408
1409
1410
1411#if defined(CONFIG_DEBUG_FS)
1412
1413static int amdgpu_debugfs_firmware_info_show(struct seq_file *m, void *unused)
1414{
1415 struct amdgpu_device *adev = (struct amdgpu_device *)m->private;
1416 struct drm_amdgpu_info_firmware fw_info;
1417 struct drm_amdgpu_query_fw query_fw;
1418 struct atom_context *ctx = adev->mode_info.atom_context;
1419 int ret, i;
1420
1421 static const char *ta_fw_name[TA_FW_TYPE_MAX_INDEX] = {
1422#define TA_FW_NAME(type) [TA_FW_TYPE_PSP_##type] = #type
1423 TA_FW_NAME(XGMI),
1424 TA_FW_NAME(RAS),
1425 TA_FW_NAME(HDCP),
1426 TA_FW_NAME(DTM),
1427 TA_FW_NAME(RAP),
1428 TA_FW_NAME(SECUREDISPLAY),
1429#undef TA_FW_NAME
1430 };
1431
1432
1433 query_fw.fw_type = AMDGPU_INFO_FW_VCE;
1434 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1435 if (ret)
1436 return ret;
1437 seq_printf(m, "VCE feature version: %u, firmware version: 0x%08x\n",
1438 fw_info.feature, fw_info.ver);
1439
1440
1441 query_fw.fw_type = AMDGPU_INFO_FW_UVD;
1442 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1443 if (ret)
1444 return ret;
1445 seq_printf(m, "UVD feature version: %u, firmware version: 0x%08x\n",
1446 fw_info.feature, fw_info.ver);
1447
1448
1449 query_fw.fw_type = AMDGPU_INFO_FW_GMC;
1450 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1451 if (ret)
1452 return ret;
1453 seq_printf(m, "MC feature version: %u, firmware version: 0x%08x\n",
1454 fw_info.feature, fw_info.ver);
1455
1456
1457 query_fw.fw_type = AMDGPU_INFO_FW_GFX_ME;
1458 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1459 if (ret)
1460 return ret;
1461 seq_printf(m, "ME feature version: %u, firmware version: 0x%08x\n",
1462 fw_info.feature, fw_info.ver);
1463
1464
1465 query_fw.fw_type = AMDGPU_INFO_FW_GFX_PFP;
1466 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1467 if (ret)
1468 return ret;
1469 seq_printf(m, "PFP feature version: %u, firmware version: 0x%08x\n",
1470 fw_info.feature, fw_info.ver);
1471
1472
1473 query_fw.fw_type = AMDGPU_INFO_FW_GFX_CE;
1474 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1475 if (ret)
1476 return ret;
1477 seq_printf(m, "CE feature version: %u, firmware version: 0x%08x\n",
1478 fw_info.feature, fw_info.ver);
1479
1480
1481 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC;
1482 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1483 if (ret)
1484 return ret;
1485 seq_printf(m, "RLC feature version: %u, firmware version: 0x%08x\n",
1486 fw_info.feature, fw_info.ver);
1487
1488
1489 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_CNTL;
1490 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1491 if (ret)
1492 return ret;
1493 seq_printf(m, "RLC SRLC feature version: %u, firmware version: 0x%08x\n",
1494 fw_info.feature, fw_info.ver);
1495
1496
1497 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_GPM_MEM;
1498 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1499 if (ret)
1500 return ret;
1501 seq_printf(m, "RLC SRLG feature version: %u, firmware version: 0x%08x\n",
1502 fw_info.feature, fw_info.ver);
1503
1504
1505 query_fw.fw_type = AMDGPU_INFO_FW_GFX_RLC_RESTORE_LIST_SRM_MEM;
1506 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1507 if (ret)
1508 return ret;
1509 seq_printf(m, "RLC SRLS feature version: %u, firmware version: 0x%08x\n",
1510 fw_info.feature, fw_info.ver);
1511
1512
1513 query_fw.fw_type = AMDGPU_INFO_FW_GFX_MEC;
1514 query_fw.index = 0;
1515 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1516 if (ret)
1517 return ret;
1518 seq_printf(m, "MEC feature version: %u, firmware version: 0x%08x\n",
1519 fw_info.feature, fw_info.ver);
1520
1521
1522 if (adev->gfx.mec2_fw) {
1523 query_fw.index = 1;
1524 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1525 if (ret)
1526 return ret;
1527 seq_printf(m, "MEC2 feature version: %u, firmware version: 0x%08x\n",
1528 fw_info.feature, fw_info.ver);
1529 }
1530
1531
1532 query_fw.fw_type = AMDGPU_INFO_FW_SOS;
1533 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1534 if (ret)
1535 return ret;
1536 seq_printf(m, "SOS feature version: %u, firmware version: 0x%08x\n",
1537 fw_info.feature, fw_info.ver);
1538
1539
1540
1541 query_fw.fw_type = AMDGPU_INFO_FW_ASD;
1542 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1543 if (ret)
1544 return ret;
1545 seq_printf(m, "ASD feature version: %u, firmware version: 0x%08x\n",
1546 fw_info.feature, fw_info.ver);
1547
1548 query_fw.fw_type = AMDGPU_INFO_FW_TA;
1549 for (i = TA_FW_TYPE_PSP_XGMI; i < TA_FW_TYPE_MAX_INDEX; i++) {
1550 query_fw.index = i;
1551 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1552 if (ret)
1553 continue;
1554
1555 seq_printf(m, "TA %s feature version: 0x%08x, firmware version: 0x%08x\n",
1556 ta_fw_name[i], fw_info.feature, fw_info.ver);
1557 }
1558
1559
1560 query_fw.fw_type = AMDGPU_INFO_FW_SMC;
1561 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1562 if (ret)
1563 return ret;
1564 seq_printf(m, "SMC feature version: %u, firmware version: 0x%08x\n",
1565 fw_info.feature, fw_info.ver);
1566
1567
1568 query_fw.fw_type = AMDGPU_INFO_FW_SDMA;
1569 for (i = 0; i < adev->sdma.num_instances; i++) {
1570 query_fw.index = i;
1571 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1572 if (ret)
1573 return ret;
1574 seq_printf(m, "SDMA%d feature version: %u, firmware version: 0x%08x\n",
1575 i, fw_info.feature, fw_info.ver);
1576 }
1577
1578
1579 query_fw.fw_type = AMDGPU_INFO_FW_VCN;
1580 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1581 if (ret)
1582 return ret;
1583 seq_printf(m, "VCN feature version: %u, firmware version: 0x%08x\n",
1584 fw_info.feature, fw_info.ver);
1585
1586
1587 query_fw.fw_type = AMDGPU_INFO_FW_DMCU;
1588 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1589 if (ret)
1590 return ret;
1591 seq_printf(m, "DMCU feature version: %u, firmware version: 0x%08x\n",
1592 fw_info.feature, fw_info.ver);
1593
1594
1595 query_fw.fw_type = AMDGPU_INFO_FW_DMCUB;
1596 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1597 if (ret)
1598 return ret;
1599 seq_printf(m, "DMCUB feature version: %u, firmware version: 0x%08x\n",
1600 fw_info.feature, fw_info.ver);
1601
1602
1603 query_fw.fw_type = AMDGPU_INFO_FW_TOC;
1604 ret = amdgpu_firmware_info(&fw_info, &query_fw, adev);
1605 if (ret)
1606 return ret;
1607 seq_printf(m, "TOC feature version: %u, firmware version: 0x%08x\n",
1608 fw_info.feature, fw_info.ver);
1609
1610 seq_printf(m, "VBIOS version: %s\n", ctx->vbios_version);
1611
1612 return 0;
1613}
1614
1615DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_firmware_info);
1616
1617#endif
1618
1619void amdgpu_debugfs_firmware_init(struct amdgpu_device *adev)
1620{
1621#if defined(CONFIG_DEBUG_FS)
1622 struct drm_minor *minor = adev_to_drm(adev)->primary;
1623 struct dentry *root = minor->debugfs_root;
1624
1625 debugfs_create_file("amdgpu_firmware_info", 0444, root,
1626 adev, &amdgpu_debugfs_firmware_info_fops);
1627
1628#endif
1629}
1630
