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29#include <linux/seq_file.h>
30#include <linux/slab.h>
31#include <linux/uaccess.h>
32#include <linux/debugfs.h>
33
34#include <drm/amdgpu_drm.h>
35#include "amdgpu.h"
36#include "atom.h"
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61int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw)
62{
63
64
65 ndw = (ndw + ring->funcs->align_mask) & ~ring->funcs->align_mask;
66
67
68
69
70 if (WARN_ON_ONCE(ndw > ring->max_dw))
71 return -ENOMEM;
72
73 ring->count_dw = ndw;
74 ring->wptr_old = ring->wptr;
75
76 if (ring->funcs->begin_use)
77 ring->funcs->begin_use(ring);
78
79 return 0;
80}
81
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87
88
89void amdgpu_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
90{
91 int i;
92
93 for (i = 0; i < count; i++)
94 amdgpu_ring_write(ring, ring->funcs->nop);
95}
96
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103
104
105void amdgpu_ring_generic_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
106{
107 while (ib->length_dw & ring->funcs->align_mask)
108 ib->ptr[ib->length_dw++] = ring->funcs->nop;
109}
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119
120void amdgpu_ring_commit(struct amdgpu_ring *ring)
121{
122 uint32_t count;
123
124
125 count = ring->funcs->align_mask + 1 -
126 (ring->wptr & ring->funcs->align_mask);
127 count %= ring->funcs->align_mask + 1;
128 ring->funcs->insert_nop(ring, count);
129
130 mb();
131 amdgpu_ring_set_wptr(ring);
132
133 if (ring->funcs->end_use)
134 ring->funcs->end_use(ring);
135}
136
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143
144void amdgpu_ring_undo(struct amdgpu_ring *ring)
145{
146 ring->wptr = ring->wptr_old;
147
148 if (ring->funcs->end_use)
149 ring->funcs->end_use(ring);
150}
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165
166int amdgpu_ring_init(struct amdgpu_device *adev, struct amdgpu_ring *ring,
167 unsigned int max_dw, struct amdgpu_irq_src *irq_src,
168 unsigned int irq_type, unsigned int hw_prio,
169 atomic_t *sched_score)
170{
171 int r;
172 int sched_hw_submission = amdgpu_sched_hw_submission;
173 u32 *num_sched;
174 u32 hw_ip;
175
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180
181
182 if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
183 sched_hw_submission = max(sched_hw_submission, 256);
184 else if (ring == &adev->sdma.instance[0].page)
185 sched_hw_submission = 256;
186
187 if (ring->adev == NULL) {
188 if (adev->num_rings >= AMDGPU_MAX_RINGS)
189 return -EINVAL;
190
191 ring->adev = adev;
192 ring->idx = adev->num_rings++;
193 adev->rings[ring->idx] = ring;
194 r = amdgpu_fence_driver_init_ring(ring, sched_hw_submission,
195 sched_score);
196 if (r)
197 return r;
198 }
199
200 r = amdgpu_device_wb_get(adev, &ring->rptr_offs);
201 if (r) {
202 dev_err(adev->dev, "(%d) ring rptr_offs wb alloc failed\n", r);
203 return r;
204 }
205
206 r = amdgpu_device_wb_get(adev, &ring->wptr_offs);
207 if (r) {
208 dev_err(adev->dev, "(%d) ring wptr_offs wb alloc failed\n", r);
209 return r;
210 }
211
212 r = amdgpu_device_wb_get(adev, &ring->fence_offs);
213 if (r) {
214 dev_err(adev->dev, "(%d) ring fence_offs wb alloc failed\n", r);
215 return r;
216 }
217
218 r = amdgpu_device_wb_get(adev, &ring->trail_fence_offs);
219 if (r) {
220 dev_err(adev->dev,
221 "(%d) ring trail_fence_offs wb alloc failed\n", r);
222 return r;
223 }
224 ring->trail_fence_gpu_addr =
225 adev->wb.gpu_addr + (ring->trail_fence_offs * 4);
226 ring->trail_fence_cpu_addr = &adev->wb.wb[ring->trail_fence_offs];
227
228 r = amdgpu_device_wb_get(adev, &ring->cond_exe_offs);
229 if (r) {
230 dev_err(adev->dev, "(%d) ring cond_exec_polling wb alloc failed\n", r);
231 return r;
232 }
233 ring->cond_exe_gpu_addr = adev->wb.gpu_addr + (ring->cond_exe_offs * 4);
234 ring->cond_exe_cpu_addr = &adev->wb.wb[ring->cond_exe_offs];
235
236 *ring->cond_exe_cpu_addr = 1;
237
238 r = amdgpu_fence_driver_start_ring(ring, irq_src, irq_type);
239 if (r) {
240 dev_err(adev->dev, "failed initializing fences (%d).\n", r);
241 return r;
242 }
243
244 ring->ring_size = roundup_pow_of_two(max_dw * 4 * sched_hw_submission);
245
246 ring->buf_mask = (ring->ring_size / 4) - 1;
247 ring->ptr_mask = ring->funcs->support_64bit_ptrs ?
248 0xffffffffffffffff : ring->buf_mask;
249
250 if (ring->ring_obj == NULL) {
251 r = amdgpu_bo_create_kernel(adev, ring->ring_size + ring->funcs->extra_dw, PAGE_SIZE,
252 AMDGPU_GEM_DOMAIN_GTT,
253 &ring->ring_obj,
254 &ring->gpu_addr,
255 (void **)&ring->ring);
256 if (r) {
257 dev_err(adev->dev, "(%d) ring create failed\n", r);
258 return r;
259 }
260 amdgpu_ring_clear_ring(ring);
261 }
262
263 ring->max_dw = max_dw;
264 ring->hw_prio = hw_prio;
265
266 if (!ring->no_scheduler) {
267 hw_ip = ring->funcs->type;
268 num_sched = &adev->gpu_sched[hw_ip][hw_prio].num_scheds;
269 adev->gpu_sched[hw_ip][hw_prio].sched[(*num_sched)++] =
270 &ring->sched;
271 }
272
273 return 0;
274}
275
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282
283void amdgpu_ring_fini(struct amdgpu_ring *ring)
284{
285
286
287 if (!(ring->adev) || !(ring->adev->rings[ring->idx]))
288 return;
289
290 ring->sched.ready = false;
291
292 amdgpu_device_wb_free(ring->adev, ring->rptr_offs);
293 amdgpu_device_wb_free(ring->adev, ring->wptr_offs);
294
295 amdgpu_device_wb_free(ring->adev, ring->cond_exe_offs);
296 amdgpu_device_wb_free(ring->adev, ring->fence_offs);
297
298 amdgpu_bo_free_kernel(&ring->ring_obj,
299 &ring->gpu_addr,
300 (void **)&ring->ring);
301
302 dma_fence_put(ring->vmid_wait);
303 ring->vmid_wait = NULL;
304 ring->me = 0;
305
306 ring->adev->rings[ring->idx] = NULL;
307}
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321void amdgpu_ring_emit_reg_write_reg_wait_helper(struct amdgpu_ring *ring,
322 uint32_t reg0, uint32_t reg1,
323 uint32_t ref, uint32_t mask)
324{
325 amdgpu_ring_emit_wreg(ring, reg0, ref);
326 amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask);
327}
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338bool amdgpu_ring_soft_recovery(struct amdgpu_ring *ring, unsigned int vmid,
339 struct dma_fence *fence)
340{
341 ktime_t deadline = ktime_add_us(ktime_get(), 10000);
342
343 if (amdgpu_sriov_vf(ring->adev) || !ring->funcs->soft_recovery || !fence)
344 return false;
345
346 atomic_inc(&ring->adev->gpu_reset_counter);
347 while (!dma_fence_is_signaled(fence) &&
348 ktime_to_ns(ktime_sub(deadline, ktime_get())) > 0)
349 ring->funcs->soft_recovery(ring, vmid);
350
351 return dma_fence_is_signaled(fence);
352}
353
354
355
356
357#if defined(CONFIG_DEBUG_FS)
358
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366static ssize_t amdgpu_debugfs_ring_read(struct file *f, char __user *buf,
367 size_t size, loff_t *pos)
368{
369 struct amdgpu_ring *ring = file_inode(f)->i_private;
370 int r, i;
371 uint32_t value, result, early[3];
372
373 if (*pos & 3 || size & 3)
374 return -EINVAL;
375
376 result = 0;
377
378 if (*pos < 12) {
379 early[0] = amdgpu_ring_get_rptr(ring) & ring->buf_mask;
380 early[1] = amdgpu_ring_get_wptr(ring) & ring->buf_mask;
381 early[2] = ring->wptr & ring->buf_mask;
382 for (i = *pos / 4; i < 3 && size; i++) {
383 r = put_user(early[i], (uint32_t *)buf);
384 if (r)
385 return r;
386 buf += 4;
387 result += 4;
388 size -= 4;
389 *pos += 4;
390 }
391 }
392
393 while (size) {
394 if (*pos >= (ring->ring_size + 12))
395 return result;
396
397 value = ring->ring[(*pos - 12)/4];
398 r = put_user(value, (uint32_t *)buf);
399 if (r)
400 return r;
401 buf += 4;
402 result += 4;
403 size -= 4;
404 *pos += 4;
405 }
406
407 return result;
408}
409
410static const struct file_operations amdgpu_debugfs_ring_fops = {
411 .owner = THIS_MODULE,
412 .read = amdgpu_debugfs_ring_read,
413 .llseek = default_llseek
414};
415
416#endif
417
418int amdgpu_debugfs_ring_init(struct amdgpu_device *adev,
419 struct amdgpu_ring *ring)
420{
421#if defined(CONFIG_DEBUG_FS)
422 struct drm_minor *minor = adev_to_drm(adev)->primary;
423 struct dentry *ent, *root = minor->debugfs_root;
424 char name[32];
425
426 sprintf(name, "amdgpu_ring_%s", ring->name);
427
428 ent = debugfs_create_file(name,
429 S_IFREG | S_IRUGO, root,
430 ring, &amdgpu_debugfs_ring_fops);
431 if (IS_ERR(ent))
432 return PTR_ERR(ent);
433
434 i_size_write(ent->d_inode, ring->ring_size + 12);
435 ring->ent = ent;
436#endif
437 return 0;
438}
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448
449int amdgpu_ring_test_helper(struct amdgpu_ring *ring)
450{
451 struct amdgpu_device *adev = ring->adev;
452 int r;
453
454 r = amdgpu_ring_test_ring(ring);
455 if (r)
456 DRM_DEV_ERROR(adev->dev, "ring %s test failed (%d)\n",
457 ring->name, r);
458 else
459 DRM_DEV_DEBUG(adev->dev, "ring test on %s succeeded\n",
460 ring->name);
461
462 ring->sched.ready = !r;
463 return r;
464}
465