LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: Christian König
  23 */
  24#ifndef __AMDGPU_SYNC_H__
  25#define __AMDGPU_SYNC_H__
  26
  27#include <linux/hashtable.h>
  28
  29struct dma_fence;
  30struct dma_resv;
  31struct amdgpu_device;
  32struct amdgpu_ring;
  33
  34enum amdgpu_sync_mode {
  35        AMDGPU_SYNC_ALWAYS,
  36        AMDGPU_SYNC_NE_OWNER,
  37        AMDGPU_SYNC_EQ_OWNER,
  38        AMDGPU_SYNC_EXPLICIT
  39};
  40
  41/*
  42 * Container for fences used to sync command submissions.
  43 */
  44struct amdgpu_sync {
  45        DECLARE_HASHTABLE(fences, 4);
  46        struct dma_fence        *last_vm_update;
  47};
  48
  49void amdgpu_sync_create(struct amdgpu_sync *sync);
  50int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f);
  51int amdgpu_sync_vm_fence(struct amdgpu_sync *sync, struct dma_fence *fence);
  52int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync,
  53                     struct dma_resv *resv, enum amdgpu_sync_mode mode,
  54                     void *owner);
  55struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync,
  56                                     struct amdgpu_ring *ring);
  57struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync);
  58int amdgpu_sync_clone(struct amdgpu_sync *source, struct amdgpu_sync *clone);
  59int amdgpu_sync_wait(struct amdgpu_sync *sync, bool intr);
  60void amdgpu_sync_free(struct amdgpu_sync *sync);
  61int amdgpu_sync_init(void);
  62void amdgpu_sync_fini(void);
  63
  64#endif
  65