LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2012 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef __AMDGPU_UCODE_H__
  24#define __AMDGPU_UCODE_H__
  25
  26#include "amdgpu_socbb.h"
  27
  28struct common_firmware_header {
  29        uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
  30        uint32_t header_size_bytes; /* size of just the header in bytes */
  31        uint16_t header_version_major; /* header version */
  32        uint16_t header_version_minor; /* header version */
  33        uint16_t ip_version_major; /* IP version */
  34        uint16_t ip_version_minor; /* IP version */
  35        uint32_t ucode_version;
  36        uint32_t ucode_size_bytes; /* size of ucode in bytes */
  37        uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
  38        uint32_t crc32;  /* crc32 checksum of the payload */
  39};
  40
  41/* version_major=1, version_minor=0 */
  42struct mc_firmware_header_v1_0 {
  43        struct common_firmware_header header;
  44        uint32_t io_debug_size_bytes; /* size of debug array in dwords */
  45        uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
  46};
  47
  48/* version_major=1, version_minor=0 */
  49struct smc_firmware_header_v1_0 {
  50        struct common_firmware_header header;
  51        uint32_t ucode_start_addr;
  52};
  53
  54/* version_major=2, version_minor=0 */
  55struct smc_firmware_header_v2_0 {
  56        struct smc_firmware_header_v1_0 v1_0;
  57        uint32_t ppt_offset_bytes; /* soft pptable offset */
  58        uint32_t ppt_size_bytes; /* soft pptable size */
  59};
  60
  61struct smc_soft_pptable_entry {
  62        uint32_t id;
  63        uint32_t ppt_offset_bytes;
  64        uint32_t ppt_size_bytes;
  65};
  66
  67/* version_major=2, version_minor=1 */
  68struct smc_firmware_header_v2_1 {
  69        struct smc_firmware_header_v1_0 v1_0;
  70        uint32_t pptable_count;
  71        uint32_t pptable_entry_offset;
  72};
  73
  74struct psp_fw_legacy_bin_desc {
  75        uint32_t fw_version;
  76        uint32_t offset_bytes;
  77        uint32_t size_bytes;
  78};
  79
  80/* version_major=1, version_minor=0 */
  81struct psp_firmware_header_v1_0 {
  82        struct common_firmware_header header;
  83        struct psp_fw_legacy_bin_desc sos;
  84};
  85
  86/* version_major=1, version_minor=1 */
  87struct psp_firmware_header_v1_1 {
  88        struct psp_firmware_header_v1_0 v1_0;
  89        struct psp_fw_legacy_bin_desc toc;
  90        struct psp_fw_legacy_bin_desc kdb;
  91};
  92
  93/* version_major=1, version_minor=2 */
  94struct psp_firmware_header_v1_2 {
  95        struct psp_firmware_header_v1_0 v1_0;
  96        struct psp_fw_legacy_bin_desc res;
  97        struct psp_fw_legacy_bin_desc kdb;
  98};
  99
 100/* version_major=1, version_minor=3 */
 101struct psp_firmware_header_v1_3 {
 102        struct psp_firmware_header_v1_1 v1_1;
 103        struct psp_fw_legacy_bin_desc spl;
 104        struct psp_fw_legacy_bin_desc rl;
 105        struct psp_fw_legacy_bin_desc sys_drv_aux;
 106        struct psp_fw_legacy_bin_desc sos_aux;
 107};
 108
 109struct psp_fw_bin_desc {
 110        uint32_t fw_type;
 111        uint32_t fw_version;
 112        uint32_t offset_bytes;
 113        uint32_t size_bytes;
 114};
 115
 116enum psp_fw_type {
 117        PSP_FW_TYPE_UNKOWN,
 118        PSP_FW_TYPE_PSP_SOS,
 119        PSP_FW_TYPE_PSP_SYS_DRV,
 120        PSP_FW_TYPE_PSP_KDB,
 121        PSP_FW_TYPE_PSP_TOC,
 122        PSP_FW_TYPE_PSP_SPL,
 123        PSP_FW_TYPE_PSP_RL,
 124        PSP_FW_TYPE_PSP_SOC_DRV,
 125        PSP_FW_TYPE_PSP_INTF_DRV,
 126        PSP_FW_TYPE_PSP_DBG_DRV,
 127};
 128
 129/* version_major=2, version_minor=0 */
 130struct psp_firmware_header_v2_0 {
 131        struct common_firmware_header header;
 132        uint32_t psp_fw_bin_count;
 133        struct psp_fw_bin_desc psp_fw_bin[];
 134};
 135
 136/* version_major=1, version_minor=0 */
 137struct ta_firmware_header_v1_0 {
 138        struct common_firmware_header header;
 139        struct psp_fw_legacy_bin_desc xgmi;
 140        struct psp_fw_legacy_bin_desc ras;
 141        struct psp_fw_legacy_bin_desc hdcp;
 142        struct psp_fw_legacy_bin_desc dtm;
 143        struct psp_fw_legacy_bin_desc securedisplay;
 144};
 145
 146enum ta_fw_type {
 147        TA_FW_TYPE_UNKOWN,
 148        TA_FW_TYPE_PSP_ASD,
 149        TA_FW_TYPE_PSP_XGMI,
 150        TA_FW_TYPE_PSP_RAS,
 151        TA_FW_TYPE_PSP_HDCP,
 152        TA_FW_TYPE_PSP_DTM,
 153        TA_FW_TYPE_PSP_RAP,
 154        TA_FW_TYPE_PSP_SECUREDISPLAY,
 155        TA_FW_TYPE_MAX_INDEX,
 156};
 157
 158/* version_major=2, version_minor=0 */
 159struct ta_firmware_header_v2_0 {
 160        struct common_firmware_header header;
 161        uint32_t ta_fw_bin_count;
 162        struct psp_fw_bin_desc ta_fw_bin[];
 163};
 164
 165/* version_major=1, version_minor=0 */
 166struct gfx_firmware_header_v1_0 {
 167        struct common_firmware_header header;
 168        uint32_t ucode_feature_version;
 169        uint32_t jt_offset; /* jt location */
 170        uint32_t jt_size;  /* size of jt */
 171};
 172
 173/* version_major=1, version_minor=0 */
 174struct mes_firmware_header_v1_0 {
 175        struct common_firmware_header header;
 176        uint32_t mes_ucode_version;
 177        uint32_t mes_ucode_size_bytes;
 178        uint32_t mes_ucode_offset_bytes;
 179        uint32_t mes_ucode_data_version;
 180        uint32_t mes_ucode_data_size_bytes;
 181        uint32_t mes_ucode_data_offset_bytes;
 182        uint32_t mes_uc_start_addr_lo;
 183        uint32_t mes_uc_start_addr_hi;
 184        uint32_t mes_data_start_addr_lo;
 185        uint32_t mes_data_start_addr_hi;
 186};
 187
 188/* version_major=1, version_minor=0 */
 189struct rlc_firmware_header_v1_0 {
 190        struct common_firmware_header header;
 191        uint32_t ucode_feature_version;
 192        uint32_t save_and_restore_offset;
 193        uint32_t clear_state_descriptor_offset;
 194        uint32_t avail_scratch_ram_locations;
 195        uint32_t master_pkt_description_offset;
 196};
 197
 198/* version_major=2, version_minor=0 */
 199struct rlc_firmware_header_v2_0 {
 200        struct common_firmware_header header;
 201        uint32_t ucode_feature_version;
 202        uint32_t jt_offset; /* jt location */
 203        uint32_t jt_size;  /* size of jt */
 204        uint32_t save_and_restore_offset;
 205        uint32_t clear_state_descriptor_offset;
 206        uint32_t avail_scratch_ram_locations;
 207        uint32_t reg_restore_list_size;
 208        uint32_t reg_list_format_start;
 209        uint32_t reg_list_format_separate_start;
 210        uint32_t starting_offsets_start;
 211        uint32_t reg_list_format_size_bytes; /* size of reg list format array in bytes */
 212        uint32_t reg_list_format_array_offset_bytes; /* payload offset from the start of the header */
 213        uint32_t reg_list_size_bytes; /* size of reg list array in bytes */
 214        uint32_t reg_list_array_offset_bytes; /* payload offset from the start of the header */
 215        uint32_t reg_list_format_separate_size_bytes; /* size of reg list format array in bytes */
 216        uint32_t reg_list_format_separate_array_offset_bytes; /* payload offset from the start of the header */
 217        uint32_t reg_list_separate_size_bytes; /* size of reg list array in bytes */
 218        uint32_t reg_list_separate_array_offset_bytes; /* payload offset from the start of the header */
 219};
 220
 221/* version_major=2, version_minor=1 */
 222struct rlc_firmware_header_v2_1 {
 223        struct rlc_firmware_header_v2_0 v2_0;
 224        uint32_t reg_list_format_direct_reg_list_length; /* length of direct reg list format array */
 225        uint32_t save_restore_list_cntl_ucode_ver;
 226        uint32_t save_restore_list_cntl_feature_ver;
 227        uint32_t save_restore_list_cntl_size_bytes;
 228        uint32_t save_restore_list_cntl_offset_bytes;
 229        uint32_t save_restore_list_gpm_ucode_ver;
 230        uint32_t save_restore_list_gpm_feature_ver;
 231        uint32_t save_restore_list_gpm_size_bytes;
 232        uint32_t save_restore_list_gpm_offset_bytes;
 233        uint32_t save_restore_list_srm_ucode_ver;
 234        uint32_t save_restore_list_srm_feature_ver;
 235        uint32_t save_restore_list_srm_size_bytes;
 236        uint32_t save_restore_list_srm_offset_bytes;
 237};
 238
 239/* version_major=2, version_minor=1 */
 240struct rlc_firmware_header_v2_2 {
 241        struct rlc_firmware_header_v2_1 v2_1;
 242        uint32_t rlc_iram_ucode_size_bytes;
 243        uint32_t rlc_iram_ucode_offset_bytes;
 244        uint32_t rlc_dram_ucode_size_bytes;
 245        uint32_t rlc_dram_ucode_offset_bytes;
 246};
 247
 248/* version_major=1, version_minor=0 */
 249struct sdma_firmware_header_v1_0 {
 250        struct common_firmware_header header;
 251        uint32_t ucode_feature_version;
 252        uint32_t ucode_change_version;
 253        uint32_t jt_offset; /* jt location */
 254        uint32_t jt_size; /* size of jt */
 255};
 256
 257/* version_major=1, version_minor=1 */
 258struct sdma_firmware_header_v1_1 {
 259        struct sdma_firmware_header_v1_0 v1_0;
 260        uint32_t digest_size;
 261};
 262
 263/* gpu info payload */
 264struct gpu_info_firmware_v1_0 {
 265        uint32_t gc_num_se;
 266        uint32_t gc_num_cu_per_sh;
 267        uint32_t gc_num_sh_per_se;
 268        uint32_t gc_num_rb_per_se;
 269        uint32_t gc_num_tccs;
 270        uint32_t gc_num_gprs;
 271        uint32_t gc_num_max_gs_thds;
 272        uint32_t gc_gs_table_depth;
 273        uint32_t gc_gsprim_buff_depth;
 274        uint32_t gc_parameter_cache_depth;
 275        uint32_t gc_double_offchip_lds_buffer;
 276        uint32_t gc_wave_size;
 277        uint32_t gc_max_waves_per_simd;
 278        uint32_t gc_max_scratch_slots_per_cu;
 279        uint32_t gc_lds_size;
 280};
 281
 282struct gpu_info_firmware_v1_1 {
 283        struct gpu_info_firmware_v1_0 v1_0;
 284        uint32_t num_sc_per_sh;
 285        uint32_t num_packer_per_sc;
 286};
 287
 288/* gpu info payload
 289 * version_major=1, version_minor=1 */
 290struct gpu_info_firmware_v1_2 {
 291        struct gpu_info_firmware_v1_1 v1_1;
 292        struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;
 293};
 294
 295/* version_major=1, version_minor=0 */
 296struct gpu_info_firmware_header_v1_0 {
 297        struct common_firmware_header header;
 298        uint16_t version_major; /* version */
 299        uint16_t version_minor; /* version */
 300};
 301
 302/* version_major=1, version_minor=0 */
 303struct dmcu_firmware_header_v1_0 {
 304        struct common_firmware_header header;
 305        uint32_t intv_offset_bytes; /* interrupt vectors offset from end of header, in bytes */
 306        uint32_t intv_size_bytes;  /* size of interrupt vectors, in bytes */
 307};
 308
 309/* version_major=1, version_minor=0 */
 310struct dmcub_firmware_header_v1_0 {
 311        struct common_firmware_header header;
 312        uint32_t inst_const_bytes; /* size of instruction region, in bytes */
 313        uint32_t bss_data_bytes; /* size of bss/data region, in bytes */
 314};
 315
 316/* header is fixed size */
 317union amdgpu_firmware_header {
 318        struct common_firmware_header common;
 319        struct mc_firmware_header_v1_0 mc;
 320        struct smc_firmware_header_v1_0 smc;
 321        struct smc_firmware_header_v2_0 smc_v2_0;
 322        struct psp_firmware_header_v1_0 psp;
 323        struct psp_firmware_header_v1_1 psp_v1_1;
 324        struct psp_firmware_header_v1_3 psp_v1_3;
 325        struct psp_firmware_header_v2_0 psp_v2_0;
 326        struct ta_firmware_header_v1_0 ta;
 327        struct ta_firmware_header_v2_0 ta_v2_0;
 328        struct gfx_firmware_header_v1_0 gfx;
 329        struct rlc_firmware_header_v1_0 rlc;
 330        struct rlc_firmware_header_v2_0 rlc_v2_0;
 331        struct rlc_firmware_header_v2_1 rlc_v2_1;
 332        struct sdma_firmware_header_v1_0 sdma;
 333        struct sdma_firmware_header_v1_1 sdma_v1_1;
 334        struct gpu_info_firmware_header_v1_0 gpu_info;
 335        struct dmcu_firmware_header_v1_0 dmcu;
 336        struct dmcub_firmware_header_v1_0 dmcub;
 337        uint8_t raw[0x100];
 338};
 339
 340#define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc))
 341
 342/*
 343 * fw loading support
 344 */
 345enum AMDGPU_UCODE_ID {
 346        AMDGPU_UCODE_ID_SDMA0 = 0,
 347        AMDGPU_UCODE_ID_SDMA1,
 348        AMDGPU_UCODE_ID_SDMA2,
 349        AMDGPU_UCODE_ID_SDMA3,
 350        AMDGPU_UCODE_ID_SDMA4,
 351        AMDGPU_UCODE_ID_SDMA5,
 352        AMDGPU_UCODE_ID_SDMA6,
 353        AMDGPU_UCODE_ID_SDMA7,
 354        AMDGPU_UCODE_ID_CP_CE,
 355        AMDGPU_UCODE_ID_CP_PFP,
 356        AMDGPU_UCODE_ID_CP_ME,
 357        AMDGPU_UCODE_ID_CP_MEC1,
 358        AMDGPU_UCODE_ID_CP_MEC1_JT,
 359        AMDGPU_UCODE_ID_CP_MEC2,
 360        AMDGPU_UCODE_ID_CP_MEC2_JT,
 361        AMDGPU_UCODE_ID_CP_MES,
 362        AMDGPU_UCODE_ID_CP_MES_DATA,
 363        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL,
 364        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM,
 365        AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM,
 366        AMDGPU_UCODE_ID_RLC_IRAM,
 367        AMDGPU_UCODE_ID_RLC_DRAM,
 368        AMDGPU_UCODE_ID_RLC_G,
 369        AMDGPU_UCODE_ID_STORAGE,
 370        AMDGPU_UCODE_ID_SMC,
 371        AMDGPU_UCODE_ID_UVD,
 372        AMDGPU_UCODE_ID_UVD1,
 373        AMDGPU_UCODE_ID_VCE,
 374        AMDGPU_UCODE_ID_VCN,
 375        AMDGPU_UCODE_ID_VCN1,
 376        AMDGPU_UCODE_ID_DMCU_ERAM,
 377        AMDGPU_UCODE_ID_DMCU_INTV,
 378        AMDGPU_UCODE_ID_VCN0_RAM,
 379        AMDGPU_UCODE_ID_VCN1_RAM,
 380        AMDGPU_UCODE_ID_DMCUB,
 381        AMDGPU_UCODE_ID_MAXIMUM,
 382};
 383
 384/* engine firmware status */
 385enum AMDGPU_UCODE_STATUS {
 386        AMDGPU_UCODE_STATUS_INVALID,
 387        AMDGPU_UCODE_STATUS_NOT_LOADED,
 388        AMDGPU_UCODE_STATUS_LOADED,
 389};
 390
 391enum amdgpu_firmware_load_type {
 392        AMDGPU_FW_LOAD_DIRECT = 0,
 393        AMDGPU_FW_LOAD_SMU,
 394        AMDGPU_FW_LOAD_PSP,
 395        AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO,
 396};
 397
 398/* conform to smu_ucode_xfer_cz.h */
 399#define AMDGPU_SDMA0_UCODE_LOADED       0x00000001
 400#define AMDGPU_SDMA1_UCODE_LOADED       0x00000002
 401#define AMDGPU_CPCE_UCODE_LOADED        0x00000004
 402#define AMDGPU_CPPFP_UCODE_LOADED       0x00000008
 403#define AMDGPU_CPME_UCODE_LOADED        0x00000010
 404#define AMDGPU_CPMEC1_UCODE_LOADED      0x00000020
 405#define AMDGPU_CPMEC2_UCODE_LOADED      0x00000040
 406#define AMDGPU_CPRLC_UCODE_LOADED       0x00000100
 407
 408/* amdgpu firmware info */
 409struct amdgpu_firmware_info {
 410        /* ucode ID */
 411        enum AMDGPU_UCODE_ID ucode_id;
 412        /* request_firmware */
 413        const struct firmware *fw;
 414        /* starting mc address */
 415        uint64_t mc_addr;
 416        /* kernel linear address */
 417        void *kaddr;
 418        /* ucode_size_bytes */
 419        uint32_t ucode_size;
 420        /* starting tmr mc address */
 421        uint32_t tmr_mc_addr_lo;
 422        uint32_t tmr_mc_addr_hi;
 423};
 424
 425struct amdgpu_firmware {
 426        struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
 427        enum amdgpu_firmware_load_type load_type;
 428        struct amdgpu_bo *fw_buf;
 429        unsigned int fw_size;
 430        unsigned int max_ucodes;
 431        /* firmwares are loaded by psp instead of smu from vega10 */
 432        const struct amdgpu_psp_funcs *funcs;
 433        struct amdgpu_bo *rbuf;
 434        struct mutex mutex;
 435
 436        /* gpu info firmware data pointer */
 437        const struct firmware *gpu_info_fw;
 438
 439        void *fw_buf_ptr;
 440        uint64_t fw_buf_mc;
 441};
 442
 443void amdgpu_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
 444void amdgpu_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
 445void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
 446void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
 447void amdgpu_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
 448void amdgpu_ucode_print_psp_hdr(const struct common_firmware_header *hdr);
 449void amdgpu_ucode_print_gpu_info_hdr(const struct common_firmware_header *hdr);
 450int amdgpu_ucode_validate(const struct firmware *fw);
 451bool amdgpu_ucode_hdr_version(union amdgpu_firmware_header *hdr,
 452                                uint16_t hdr_major, uint16_t hdr_minor);
 453
 454int amdgpu_ucode_init_bo(struct amdgpu_device *adev);
 455int amdgpu_ucode_create_bo(struct amdgpu_device *adev);
 456int amdgpu_ucode_sysfs_init(struct amdgpu_device *adev);
 457void amdgpu_ucode_free_bo(struct amdgpu_device *adev);
 458void amdgpu_ucode_sysfs_fini(struct amdgpu_device *adev);
 459
 460enum amdgpu_firmware_load_type
 461amdgpu_ucode_get_load_type(struct amdgpu_device *adev, int load_type);
 462
 463const char *amdgpu_ucode_name(enum AMDGPU_UCODE_ID ucode_id);
 464
 465#endif
 466