LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright (C) 2019  Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included
  12 * in all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
  18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  20 */
  21#ifndef __AMDGPU_UMC_H__
  22#define __AMDGPU_UMC_H__
  23
  24/*
  25 * (addr / 256) * 4096, the higher 26 bits in ErrorAddr
  26 * is the index of 4KB block
  27 */
  28#define ADDR_OF_4KB_BLOCK(addr)                 (((addr) & ~0xffULL) << 4)
  29/*
  30 * (addr / 256) * 8192, the higher 26 bits in ErrorAddr
  31 * is the index of 8KB block
  32 */
  33#define ADDR_OF_8KB_BLOCK(addr)                 (((addr) & ~0xffULL) << 5)
  34/* channel index is the index of 256B block */
  35#define ADDR_OF_256B_BLOCK(channel_index)       ((channel_index) << 8)
  36/* offset in 256B block */
  37#define OFFSET_IN_256B_BLOCK(addr)              ((addr) & 0xffULL)
  38
  39#define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++)
  40#define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++)
  41#define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst))
  42
  43struct amdgpu_umc_ras_funcs {
  44        void (*err_cnt_init)(struct amdgpu_device *adev);
  45        int (*ras_late_init)(struct amdgpu_device *adev);
  46        void (*ras_fini)(struct amdgpu_device *adev);
  47        void (*query_ras_error_count)(struct amdgpu_device *adev,
  48                                      void *ras_error_status);
  49        void (*query_ras_error_address)(struct amdgpu_device *adev,
  50                                        void *ras_error_status);
  51};
  52
  53struct amdgpu_umc_funcs {
  54        void (*init_registers)(struct amdgpu_device *adev);
  55};
  56
  57struct amdgpu_umc {
  58        /* max error count in one ras query call */
  59        uint32_t max_ras_err_cnt_per_query;
  60        /* number of umc channel instance with memory map register access */
  61        uint32_t channel_inst_num;
  62        /* number of umc instance with memory map register access */
  63        uint32_t umc_inst_num;
  64        /* UMC regiser per channel offset */
  65        uint32_t channel_offs;
  66        /* channel index table of interleaved memory */
  67        const uint32_t *channel_idx_tbl;
  68        struct ras_common_if *ras_if;
  69
  70        const struct amdgpu_umc_funcs *funcs;
  71        const struct amdgpu_umc_ras_funcs *ras_funcs;
  72};
  73
  74int amdgpu_umc_ras_late_init(struct amdgpu_device *adev);
  75void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
  76int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev,
  77                void *ras_error_status,
  78                struct amdgpu_iv_entry *entry);
  79int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev,
  80                struct amdgpu_irq_src *source,
  81                struct amdgpu_iv_entry *entry);
  82#endif
  83