LXR linux/drivers/gpu/drm/amd/amdgpu/amdgpu

   1/*
   2 * Copyright 2016 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 */
  22#ifndef __AMDGPU_XGMI_H__
  23#define __AMDGPU_XGMI_H__
  24
  25#include <drm/task_barrier.h>
  26#include "amdgpu_psp.h"
  27
  28
  29struct amdgpu_hive_info {
  30        struct kobject kobj;
  31        uint64_t hive_id;
  32        struct list_head device_list;
  33        struct list_head node;
  34        atomic_t number_devices;
  35        struct mutex hive_lock;
  36        atomic_t in_reset;
  37        int hi_req_count;
  38        struct amdgpu_device *hi_req_gpu;
  39        struct task_barrier tb;
  40        enum {
  41                AMDGPU_XGMI_PSTATE_MIN,
  42                AMDGPU_XGMI_PSTATE_MAX_VEGA20,
  43                AMDGPU_XGMI_PSTATE_UNKNOWN
  44        } pstate;
  45};
  46
  47struct amdgpu_pcs_ras_field {
  48        const char *err_name;
  49        uint32_t pcs_err_mask;
  50        uint32_t pcs_err_shift;
  51};
  52
  53extern const struct amdgpu_xgmi_ras_funcs xgmi_ras_funcs;
  54struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
  55void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive);
  56int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
  57int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
  58int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
  59int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
  60int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
  61                struct amdgpu_device *peer_adev);
  62int amdgpu_xgmi_get_num_links(struct amdgpu_device *adev,
  63                struct amdgpu_device *peer_adev);
  64uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
  65                                           uint64_t addr);
  66static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
  67                struct amdgpu_device *bo_adev)
  68{
  69        return (adev != bo_adev &&
  70                adev->gmc.xgmi.hive_id &&
  71                adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);
  72}
  73
  74#endif
  75