LXR linux/drivers/gpu/drm/amd/amdgpu/df_v1

   1/*
   2 * Copyright 2018 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#include "amdgpu.h"
  24#include "df_v1_7.h"
  25
  26#include "df/df_1_7_default.h"
  27#include "df/df_1_7_offset.h"
  28#include "df/df_1_7_sh_mask.h"
  29
  30static u32 df_v1_7_channel_number[] = {1, 2, 0, 4, 0, 8, 0, 16, 2};
  31
  32static void df_v1_7_sw_init(struct amdgpu_device *adev)
  33{
  34        adev->df.hash_status.hash_64k = false;
  35        adev->df.hash_status.hash_2m = false;
  36        adev->df.hash_status.hash_1g = false;
  37}
  38
  39static void df_v1_7_sw_fini(struct amdgpu_device *adev)
  40{
  41}
  42
  43static void df_v1_7_enable_broadcast_mode(struct amdgpu_device *adev,
  44                                          bool enable)
  45{
  46        u32 tmp;
  47
  48        if (enable) {
  49                tmp = RREG32_SOC15(DF, 0, mmFabricConfigAccessControl);
  50                tmp &= ~FabricConfigAccessControl__CfgRegInstAccEn_MASK;
  51                WREG32_SOC15(DF, 0, mmFabricConfigAccessControl, tmp);
  52        } else
  53                WREG32_SOC15(DF, 0, mmFabricConfigAccessControl,
  54                             mmFabricConfigAccessControl_DEFAULT);
  55}
  56
  57static u32 df_v1_7_get_fb_channel_number(struct amdgpu_device *adev)
  58{
  59        u32 tmp;
  60
  61        tmp = RREG32_SOC15(DF, 0, mmDF_CS_AON0_DramBaseAddress0);
  62        tmp &= DF_CS_AON0_DramBaseAddress0__IntLvNumChan_MASK;
  63        tmp >>= DF_CS_AON0_DramBaseAddress0__IntLvNumChan__SHIFT;
  64
  65        return tmp;
  66}
  67
  68static u32 df_v1_7_get_hbm_channel_number(struct amdgpu_device *adev)
  69{
  70        int fb_channel_number;
  71
  72        fb_channel_number = adev->df.funcs->get_fb_channel_number(adev);
  73
  74        return df_v1_7_channel_number[fb_channel_number];
  75}
  76
  77static void df_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
  78                                                     bool enable)
  79{
  80        u32 tmp;
  81
  82        /* Put DF on broadcast mode */
  83        adev->df.funcs->enable_broadcast_mode(adev, true);
  84
  85        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_DF_MGCG)) {
  86                tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
  87                tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
  88                tmp |= DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY;
  89                WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
  90        } else {
  91                tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
  92                tmp &= ~DF_PIE_AON0_DfGlobalClkGater__MGCGMode_MASK;
  93                tmp |= DF_V1_7_MGCG_DISABLE;
  94                WREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater, tmp);
  95        }
  96
  97        /* Exit boradcast mode */
  98        adev->df.funcs->enable_broadcast_mode(adev, false);
  99}
 100
 101static void df_v1_7_get_clockgating_state(struct amdgpu_device *adev,
 102                                          u32 *flags)
 103{
 104        u32 tmp;
 105
 106        /* AMD_CG_SUPPORT_DF_MGCG */
 107        tmp = RREG32_SOC15(DF, 0, mmDF_PIE_AON0_DfGlobalClkGater);
 108        if (tmp & DF_V1_7_MGCG_ENABLE_15_CYCLE_DELAY)
 109                *flags |= AMD_CG_SUPPORT_DF_MGCG;
 110}
 111
 112static void df_v1_7_enable_ecc_force_par_wr_rmw(struct amdgpu_device *adev,
 113                                                bool enable)
 114{
 115        WREG32_FIELD15(DF, 0, DF_CS_AON0_CoherentSlaveModeCtrlA0,
 116                       ForceParWrRMW, enable);
 117}
 118
 119const struct amdgpu_df_funcs df_v1_7_funcs = {
 120        .sw_init = df_v1_7_sw_init,
 121        .sw_fini = df_v1_7_sw_fini,
 122        .enable_broadcast_mode = df_v1_7_enable_broadcast_mode,
 123        .get_fb_channel_number = df_v1_7_get_fb_channel_number,
 124        .get_hbm_channel_number = df_v1_7_get_hbm_channel_number,
 125        .update_medium_grain_clock_gating = df_v1_7_update_medium_grain_clock_gating,
 126        .get_clockgating_state = df_v1_7_get_clockgating_state,
 127        .enable_ecc_force_par_wr_rmw = df_v1_7_enable_ecc_force_par_wr_rmw,
 128};
 129