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23#include "amdgpu.h"
24#include "amdgpu_atombios.h"
25#include "nbio_v7_4.h"
26#include "amdgpu_ras.h"
27
28#include "nbio/nbio_7_4_offset.h"
29#include "nbio/nbio_7_4_sh_mask.h"
30#include "nbio/nbio_7_4_0_smn.h"
31#include "ivsrcid/nbio/irqsrcs_nbif_7_4.h"
32#include <uapi/linux/kfd_ioctl.h>
33
34#define smnPCIE_LC_CNTL 0x11140280
35#define smnPCIE_LC_CNTL3 0x111402d4
36#define smnPCIE_LC_CNTL6 0x111402ec
37#define smnPCIE_LC_CNTL7 0x111402f0
38#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
39#define smnRCC_BIF_STRAP3 0x1012348c
40#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK 0x0000FFFFL
41#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK 0xFFFF0000L
42#define smnRCC_BIF_STRAP5 0x10123494
43#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK 0x0000FFFFL
44#define smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2 0x1014008c
45#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK 0x0400L
46#define smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP 0x10140324
47#define smnPSWUSP0_PCIE_LC_CNTL2 0x111402c4
48#define smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL 0x10123538
49#define smnRCC_BIF_STRAP2 0x10123488
50#define RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK 0x00004000L
51#define RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT 0x0
52#define RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT 0x10
53#define RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT 0x0
54
55
56
57
58
59#define GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK 0x00001000L
60#define GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK 0x00002000L
61#define GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK 0x00004000L
62#define GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK 0x00008000L
63#define GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK 0x00010000L
64#define GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK 0x00020000L
65
66#define mmBIF_MMSCH1_DOORBELL_RANGE 0x01dc
67#define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX 2
68
69#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET__SHIFT 0x2
70#define BIF_MMSCH1_DOORBELL_RANGE__SIZE__SHIFT 0x10
71#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
72#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
73
74#define BIF_MMSCH1_DOORBELL_RANGE__OFFSET_MASK 0x00000FFCL
75#define BIF_MMSCH1_DOORBELL_RANGE__SIZE_MASK 0x001F0000L
76
77#define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE 0x01d8
78#define mmBIF_MMSCH1_DOORBELL_RANGE_ALDE_BASE_IDX 2
79
80#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET__SHIFT 0x2
81#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE__SHIFT 0x10
82#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__OFFSET_MASK 0x00000FFCL
83#define BIF_MMSCH1_DOORBELL_RANGE_ALDE__SIZE_MASK 0x001F0000L
84
85#define mmRCC_DEV0_EPF0_STRAP0_ALDE 0x0015
86#define mmRCC_DEV0_EPF0_STRAP0_ALDE_BASE_IDX 2
87
88#define mmBIF_DOORBELL_INT_CNTL_ALDE 0x00fe
89#define mmBIF_DOORBELL_INT_CNTL_ALDE_BASE_IDX 2
90#define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE__SHIFT 0x18
91#define BIF_DOORBELL_INT_CNTL_ALDE__DOORBELL_INTERRUPT_DISABLE_MASK 0x01000000L
92
93#define mmBIF_INTR_CNTL_ALDE 0x0101
94#define mmBIF_INTR_CNTL_ALDE_BASE_IDX 2
95
96static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
97 void *ras_error_status);
98
99static void nbio_v7_4_remap_hdp_registers(struct amdgpu_device *adev)
100{
101 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
102 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL);
103 WREG32_SOC15(NBIO, 0, mmREMAP_HDP_REG_FLUSH_CNTL,
104 adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL);
105}
106
107static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
108{
109 u32 tmp;
110
111 if (adev->asic_type == CHIP_ALDEBARAN)
112 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0_ALDE);
113 else
114 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
115
116 tmp &= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK;
117 tmp >>= RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT;
118
119 return tmp;
120}
121
122static void nbio_v7_4_mc_access_enable(struct amdgpu_device *adev, bool enable)
123{
124 if (enable)
125 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN,
126 BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK);
127 else
128 WREG32_SOC15(NBIO, 0, mmBIF_FB_EN, 0);
129}
130
131static u32 nbio_v7_4_get_memsize(struct amdgpu_device *adev)
132{
133 return RREG32_SOC15(NBIO, 0, mmRCC_CONFIG_MEMSIZE);
134}
135
136static void nbio_v7_4_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
137 bool use_doorbell, int doorbell_index, int doorbell_size)
138{
139 u32 reg, doorbell_range;
140
141 if (instance < 2) {
142 reg = instance +
143 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
144 } else {
145
146
147
148
149
150
151
152
153
154
155
156 if (adev->asic_type == CHIP_ALDEBARAN && instance == 4)
157 reg = instance + 0x4 + 0x1 +
158 SOC15_REG_OFFSET(NBIO, 0,
159 mmBIF_SDMA0_DOORBELL_RANGE);
160 else
161 reg = instance + 0x4 +
162 SOC15_REG_OFFSET(NBIO, 0,
163 mmBIF_SDMA0_DOORBELL_RANGE);
164 }
165
166 doorbell_range = RREG32(reg);
167
168 if (use_doorbell) {
169 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, OFFSET, doorbell_index);
170 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, doorbell_size);
171 } else
172 doorbell_range = REG_SET_FIELD(doorbell_range, BIF_SDMA0_DOORBELL_RANGE, SIZE, 0);
173
174 WREG32(reg, doorbell_range);
175}
176
177static void nbio_v7_4_vcn_doorbell_range(struct amdgpu_device *adev, bool use_doorbell,
178 int doorbell_index, int instance)
179{
180 u32 reg;
181 u32 doorbell_range;
182
183 if (instance) {
184 if (adev->asic_type == CHIP_ALDEBARAN)
185 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE_ALDE);
186 else
187 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH1_DOORBELL_RANGE);
188 } else
189 reg = SOC15_REG_OFFSET(NBIO, 0, mmBIF_MMSCH0_DOORBELL_RANGE);
190
191 doorbell_range = RREG32(reg);
192
193 if (use_doorbell) {
194 doorbell_range = REG_SET_FIELD(doorbell_range,
195 BIF_MMSCH0_DOORBELL_RANGE, OFFSET,
196 doorbell_index);
197 doorbell_range = REG_SET_FIELD(doorbell_range,
198 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 8);
199 } else
200 doorbell_range = REG_SET_FIELD(doorbell_range,
201 BIF_MMSCH0_DOORBELL_RANGE, SIZE, 0);
202
203 WREG32(reg, doorbell_range);
204}
205
206static void nbio_v7_4_enable_doorbell_aperture(struct amdgpu_device *adev,
207 bool enable)
208{
209 WREG32_FIELD15(NBIO, 0, RCC_DOORBELL_APER_EN, BIF_DOORBELL_APER_EN, enable ? 1 : 0);
210}
211
212static void nbio_v7_4_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
213 bool enable)
214{
215 u32 tmp = 0;
216
217 if (enable) {
218 tmp = REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_EN, 1) |
219 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_MODE, 1) |
220 REG_SET_FIELD(tmp, DOORBELL_SELFRING_GPA_APER_CNTL, DOORBELL_SELFRING_GPA_APER_SIZE, 0);
221
222 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_LOW,
223 lower_32_bits(adev->doorbell.base));
224 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_BASE_HIGH,
225 upper_32_bits(adev->doorbell.base));
226 }
227
228 WREG32_SOC15(NBIO, 0, mmDOORBELL_SELFRING_GPA_APER_CNTL, tmp);
229}
230
231static void nbio_v7_4_ih_doorbell_range(struct amdgpu_device *adev,
232 bool use_doorbell, int doorbell_index)
233{
234 u32 ih_doorbell_range = RREG32_SOC15(NBIO, 0 , mmBIF_IH_DOORBELL_RANGE);
235
236 if (use_doorbell) {
237 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, OFFSET, doorbell_index);
238 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 4);
239 } else
240 ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range, BIF_IH_DOORBELL_RANGE, SIZE, 0);
241
242 WREG32_SOC15(NBIO, 0, mmBIF_IH_DOORBELL_RANGE, ih_doorbell_range);
243}
244
245
246static void nbio_v7_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
247 bool enable)
248{
249
250}
251
252static void nbio_v7_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
253 bool enable)
254{
255 uint32_t def, data;
256
257 def = data = RREG32_PCIE(smnPCIE_CNTL2);
258 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS)) {
259 data |= (PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
260 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
261 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
262 } else {
263 data &= ~(PCIE_CNTL2__SLV_MEM_LS_EN_MASK |
264 PCIE_CNTL2__MST_MEM_LS_EN_MASK |
265 PCIE_CNTL2__REPLAY_MEM_LS_EN_MASK);
266 }
267
268 if (def != data)
269 WREG32_PCIE(smnPCIE_CNTL2, data);
270}
271
272static void nbio_v7_4_get_clockgating_state(struct amdgpu_device *adev,
273 u32 *flags)
274{
275 int data;
276
277
278 data = RREG32_PCIE(smnCPM_CONTROL);
279 if (data & CPM_CONTROL__LCLK_DYN_GATE_ENABLE_MASK)
280 *flags |= AMD_CG_SUPPORT_BIF_MGCG;
281
282
283 data = RREG32_PCIE(smnPCIE_CNTL2);
284 if (data & PCIE_CNTL2__SLV_MEM_LS_EN_MASK)
285 *flags |= AMD_CG_SUPPORT_BIF_LS;
286}
287
288static void nbio_v7_4_ih_control(struct amdgpu_device *adev)
289{
290 u32 interrupt_cntl;
291
292
293 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
294 interrupt_cntl = RREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL);
295
296
297
298 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_DUMMY_RD_OVERRIDE, 0);
299
300 interrupt_cntl = REG_SET_FIELD(interrupt_cntl, INTERRUPT_CNTL, IH_REQ_NONSNOOP_EN, 0);
301 WREG32_SOC15(NBIO, 0, mmINTERRUPT_CNTL, interrupt_cntl);
302}
303
304static u32 nbio_v7_4_get_hdp_flush_req_offset(struct amdgpu_device *adev)
305{
306 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_REQ);
307}
308
309static u32 nbio_v7_4_get_hdp_flush_done_offset(struct amdgpu_device *adev)
310{
311 return SOC15_REG_OFFSET(NBIO, 0, mmGPU_HDP_FLUSH_DONE);
312}
313
314static u32 nbio_v7_4_get_pcie_index_offset(struct amdgpu_device *adev)
315{
316 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_INDEX2);
317}
318
319static u32 nbio_v7_4_get_pcie_data_offset(struct amdgpu_device *adev)
320{
321 return SOC15_REG_OFFSET(NBIO, 0, mmPCIE_DATA2);
322}
323
324const struct nbio_hdp_flush_reg nbio_v7_4_hdp_flush_reg = {
325 .ref_and_mask_cp0 = GPU_HDP_FLUSH_DONE__CP0_MASK,
326 .ref_and_mask_cp1 = GPU_HDP_FLUSH_DONE__CP1_MASK,
327 .ref_and_mask_cp2 = GPU_HDP_FLUSH_DONE__CP2_MASK,
328 .ref_and_mask_cp3 = GPU_HDP_FLUSH_DONE__CP3_MASK,
329 .ref_and_mask_cp4 = GPU_HDP_FLUSH_DONE__CP4_MASK,
330 .ref_and_mask_cp5 = GPU_HDP_FLUSH_DONE__CP5_MASK,
331 .ref_and_mask_cp6 = GPU_HDP_FLUSH_DONE__CP6_MASK,
332 .ref_and_mask_cp7 = GPU_HDP_FLUSH_DONE__CP7_MASK,
333 .ref_and_mask_cp8 = GPU_HDP_FLUSH_DONE__CP8_MASK,
334 .ref_and_mask_cp9 = GPU_HDP_FLUSH_DONE__CP9_MASK,
335 .ref_and_mask_sdma0 = GPU_HDP_FLUSH_DONE__SDMA0_MASK,
336 .ref_and_mask_sdma1 = GPU_HDP_FLUSH_DONE__SDMA1_MASK,
337 .ref_and_mask_sdma2 = GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK,
338 .ref_and_mask_sdma3 = GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK,
339 .ref_and_mask_sdma4 = GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK,
340 .ref_and_mask_sdma5 = GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK,
341 .ref_and_mask_sdma6 = GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK,
342 .ref_and_mask_sdma7 = GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK,
343};
344
345static void nbio_v7_4_init_registers(struct amdgpu_device *adev)
346{
347
348}
349
350static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device *adev)
351{
352 uint32_t bif_doorbell_intr_cntl;
353 struct ras_manager *obj = amdgpu_ras_find_obj(adev, adev->nbio.ras_if);
354 struct ras_err_data err_data = {0, 0, 0, NULL};
355 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev);
356
357 if (adev->asic_type == CHIP_ALDEBARAN)
358 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);
359 else
360 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
361
362 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
363 BIF_DOORBELL_INT_CNTL, RAS_CNTLR_INTERRUPT_STATUS)) {
364
365 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
366 BIF_DOORBELL_INT_CNTL,
367 RAS_CNTLR_INTERRUPT_CLEAR, 1);
368 if (adev->asic_type == CHIP_ALDEBARAN)
369 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl);
370 else
371 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
372
373 if (!ras->disable_ras_err_cnt_harvest) {
374
375
376
377
378
379 nbio_v7_4_query_ras_error_count(adev, &err_data);
380
381
382 obj->err_data.ue_count += err_data.ue_count;
383 obj->err_data.ce_count += err_data.ce_count;
384
385 if (err_data.ce_count)
386 dev_info(adev->dev, "%ld correctable hardware "
387 "errors detected in %s block, "
388 "no user action is needed.\n",
389 obj->err_data.ce_count,
390 ras_block_str(adev->nbio.ras_if->block));
391
392 if (err_data.ue_count)
393 dev_info(adev->dev, "%ld uncorrectable hardware "
394 "errors detected in %s block\n",
395 obj->err_data.ue_count,
396 ras_block_str(adev->nbio.ras_if->block));
397 }
398
399 dev_info(adev->dev, "RAS controller interrupt triggered "
400 "by NBIF error\n");
401
402
403
404
405 amdgpu_ras_reset_gpu(adev);
406 }
407}
408
409static void nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring(struct amdgpu_device *adev)
410{
411 uint32_t bif_doorbell_intr_cntl;
412
413 if (adev->asic_type == CHIP_ALDEBARAN)
414 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE);
415 else
416 bif_doorbell_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL);
417
418 if (REG_GET_FIELD(bif_doorbell_intr_cntl,
419 BIF_DOORBELL_INT_CNTL, RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS)) {
420
421 bif_doorbell_intr_cntl = REG_SET_FIELD(bif_doorbell_intr_cntl,
422 BIF_DOORBELL_INT_CNTL,
423 RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR, 1);
424
425 if (adev->asic_type == CHIP_ALDEBARAN)
426 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL_ALDE, bif_doorbell_intr_cntl);
427 else
428 WREG32_SOC15(NBIO, 0, mmBIF_DOORBELL_INT_CNTL, bif_doorbell_intr_cntl);
429
430 amdgpu_ras_global_ras_isr(adev);
431 }
432}
433
434
435static int nbio_v7_4_set_ras_controller_irq_state(struct amdgpu_device *adev,
436 struct amdgpu_irq_src *src,
437 unsigned type,
438 enum amdgpu_interrupt_state state)
439{
440
441
442
443
444 uint32_t bif_intr_cntl;
445
446 if (adev->asic_type == CHIP_ALDEBARAN)
447 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);
448 else
449 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
450
451 if (state == AMDGPU_IRQ_STATE_ENABLE) {
452
453
454 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
455 BIF_INTR_CNTL,
456 RAS_INTR_VEC_SEL, 0);
457
458 if (adev->asic_type == CHIP_ALDEBARAN)
459 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl);
460 else
461 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
462
463 }
464
465 return 0;
466}
467
468static int nbio_v7_4_process_ras_controller_irq(struct amdgpu_device *adev,
469 struct amdgpu_irq_src *source,
470 struct amdgpu_iv_entry *entry)
471{
472
473
474
475
476
477 return 0;
478}
479
480static int nbio_v7_4_set_ras_err_event_athub_irq_state(struct amdgpu_device *adev,
481 struct amdgpu_irq_src *src,
482 unsigned type,
483 enum amdgpu_interrupt_state state)
484{
485
486
487
488
489 uint32_t bif_intr_cntl;
490
491 if (adev->asic_type == CHIP_ALDEBARAN)
492 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE);
493 else
494 bif_intr_cntl = RREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL);
495
496 if (state == AMDGPU_IRQ_STATE_ENABLE) {
497
498
499 bif_intr_cntl = REG_SET_FIELD(bif_intr_cntl,
500 BIF_INTR_CNTL,
501 RAS_INTR_VEC_SEL, 0);
502
503 if (adev->asic_type == CHIP_ALDEBARAN)
504 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL_ALDE, bif_intr_cntl);
505 else
506 WREG32_SOC15(NBIO, 0, mmBIF_INTR_CNTL, bif_intr_cntl);
507 }
508
509 return 0;
510}
511
512static int nbio_v7_4_process_err_event_athub_irq(struct amdgpu_device *adev,
513 struct amdgpu_irq_src *source,
514 struct amdgpu_iv_entry *entry)
515{
516
517
518
519
520
521 return 0;
522}
523
524static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_controller_irq_funcs = {
525 .set = nbio_v7_4_set_ras_controller_irq_state,
526 .process = nbio_v7_4_process_ras_controller_irq,
527};
528
529static const struct amdgpu_irq_src_funcs nbio_v7_4_ras_err_event_athub_irq_funcs = {
530 .set = nbio_v7_4_set_ras_err_event_athub_irq_state,
531 .process = nbio_v7_4_process_err_event_athub_irq,
532};
533
534static int nbio_v7_4_init_ras_controller_interrupt (struct amdgpu_device *adev)
535{
536 int r;
537
538
539 adev->nbio.ras_controller_irq.funcs =
540 &nbio_v7_4_ras_controller_irq_funcs;
541 adev->nbio.ras_controller_irq.num_types = 1;
542
543
544 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
545 NBIF_7_4__SRCID__RAS_CONTROLLER_INTERRUPT,
546 &adev->nbio.ras_controller_irq);
547
548 return r;
549}
550
551static int nbio_v7_4_init_ras_err_event_athub_interrupt (struct amdgpu_device *adev)
552{
553
554 int r;
555
556
557 adev->nbio.ras_err_event_athub_irq.funcs =
558 &nbio_v7_4_ras_err_event_athub_irq_funcs;
559 adev->nbio.ras_err_event_athub_irq.num_types = 1;
560
561
562 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_BIF,
563 NBIF_7_4__SRCID__ERREVENT_ATHUB_INTERRUPT,
564 &adev->nbio.ras_err_event_athub_irq);
565
566 return r;
567}
568
569#define smnPARITY_ERROR_STATUS_UNCORR_GRP2 0x13a20030
570
571static void nbio_v7_4_query_ras_error_count(struct amdgpu_device *adev,
572 void *ras_error_status)
573{
574 uint32_t global_sts, central_sts, int_eoi, parity_sts;
575 uint32_t corr, fatal, non_fatal;
576 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
577
578 global_sts = RREG32_PCIE(smnRAS_GLOBAL_STATUS_LO);
579 corr = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrCorr);
580 fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO, ParityErrFatal);
581 non_fatal = REG_GET_FIELD(global_sts, RAS_GLOBAL_STATUS_LO,
582 ParityErrNonFatal);
583 parity_sts = RREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2);
584
585 if (corr)
586 err_data->ce_count++;
587 if (fatal)
588 err_data->ue_count++;
589
590 if (corr || fatal || non_fatal) {
591 central_sts = RREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS);
592
593 WREG32_PCIE(smnRAS_GLOBAL_STATUS_LO, global_sts);
594
595 if (fatal)
596
597 WREG32_PCIE(smnPARITY_ERROR_STATUS_UNCORR_GRP2,
598 parity_sts);
599
600 if (REG_GET_FIELD(central_sts, BIFL_RAS_CENTRAL_STATUS,
601 BIFL_RasContller_Intr_Recv)) {
602
603 WREG32_PCIE(smnBIFL_RAS_CENTRAL_STATUS, central_sts);
604 int_eoi = RREG32_PCIE(smnIOHC_INTERRUPT_EOI);
605 int_eoi = REG_SET_FIELD(int_eoi,
606 IOHC_INTERRUPT_EOI, SMI_EOI, 1);
607 WREG32_PCIE(smnIOHC_INTERRUPT_EOI, int_eoi);
608 }
609 }
610}
611
612static void nbio_v7_4_enable_doorbell_interrupt(struct amdgpu_device *adev,
613 bool enable)
614{
615 if (adev->asic_type == CHIP_ALDEBARAN)
616 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL_ALDE,
617 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
618 else
619 WREG32_FIELD15(NBIO, 0, BIF_DOORBELL_INT_CNTL,
620 DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
621}
622
623const struct amdgpu_nbio_ras_funcs nbio_v7_4_ras_funcs = {
624 .handle_ras_controller_intr_no_bifring = nbio_v7_4_handle_ras_controller_intr_no_bifring,
625 .handle_ras_err_event_athub_intr_no_bifring = nbio_v7_4_handle_ras_err_event_athub_intr_no_bifring,
626 .init_ras_controller_interrupt = nbio_v7_4_init_ras_controller_interrupt,
627 .init_ras_err_event_athub_interrupt = nbio_v7_4_init_ras_err_event_athub_interrupt,
628 .query_ras_error_count = nbio_v7_4_query_ras_error_count,
629 .ras_late_init = amdgpu_nbio_ras_late_init,
630 .ras_fini = amdgpu_nbio_ras_fini,
631};
632
633static void nbio_v7_4_program_ltr(struct amdgpu_device *adev)
634{
635 uint32_t def, data;
636
637 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, 0x75EB);
638
639 def = data = RREG32_PCIE(smnRCC_BIF_STRAP2);
640 data &= ~RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK;
641 if (def != data)
642 WREG32_PCIE(smnRCC_BIF_STRAP2, data);
643
644 def = data = RREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL);
645 data &= ~EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK;
646 if (def != data)
647 WREG32_PCIE(smnRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL, data);
648
649 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
650 data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
651 if (def != data)
652 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
653}
654
655static void nbio_v7_4_program_aspm(struct amdgpu_device *adev)
656{
657 uint32_t def, data;
658
659 def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
660 data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK;
661 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
662 data |= PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK;
663 if (def != data)
664 WREG32_PCIE(smnPCIE_LC_CNTL, data);
665
666 def = data = RREG32_PCIE(smnPCIE_LC_CNTL7);
667 data |= PCIE_LC_CNTL7__LC_NBIF_ASPM_INPUT_EN_MASK;
668 if (def != data)
669 WREG32_PCIE(smnPCIE_LC_CNTL7, data);
670
671 def = data = RREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK);
672 data |= NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK;
673 if (def != data)
674 WREG32_PCIE(smnNBIF_MGCG_CTRL_LCLK, data);
675
676 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
677 data |= PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
678 if (def != data)
679 WREG32_PCIE(smnPCIE_LC_CNTL3, data);
680
681 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
682 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK;
683 data &= ~RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK;
684 if (def != data)
685 WREG32_PCIE(smnRCC_BIF_STRAP3, data);
686
687 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
688 data &= ~RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK;
689 if (def != data)
690 WREG32_PCIE(smnRCC_BIF_STRAP5, data);
691
692 def = data = RREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2);
693 data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK;
694 if (def != data)
695 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data);
696
697 WREG32_PCIE(smnBIF_CFG_DEV0_EPF0_PCIE_LTR_CAP, 0x10011001);
698
699 def = data = RREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2);
700 data |= PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L1_MASK |
701 PSWUSP0_PCIE_LC_CNTL2__LC_ALLOW_PDWN_IN_L23_MASK;
702 data &= ~PSWUSP0_PCIE_LC_CNTL2__LC_RCV_L0_TO_RCV_L0S_DIS_MASK;
703 if (def != data)
704 WREG32_PCIE(smnPSWUSP0_PCIE_LC_CNTL2, data);
705
706 def = data = RREG32_PCIE(smnPCIE_LC_CNTL6);
707 data |= PCIE_LC_CNTL6__LC_L1_POWERDOWN_MASK |
708 PCIE_LC_CNTL6__LC_RX_L0S_STANDBY_EN_MASK;
709 if (def != data)
710 WREG32_PCIE(smnPCIE_LC_CNTL6, data);
711
712 nbio_v7_4_program_ltr(adev);
713
714 def = data = RREG32_PCIE(smnRCC_BIF_STRAP3);
715 data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT;
716 data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT;
717 if (def != data)
718 WREG32_PCIE(smnRCC_BIF_STRAP3, data);
719
720 def = data = RREG32_PCIE(smnRCC_BIF_STRAP5);
721 data |= 0x0010 << RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT;
722 if (def != data)
723 WREG32_PCIE(smnRCC_BIF_STRAP5, data);
724
725 def = data = RREG32_PCIE(smnPCIE_LC_CNTL);
726 data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK;
727 data |= 0x9 << PCIE_LC_CNTL__LC_L1_INACTIVITY__SHIFT;
728 data |= 0x1 << PCIE_LC_CNTL__LC_PMI_TO_L1_DIS__SHIFT;
729 if (def != data)
730 WREG32_PCIE(smnPCIE_LC_CNTL, data);
731
732 def = data = RREG32_PCIE(smnPCIE_LC_CNTL3);
733 data &= ~PCIE_LC_CNTL3__LC_DSC_DONT_ENTER_L23_AFTER_PME_ACK_MASK;
734 if (def != data)
735 WREG32_PCIE(smnPCIE_LC_CNTL3, data);
736}
737
738const struct amdgpu_nbio_funcs nbio_v7_4_funcs = {
739 .get_hdp_flush_req_offset = nbio_v7_4_get_hdp_flush_req_offset,
740 .get_hdp_flush_done_offset = nbio_v7_4_get_hdp_flush_done_offset,
741 .get_pcie_index_offset = nbio_v7_4_get_pcie_index_offset,
742 .get_pcie_data_offset = nbio_v7_4_get_pcie_data_offset,
743 .get_rev_id = nbio_v7_4_get_rev_id,
744 .mc_access_enable = nbio_v7_4_mc_access_enable,
745 .get_memsize = nbio_v7_4_get_memsize,
746 .sdma_doorbell_range = nbio_v7_4_sdma_doorbell_range,
747 .vcn_doorbell_range = nbio_v7_4_vcn_doorbell_range,
748 .enable_doorbell_aperture = nbio_v7_4_enable_doorbell_aperture,
749 .enable_doorbell_selfring_aperture = nbio_v7_4_enable_doorbell_selfring_aperture,
750 .ih_doorbell_range = nbio_v7_4_ih_doorbell_range,
751 .enable_doorbell_interrupt = nbio_v7_4_enable_doorbell_interrupt,
752 .update_medium_grain_clock_gating = nbio_v7_4_update_medium_grain_clock_gating,
753 .update_medium_grain_light_sleep = nbio_v7_4_update_medium_grain_light_sleep,
754 .get_clockgating_state = nbio_v7_4_get_clockgating_state,
755 .ih_control = nbio_v7_4_ih_control,
756 .init_registers = nbio_v7_4_init_registers,
757 .remap_hdp_registers = nbio_v7_4_remap_hdp_registers,
758 .program_aspm = nbio_v7_4_program_aspm,
759};
760
