1/* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24#ifndef NVD_H 25#define NVD_H 26 27/** 28 * Navi's PM4 definitions 29 */ 30#define PACKET_TYPE0 0 31#define PACKET_TYPE1 1 32#define PACKET_TYPE2 2 33#define PACKET_TYPE3 3 34 35#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 36#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 37#define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 38#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 39#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 40 ((reg) & 0xFFFF) | \ 41 ((n) & 0x3FFF) << 16) 42#define CP_PACKET2 0x80000000 43#define PACKET2_PAD_SHIFT 0 44#define PACKET2_PAD_MASK (0x3fffffff << 0) 45 46#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 47 48#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 49 (((op) & 0xFF) << 8) | \ 50 ((n) & 0x3FFF) << 16) 51 52#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 53 54/* Packet 3 types */ 55#define PACKET3_NOP 0x10 56#define PACKET3_SET_BASE 0x11 57#define PACKET3_BASE_INDEX(x) ((x) << 0) 58#define CE_PARTITION_BASE 3 59#define PACKET3_CLEAR_STATE 0x12 60#define PACKET3_INDEX_BUFFER_SIZE 0x13 61#define PACKET3_DISPATCH_DIRECT 0x15 62#define PACKET3_DISPATCH_INDIRECT 0x16 63#define PACKET3_INDIRECT_BUFFER_END 0x17 64#define PACKET3_INDIRECT_BUFFER_CNST_END 0x19 65#define PACKET3_ATOMIC_GDS 0x1D 66#define PACKET3_ATOMIC_MEM 0x1E 67#define PACKET3_OCCLUSION_QUERY 0x1F 68#define PACKET3_SET_PREDICATION 0x20 69#define PACKET3_REG_RMW 0x21 70#define PACKET3_COND_EXEC 0x22 71#define PACKET3_PRED_EXEC 0x23 72#define PACKET3_DRAW_INDIRECT 0x24 73#define PACKET3_DRAW_INDEX_INDIRECT 0x25 74#define PACKET3_INDEX_BASE 0x26 75#define PACKET3_DRAW_INDEX_2 0x27 76#define PACKET3_CONTEXT_CONTROL 0x28 77#define PACKET3_INDEX_TYPE 0x2A 78#define PACKET3_DRAW_INDIRECT_MULTI 0x2C 79#define PACKET3_DRAW_INDEX_AUTO 0x2D 80#define PACKET3_NUM_INSTANCES 0x2F 81#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 82#define PACKET3_INDIRECT_BUFFER_PRIV 0x32 83#define PACKET3_INDIRECT_BUFFER_CNST 0x33 84#define PACKET3_COND_INDIRECT_BUFFER_CNST 0x33 85#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 86#define PACKET3_DRAW_INDEX_OFFSET_2 0x35 87#define PACKET3_DRAW_PREAMBLE 0x36 88#define PACKET3_WRITE_DATA 0x37 89#define WRITE_DATA_DST_SEL(x) ((x) << 8) 90 /* 0 - register 91 * 1 - memory (sync - via GRBM) 92 * 2 - gl2 93 * 3 - gds 94 * 4 - reserved 95 * 5 - memory (async - direct) 96 */ 97#define WR_ONE_ADDR (1 << 16) 98#define WR_CONFIRM (1 << 20) 99#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 100 /* 0 - LRU 101 * 1 - Stream 102 */ 103#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 104 /* 0 - me 105 * 1 - pfp 106 * 2 - ce 107 */ 108#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 109#define PACKET3_MEM_SEMAPHORE 0x39 110# define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 111# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 112# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 113# define PACKET3_SEM_SEL_WAIT (0x7 << 29) 114#define PACKET3_DRAW_INDEX_MULTI_INST 0x3A 115#define PACKET3_COPY_DW 0x3B 116#define PACKET3_WAIT_REG_MEM 0x3C 117#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 118 /* 0 - always 119 * 1 - < 120 * 2 - <= 121 * 3 - == 122 * 4 - != 123 * 5 - >= 124 * 6 - > 125 */ 126#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 127 /* 0 - reg 128 * 1 - mem 129 */ 130#define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 131 /* 0 - wait_reg_mem 132 * 1 - wr_wait_wr_reg 133 */ 134#define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 135 /* 0 - me 136 * 1 - pfp 137 */ 138#define PACKET3_INDIRECT_BUFFER 0x3F 139#define INDIRECT_BUFFER_VALID (1 << 23) 140#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 141 /* 0 - LRU 142 * 1 - Stream 143 * 2 - Bypass 144 */ 145#define INDIRECT_BUFFER_PRE_ENB(x) ((x) << 21) 146#define INDIRECT_BUFFER_PRE_RESUME(x) ((x) << 30) 147#define PACKET3_COND_INDIRECT_BUFFER 0x3F 148#define PACKET3_COPY_DATA 0x40 149#define PACKET3_CP_DMA 0x41 150#define PACKET3_PFP_SYNC_ME 0x42 151#define PACKET3_SURFACE_SYNC 0x43 152#define PACKET3_ME_INITIALIZE 0x44 153#define PACKET3_COND_WRITE 0x45 154#define PACKET3_EVENT_WRITE 0x46 155#define EVENT_TYPE(x) ((x) << 0) 156#define EVENT_INDEX(x) ((x) << 8) 157 /* 0 - any non-TS event 158 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 159 * 2 - SAMPLE_PIPELINESTAT 160 * 3 - SAMPLE_STREAMOUTSTAT* 161 * 4 - *S_PARTIAL_FLUSH 162 */ 163#define PACKET3_EVENT_WRITE_EOP 0x47 164#define PACKET3_EVENT_WRITE_EOS 0x48 165#define PACKET3_RELEASE_MEM 0x49 166#define PACKET3_RELEASE_MEM_EVENT_TYPE(x) ((x) << 0) 167#define PACKET3_RELEASE_MEM_EVENT_INDEX(x) ((x) << 8) 168#define PACKET3_RELEASE_MEM_GCR_GLM_WB (1 << 12) 169#define PACKET3_RELEASE_MEM_GCR_GLM_INV (1 << 13) 170#define PACKET3_RELEASE_MEM_GCR_GLV_INV (1 << 14) 171#define PACKET3_RELEASE_MEM_GCR_GL1_INV (1 << 15) 172#define PACKET3_RELEASE_MEM_GCR_GL2_US (1 << 16) 173#define PACKET3_RELEASE_MEM_GCR_GL2_RANGE (1 << 17) 174#define PACKET3_RELEASE_MEM_GCR_GL2_DISCARD (1 << 19) 175#define PACKET3_RELEASE_MEM_GCR_GL2_INV (1 << 20) 176#define PACKET3_RELEASE_MEM_GCR_GL2_WB (1 << 21) 177#define PACKET3_RELEASE_MEM_GCR_SEQ (1 << 22) 178#define PACKET3_RELEASE_MEM_CACHE_POLICY(x) ((x) << 25) 179 /* 0 - cache_policy__me_release_mem__lru 180 * 1 - cache_policy__me_release_mem__stream 181 * 2 - cache_policy__me_release_mem__noa 182 * 3 - cache_policy__me_release_mem__bypass 183 */ 184#define PACKET3_RELEASE_MEM_EXECUTE (1 << 28) 185 186#define PACKET3_RELEASE_MEM_DATA_SEL(x) ((x) << 29) 187 /* 0 - discard 188 * 1 - send low 32bit data 189 * 2 - send 64bit data 190 * 3 - send 64bit GPU counter value 191 * 4 - send 64bit sys counter value 192 */ 193#define PACKET3_RELEASE_MEM_INT_SEL(x) ((x) << 24) 194 /* 0 - none 195 * 1 - interrupt only (DATA_SEL = 0) 196 * 2 - interrupt when data write is confirmed 197 */ 198#define PACKET3_RELEASE_MEM_DST_SEL(x) ((x) << 16) 199 /* 0 - MC 200 * 1 - TC/L2 201 */ 202 203 204 205#define PACKET3_PREAMBLE_CNTL 0x4A 206# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 207# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 208#define PACKET3_DMA_DATA 0x50 209/* 1. header 210 * 2. CONTROL 211 * 3. SRC_ADDR_LO or DATA [31:0] 212 * 4. SRC_ADDR_HI [31:0] 213 * 5. DST_ADDR_LO [31:0] 214 * 6. DST_ADDR_HI [7:0] 215 * 7. COMMAND [31:26] | BYTE_COUNT [25:0] 216 */ 217/* CONTROL */ 218# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 219 /* 0 - ME 220 * 1 - PFP 221 */ 222# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 223 /* 0 - LRU 224 * 1 - Stream 225 */ 226# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 227 /* 0 - DST_ADDR using DAS 228 * 1 - GDS 229 * 3 - DST_ADDR using L2 230 */ 231# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 232 /* 0 - LRU 233 * 1 - Stream 234 */ 235# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 236 /* 0 - SRC_ADDR using SAS 237 * 1 - GDS 238 * 2 - DATA 239 * 3 - SRC_ADDR using L2 240 */ 241# define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 242/* COMMAND */ 243# define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 244 /* 0 - memory 245 * 1 - register 246 */ 247# define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 248 /* 0 - memory 249 * 1 - register 250 */ 251# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 252# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 253# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 254#define PACKET3_CONTEXT_REG_RMW 0x51 255#define PACKET3_GFX_CNTX_UPDATE 0x52 256#define PACKET3_BLK_CNTX_UPDATE 0x53 257#define PACKET3_INCR_UPDT_STATE 0x55 258#define PACKET3_ACQUIRE_MEM 0x58 259/* 1. HEADER 260 * 2. COHER_CNTL [30:0] 261 * 2.1 ENGINE_SEL [31:31] 262 * 2. COHER_SIZE [31:0] 263 * 3. COHER_SIZE_HI [7:0] 264 * 4. COHER_BASE_LO [31:0] 265 * 5. COHER_BASE_HI [23:0] 266 * 7. POLL_INTERVAL [15:0] 267 * 8. GCR_CNTL [18:0] 268 */ 269#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0) 270 /* 271 * 0:NOP 272 * 1:ALL 273 * 2:RANGE 274 * 3:FIRST_LAST 275 */ 276#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2) 277 /* 278 * 0:ALL 279 * 1:reserved 280 * 2:RANGE 281 * 3:FIRST_LAST 282 */ 283#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(x) ((x) << 4) 284#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(x) ((x) << 5) 285#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_WB(x) ((x) << 6) 286#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7) 287#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8) 288#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(x) ((x) << 9) 289#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10) 290#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11) 291 /* 292 * 0:ALL 293 * 1:VOL 294 * 2:RANGE 295 * 3:FIRST_LAST 296 */ 297#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x) ((x) << 13) 298#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14) 299#define PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15) 300#define PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16) 301 /* 302 * 0: PARALLEL 303 * 1: FORWARD 304 * 2: REVERSE 305 */ 306#define PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA (1 << 18) 307#define PACKET3_REWIND 0x59 308#define PACKET3_INTERRUPT 0x5A 309#define PACKET3_GEN_PDEPTE 0x5B 310#define PACKET3_INDIRECT_BUFFER_PASID 0x5C 311#define PACKET3_PRIME_UTCL2 0x5D 312#define PACKET3_LOAD_UCONFIG_REG 0x5E 313#define PACKET3_LOAD_SH_REG 0x5F 314#define PACKET3_LOAD_CONFIG_REG 0x60 315#define PACKET3_LOAD_CONTEXT_REG 0x61 316#define PACKET3_LOAD_COMPUTE_STATE 0x62 317#define PACKET3_LOAD_SH_REG_INDEX 0x63 318#define PACKET3_SET_CONFIG_REG 0x68 319#define PACKET3_SET_CONFIG_REG_START 0x00002000 320#define PACKET3_SET_CONFIG_REG_END 0x00002c00 321#define PACKET3_SET_CONTEXT_REG 0x69 322#define PACKET3_SET_CONTEXT_REG_START 0x0000a000 323#define PACKET3_SET_CONTEXT_REG_END 0x0000a400 324#define PACKET3_SET_CONTEXT_REG_INDEX 0x6A 325#define PACKET3_SET_VGPR_REG_DI_MULTI 0x71 326#define PACKET3_SET_SH_REG_DI 0x72 327#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 328#define PACKET3_SET_SH_REG_DI_MULTI 0x74 329#define PACKET3_GFX_PIPE_LOCK 0x75 330#define PACKET3_SET_SH_REG 0x76 331#define PACKET3_SET_SH_REG_START 0x00002c00 332#define PACKET3_SET_SH_REG_END 0x00003000 333#define PACKET3_SET_SH_REG_OFFSET 0x77 334#define PACKET3_SET_QUEUE_REG 0x78 335#define PACKET3_SET_UCONFIG_REG 0x79 336#define PACKET3_SET_UCONFIG_REG_START 0x0000c000 337#define PACKET3_SET_UCONFIG_REG_END 0x0000c400 338#define PACKET3_SET_UCONFIG_REG_INDEX 0x7A 339#define PACKET3_FORWARD_HEADER 0x7C 340#define PACKET3_SCRATCH_RAM_WRITE 0x7D 341#define PACKET3_SCRATCH_RAM_READ 0x7E 342#define PACKET3_LOAD_CONST_RAM 0x80 343#define PACKET3_WRITE_CONST_RAM 0x81 344#define PACKET3_DUMP_CONST_RAM 0x83 345#define PACKET3_INCREMENT_CE_COUNTER 0x84 346#define PACKET3_INCREMENT_DE_COUNTER 0x85 347#define PACKET3_WAIT_ON_CE_COUNTER 0x86 348#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 349#define PACKET3_SWITCH_BUFFER 0x8B 350#define PACKET3_DISPATCH_DRAW_PREAMBLE 0x8C 351#define PACKET3_DISPATCH_DRAW_PREAMBLE_ACE 0x8C 352#define PACKET3_DISPATCH_DRAW 0x8D 353#define PACKET3_DISPATCH_DRAW_ACE 0x8D 354#define PACKET3_GET_LOD_STATS 0x8E 355#define PACKET3_DRAW_MULTI_PREAMBLE 0x8F 356#define PACKET3_FRAME_CONTROL 0x90 357# define FRAME_TMZ (1 << 0) 358# define FRAME_CMD(x) ((x) << 28) 359 /* 360 * x=0: tmz_begin 361 * x=1: tmz_end 362 */ 363#define PACKET3_INDEX_ATTRIBUTES_INDIRECT 0x91 364#define PACKET3_WAIT_REG_MEM64 0x93 365#define PACKET3_COND_PREEMPT 0x94 366#define PACKET3_HDP_FLUSH 0x95 367#define PACKET3_COPY_DATA_RB 0x96 368#define PACKET3_INVALIDATE_TLBS 0x98 369# define PACKET3_INVALIDATE_TLBS_DST_SEL(x) ((x) << 0) 370# define PACKET3_INVALIDATE_TLBS_ALL_HUB(x) ((x) << 4) 371# define PACKET3_INVALIDATE_TLBS_PASID(x) ((x) << 5) 372#define PACKET3_AQL_PACKET 0x99 373#define PACKET3_DMA_DATA_FILL_MULTI 0x9A 374#define PACKET3_SET_SH_REG_INDEX 0x9B 375#define PACKET3_DRAW_INDIRECT_COUNT_MULTI 0x9C 376#define PACKET3_DRAW_INDEX_INDIRECT_COUNT_MULTI 0x9D 377#define PACKET3_DUMP_CONST_RAM_OFFSET 0x9E 378#define PACKET3_LOAD_CONTEXT_REG_INDEX 0x9F 379#define PACKET3_SET_RESOURCES 0xA0 380/* 1. header 381 * 2. CONTROL 382 * 3. QUEUE_MASK_LO [31:0] 383 * 4. QUEUE_MASK_HI [31:0] 384 * 5. GWS_MASK_LO [31:0] 385 * 6. GWS_MASK_HI [31:0] 386 * 7. OAC_MASK [15:0] 387 * 8. GDS_HEAP_SIZE [16:11] | GDS_HEAP_BASE [5:0] 388 */ 389# define PACKET3_SET_RESOURCES_VMID_MASK(x) ((x) << 0) 390# define PACKET3_SET_RESOURCES_UNMAP_LATENTY(x) ((x) << 16) 391# define PACKET3_SET_RESOURCES_QUEUE_TYPE(x) ((x) << 29) 392#define PACKET3_MAP_PROCESS 0xA1 393#define PACKET3_MAP_QUEUES 0xA2 394/* 1. header 395 * 2. CONTROL 396 * 3. CONTROL2 397 * 4. MQD_ADDR_LO [31:0] 398 * 5. MQD_ADDR_HI [31:0] 399 * 6. WPTR_ADDR_LO [31:0] 400 * 7. WPTR_ADDR_HI [31:0] 401 */ 402/* CONTROL */ 403# define PACKET3_MAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 404# define PACKET3_MAP_QUEUES_VMID(x) ((x) << 8) 405# define PACKET3_MAP_QUEUES_QUEUE(x) ((x) << 13) 406# define PACKET3_MAP_QUEUES_PIPE(x) ((x) << 16) 407# define PACKET3_MAP_QUEUES_ME(x) ((x) << 18) 408# define PACKET3_MAP_QUEUES_QUEUE_TYPE(x) ((x) << 21) 409# define PACKET3_MAP_QUEUES_ALLOC_FORMAT(x) ((x) << 24) 410# define PACKET3_MAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 411# define PACKET3_MAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 412/* CONTROL2 */ 413# define PACKET3_MAP_QUEUES_CHECK_DISABLE(x) ((x) << 1) 414# define PACKET3_MAP_QUEUES_DOORBELL_OFFSET(x) ((x) << 2) 415#define PACKET3_UNMAP_QUEUES 0xA3 416/* 1. header 417 * 2. CONTROL 418 * 3. CONTROL2 419 * 4. CONTROL3 420 * 5. CONTROL4 421 * 6. CONTROL5 422 */ 423/* CONTROL */ 424# define PACKET3_UNMAP_QUEUES_ACTION(x) ((x) << 0) 425 /* 0 - PREEMPT_QUEUES 426 * 1 - RESET_QUEUES 427 * 2 - DISABLE_PROCESS_QUEUES 428 * 3 - PREEMPT_QUEUES_NO_UNMAP 429 */ 430# define PACKET3_UNMAP_QUEUES_QUEUE_SEL(x) ((x) << 4) 431# define PACKET3_UNMAP_QUEUES_ENGINE_SEL(x) ((x) << 26) 432# define PACKET3_UNMAP_QUEUES_NUM_QUEUES(x) ((x) << 29) 433/* CONTROL2a */ 434# define PACKET3_UNMAP_QUEUES_PASID(x) ((x) << 0) 435/* CONTROL2b */ 436# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(x) ((x) << 2) 437/* CONTROL3a */ 438# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET1(x) ((x) << 2) 439/* CONTROL3b */ 440# define PACKET3_UNMAP_QUEUES_RB_WPTR(x) ((x) << 0) 441/* CONTROL4 */ 442# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET2(x) ((x) << 2) 443/* CONTROL5 */ 444# define PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET3(x) ((x) << 2) 445#define PACKET3_QUERY_STATUS 0xA4 446/* 1. header 447 * 2. CONTROL 448 * 3. CONTROL2 449 * 4. ADDR_LO [31:0] 450 * 5. ADDR_HI [31:0] 451 * 6. DATA_LO [31:0] 452 * 7. DATA_HI [31:0] 453 */ 454/* CONTROL */ 455# define PACKET3_QUERY_STATUS_CONTEXT_ID(x) ((x) << 0) 456# define PACKET3_QUERY_STATUS_INTERRUPT_SEL(x) ((x) << 28) 457# define PACKET3_QUERY_STATUS_COMMAND(x) ((x) << 30) 458/* CONTROL2a */ 459# define PACKET3_QUERY_STATUS_PASID(x) ((x) << 0) 460/* CONTROL2b */ 461# define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) 462# define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) 463#define PACKET3_RUN_LIST 0xA5 464#define PACKET3_MAP_PROCESS_VM 0xA6 465 466 467#endif 468