LXR linux/drivers/gpu/drm/amd/amdgpu/psp_v12

   1/*
   2 * Copyright 2019 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 */
  22
  23#include <linux/firmware.h>
  24#include <linux/module.h>
  25#include "amdgpu.h"
  26#include "amdgpu_psp.h"
  27#include "amdgpu_ucode.h"
  28#include "soc15_common.h"
  29#include "psp_v12_0.h"
  30
  31#include "mp/mp_12_0_0_offset.h"
  32#include "mp/mp_12_0_0_sh_mask.h"
  33#include "gc/gc_9_0_offset.h"
  34#include "sdma0/sdma0_4_0_offset.h"
  35#include "nbio/nbio_7_4_offset.h"
  36
  37#include "oss/osssys_4_0_offset.h"
  38#include "oss/osssys_4_0_sh_mask.h"
  39
  40MODULE_FIRMWARE("amdgpu/renoir_asd.bin");
  41MODULE_FIRMWARE("amdgpu/renoir_ta.bin");
  42MODULE_FIRMWARE("amdgpu/green_sardine_asd.bin");
  43MODULE_FIRMWARE("amdgpu/green_sardine_ta.bin");
  44
  45/* address block */
  46#define smnMP1_FIRMWARE_FLAGS           0x3010024
  47
  48static int psp_v12_0_init_microcode(struct psp_context *psp)
  49{
  50        struct amdgpu_device *adev = psp->adev;
  51        const char *chip_name;
  52        char fw_name[30];
  53        int err = 0;
  54        const struct ta_firmware_header_v1_0 *ta_hdr;
  55        DRM_DEBUG("\n");
  56
  57        switch (adev->asic_type) {
  58        case CHIP_RENOIR:
  59                if (adev->apu_flags & AMD_APU_IS_RENOIR)
  60                        chip_name = "renoir";
  61                else
  62                        chip_name = "green_sardine";
  63                break;
  64        default:
  65                BUG();
  66        }
  67
  68        err = psp_init_asd_microcode(psp, chip_name);
  69        if (err)
  70                return err;
  71
  72        snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
  73        err = request_firmware(&adev->psp.ta_fw, fw_name, adev->dev);
  74        if (err) {
  75                release_firmware(adev->psp.ta_fw);
  76                adev->psp.ta_fw = NULL;
  77                dev_info(adev->dev,
  78                         "psp v12.0: Failed to load firmware \"%s\"\n",
  79                         fw_name);
  80        } else {
  81                err = amdgpu_ucode_validate(adev->psp.ta_fw);
  82                if (err)
  83                        goto out;
  84
  85                ta_hdr = (const struct ta_firmware_header_v1_0 *)
  86                                 adev->psp.ta_fw->data;
  87                adev->psp.hdcp.feature_version =
  88                        le32_to_cpu(ta_hdr->hdcp.fw_version);
  89                adev->psp.hdcp.size_bytes =
  90                        le32_to_cpu(ta_hdr->hdcp.size_bytes);
  91                adev->psp.hdcp.start_addr =
  92                        (uint8_t *)ta_hdr +
  93                        le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
  94
  95                adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
  96
  97                adev->psp.dtm.feature_version =
  98                        le32_to_cpu(ta_hdr->dtm.fw_version);
  99                adev->psp.dtm.size_bytes =
 100                        le32_to_cpu(ta_hdr->dtm.size_bytes);
 101                adev->psp.dtm.start_addr =
 102                        (uint8_t *)adev->psp.hdcp.start_addr +
 103                        le32_to_cpu(ta_hdr->dtm.offset_bytes);
 104        }
 105
 106        return 0;
 107
 108out:
 109        release_firmware(adev->psp.ta_fw);
 110        adev->psp.ta_fw = NULL;
 111        if (err) {
 112                dev_err(adev->dev,
 113                        "psp v12.0: Failed to load firmware \"%s\"\n",
 114                        fw_name);
 115        }
 116
 117        return err;
 118}
 119
 120static int psp_v12_0_bootloader_load_sysdrv(struct psp_context *psp)
 121{
 122        int ret;
 123        uint32_t psp_gfxdrv_command_reg = 0;
 124        struct amdgpu_device *adev = psp->adev;
 125        uint32_t sol_reg;
 126
 127        /* Check sOS sign of life register to confirm sys driver and sOS
 128         * are already been loaded.
 129         */
 130        sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 131        if (sol_reg)
 132                return 0;
 133
 134        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 135        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 136                           0x80000000, 0x80000000, false);
 137        if (ret)
 138                return ret;
 139
 140        /* Copy PSP System Driver binary to memory */
 141        psp_copy_fw(psp, psp->sys.start_addr, psp->sys.size_bytes);
 142
 143        /* Provide the sys driver to bootloader */
 144        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 145               (uint32_t)(psp->fw_pri_mc_addr >> 20));
 146        psp_gfxdrv_command_reg = 1 << 16;
 147        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 148               psp_gfxdrv_command_reg);
 149
 150        /* there might be handshake issue with hardware which needs delay */
 151        mdelay(20);
 152
 153        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 154                           0x80000000, 0x80000000, false);
 155
 156        return ret;
 157}
 158
 159static int psp_v12_0_bootloader_load_sos(struct psp_context *psp)
 160{
 161        int ret;
 162        unsigned int psp_gfxdrv_command_reg = 0;
 163        struct amdgpu_device *adev = psp->adev;
 164        uint32_t sol_reg;
 165
 166        /* Check sOS sign of life register to confirm sys driver and sOS
 167         * are already been loaded.
 168         */
 169        sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
 170        if (sol_reg)
 171                return 0;
 172
 173        /* Wait for bootloader to signify that is ready having bit 31 of C2PMSG_35 set to 1 */
 174        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
 175                           0x80000000, 0x80000000, false);
 176        if (ret)
 177                return ret;
 178
 179        /* Copy Secure OS binary to PSP memory */
 180        psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
 181
 182        /* Provide the PSP secure OS to bootloader */
 183        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
 184               (uint32_t)(psp->fw_pri_mc_addr >> 20));
 185        psp_gfxdrv_command_reg = 2 << 16;
 186        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
 187               psp_gfxdrv_command_reg);
 188
 189        /* there might be handshake issue with hardware which needs delay */
 190        mdelay(20);
 191        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
 192                           RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81),
 193                           0, true);
 194
 195        return ret;
 196}
 197
 198static void psp_v12_0_reroute_ih(struct psp_context *psp)
 199{
 200        struct amdgpu_device *adev = psp->adev;
 201        uint32_t tmp;
 202
 203        /* Change IH ring for VMC */
 204        tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1244b);
 205        tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, CLIENT_TYPE, 1);
 206        tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 207
 208        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 3);
 209        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 210        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 211
 212        mdelay(20);
 213        psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 214                     0x80000000, 0x8000FFFF, false);
 215
 216        /* Change IH ring for UMC */
 217        tmp = REG_SET_FIELD(0, IH_CLIENT_CFG_DATA, CREDIT_RETURN_ADDR, 0x1216b);
 218        tmp = REG_SET_FIELD(tmp, IH_CLIENT_CFG_DATA, RING_ID, 1);
 219
 220        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, 4);
 221        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, tmp);
 222        WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, GFX_CTRL_CMD_ID_GBR_IH_SET);
 223
 224        mdelay(20);
 225        psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 226                     0x80000000, 0x8000FFFF, false);
 227}
 228
 229static int psp_v12_0_ring_init(struct psp_context *psp,
 230                              enum psp_ring_type ring_type)
 231{
 232        int ret = 0;
 233        struct psp_ring *ring;
 234        struct amdgpu_device *adev = psp->adev;
 235
 236        psp_v12_0_reroute_ih(psp);
 237
 238        ring = &psp->km_ring;
 239
 240        ring->ring_type = ring_type;
 241
 242        /* allocate 4k Page of Local Frame Buffer memory for ring */
 243        ring->ring_size = 0x1000;
 244        ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 245                                      AMDGPU_GEM_DOMAIN_VRAM,
 246                                      &adev->firmware.rbuf,
 247                                      &ring->ring_mem_mc_addr,
 248                                      (void **)&ring->ring_mem);
 249        if (ret) {
 250                ring->ring_size = 0;
 251                return ret;
 252        }
 253
 254        return 0;
 255}
 256
 257static int psp_v12_0_ring_create(struct psp_context *psp,
 258                                enum psp_ring_type ring_type)
 259{
 260        int ret = 0;
 261        unsigned int psp_ring_reg = 0;
 262        struct psp_ring *ring = &psp->km_ring;
 263        struct amdgpu_device *adev = psp->adev;
 264
 265        if (amdgpu_sriov_vf(psp->adev)) {
 266                /* Write low address of the ring to C2PMSG_102 */
 267                psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 268                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
 269                /* Write high address of the ring to C2PMSG_103 */
 270                psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 271                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
 272
 273                /* Write the ring initialization command to C2PMSG_101 */
 274                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 275                                             GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 276
 277                /* there might be handshake issue with hardware which needs delay */
 278                mdelay(20);
 279
 280                /* Wait for response flag (bit 31) in C2PMSG_101 */
 281                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 282                                   0x80000000, 0x8000FFFF, false);
 283
 284        } else {
 285                /* Write low address of the ring to C2PMSG_69 */
 286                psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 287                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
 288                /* Write high address of the ring to C2PMSG_70 */
 289                psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 290                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
 291                /* Write size of ring to C2PMSG_71 */
 292                psp_ring_reg = ring->ring_size;
 293                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
 294                /* Write the ring initialization command to C2PMSG_64 */
 295                psp_ring_reg = ring_type;
 296                psp_ring_reg = psp_ring_reg << 16;
 297                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
 298
 299                /* there might be handshake issue with hardware which needs delay */
 300                mdelay(20);
 301
 302                /* Wait for response flag (bit 31) in C2PMSG_64 */
 303                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 304                                   0x80000000, 0x8000FFFF, false);
 305        }
 306
 307        return ret;
 308}
 309
 310static int psp_v12_0_ring_stop(struct psp_context *psp,
 311                              enum psp_ring_type ring_type)
 312{
 313        int ret = 0;
 314        struct amdgpu_device *adev = psp->adev;
 315
 316        /* Write the ring destroy command*/
 317        if (amdgpu_sriov_vf(adev))
 318                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
 319                                     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 320        else
 321                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
 322                                     GFX_CTRL_CMD_ID_DESTROY_RINGS);
 323
 324        /* there might be handshake issue with hardware which needs delay */
 325        mdelay(20);
 326
 327        /* Wait for response flag (bit 31) */
 328        if (amdgpu_sriov_vf(adev))
 329                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
 330                                   0x80000000, 0x80000000, false);
 331        else
 332                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
 333                                   0x80000000, 0x80000000, false);
 334
 335        return ret;
 336}
 337
 338static int psp_v12_0_ring_destroy(struct psp_context *psp,
 339                                 enum psp_ring_type ring_type)
 340{
 341        int ret = 0;
 342        struct psp_ring *ring = &psp->km_ring;
 343        struct amdgpu_device *adev = psp->adev;
 344
 345        ret = psp_v12_0_ring_stop(psp, ring_type);
 346        if (ret)
 347                DRM_ERROR("Fail to stop psp ring\n");
 348
 349        amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 350                              &ring->ring_mem_mc_addr,
 351                              (void **)&ring->ring_mem);
 352
 353        return ret;
 354}
 355
 356static int psp_v12_0_mode1_reset(struct psp_context *psp)
 357{
 358        int ret;
 359        uint32_t offset;
 360        struct amdgpu_device *adev = psp->adev;
 361
 362        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
 363
 364        ret = psp_wait_for(psp, offset, 0x80000000, 0x8000FFFF, false);
 365
 366        if (ret) {
 367                DRM_INFO("psp is not working correctly before mode1 reset!\n");
 368                return -EINVAL;
 369        }
 370
 371        /*send the mode 1 reset command*/
 372        WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
 373
 374        msleep(500);
 375
 376        offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
 377
 378        ret = psp_wait_for(psp, offset, 0x80000000, 0x80000000, false);
 379
 380        if (ret) {
 381                DRM_INFO("psp mode 1 reset failed!\n");
 382                return -EINVAL;
 383        }
 384
 385        DRM_INFO("psp mode1 reset succeed \n");
 386
 387        return 0;
 388}
 389
 390static uint32_t psp_v12_0_ring_get_wptr(struct psp_context *psp)
 391{
 392        uint32_t data;
 393        struct amdgpu_device *adev = psp->adev;
 394
 395        if (amdgpu_sriov_vf(adev))
 396                data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
 397        else
 398                data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
 399
 400        return data;
 401}
 402
 403static void psp_v12_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 404{
 405        struct amdgpu_device *adev = psp->adev;
 406
 407        if (amdgpu_sriov_vf(adev)) {
 408                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
 409                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
 410        } else
 411                WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
 412}
 413
 414static const struct psp_funcs psp_v12_0_funcs = {
 415        .init_microcode = psp_v12_0_init_microcode,
 416        .bootloader_load_sysdrv = psp_v12_0_bootloader_load_sysdrv,
 417        .bootloader_load_sos = psp_v12_0_bootloader_load_sos,
 418        .ring_init = psp_v12_0_ring_init,
 419        .ring_create = psp_v12_0_ring_create,
 420        .ring_stop = psp_v12_0_ring_stop,
 421        .ring_destroy = psp_v12_0_ring_destroy,
 422        .mode1_reset = psp_v12_0_mode1_reset,
 423        .ring_get_wptr = psp_v12_0_ring_get_wptr,
 424        .ring_set_wptr = psp_v12_0_ring_set_wptr,
 425};
 426
 427void psp_v12_0_set_psp_funcs(struct psp_context *psp)
 428{
 429        psp->funcs = &psp_v12_0_funcs;
 430}
 431