LXR linux/drivers/gpu/drm/amd/amdgpu/psp_v13

   1/*
   2 * Copyright 2020 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#include "amdgpu.h"
  24#include "amdgpu_psp.h"
  25#include "amdgpu_ucode.h"
  26#include "soc15_common.h"
  27#include "psp_v13_0.h"
  28
  29#include "mp/mp_13_0_2_offset.h"
  30#include "mp/mp_13_0_2_sh_mask.h"
  31
  32MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
  33MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
  34MODULE_FIRMWARE("amdgpu/yellow_carp_asd.bin");
  35MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
  36MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
  37
  38/* For large FW files the time to complete can be very long */
  39#define USBC_PD_POLLING_LIMIT_S 240
  40
  41/* Read USB-PD from LFB */
  42#define GFX_CMD_USB_PD_USE_LFB 0x480
  43
  44static int psp_v13_0_init_microcode(struct psp_context *psp)
  45{
  46        struct amdgpu_device *adev = psp->adev;
  47        const char *chip_name;
  48        int err = 0;
  49
  50        switch (adev->asic_type) {
  51        case CHIP_ALDEBARAN:
  52                chip_name = "aldebaran";
  53                break;
  54        case CHIP_YELLOW_CARP:
  55                chip_name = "yellow_carp";
  56                break;
  57        default:
  58                BUG();
  59        }
  60        switch (adev->asic_type) {
  61        case CHIP_ALDEBARAN:
  62                err = psp_init_sos_microcode(psp, chip_name);
  63                if (err)
  64                        return err;
  65                err = psp_init_ta_microcode(&adev->psp, chip_name);
  66                if (err)
  67                        return err;
  68                break;
  69        case CHIP_YELLOW_CARP:
  70                err = psp_init_asd_microcode(psp, chip_name);
  71                if (err)
  72                        return err;
  73                err = psp_init_toc_microcode(psp, chip_name);
  74                if (err)
  75                        return err;
  76                err = psp_init_ta_microcode(psp, chip_name);
  77                if (err)
  78                        return err;
  79                break;
  80        default:
  81                BUG();
  82        }
  83
  84        return 0;
  85}
  86
  87static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
  88{
  89        struct amdgpu_device *adev = psp->adev;
  90        uint32_t sol_reg;
  91
  92        sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
  93
  94        return sol_reg != 0x0;
  95}
  96
  97static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
  98{
  99        struct amdgpu_device *adev = psp->adev;
 100
 101        int ret;
 102        int retry_loop;
 103
 104        for (retry_loop = 0; retry_loop < 10; retry_loop++) {
 105                /* Wait for bootloader to signify that is
 106                    ready having bit 31 of C2PMSG_35 set to 1 */
 107                ret = psp_wait_for(psp,
 108                                   SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 109                                   0x80000000,
 110                                   0x80000000,
 111                                   false);
 112
 113                if (ret == 0)
 114                        return 0;
 115        }
 116
 117        return ret;
 118}
 119
 120static int psp_v13_0_bootloader_load_component(struct psp_context       *psp,
 121                                               struct psp_bin_desc      *bin_desc,
 122                                               enum psp_bootloader_cmd  bl_cmd)
 123{
 124        int ret;
 125        uint32_t psp_gfxdrv_command_reg = 0;
 126        struct amdgpu_device *adev = psp->adev;
 127
 128        /* Check tOS sign of life register to confirm sys driver and sOS
 129         * are already been loaded.
 130         */
 131        if (psp_v13_0_is_sos_alive(psp))
 132                return 0;
 133
 134        ret = psp_v13_0_wait_for_bootloader(psp);
 135        if (ret)
 136                return ret;
 137
 138        memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 139
 140        /* Copy PSP KDB binary to memory */
 141        memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
 142
 143        /* Provide the PSP KDB to bootloader */
 144        WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 145               (uint32_t)(psp->fw_pri_mc_addr >> 20));
 146        psp_gfxdrv_command_reg = bl_cmd;
 147        WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 148               psp_gfxdrv_command_reg);
 149
 150        ret = psp_v13_0_wait_for_bootloader(psp);
 151
 152        return ret;
 153}
 154
 155static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
 156{
 157        return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
 158}
 159
 160static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
 161{
 162        return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
 163}
 164
 165static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
 166{
 167        return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
 168}
 169
 170static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
 171{
 172        return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
 173}
 174
 175static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
 176{
 177        return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
 178}
 179
 180static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
 181{
 182        int ret;
 183        unsigned int psp_gfxdrv_command_reg = 0;
 184        struct amdgpu_device *adev = psp->adev;
 185
 186        /* Check sOS sign of life register to confirm sys driver and sOS
 187         * are already been loaded.
 188         */
 189        if (psp_v13_0_is_sos_alive(psp))
 190                return 0;
 191
 192        ret = psp_v13_0_wait_for_bootloader(psp);
 193        if (ret)
 194                return ret;
 195
 196        memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 197
 198        /* Copy Secure OS binary to PSP memory */
 199        memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
 200
 201        /* Provide the PSP secure OS to bootloader */
 202        WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
 203               (uint32_t)(psp->fw_pri_mc_addr >> 20));
 204        psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
 205        WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
 206               psp_gfxdrv_command_reg);
 207
 208        /* there might be handshake issue with hardware which needs delay */
 209        mdelay(20);
 210        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
 211                           RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
 212                           0, true);
 213
 214        return ret;
 215}
 216
 217static int psp_v13_0_ring_init(struct psp_context *psp,
 218                              enum psp_ring_type ring_type)
 219{
 220        int ret = 0;
 221        struct psp_ring *ring;
 222        struct amdgpu_device *adev = psp->adev;
 223
 224        ring = &psp->km_ring;
 225
 226        ring->ring_type = ring_type;
 227
 228        /* allocate 4k Page of Local Frame Buffer memory for ring */
 229        ring->ring_size = 0x1000;
 230        ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
 231                                      AMDGPU_GEM_DOMAIN_VRAM,
 232                                      &adev->firmware.rbuf,
 233                                      &ring->ring_mem_mc_addr,
 234                                      (void **)&ring->ring_mem);
 235        if (ret) {
 236                ring->ring_size = 0;
 237                return ret;
 238        }
 239
 240        return 0;
 241}
 242
 243static int psp_v13_0_ring_stop(struct psp_context *psp,
 244                               enum psp_ring_type ring_type)
 245{
 246        int ret = 0;
 247        struct amdgpu_device *adev = psp->adev;
 248
 249        if (amdgpu_sriov_vf(adev)) {
 250                /* Write the ring destroy command*/
 251                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 252                             GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
 253                /* there might be handshake issue with hardware which needs delay */
 254                mdelay(20);
 255                /* Wait for response flag (bit 31) */
 256                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 257                                   0x80000000, 0x80000000, false);
 258        } else {
 259                /* Write the ring destroy command*/
 260                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
 261                             GFX_CTRL_CMD_ID_DESTROY_RINGS);
 262                /* there might be handshake issue with hardware which needs delay */
 263                mdelay(20);
 264                /* Wait for response flag (bit 31) */
 265                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 266                                   0x80000000, 0x80000000, false);
 267        }
 268
 269        return ret;
 270}
 271
 272static int psp_v13_0_ring_create(struct psp_context *psp,
 273                                 enum psp_ring_type ring_type)
 274{
 275        int ret = 0;
 276        unsigned int psp_ring_reg = 0;
 277        struct psp_ring *ring = &psp->km_ring;
 278        struct amdgpu_device *adev = psp->adev;
 279
 280        if (amdgpu_sriov_vf(adev)) {
 281                ret = psp_v13_0_ring_stop(psp, ring_type);
 282                if (ret) {
 283                        DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
 284                        return ret;
 285                }
 286
 287                /* Write low address of the ring to C2PMSG_102 */
 288                psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 289                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
 290                /* Write high address of the ring to C2PMSG_103 */
 291                psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 292                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
 293
 294                /* Write the ring initialization command to C2PMSG_101 */
 295                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 296                             GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
 297
 298                /* there might be handshake issue with hardware which needs delay */
 299                mdelay(20);
 300
 301                /* Wait for response flag (bit 31) in C2PMSG_101 */
 302                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
 303                                   0x80000000, 0x8000FFFF, false);
 304
 305        } else {
 306                /* Wait for sOS ready for ring creation */
 307                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 308                                   0x80000000, 0x80000000, false);
 309                if (ret) {
 310                        DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
 311                        return ret;
 312                }
 313
 314                /* Write low address of the ring to C2PMSG_69 */
 315                psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
 316                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
 317                /* Write high address of the ring to C2PMSG_70 */
 318                psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
 319                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
 320                /* Write size of ring to C2PMSG_71 */
 321                psp_ring_reg = ring->ring_size;
 322                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
 323                /* Write the ring initialization command to C2PMSG_64 */
 324                psp_ring_reg = ring_type;
 325                psp_ring_reg = psp_ring_reg << 16;
 326                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
 327
 328                /* there might be handshake issue with hardware which needs delay */
 329                mdelay(20);
 330
 331                /* Wait for response flag (bit 31) in C2PMSG_64 */
 332                ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
 333                                   0x80000000, 0x8000FFFF, false);
 334        }
 335
 336        return ret;
 337}
 338
 339static int psp_v13_0_ring_destroy(struct psp_context *psp,
 340                                  enum psp_ring_type ring_type)
 341{
 342        int ret = 0;
 343        struct psp_ring *ring = &psp->km_ring;
 344        struct amdgpu_device *adev = psp->adev;
 345
 346        ret = psp_v13_0_ring_stop(psp, ring_type);
 347        if (ret)
 348                DRM_ERROR("Fail to stop psp ring\n");
 349
 350        amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 351                              &ring->ring_mem_mc_addr,
 352                              (void **)&ring->ring_mem);
 353
 354        return ret;
 355}
 356
 357static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
 358{
 359        uint32_t data;
 360        struct amdgpu_device *adev = psp->adev;
 361
 362        if (amdgpu_sriov_vf(adev))
 363                data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
 364        else
 365                data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
 366
 367        return data;
 368}
 369
 370static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
 371{
 372        struct amdgpu_device *adev = psp->adev;
 373
 374        if (amdgpu_sriov_vf(adev)) {
 375                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
 376                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
 377                             GFX_CTRL_CMD_ID_CONSUME_CMD);
 378        } else
 379                WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
 380}
 381
 382static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
 383{
 384        struct amdgpu_device *adev = psp->adev;
 385        uint32_t reg_status;
 386        int ret, i = 0;
 387
 388        /*
 389         * LFB address which is aligned to 1MB address and has to be
 390         * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
 391         * register
 392         */
 393        WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
 394
 395        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 396                             0x80000000, 0x80000000, false);
 397        if (ret)
 398                return ret;
 399
 400        /* Fireup interrupt so PSP can pick up the address */
 401        WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
 402
 403        /* FW load takes very long time */
 404        do {
 405                msleep(1000);
 406                reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
 407
 408                if (reg_status & 0x80000000)
 409                        goto done;
 410
 411        } while (++i < USBC_PD_POLLING_LIMIT_S);
 412
 413        return -ETIME;
 414done:
 415
 416        if ((reg_status & 0xFFFF) != 0) {
 417                DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
 418                                reg_status & 0xFFFF);
 419                return -EIO;
 420        }
 421
 422        return 0;
 423}
 424
 425static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
 426{
 427        struct amdgpu_device *adev = psp->adev;
 428        int ret;
 429
 430        WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
 431
 432        ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
 433                                     0x80000000, 0x80000000, false);
 434        if (!ret)
 435                *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
 436
 437        return ret;
 438}
 439
 440static const struct psp_funcs psp_v13_0_funcs = {
 441        .init_microcode = psp_v13_0_init_microcode,
 442        .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
 443        .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
 444        .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
 445        .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
 446        .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
 447        .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
 448        .ring_init = psp_v13_0_ring_init,
 449        .ring_create = psp_v13_0_ring_create,
 450        .ring_stop = psp_v13_0_ring_stop,
 451        .ring_destroy = psp_v13_0_ring_destroy,
 452        .ring_get_wptr = psp_v13_0_ring_get_wptr,
 453        .ring_set_wptr = psp_v13_0_ring_set_wptr,
 454        .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
 455        .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw
 456};
 457
 458void psp_v13_0_set_psp_funcs(struct psp_context *psp)
 459{
 460        psp->funcs = &psp_v13_0_funcs;
 461}
 462