LXR linux/drivers/gpu/drm/amd/amdgpu/smuio_v9

   1/*
   2 * Copyright 2020 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#include "amdgpu.h"
  24#include "smuio_v9_0.h"
  25#include "smuio/smuio_9_0_offset.h"
  26#include "smuio/smuio_9_0_sh_mask.h"
  27
  28static u32 smuio_v9_0_get_rom_index_offset(struct amdgpu_device *adev)
  29{
  30        return SOC15_REG_OFFSET(SMUIO, 0, mmROM_INDEX);
  31}
  32
  33static u32 smuio_v9_0_get_rom_data_offset(struct amdgpu_device *adev)
  34{
  35        return SOC15_REG_OFFSET(SMUIO, 0, mmROM_DATA);
  36}
  37
  38static void smuio_v9_0_update_rom_clock_gating(struct amdgpu_device *adev, bool enable)
  39{
  40        u32 def, data;
  41
  42        /* enable/disable ROM CG is not supported on APU */
  43        if (adev->flags & AMD_IS_APU)
  44                return;
  45
  46        def = data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
  47
  48        if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG))
  49                data &= ~(CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
  50                        CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK);
  51        else
  52                data |= CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK |
  53                        CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE1_MASK;
  54
  55        if (def != data)
  56                WREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0, data);
  57}
  58
  59static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u32 *flags)
  60{
  61        u32 data;
  62
  63        /* CGTT_ROM_CLK_CTRL0 is not availabe for APUs */
  64        if (adev->flags & AMD_IS_APU)
  65                return;
  66
  67        data = RREG32_SOC15(SMUIO, 0, mmCGTT_ROM_CLK_CTRL0);
  68        if (!(data & CGTT_ROM_CLK_CTRL0__SOFT_OVERRIDE0_MASK))
  69                *flags |= AMD_CG_SUPPORT_ROM_MGCG;
  70}
  71
  72const struct amdgpu_smuio_funcs smuio_v9_0_funcs = {
  73        .get_rom_index_offset = smuio_v9_0_get_rom_index_offset,
  74        .get_rom_data_offset = smuio_v9_0_get_rom_data_offset,
  75        .update_rom_clock_gating = smuio_v9_0_update_rom_clock_gating,
  76        .get_clock_gating_state = smuio_v9_0_get_clock_gating_state,
  77};
  78