linux/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
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   1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26/* The caprices of the preprocessor require that this be declared right here */
  27#define CREATE_TRACE_POINTS
  28
  29#include "dm_services_types.h"
  30#include "dc.h"
  31#include "dc/inc/core_types.h"
  32#include "dal_asic_id.h"
  33
  34#include "vid.h"
  35#include "amdgpu.h"
  36#include "amdgpu_display.h"
  37#include "amdgpu_ucode.h"
  38#include "atom.h"
  39#include "amdgpu_dm.h"
  40#include "amdgpu_pm.h"
  41
  42#include "amd_shared.h"
  43#include "amdgpu_dm_irq.h"
  44#include "dm_helpers.h"
  45#include "amdgpu_dm_mst_types.h"
  46#if defined(CONFIG_DEBUG_FS)
  47#include "amdgpu_dm_debugfs.h"
  48#endif
  49
  50#include "ivsrcid/ivsrcid_vislands30.h"
  51
  52#include <linux/module.h>
  53#include <linux/moduleparam.h>
  54#include <linux/version.h>
  55#include <linux/types.h>
  56#include <linux/pm_runtime.h>
  57#include <linux/pci.h>
  58#include <linux/firmware.h>
  59#include <linux/component.h>
  60
  61#include <drm/drm_atomic.h>
  62#include <drm/drm_atomic_uapi.h>
  63#include <drm/drm_atomic_helper.h>
  64#include <drm/drm_dp_mst_helper.h>
  65#include <drm/drm_fb_helper.h>
  66#include <drm/drm_fourcc.h>
  67#include <drm/drm_edid.h>
  68#include <drm/drm_vblank.h>
  69#include <drm/drm_audio_component.h>
  70
  71#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
  72#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
  73
  74#include "dcn/dcn_1_0_offset.h"
  75#include "dcn/dcn_1_0_sh_mask.h"
  76#include "soc15_hw_ip.h"
  77#include "vega10_ip_offset.h"
  78
  79#include "soc15_common.h"
  80#endif
  81
  82#include "modules/inc/mod_freesync.h"
  83#include "modules/power/power_helpers.h"
  84#include "modules/inc/mod_info_packet.h"
  85
  86#define FIRMWARE_RAVEN_DMCU             "amdgpu/raven_dmcu.bin"
  87MODULE_FIRMWARE(FIRMWARE_RAVEN_DMCU);
  88
  89/**
  90 * DOC: overview
  91 *
  92 * The AMDgpu display manager, **amdgpu_dm** (or even simpler,
  93 * **dm**) sits between DRM and DC. It acts as a liason, converting DRM
  94 * requests into DC requests, and DC responses into DRM responses.
  95 *
  96 * The root control structure is &struct amdgpu_display_manager.
  97 */
  98
  99/* basic init/fini API */
 100static int amdgpu_dm_init(struct amdgpu_device *adev);
 101static void amdgpu_dm_fini(struct amdgpu_device *adev);
 102
 103/*
 104 * initializes drm_device display related structures, based on the information
 105 * provided by DAL. The drm strcutures are: drm_crtc, drm_connector,
 106 * drm_encoder, drm_mode_config
 107 *
 108 * Returns 0 on success
 109 */
 110static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev);
 111/* removes and deallocates the drm structures, created by the above function */
 112static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm);
 113
 114static void
 115amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector);
 116
 117static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
 118                                struct drm_plane *plane,
 119                                unsigned long possible_crtcs,
 120                                const struct dc_plane_cap *plane_cap);
 121static int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
 122                               struct drm_plane *plane,
 123                               uint32_t link_index);
 124static int amdgpu_dm_connector_init(struct amdgpu_display_manager *dm,
 125                                    struct amdgpu_dm_connector *amdgpu_dm_connector,
 126                                    uint32_t link_index,
 127                                    struct amdgpu_encoder *amdgpu_encoder);
 128static int amdgpu_dm_encoder_init(struct drm_device *dev,
 129                                  struct amdgpu_encoder *aencoder,
 130                                  uint32_t link_index);
 131
 132static int amdgpu_dm_connector_get_modes(struct drm_connector *connector);
 133
 134static int amdgpu_dm_atomic_commit(struct drm_device *dev,
 135                                   struct drm_atomic_state *state,
 136                                   bool nonblock);
 137
 138static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state);
 139
 140static int amdgpu_dm_atomic_check(struct drm_device *dev,
 141                                  struct drm_atomic_state *state);
 142
 143static void handle_cursor_update(struct drm_plane *plane,
 144                                 struct drm_plane_state *old_plane_state);
 145
 146/*
 147 * dm_vblank_get_counter
 148 *
 149 * @brief
 150 * Get counter for number of vertical blanks
 151 *
 152 * @param
 153 * struct amdgpu_device *adev - [in] desired amdgpu device
 154 * int disp_idx - [in] which CRTC to get the counter from
 155 *
 156 * @return
 157 * Counter for vertical blanks
 158 */
 159static u32 dm_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 160{
 161        if (crtc >= adev->mode_info.num_crtc)
 162                return 0;
 163        else {
 164                struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 165                struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 166                                acrtc->base.state);
 167
 168
 169                if (acrtc_state->stream == NULL) {
 170                        DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 171                                  crtc);
 172                        return 0;
 173                }
 174
 175                return dc_stream_get_vblank_counter(acrtc_state->stream);
 176        }
 177}
 178
 179static int dm_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
 180                                  u32 *vbl, u32 *position)
 181{
 182        uint32_t v_blank_start, v_blank_end, h_position, v_position;
 183
 184        if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
 185                return -EINVAL;
 186        else {
 187                struct amdgpu_crtc *acrtc = adev->mode_info.crtcs[crtc];
 188                struct dm_crtc_state *acrtc_state = to_dm_crtc_state(
 189                                                acrtc->base.state);
 190
 191                if (acrtc_state->stream ==  NULL) {
 192                        DRM_ERROR("dc_stream_state is NULL for crtc '%d'!\n",
 193                                  crtc);
 194                        return 0;
 195                }
 196
 197                /*
 198                 * TODO rework base driver to use values directly.
 199                 * for now parse it back into reg-format
 200                 */
 201                dc_stream_get_scanoutpos(acrtc_state->stream,
 202                                         &v_blank_start,
 203                                         &v_blank_end,
 204                                         &h_position,
 205                                         &v_position);
 206
 207                *position = v_position | (h_position << 16);
 208                *vbl = v_blank_start | (v_blank_end << 16);
 209        }
 210
 211        return 0;
 212}
 213
 214static bool dm_is_idle(void *handle)
 215{
 216        /* XXX todo */
 217        return true;
 218}
 219
 220static int dm_wait_for_idle(void *handle)
 221{
 222        /* XXX todo */
 223        return 0;
 224}
 225
 226static bool dm_check_soft_reset(void *handle)
 227{
 228        return false;
 229}
 230
 231static int dm_soft_reset(void *handle)
 232{
 233        /* XXX todo */
 234        return 0;
 235}
 236
 237static struct amdgpu_crtc *
 238get_crtc_by_otg_inst(struct amdgpu_device *adev,
 239                     int otg_inst)
 240{
 241        struct drm_device *dev = adev->ddev;
 242        struct drm_crtc *crtc;
 243        struct amdgpu_crtc *amdgpu_crtc;
 244
 245        if (otg_inst == -1) {
 246                WARN_ON(1);
 247                return adev->mode_info.crtcs[0];
 248        }
 249
 250        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
 251                amdgpu_crtc = to_amdgpu_crtc(crtc);
 252
 253                if (amdgpu_crtc->otg_inst == otg_inst)
 254                        return amdgpu_crtc;
 255        }
 256
 257        return NULL;
 258}
 259
 260static inline bool amdgpu_dm_vrr_active(struct dm_crtc_state *dm_state)
 261{
 262        return dm_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE ||
 263               dm_state->freesync_config.state == VRR_STATE_ACTIVE_FIXED;
 264}
 265
 266static void dm_pflip_high_irq(void *interrupt_params)
 267{
 268        struct amdgpu_crtc *amdgpu_crtc;
 269        struct common_irq_params *irq_params = interrupt_params;
 270        struct amdgpu_device *adev = irq_params->adev;
 271        unsigned long flags;
 272        struct drm_pending_vblank_event *e;
 273        struct dm_crtc_state *acrtc_state;
 274        uint32_t vpos, hpos, v_blank_start, v_blank_end;
 275        bool vrr_active;
 276
 277        amdgpu_crtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_PFLIP);
 278
 279        /* IRQ could occur when in initial stage */
 280        /* TODO work and BO cleanup */
 281        if (amdgpu_crtc == NULL) {
 282                DRM_DEBUG_DRIVER("CRTC is null, returning.\n");
 283                return;
 284        }
 285
 286        spin_lock_irqsave(&adev->ddev->event_lock, flags);
 287
 288        if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
 289                DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d !=AMDGPU_FLIP_SUBMITTED(%d) on crtc:%d[%p] \n",
 290                                                 amdgpu_crtc->pflip_status,
 291                                                 AMDGPU_FLIP_SUBMITTED,
 292                                                 amdgpu_crtc->crtc_id,
 293                                                 amdgpu_crtc);
 294                spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 295                return;
 296        }
 297
 298        /* page flip completed. */
 299        e = amdgpu_crtc->event;
 300        amdgpu_crtc->event = NULL;
 301
 302        if (!e)
 303                WARN_ON(1);
 304
 305        acrtc_state = to_dm_crtc_state(amdgpu_crtc->base.state);
 306        vrr_active = amdgpu_dm_vrr_active(acrtc_state);
 307
 308        /* Fixed refresh rate, or VRR scanout position outside front-porch? */
 309        if (!vrr_active ||
 310            !dc_stream_get_scanoutpos(acrtc_state->stream, &v_blank_start,
 311                                      &v_blank_end, &hpos, &vpos) ||
 312            (vpos < v_blank_start)) {
 313                /* Update to correct count and vblank timestamp if racing with
 314                 * vblank irq. This also updates to the correct vblank timestamp
 315                 * even in VRR mode, as scanout is past the front-porch atm.
 316                 */
 317                drm_crtc_accurate_vblank_count(&amdgpu_crtc->base);
 318
 319                /* Wake up userspace by sending the pageflip event with proper
 320                 * count and timestamp of vblank of flip completion.
 321                 */
 322                if (e) {
 323                        drm_crtc_send_vblank_event(&amdgpu_crtc->base, e);
 324
 325                        /* Event sent, so done with vblank for this flip */
 326                        drm_crtc_vblank_put(&amdgpu_crtc->base);
 327                }
 328        } else if (e) {
 329                /* VRR active and inside front-porch: vblank count and
 330                 * timestamp for pageflip event will only be up to date after
 331                 * drm_crtc_handle_vblank() has been executed from late vblank
 332                 * irq handler after start of back-porch (vline 0). We queue the
 333                 * pageflip event for send-out by drm_crtc_handle_vblank() with
 334                 * updated timestamp and count, once it runs after us.
 335                 *
 336                 * We need to open-code this instead of using the helper
 337                 * drm_crtc_arm_vblank_event(), as that helper would
 338                 * call drm_crtc_accurate_vblank_count(), which we must
 339                 * not call in VRR mode while we are in front-porch!
 340                 */
 341
 342                /* sequence will be replaced by real count during send-out. */
 343                e->sequence = drm_crtc_vblank_count(&amdgpu_crtc->base);
 344                e->pipe = amdgpu_crtc->crtc_id;
 345
 346                list_add_tail(&e->base.link, &adev->ddev->vblank_event_list);
 347                e = NULL;
 348        }
 349
 350        /* Keep track of vblank of this flip for flip throttling. We use the
 351         * cooked hw counter, as that one incremented at start of this vblank
 352         * of pageflip completion, so last_flip_vblank is the forbidden count
 353         * for queueing new pageflips if vsync + VRR is enabled.
 354         */
 355        amdgpu_crtc->last_flip_vblank = amdgpu_get_vblank_counter_kms(adev->ddev,
 356                                                        amdgpu_crtc->crtc_id);
 357
 358        amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
 359        spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 360
 361        DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_NONE, vrr[%d]-fp %d\n",
 362                         amdgpu_crtc->crtc_id, amdgpu_crtc,
 363                         vrr_active, (int) !e);
 364}
 365
 366static void dm_vupdate_high_irq(void *interrupt_params)
 367{
 368        struct common_irq_params *irq_params = interrupt_params;
 369        struct amdgpu_device *adev = irq_params->adev;
 370        struct amdgpu_crtc *acrtc;
 371        struct dm_crtc_state *acrtc_state;
 372        unsigned long flags;
 373
 374        acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VUPDATE);
 375
 376        if (acrtc) {
 377                acrtc_state = to_dm_crtc_state(acrtc->base.state);
 378
 379                DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 380                                 amdgpu_dm_vrr_active(acrtc_state));
 381
 382                /* Core vblank handling is done here after end of front-porch in
 383                 * vrr mode, as vblank timestamping will give valid results
 384                 * while now done after front-porch. This will also deliver
 385                 * page-flip completion events that have been queued to us
 386                 * if a pageflip happened inside front-porch.
 387                 */
 388                if (amdgpu_dm_vrr_active(acrtc_state)) {
 389                        drm_crtc_handle_vblank(&acrtc->base);
 390
 391                        /* BTR processing for pre-DCE12 ASICs */
 392                        if (acrtc_state->stream &&
 393                            adev->family < AMDGPU_FAMILY_AI) {
 394                                spin_lock_irqsave(&adev->ddev->event_lock, flags);
 395                                mod_freesync_handle_v_update(
 396                                    adev->dm.freesync_module,
 397                                    acrtc_state->stream,
 398                                    &acrtc_state->vrr_params);
 399
 400                                dc_stream_adjust_vmin_vmax(
 401                                    adev->dm.dc,
 402                                    acrtc_state->stream,
 403                                    &acrtc_state->vrr_params.adjust);
 404                                spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 405                        }
 406                }
 407        }
 408}
 409
 410static void dm_crtc_high_irq(void *interrupt_params)
 411{
 412        struct common_irq_params *irq_params = interrupt_params;
 413        struct amdgpu_device *adev = irq_params->adev;
 414        struct amdgpu_crtc *acrtc;
 415        struct dm_crtc_state *acrtc_state;
 416        unsigned long flags;
 417
 418        acrtc = get_crtc_by_otg_inst(adev, irq_params->irq_src - IRQ_TYPE_VBLANK);
 419
 420        if (acrtc) {
 421                acrtc_state = to_dm_crtc_state(acrtc->base.state);
 422
 423                DRM_DEBUG_DRIVER("crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id,
 424                                 amdgpu_dm_vrr_active(acrtc_state));
 425
 426                /* Core vblank handling at start of front-porch is only possible
 427                 * in non-vrr mode, as only there vblank timestamping will give
 428                 * valid results while done in front-porch. Otherwise defer it
 429                 * to dm_vupdate_high_irq after end of front-porch.
 430                 */
 431                if (!amdgpu_dm_vrr_active(acrtc_state))
 432                        drm_crtc_handle_vblank(&acrtc->base);
 433
 434                /* Following stuff must happen at start of vblank, for crc
 435                 * computation and below-the-range btr support in vrr mode.
 436                 */
 437                amdgpu_dm_crtc_handle_crc_irq(&acrtc->base);
 438
 439                if (acrtc_state->stream && adev->family >= AMDGPU_FAMILY_AI &&
 440                    acrtc_state->vrr_params.supported &&
 441                    acrtc_state->freesync_config.state == VRR_STATE_ACTIVE_VARIABLE) {
 442                        spin_lock_irqsave(&adev->ddev->event_lock, flags);
 443                        mod_freesync_handle_v_update(
 444                                adev->dm.freesync_module,
 445                                acrtc_state->stream,
 446                                &acrtc_state->vrr_params);
 447
 448                        dc_stream_adjust_vmin_vmax(
 449                                adev->dm.dc,
 450                                acrtc_state->stream,
 451                                &acrtc_state->vrr_params.adjust);
 452                        spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
 453                }
 454        }
 455}
 456
 457static int dm_set_clockgating_state(void *handle,
 458                  enum amd_clockgating_state state)
 459{
 460        return 0;
 461}
 462
 463static int dm_set_powergating_state(void *handle,
 464                  enum amd_powergating_state state)
 465{
 466        return 0;
 467}
 468
 469/* Prototypes of private functions */
 470static int dm_early_init(void* handle);
 471
 472/* Allocate memory for FBC compressed data  */
 473static void amdgpu_dm_fbc_init(struct drm_connector *connector)
 474{
 475        struct drm_device *dev = connector->dev;
 476        struct amdgpu_device *adev = dev->dev_private;
 477        struct dm_comressor_info *compressor = &adev->dm.compressor;
 478        struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector);
 479        struct drm_display_mode *mode;
 480        unsigned long max_size = 0;
 481
 482        if (adev->dm.dc->fbc_compressor == NULL)
 483                return;
 484
 485        if (aconn->dc_link->connector_signal != SIGNAL_TYPE_EDP)
 486                return;
 487
 488        if (compressor->bo_ptr)
 489                return;
 490
 491
 492        list_for_each_entry(mode, &connector->modes, head) {
 493                if (max_size < mode->htotal * mode->vtotal)
 494                        max_size = mode->htotal * mode->vtotal;
 495        }
 496
 497        if (max_size) {
 498                int r = amdgpu_bo_create_kernel(adev, max_size * 4, PAGE_SIZE,
 499                            AMDGPU_GEM_DOMAIN_GTT, &compressor->bo_ptr,
 500                            &compressor->gpu_addr, &compressor->cpu_addr);
 501
 502                if (r)
 503                        DRM_ERROR("DM: Failed to initialize FBC\n");
 504                else {
 505                        adev->dm.dc->ctx->fbc_gpu_addr = compressor->gpu_addr;
 506                        DRM_INFO("DM: FBC alloc %lu\n", max_size*4);
 507                }
 508
 509        }
 510
 511}
 512
 513static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port,
 514                                          int pipe, bool *enabled,
 515                                          unsigned char *buf, int max_bytes)
 516{
 517        struct drm_device *dev = dev_get_drvdata(kdev);
 518        struct amdgpu_device *adev = dev->dev_private;
 519        struct drm_connector *connector;
 520        struct drm_connector_list_iter conn_iter;
 521        struct amdgpu_dm_connector *aconnector;
 522        int ret = 0;
 523
 524        *enabled = false;
 525
 526        mutex_lock(&adev->dm.audio_lock);
 527
 528        drm_connector_list_iter_begin(dev, &conn_iter);
 529        drm_for_each_connector_iter(connector, &conn_iter) {
 530                aconnector = to_amdgpu_dm_connector(connector);
 531                if (aconnector->audio_inst != port)
 532                        continue;
 533
 534                *enabled = true;
 535                ret = drm_eld_size(connector->eld);
 536                memcpy(buf, connector->eld, min(max_bytes, ret));
 537
 538                break;
 539        }
 540        drm_connector_list_iter_end(&conn_iter);
 541
 542        mutex_unlock(&adev->dm.audio_lock);
 543
 544        DRM_DEBUG_KMS("Get ELD : idx=%d ret=%d en=%d\n", port, ret, *enabled);
 545
 546        return ret;
 547}
 548
 549static const struct drm_audio_component_ops amdgpu_dm_audio_component_ops = {
 550        .get_eld = amdgpu_dm_audio_component_get_eld,
 551};
 552
 553static int amdgpu_dm_audio_component_bind(struct device *kdev,
 554                                       struct device *hda_kdev, void *data)
 555{
 556        struct drm_device *dev = dev_get_drvdata(kdev);
 557        struct amdgpu_device *adev = dev->dev_private;
 558        struct drm_audio_component *acomp = data;
 559
 560        acomp->ops = &amdgpu_dm_audio_component_ops;
 561        acomp->dev = kdev;
 562        adev->dm.audio_component = acomp;
 563
 564        return 0;
 565}
 566
 567static void amdgpu_dm_audio_component_unbind(struct device *kdev,
 568                                          struct device *hda_kdev, void *data)
 569{
 570        struct drm_device *dev = dev_get_drvdata(kdev);
 571        struct amdgpu_device *adev = dev->dev_private;
 572        struct drm_audio_component *acomp = data;
 573
 574        acomp->ops = NULL;
 575        acomp->dev = NULL;
 576        adev->dm.audio_component = NULL;
 577}
 578
 579static const struct component_ops amdgpu_dm_audio_component_bind_ops = {
 580        .bind   = amdgpu_dm_audio_component_bind,
 581        .unbind = amdgpu_dm_audio_component_unbind,
 582};
 583
 584static int amdgpu_dm_audio_init(struct amdgpu_device *adev)
 585{
 586        int i, ret;
 587
 588        if (!amdgpu_audio)
 589                return 0;
 590
 591        adev->mode_info.audio.enabled = true;
 592
 593        adev->mode_info.audio.num_pins = adev->dm.dc->res_pool->audio_count;
 594
 595        for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
 596                adev->mode_info.audio.pin[i].channels = -1;
 597                adev->mode_info.audio.pin[i].rate = -1;
 598                adev->mode_info.audio.pin[i].bits_per_sample = -1;
 599                adev->mode_info.audio.pin[i].status_bits = 0;
 600                adev->mode_info.audio.pin[i].category_code = 0;
 601                adev->mode_info.audio.pin[i].connected = false;
 602                adev->mode_info.audio.pin[i].id =
 603                        adev->dm.dc->res_pool->audios[i]->inst;
 604                adev->mode_info.audio.pin[i].offset = 0;
 605        }
 606
 607        ret = component_add(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 608        if (ret < 0)
 609                return ret;
 610
 611        adev->dm.audio_registered = true;
 612
 613        return 0;
 614}
 615
 616static void amdgpu_dm_audio_fini(struct amdgpu_device *adev)
 617{
 618        if (!amdgpu_audio)
 619                return;
 620
 621        if (!adev->mode_info.audio.enabled)
 622                return;
 623
 624        if (adev->dm.audio_registered) {
 625                component_del(adev->dev, &amdgpu_dm_audio_component_bind_ops);
 626                adev->dm.audio_registered = false;
 627        }
 628
 629        /* TODO: Disable audio? */
 630
 631        adev->mode_info.audio.enabled = false;
 632}
 633
 634void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin)
 635{
 636        struct drm_audio_component *acomp = adev->dm.audio_component;
 637
 638        if (acomp && acomp->audio_ops && acomp->audio_ops->pin_eld_notify) {
 639                DRM_DEBUG_KMS("Notify ELD: %d\n", pin);
 640
 641                acomp->audio_ops->pin_eld_notify(acomp->audio_ops->audio_ptr,
 642                                                 pin, -1);
 643        }
 644}
 645
 646static int amdgpu_dm_init(struct amdgpu_device *adev)
 647{
 648        struct dc_init_data init_data;
 649        adev->dm.ddev = adev->ddev;
 650        adev->dm.adev = adev;
 651
 652        /* Zero all the fields */
 653        memset(&init_data, 0, sizeof(init_data));
 654
 655        mutex_init(&adev->dm.dc_lock);
 656        mutex_init(&adev->dm.audio_lock);
 657
 658        if(amdgpu_dm_irq_init(adev)) {
 659                DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n");
 660                goto error;
 661        }
 662
 663        init_data.asic_id.chip_family = adev->family;
 664
 665        init_data.asic_id.pci_revision_id = adev->rev_id;
 666        init_data.asic_id.hw_internal_rev = adev->external_rev_id;
 667
 668        init_data.asic_id.vram_width = adev->gmc.vram_width;
 669        /* TODO: initialize init_data.asic_id.vram_type here!!!! */
 670        init_data.asic_id.atombios_base_address =
 671                adev->mode_info.atom_context->bios;
 672
 673        init_data.driver = adev;
 674
 675        adev->dm.cgs_device = amdgpu_cgs_create_device(adev);
 676
 677        if (!adev->dm.cgs_device) {
 678                DRM_ERROR("amdgpu: failed to create cgs device.\n");
 679                goto error;
 680        }
 681
 682        init_data.cgs_device = adev->dm.cgs_device;
 683
 684        init_data.dce_environment = DCE_ENV_PRODUCTION_DRV;
 685
 686        /*
 687         * TODO debug why this doesn't work on Raven
 688         */
 689        if (adev->flags & AMD_IS_APU &&
 690            adev->asic_type >= CHIP_CARRIZO &&
 691            adev->asic_type < CHIP_RAVEN)
 692                init_data.flags.gpu_vm_support = true;
 693
 694        if (amdgpu_dc_feature_mask & DC_FBC_MASK)
 695                init_data.flags.fbc_support = true;
 696
 697        if (amdgpu_dc_feature_mask & DC_MULTI_MON_PP_MCLK_SWITCH_MASK)
 698                init_data.flags.multi_mon_pp_mclk_switch = true;
 699
 700        init_data.flags.power_down_display_on_boot = true;
 701
 702#ifdef CONFIG_DRM_AMD_DC_DCN2_0
 703        init_data.soc_bounding_box = adev->dm.soc_bounding_box;
 704#endif
 705
 706        /* Display Core create. */
 707        adev->dm.dc = dc_create(&init_data);
 708
 709        if (adev->dm.dc) {
 710                DRM_INFO("Display Core initialized with v%s!\n", DC_VER);
 711        } else {
 712                DRM_INFO("Display Core failed to initialize with v%s!\n", DC_VER);
 713                goto error;
 714        }
 715
 716        adev->dm.freesync_module = mod_freesync_create(adev->dm.dc);
 717        if (!adev->dm.freesync_module) {
 718                DRM_ERROR(
 719                "amdgpu: failed to initialize freesync_module.\n");
 720        } else
 721                DRM_DEBUG_DRIVER("amdgpu: freesync_module init done %p.\n",
 722                                adev->dm.freesync_module);
 723
 724        amdgpu_dm_init_color_mod();
 725
 726        if (amdgpu_dm_initialize_drm_device(adev)) {
 727                DRM_ERROR(
 728                "amdgpu: failed to initialize sw for display support.\n");
 729                goto error;
 730        }
 731
 732        /* Update the actual used number of crtc */
 733        adev->mode_info.num_crtc = adev->dm.display_indexes_num;
 734
 735        /* TODO: Add_display_info? */
 736
 737        /* TODO use dynamic cursor width */
 738        adev->ddev->mode_config.cursor_width = adev->dm.dc->caps.max_cursor_size;
 739        adev->ddev->mode_config.cursor_height = adev->dm.dc->caps.max_cursor_size;
 740
 741        if (drm_vblank_init(adev->ddev, adev->dm.display_indexes_num)) {
 742                DRM_ERROR(
 743                "amdgpu: failed to initialize sw for display support.\n");
 744                goto error;
 745        }
 746
 747#if defined(CONFIG_DEBUG_FS)
 748        if (dtn_debugfs_init(adev))
 749                DRM_ERROR("amdgpu: failed initialize dtn debugfs support.\n");
 750#endif
 751
 752        DRM_DEBUG_DRIVER("KMS initialized.\n");
 753
 754        return 0;
 755error:
 756        amdgpu_dm_fini(adev);
 757
 758        return -EINVAL;
 759}
 760
 761static void amdgpu_dm_fini(struct amdgpu_device *adev)
 762{
 763        amdgpu_dm_audio_fini(adev);
 764
 765        amdgpu_dm_destroy_drm_device(&adev->dm);
 766
 767        /* DC Destroy TODO: Replace destroy DAL */
 768        if (adev->dm.dc)
 769                dc_destroy(&adev->dm.dc);
 770        /*
 771         * TODO: pageflip, vlank interrupt
 772         *
 773         * amdgpu_dm_irq_fini(adev);
 774         */
 775
 776        if (adev->dm.cgs_device) {
 777                amdgpu_cgs_destroy_device(adev->dm.cgs_device);
 778                adev->dm.cgs_device = NULL;
 779        }
 780        if (adev->dm.freesync_module) {
 781                mod_freesync_destroy(adev->dm.freesync_module);
 782                adev->dm.freesync_module = NULL;
 783        }
 784
 785        mutex_destroy(&adev->dm.audio_lock);
 786        mutex_destroy(&adev->dm.dc_lock);
 787
 788        return;
 789}
 790
 791static int load_dmcu_fw(struct amdgpu_device *adev)
 792{
 793        const char *fw_name_dmcu = NULL;
 794        int r;
 795        const struct dmcu_firmware_header_v1_0 *hdr;
 796
 797        switch(adev->asic_type) {
 798        case CHIP_BONAIRE:
 799        case CHIP_HAWAII:
 800        case CHIP_KAVERI:
 801        case CHIP_KABINI:
 802        case CHIP_MULLINS:
 803        case CHIP_TONGA:
 804        case CHIP_FIJI:
 805        case CHIP_CARRIZO:
 806        case CHIP_STONEY:
 807        case CHIP_POLARIS11:
 808        case CHIP_POLARIS10:
 809        case CHIP_POLARIS12:
 810        case CHIP_VEGAM:
 811        case CHIP_VEGA10:
 812        case CHIP_VEGA12:
 813        case CHIP_VEGA20:
 814        case CHIP_NAVI10:
 815        case CHIP_NAVI14:
 816        case CHIP_NAVI12:
 817        case CHIP_RENOIR:
 818                return 0;
 819        case CHIP_RAVEN:
 820                if (ASICREV_IS_PICASSO(adev->external_rev_id))
 821                        fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 822                else if (ASICREV_IS_RAVEN2(adev->external_rev_id))
 823                        fw_name_dmcu = FIRMWARE_RAVEN_DMCU;
 824                else
 825                        return 0;
 826                break;
 827        default:
 828                DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
 829                return -EINVAL;
 830        }
 831
 832        if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 833                DRM_DEBUG_KMS("dm: DMCU firmware not supported on direct or SMU loading\n");
 834                return 0;
 835        }
 836
 837        r = request_firmware_direct(&adev->dm.fw_dmcu, fw_name_dmcu, adev->dev);
 838        if (r == -ENOENT) {
 839                /* DMCU firmware is not necessary, so don't raise a fuss if it's missing */
 840                DRM_DEBUG_KMS("dm: DMCU firmware not found\n");
 841                adev->dm.fw_dmcu = NULL;
 842                return 0;
 843        }
 844        if (r) {
 845                dev_err(adev->dev, "amdgpu_dm: Can't load firmware \"%s\"\n",
 846                        fw_name_dmcu);
 847                return r;
 848        }
 849
 850        r = amdgpu_ucode_validate(adev->dm.fw_dmcu);
 851        if (r) {
 852                dev_err(adev->dev, "amdgpu_dm: Can't validate firmware \"%s\"\n",
 853                        fw_name_dmcu);
 854                release_firmware(adev->dm.fw_dmcu);
 855                adev->dm.fw_dmcu = NULL;
 856                return r;
 857        }
 858
 859        hdr = (const struct dmcu_firmware_header_v1_0 *)adev->dm.fw_dmcu->data;
 860        adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].ucode_id = AMDGPU_UCODE_ID_DMCU_ERAM;
 861        adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_ERAM].fw = adev->dm.fw_dmcu;
 862        adev->firmware.fw_size +=
 863                ALIGN(le32_to_cpu(hdr->header.ucode_size_bytes) - le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 864
 865        adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].ucode_id = AMDGPU_UCODE_ID_DMCU_INTV;
 866        adev->firmware.ucode[AMDGPU_UCODE_ID_DMCU_INTV].fw = adev->dm.fw_dmcu;
 867        adev->firmware.fw_size +=
 868                ALIGN(le32_to_cpu(hdr->intv_size_bytes), PAGE_SIZE);
 869
 870        adev->dm.dmcu_fw_version = le32_to_cpu(hdr->header.ucode_version);
 871
 872        DRM_DEBUG_KMS("PSP loading DMCU firmware\n");
 873
 874        return 0;
 875}
 876
 877static int dm_sw_init(void *handle)
 878{
 879        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 880
 881        return load_dmcu_fw(adev);
 882}
 883
 884static int dm_sw_fini(void *handle)
 885{
 886        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 887
 888        if(adev->dm.fw_dmcu) {
 889                release_firmware(adev->dm.fw_dmcu);
 890                adev->dm.fw_dmcu = NULL;
 891        }
 892
 893        return 0;
 894}
 895
 896static int detect_mst_link_for_all_connectors(struct drm_device *dev)
 897{
 898        struct amdgpu_dm_connector *aconnector;
 899        struct drm_connector *connector;
 900        int ret = 0;
 901
 902        drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 903
 904        list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 905                aconnector = to_amdgpu_dm_connector(connector);
 906                if (aconnector->dc_link->type == dc_connection_mst_branch &&
 907                    aconnector->mst_mgr.aux) {
 908                        DRM_DEBUG_DRIVER("DM_MST: starting TM on aconnector: %p [id: %d]\n",
 909                                        aconnector, aconnector->base.base.id);
 910
 911                        ret = drm_dp_mst_topology_mgr_set_mst(&aconnector->mst_mgr, true);
 912                        if (ret < 0) {
 913                                DRM_ERROR("DM_MST: Failed to start MST\n");
 914                                ((struct dc_link *)aconnector->dc_link)->type = dc_connection_single;
 915                                return ret;
 916                                }
 917                        }
 918        }
 919
 920        drm_modeset_unlock(&dev->mode_config.connection_mutex);
 921        return ret;
 922}
 923
 924static int dm_late_init(void *handle)
 925{
 926        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 927
 928        struct dmcu_iram_parameters params;
 929        unsigned int linear_lut[16];
 930        int i;
 931        struct dmcu *dmcu = adev->dm.dc->res_pool->dmcu;
 932        bool ret = false;
 933
 934        for (i = 0; i < 16; i++)
 935                linear_lut[i] = 0xFFFF * i / 15;
 936
 937        params.set = 0;
 938        params.backlight_ramping_start = 0xCCCC;
 939        params.backlight_ramping_reduction = 0xCCCCCCCC;
 940        params.backlight_lut_array_size = 16;
 941        params.backlight_lut_array = linear_lut;
 942
 943        /* todo will enable for navi10 */
 944        if (adev->asic_type <= CHIP_RAVEN) {
 945                ret = dmcu_load_iram(dmcu, params);
 946
 947                if (!ret)
 948                        return -EINVAL;
 949        }
 950
 951        return detect_mst_link_for_all_connectors(adev->ddev);
 952}
 953
 954static void s3_handle_mst(struct drm_device *dev, bool suspend)
 955{
 956        struct amdgpu_dm_connector *aconnector;
 957        struct drm_connector *connector;
 958        struct drm_dp_mst_topology_mgr *mgr;
 959        int ret;
 960        bool need_hotplug = false;
 961
 962        drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
 963
 964        list_for_each_entry(connector, &dev->mode_config.connector_list,
 965                            head) {
 966                aconnector = to_amdgpu_dm_connector(connector);
 967                if (aconnector->dc_link->type != dc_connection_mst_branch ||
 968                    aconnector->mst_port)
 969                        continue;
 970
 971                mgr = &aconnector->mst_mgr;
 972
 973                if (suspend) {
 974                        drm_dp_mst_topology_mgr_suspend(mgr);
 975                } else {
 976                        ret = drm_dp_mst_topology_mgr_resume(mgr);
 977                        if (ret < 0) {
 978                                drm_dp_mst_topology_mgr_set_mst(mgr, false);
 979                                need_hotplug = true;
 980                        }
 981                }
 982        }
 983
 984        drm_modeset_unlock(&dev->mode_config.connection_mutex);
 985
 986        if (need_hotplug)
 987                drm_kms_helper_hotplug_event(dev);
 988}
 989
 990/**
 991 * dm_hw_init() - Initialize DC device
 992 * @handle: The base driver device containing the amdpgu_dm device.
 993 *
 994 * Initialize the &struct amdgpu_display_manager device. This involves calling
 995 * the initializers of each DM component, then populating the struct with them.
 996 *
 997 * Although the function implies hardware initialization, both hardware and
 998 * software are initialized here. Splitting them out to their relevant init
 999 * hooks is a future TODO item.
1000 *
1001 * Some notable things that are initialized here:
1002 *
1003 * - Display Core, both software and hardware
1004 * - DC modules that we need (freesync and color management)
1005 * - DRM software states
1006 * - Interrupt sources and handlers
1007 * - Vblank support
1008 * - Debug FS entries, if enabled
1009 */
1010static int dm_hw_init(void *handle)
1011{
1012        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1013        /* Create DAL display manager */
1014        amdgpu_dm_init(adev);
1015        amdgpu_dm_hpd_init(adev);
1016
1017        return 0;
1018}
1019
1020/**
1021 * dm_hw_fini() - Teardown DC device
1022 * @handle: The base driver device containing the amdpgu_dm device.
1023 *
1024 * Teardown components within &struct amdgpu_display_manager that require
1025 * cleanup. This involves cleaning up the DRM device, DC, and any modules that
1026 * were loaded. Also flush IRQ workqueues and disable them.
1027 */
1028static int dm_hw_fini(void *handle)
1029{
1030        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1031
1032        amdgpu_dm_hpd_fini(adev);
1033
1034        amdgpu_dm_irq_fini(adev);
1035        amdgpu_dm_fini(adev);
1036        return 0;
1037}
1038
1039static int dm_suspend(void *handle)
1040{
1041        struct amdgpu_device *adev = handle;
1042        struct amdgpu_display_manager *dm = &adev->dm;
1043        int ret = 0;
1044
1045        WARN_ON(adev->dm.cached_state);
1046        adev->dm.cached_state = drm_atomic_helper_suspend(adev->ddev);
1047
1048        s3_handle_mst(adev->ddev, true);
1049
1050        amdgpu_dm_irq_suspend(adev);
1051
1052
1053        dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D3);
1054
1055        return ret;
1056}
1057
1058static struct amdgpu_dm_connector *
1059amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state,
1060                                             struct drm_crtc *crtc)
1061{
1062        uint32_t i;
1063        struct drm_connector_state *new_con_state;
1064        struct drm_connector *connector;
1065        struct drm_crtc *crtc_from_state;
1066
1067        for_each_new_connector_in_state(state, connector, new_con_state, i) {
1068                crtc_from_state = new_con_state->crtc;
1069
1070                if (crtc_from_state == crtc)
1071                        return to_amdgpu_dm_connector(connector);
1072        }
1073
1074        return NULL;
1075}
1076
1077static void emulated_link_detect(struct dc_link *link)
1078{
1079        struct dc_sink_init_data sink_init_data = { 0 };
1080        struct display_sink_capability sink_caps = { 0 };
1081        enum dc_edid_status edid_status;
1082        struct dc_context *dc_ctx = link->ctx;
1083        struct dc_sink *sink = NULL;
1084        struct dc_sink *prev_sink = NULL;
1085
1086        link->type = dc_connection_none;
1087        prev_sink = link->local_sink;
1088
1089        if (prev_sink != NULL)
1090                dc_sink_retain(prev_sink);
1091
1092        switch (link->connector_signal) {
1093        case SIGNAL_TYPE_HDMI_TYPE_A: {
1094                sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1095                sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
1096                break;
1097        }
1098
1099        case SIGNAL_TYPE_DVI_SINGLE_LINK: {
1100                sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1101                sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1102                break;
1103        }
1104
1105        case SIGNAL_TYPE_DVI_DUAL_LINK: {
1106                sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1107                sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1108                break;
1109        }
1110
1111        case SIGNAL_TYPE_LVDS: {
1112                sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
1113                sink_caps.signal = SIGNAL_TYPE_LVDS;
1114                break;
1115        }
1116
1117        case SIGNAL_TYPE_EDP: {
1118                sink_caps.transaction_type =
1119                        DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1120                sink_caps.signal = SIGNAL_TYPE_EDP;
1121                break;
1122        }
1123
1124        case SIGNAL_TYPE_DISPLAY_PORT: {
1125                sink_caps.transaction_type =
1126                        DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
1127                sink_caps.signal = SIGNAL_TYPE_VIRTUAL;
1128                break;
1129        }
1130
1131        default:
1132                DC_ERROR("Invalid connector type! signal:%d\n",
1133                        link->connector_signal);
1134                return;
1135        }
1136
1137        sink_init_data.link = link;
1138        sink_init_data.sink_signal = sink_caps.signal;
1139
1140        sink = dc_sink_create(&sink_init_data);
1141        if (!sink) {
1142                DC_ERROR("Failed to create sink!\n");
1143                return;
1144        }
1145
1146        /* dc_sink_create returns a new reference */
1147        link->local_sink = sink;
1148
1149        edid_status = dm_helpers_read_local_edid(
1150                        link->ctx,
1151                        link,
1152                        sink);
1153
1154        if (edid_status != EDID_OK)
1155                DC_ERROR("Failed to read EDID");
1156
1157}
1158
1159static int dm_resume(void *handle)
1160{
1161        struct amdgpu_device *adev = handle;
1162        struct drm_device *ddev = adev->ddev;
1163        struct amdgpu_display_manager *dm = &adev->dm;
1164        struct amdgpu_dm_connector *aconnector;
1165        struct drm_connector *connector;
1166        struct drm_crtc *crtc;
1167        struct drm_crtc_state *new_crtc_state;
1168        struct dm_crtc_state *dm_new_crtc_state;
1169        struct drm_plane *plane;
1170        struct drm_plane_state *new_plane_state;
1171        struct dm_plane_state *dm_new_plane_state;
1172        struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state);
1173        enum dc_connection_type new_connection_type = dc_connection_none;
1174        int i;
1175
1176        /* Recreate dc_state - DC invalidates it when setting power state to S3. */
1177        dc_release_state(dm_state->context);
1178        dm_state->context = dc_create_state(dm->dc);
1179        /* TODO: Remove dc_state->dccg, use dc->dccg directly. */
1180        dc_resource_state_construct(dm->dc, dm_state->context);
1181
1182        /* power on hardware */
1183        dc_set_power_state(dm->dc, DC_ACPI_CM_POWER_STATE_D0);
1184
1185        /* program HPD filter */
1186        dc_resume(dm->dc);
1187
1188        /* On resume we need to  rewrite the MSTM control bits to enamble MST*/
1189        s3_handle_mst(ddev, false);
1190
1191        /*
1192         * early enable HPD Rx IRQ, should be done before set mode as short
1193         * pulse interrupts are used for MST
1194         */
1195        amdgpu_dm_irq_resume_early(adev);
1196
1197        /* Do detection*/
1198        list_for_each_entry(connector, &ddev->mode_config.connector_list, head) {
1199                aconnector = to_amdgpu_dm_connector(connector);
1200
1201                /*
1202                 * this is the case when traversing through already created
1203                 * MST connectors, should be skipped
1204                 */
1205                if (aconnector->mst_port)
1206                        continue;
1207
1208                mutex_lock(&aconnector->hpd_lock);
1209                if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1210                        DRM_ERROR("KMS: Failed to detect connector\n");
1211
1212                if (aconnector->base.force && new_connection_type == dc_connection_none)
1213                        emulated_link_detect(aconnector->dc_link);
1214                else
1215                        dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD);
1216
1217                if (aconnector->fake_enable && aconnector->dc_link->local_sink)
1218                        aconnector->fake_enable = false;
1219
1220                if (aconnector->dc_sink)
1221                        dc_sink_release(aconnector->dc_sink);
1222                aconnector->dc_sink = NULL;
1223                amdgpu_dm_update_connector_after_detect(aconnector);
1224                mutex_unlock(&aconnector->hpd_lock);
1225        }
1226
1227        /* Force mode set in atomic commit */
1228        for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i)
1229                new_crtc_state->active_changed = true;
1230
1231        /*
1232         * atomic_check is expected to create the dc states. We need to release
1233         * them here, since they were duplicated as part of the suspend
1234         * procedure.
1235         */
1236        for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) {
1237                dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
1238                if (dm_new_crtc_state->stream) {
1239                        WARN_ON(kref_read(&dm_new_crtc_state->stream->refcount) > 1);
1240                        dc_stream_release(dm_new_crtc_state->stream);
1241                        dm_new_crtc_state->stream = NULL;
1242                }
1243        }
1244
1245        for_each_new_plane_in_state(dm->cached_state, plane, new_plane_state, i) {
1246                dm_new_plane_state = to_dm_plane_state(new_plane_state);
1247                if (dm_new_plane_state->dc_state) {
1248                        WARN_ON(kref_read(&dm_new_plane_state->dc_state->refcount) > 1);
1249                        dc_plane_state_release(dm_new_plane_state->dc_state);
1250                        dm_new_plane_state->dc_state = NULL;
1251                }
1252        }
1253
1254        drm_atomic_helper_resume(ddev, dm->cached_state);
1255
1256        dm->cached_state = NULL;
1257
1258        amdgpu_dm_irq_resume_late(adev);
1259
1260        return 0;
1261}
1262
1263/**
1264 * DOC: DM Lifecycle
1265 *
1266 * DM (and consequently DC) is registered in the amdgpu base driver as a IP
1267 * block. When CONFIG_DRM_AMD_DC is enabled, the DM device IP block is added to
1268 * the base driver's device list to be initialized and torn down accordingly.
1269 *
1270 * The functions to do so are provided as hooks in &struct amd_ip_funcs.
1271 */
1272
1273static const struct amd_ip_funcs amdgpu_dm_funcs = {
1274        .name = "dm",
1275        .early_init = dm_early_init,
1276        .late_init = dm_late_init,
1277        .sw_init = dm_sw_init,
1278        .sw_fini = dm_sw_fini,
1279        .hw_init = dm_hw_init,
1280        .hw_fini = dm_hw_fini,
1281        .suspend = dm_suspend,
1282        .resume = dm_resume,
1283        .is_idle = dm_is_idle,
1284        .wait_for_idle = dm_wait_for_idle,
1285        .check_soft_reset = dm_check_soft_reset,
1286        .soft_reset = dm_soft_reset,
1287        .set_clockgating_state = dm_set_clockgating_state,
1288        .set_powergating_state = dm_set_powergating_state,
1289};
1290
1291const struct amdgpu_ip_block_version dm_ip_block =
1292{
1293        .type = AMD_IP_BLOCK_TYPE_DCE,
1294        .major = 1,
1295        .minor = 0,
1296        .rev = 0,
1297        .funcs = &amdgpu_dm_funcs,
1298};
1299
1300
1301/**
1302 * DOC: atomic
1303 *
1304 * *WIP*
1305 */
1306
1307static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = {
1308        .fb_create = amdgpu_display_user_framebuffer_create,
1309        .output_poll_changed = drm_fb_helper_output_poll_changed,
1310        .atomic_check = amdgpu_dm_atomic_check,
1311        .atomic_commit = amdgpu_dm_atomic_commit,
1312};
1313
1314static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = {
1315        .atomic_commit_tail = amdgpu_dm_atomic_commit_tail
1316};
1317
1318static void
1319amdgpu_dm_update_connector_after_detect(struct amdgpu_dm_connector *aconnector)
1320{
1321        struct drm_connector *connector = &aconnector->base;
1322        struct drm_device *dev = connector->dev;
1323        struct dc_sink *sink;
1324
1325        /* MST handled by drm_mst framework */
1326        if (aconnector->mst_mgr.mst_state == true)
1327                return;
1328
1329
1330        sink = aconnector->dc_link->local_sink;
1331        if (sink)
1332                dc_sink_retain(sink);
1333
1334        /*
1335         * Edid mgmt connector gets first update only in mode_valid hook and then
1336         * the connector sink is set to either fake or physical sink depends on link status.
1337         * Skip if already done during boot.
1338         */
1339        if (aconnector->base.force != DRM_FORCE_UNSPECIFIED
1340                        && aconnector->dc_em_sink) {
1341
1342                /*
1343                 * For S3 resume with headless use eml_sink to fake stream
1344                 * because on resume connector->sink is set to NULL
1345                 */
1346                mutex_lock(&dev->mode_config.mutex);
1347
1348                if (sink) {
1349                        if (aconnector->dc_sink) {
1350                                amdgpu_dm_update_freesync_caps(connector, NULL);
1351                                /*
1352                                 * retain and release below are used to
1353                                 * bump up refcount for sink because the link doesn't point
1354                                 * to it anymore after disconnect, so on next crtc to connector
1355                                 * reshuffle by UMD we will get into unwanted dc_sink release
1356                                 */
1357                                dc_sink_release(aconnector->dc_sink);
1358                        }
1359                        aconnector->dc_sink = sink;
1360                        dc_sink_retain(aconnector->dc_sink);
1361                        amdgpu_dm_update_freesync_caps(connector,
1362                                        aconnector->edid);
1363                } else {
1364                        amdgpu_dm_update_freesync_caps(connector, NULL);
1365                        if (!aconnector->dc_sink) {
1366                                aconnector->dc_sink = aconnector->dc_em_sink;
1367                                dc_sink_retain(aconnector->dc_sink);
1368                        }
1369                }
1370
1371                mutex_unlock(&dev->mode_config.mutex);
1372
1373                if (sink)
1374                        dc_sink_release(sink);
1375                return;
1376        }
1377
1378        /*
1379         * TODO: temporary guard to look for proper fix
1380         * if this sink is MST sink, we should not do anything
1381         */
1382        if (sink && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
1383                dc_sink_release(sink);
1384                return;
1385        }
1386
1387        if (aconnector->dc_sink == sink) {
1388                /*
1389                 * We got a DP short pulse (Link Loss, DP CTS, etc...).
1390                 * Do nothing!!
1391                 */
1392                DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: dc_sink didn't change.\n",
1393                                aconnector->connector_id);
1394                if (sink)
1395                        dc_sink_release(sink);
1396                return;
1397        }
1398
1399        DRM_DEBUG_DRIVER("DCHPD: connector_id=%d: Old sink=%p New sink=%p\n",
1400                aconnector->connector_id, aconnector->dc_sink, sink);
1401
1402        mutex_lock(&dev->mode_config.mutex);
1403
1404        /*
1405         * 1. Update status of the drm connector
1406         * 2. Send an event and let userspace tell us what to do
1407         */
1408        if (sink) {
1409                /*
1410                 * TODO: check if we still need the S3 mode update workaround.
1411                 * If yes, put it here.
1412                 */
1413                if (aconnector->dc_sink)
1414                        amdgpu_dm_update_freesync_caps(connector, NULL);
1415
1416                aconnector->dc_sink = sink;
1417                dc_sink_retain(aconnector->dc_sink);
1418                if (sink->dc_edid.length == 0) {
1419                        aconnector->edid = NULL;
1420                        drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1421                } else {
1422                        aconnector->edid =
1423                                (struct edid *) sink->dc_edid.raw_edid;
1424
1425
1426                        drm_connector_update_edid_property(connector,
1427                                        aconnector->edid);
1428                        drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,
1429                                            aconnector->edid);
1430                }
1431                amdgpu_dm_update_freesync_caps(connector, aconnector->edid);
1432
1433        } else {
1434                drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux);
1435                amdgpu_dm_update_freesync_caps(connector, NULL);
1436                drm_connector_update_edid_property(connector, NULL);
1437                aconnector->num_modes = 0;
1438                dc_sink_release(aconnector->dc_sink);
1439                aconnector->dc_sink = NULL;
1440                aconnector->edid = NULL;
1441        }
1442
1443        mutex_unlock(&dev->mode_config.mutex);
1444
1445        if (sink)
1446                dc_sink_release(sink);
1447}
1448
1449static void handle_hpd_irq(void *param)
1450{
1451        struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1452        struct drm_connector *connector = &aconnector->base;
1453        struct drm_device *dev = connector->dev;
1454        enum dc_connection_type new_connection_type = dc_connection_none;
1455
1456        /*
1457         * In case of failure or MST no need to update connector status or notify the OS
1458         * since (for MST case) MST does this in its own context.
1459         */
1460        mutex_lock(&aconnector->hpd_lock);
1461
1462        if (aconnector->fake_enable)
1463                aconnector->fake_enable = false;
1464
1465        if (!dc_link_detect_sink(aconnector->dc_link, &new_connection_type))
1466                DRM_ERROR("KMS: Failed to detect connector\n");
1467
1468        if (aconnector->base.force && new_connection_type == dc_connection_none) {
1469                emulated_link_detect(aconnector->dc_link);
1470
1471
1472                drm_modeset_lock_all(dev);
1473                dm_restore_drm_connector_state(dev, connector);
1474                drm_modeset_unlock_all(dev);
1475
1476                if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1477                        drm_kms_helper_hotplug_event(dev);
1478
1479        } else if (dc_link_detect(aconnector->dc_link, DETECT_REASON_HPD)) {
1480                amdgpu_dm_update_connector_after_detect(aconnector);
1481
1482
1483                drm_modeset_lock_all(dev);
1484                dm_restore_drm_connector_state(dev, connector);
1485                drm_modeset_unlock_all(dev);
1486
1487                if (aconnector->base.force == DRM_FORCE_UNSPECIFIED)
1488                        drm_kms_helper_hotplug_event(dev);
1489        }
1490        mutex_unlock(&aconnector->hpd_lock);
1491
1492}
1493
1494static void dm_handle_hpd_rx_irq(struct amdgpu_dm_connector *aconnector)
1495{
1496        uint8_t esi[DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI] = { 0 };
1497        uint8_t dret;
1498        bool new_irq_handled = false;
1499        int dpcd_addr;
1500        int dpcd_bytes_to_read;
1501
1502        const int max_process_count = 30;
1503        int process_count = 0;
1504
1505        const struct dc_link_status *link_status = dc_link_get_status(aconnector->dc_link);
1506
1507        if (link_status->dpcd_caps->dpcd_rev.raw < 0x12) {
1508                dpcd_bytes_to_read = DP_LANE0_1_STATUS - DP_SINK_COUNT;
1509                /* DPCD 0x200 - 0x201 for downstream IRQ */
1510                dpcd_addr = DP_SINK_COUNT;
1511        } else {
1512                dpcd_bytes_to_read = DP_PSR_ERROR_STATUS - DP_SINK_COUNT_ESI;
1513                /* DPCD 0x2002 - 0x2005 for downstream IRQ */
1514                dpcd_addr = DP_SINK_COUNT_ESI;
1515        }
1516
1517        dret = drm_dp_dpcd_read(
1518                &aconnector->dm_dp_aux.aux,
1519                dpcd_addr,
1520                esi,
1521                dpcd_bytes_to_read);
1522
1523        while (dret == dpcd_bytes_to_read &&
1524                process_count < max_process_count) {
1525                uint8_t retry;
1526                dret = 0;
1527
1528                process_count++;
1529
1530                DRM_DEBUG_DRIVER("ESI %02x %02x %02x\n", esi[0], esi[1], esi[2]);
1531                /* handle HPD short pulse irq */
1532                if (aconnector->mst_mgr.mst_state)
1533                        drm_dp_mst_hpd_irq(
1534                                &aconnector->mst_mgr,
1535                                esi,
1536                                &new_irq_handled);
1537
1538                if (new_irq_handled) {
1539                        /* ACK at DPCD to notify down stream */
1540                        const int ack_dpcd_bytes_to_write =
1541                                dpcd_bytes_to_read - 1;
1542
1543                        for (retry = 0; retry < 3; retry++) {
1544                                uint8_t wret;
1545
1546                                wret = drm_dp_dpcd_write(
1547                                        &aconnector->dm_dp_aux.aux,
1548                                        dpcd_addr + 1,
1549                                        &esi[1],
1550                                        ack_dpcd_bytes_to_write);
1551                                if (wret == ack_dpcd_bytes_to_write)
1552                                        break;
1553                        }
1554
1555                        /* check if there is new irq to be handled */
1556                        dret = drm_dp_dpcd_read(
1557                                &aconnector->dm_dp_aux.aux,
1558                                dpcd_addr,
1559                                esi,
1560                                dpcd_bytes_to_read);
1561
1562                        new_irq_handled = false;
1563                } else {
1564                        break;
1565                }
1566        }
1567
1568        if (process_count == max_process_count)
1569                DRM_DEBUG_DRIVER("Loop exceeded max iterations\n");
1570}
1571
1572static void handle_hpd_rx_irq(void *param)
1573{
1574        struct amdgpu_dm_connector *aconnector = (struct amdgpu_dm_connector *)param;
1575        struct drm_connector *connector = &aconnector->base;
1576        struct drm_device *dev = connector->dev;
1577        struct dc_link *dc_link = aconnector->dc_link;
1578        bool is_mst_root_connector = aconnector->mst_mgr.mst_state;
1579        enum dc_connection_type new_connection_type = dc_connection_none;
1580
1581        /*
1582         * TODO:Temporary add mutex to protect hpd interrupt not have a gpio
1583         * conflict, after implement i2c helper, this mutex should be
1584         * retired.
1585         */
1586        if (dc_link->type != dc_connection_mst_branch)
1587                mutex_lock(&aconnector->hpd_lock);
1588
1589        if (dc_link_handle_hpd_rx_irq(dc_link, NULL, NULL) &&
1590                        !is_mst_root_connector) {
1591                /* Downstream Port status changed. */
1592                if (!dc_link_detect_sink(dc_link, &new_connection_type))
1593                        DRM_ERROR("KMS: Failed to detect connector\n");
1594
1595                if (aconnector->base.force && new_connection_type == dc_connection_none) {
1596                        emulated_link_detect(dc_link);
1597
1598                        if (aconnector->fake_enable)
1599                                aconnector->fake_enable = false;
1600
1601                        amdgpu_dm_update_connector_after_detect(aconnector);
1602
1603
1604                        drm_modeset_lock_all(dev);
1605                        dm_restore_drm_connector_state(dev, connector);
1606                        drm_modeset_unlock_all(dev);
1607
1608                        drm_kms_helper_hotplug_event(dev);
1609                } else if (dc_link_detect(dc_link, DETECT_REASON_HPDRX)) {
1610
1611                        if (aconnector->fake_enable)
1612                                aconnector->fake_enable = false;
1613
1614                        amdgpu_dm_update_connector_after_detect(aconnector);
1615
1616
1617                        drm_modeset_lock_all(dev);
1618                        dm_restore_drm_connector_state(dev, connector);
1619                        drm_modeset_unlock_all(dev);
1620
1621                        drm_kms_helper_hotplug_event(dev);
1622                }
1623        }
1624        if ((dc_link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) ||
1625            (dc_link->type == dc_connection_mst_branch))
1626                dm_handle_hpd_rx_irq(aconnector);
1627
1628        if (dc_link->type != dc_connection_mst_branch) {
1629                drm_dp_cec_irq(&aconnector->dm_dp_aux.aux);
1630                mutex_unlock(&aconnector->hpd_lock);
1631        }
1632}
1633
1634static void register_hpd_handlers(struct amdgpu_device *adev)
1635{
1636        struct drm_device *dev = adev->ddev;
1637        struct drm_connector *connector;
1638        struct amdgpu_dm_connector *aconnector;
1639        const struct dc_link *dc_link;
1640        struct dc_interrupt_params int_params = {0};
1641
1642        int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1643        int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1644
1645        list_for_each_entry(connector,
1646                        &dev->mode_config.connector_list, head) {
1647
1648                aconnector = to_amdgpu_dm_connector(connector);
1649                dc_link = aconnector->dc_link;
1650
1651                if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd) {
1652                        int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1653                        int_params.irq_source = dc_link->irq_source_hpd;
1654
1655                        amdgpu_dm_irq_register_interrupt(adev, &int_params,
1656                                        handle_hpd_irq,
1657                                        (void *) aconnector);
1658                }
1659
1660                if (DC_IRQ_SOURCE_INVALID != dc_link->irq_source_hpd_rx) {
1661
1662                        /* Also register for DP short pulse (hpd_rx). */
1663                        int_params.int_context = INTERRUPT_LOW_IRQ_CONTEXT;
1664                        int_params.irq_source = dc_link->irq_source_hpd_rx;
1665
1666                        amdgpu_dm_irq_register_interrupt(adev, &int_params,
1667                                        handle_hpd_rx_irq,
1668                                        (void *) aconnector);
1669                }
1670        }
1671}
1672
1673/* Register IRQ sources and initialize IRQ callbacks */
1674static int dce110_register_irq_handlers(struct amdgpu_device *adev)
1675{
1676        struct dc *dc = adev->dm.dc;
1677        struct common_irq_params *c_irq_params;
1678        struct dc_interrupt_params int_params = {0};
1679        int r;
1680        int i;
1681        unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
1682
1683        if (adev->asic_type >= CHIP_VEGA10)
1684                client_id = SOC15_IH_CLIENTID_DCE;
1685
1686        int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1687        int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1688
1689        /*
1690         * Actions of amdgpu_irq_add_id():
1691         * 1. Register a set() function with base driver.
1692         *    Base driver will call set() function to enable/disable an
1693         *    interrupt in DC hardware.
1694         * 2. Register amdgpu_dm_irq_handler().
1695         *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1696         *    coming from DC hardware.
1697         *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1698         *    for acknowledging and handling. */
1699
1700        /* Use VBLANK interrupt */
1701        for (i = VISLANDS30_IV_SRCID_D1_VERTICAL_INTERRUPT0; i <= VISLANDS30_IV_SRCID_D6_VERTICAL_INTERRUPT0; i++) {
1702                r = amdgpu_irq_add_id(adev, client_id, i, &adev->crtc_irq);
1703                if (r) {
1704                        DRM_ERROR("Failed to add crtc irq id!\n");
1705                        return r;
1706                }
1707
1708                int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1709                int_params.irq_source =
1710                        dc_interrupt_to_irq_source(dc, i, 0);
1711
1712                c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1713
1714                c_irq_params->adev = adev;
1715                c_irq_params->irq_src = int_params.irq_source;
1716
1717                amdgpu_dm_irq_register_interrupt(adev, &int_params,
1718                                dm_crtc_high_irq, c_irq_params);
1719        }
1720
1721        /* Use VUPDATE interrupt */
1722        for (i = VISLANDS30_IV_SRCID_D1_V_UPDATE_INT; i <= VISLANDS30_IV_SRCID_D6_V_UPDATE_INT; i += 2) {
1723                r = amdgpu_irq_add_id(adev, client_id, i, &adev->vupdate_irq);
1724                if (r) {
1725                        DRM_ERROR("Failed to add vupdate irq id!\n");
1726                        return r;
1727                }
1728
1729                int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1730                int_params.irq_source =
1731                        dc_interrupt_to_irq_source(dc, i, 0);
1732
1733                c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1734
1735                c_irq_params->adev = adev;
1736                c_irq_params->irq_src = int_params.irq_source;
1737
1738                amdgpu_dm_irq_register_interrupt(adev, &int_params,
1739                                dm_vupdate_high_irq, c_irq_params);
1740        }
1741
1742        /* Use GRPH_PFLIP interrupt */
1743        for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP;
1744                        i <= VISLANDS30_IV_SRCID_D6_GRPH_PFLIP; i += 2) {
1745                r = amdgpu_irq_add_id(adev, client_id, i, &adev->pageflip_irq);
1746                if (r) {
1747                        DRM_ERROR("Failed to add page flip irq id!\n");
1748                        return r;
1749                }
1750
1751                int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1752                int_params.irq_source =
1753                        dc_interrupt_to_irq_source(dc, i, 0);
1754
1755                c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1756
1757                c_irq_params->adev = adev;
1758                c_irq_params->irq_src = int_params.irq_source;
1759
1760                amdgpu_dm_irq_register_interrupt(adev, &int_params,
1761                                dm_pflip_high_irq, c_irq_params);
1762
1763        }
1764
1765        /* HPD */
1766        r = amdgpu_irq_add_id(adev, client_id,
1767                        VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
1768        if (r) {
1769                DRM_ERROR("Failed to add hpd irq id!\n");
1770                return r;
1771        }
1772
1773        register_hpd_handlers(adev);
1774
1775        return 0;
1776}
1777
1778#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
1779/* Register IRQ sources and initialize IRQ callbacks */
1780static int dcn10_register_irq_handlers(struct amdgpu_device *adev)
1781{
1782        struct dc *dc = adev->dm.dc;
1783        struct common_irq_params *c_irq_params;
1784        struct dc_interrupt_params int_params = {0};
1785        int r;
1786        int i;
1787
1788        int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
1789        int_params.current_polarity = INTERRUPT_POLARITY_DEFAULT;
1790
1791        /*
1792         * Actions of amdgpu_irq_add_id():
1793         * 1. Register a set() function with base driver.
1794         *    Base driver will call set() function to enable/disable an
1795         *    interrupt in DC hardware.
1796         * 2. Register amdgpu_dm_irq_handler().
1797         *    Base driver will call amdgpu_dm_irq_handler() for ALL interrupts
1798         *    coming from DC hardware.
1799         *    amdgpu_dm_irq_handler() will re-direct the interrupt to DC
1800         *    for acknowledging and handling.
1801         */
1802
1803        /* Use VSTARTUP interrupt */
1804        for (i = DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP;
1805                        i <= DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP + adev->mode_info.num_crtc - 1;
1806                        i++) {
1807                r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->crtc_irq);
1808
1809                if (r) {
1810                        DRM_ERROR("Failed to add crtc irq id!\n");
1811                        return r;
1812                }
1813
1814                int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1815                int_params.irq_source =
1816                        dc_interrupt_to_irq_source(dc, i, 0);
1817
1818                c_irq_params = &adev->dm.vblank_params[int_params.irq_source - DC_IRQ_SOURCE_VBLANK1];
1819
1820                c_irq_params->adev = adev;
1821                c_irq_params->irq_src = int_params.irq_source;
1822
1823                amdgpu_dm_irq_register_interrupt(adev, &int_params,
1824                                dm_crtc_high_irq, c_irq_params);
1825        }
1826
1827        /* Use VUPDATE_NO_LOCK interrupt on DCN, which seems to correspond to
1828         * the regular VUPDATE interrupt on DCE. We want DC_IRQ_SOURCE_VUPDATEx
1829         * to trigger at end of each vblank, regardless of state of the lock,
1830         * matching DCE behaviour.
1831         */
1832        for (i = DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT;
1833             i <= DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT + adev->mode_info.num_crtc - 1;
1834             i++) {
1835                r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->vupdate_irq);
1836
1837                if (r) {
1838                        DRM_ERROR("Failed to add vupdate irq id!\n");
1839                        return r;
1840                }
1841
1842                int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1843                int_params.irq_source =
1844                        dc_interrupt_to_irq_source(dc, i, 0);
1845
1846                c_irq_params = &adev->dm.vupdate_params[int_params.irq_source - DC_IRQ_SOURCE_VUPDATE1];
1847
1848                c_irq_params->adev = adev;
1849                c_irq_params->irq_src = int_params.irq_source;
1850
1851                amdgpu_dm_irq_register_interrupt(adev, &int_params,
1852                                dm_vupdate_high_irq, c_irq_params);
1853        }
1854
1855        /* Use GRPH_PFLIP interrupt */
1856        for (i = DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT;
1857                        i <= DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT + adev->mode_info.num_crtc - 1;
1858                        i++) {
1859                r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, i, &adev->pageflip_irq);
1860                if (r) {
1861                        DRM_ERROR("Failed to add page flip irq id!\n");
1862                        return r;
1863                }
1864
1865                int_params.int_context = INTERRUPT_HIGH_IRQ_CONTEXT;
1866                int_params.irq_source =
1867                        dc_interrupt_to_irq_source(dc, i, 0);
1868
1869                c_irq_params = &adev->dm.pflip_params[int_params.irq_source - DC_IRQ_SOURCE_PFLIP_FIRST];
1870
1871                c_irq_params->adev = adev;
1872                c_irq_params->irq_src = int_params.irq_source;
1873
1874                amdgpu_dm_irq_register_interrupt(adev, &int_params,
1875                                dm_pflip_high_irq, c_irq_params);
1876
1877        }
1878
1879        /* HPD */
1880        r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DCE, DCN_1_0__SRCID__DC_HPD1_INT,
1881                        &adev->hpd_irq);
1882        if (r) {
1883                DRM_ERROR("Failed to add hpd irq id!\n");
1884                return r;
1885        }
1886
1887        register_hpd_handlers(adev);
1888
1889        return 0;
1890}
1891#endif
1892
1893/*
1894 * Acquires the lock for the atomic state object and returns
1895 * the new atomic state.
1896 *
1897 * This should only be called during atomic check.
1898 */
1899static int dm_atomic_get_state(struct drm_atomic_state *state,
1900                               struct dm_atomic_state **dm_state)
1901{
1902        struct drm_device *dev = state->dev;
1903        struct amdgpu_device *adev = dev->dev_private;
1904        struct amdgpu_display_manager *dm = &adev->dm;
1905        struct drm_private_state *priv_state;
1906
1907        if (*dm_state)
1908                return 0;
1909
1910        priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
1911        if (IS_ERR(priv_state))
1912                return PTR_ERR(priv_state);
1913
1914        *dm_state = to_dm_atomic_state(priv_state);
1915
1916        return 0;
1917}
1918
1919struct dm_atomic_state *
1920dm_atomic_get_new_state(struct drm_atomic_state *state)
1921{
1922        struct drm_device *dev = state->dev;
1923        struct amdgpu_device *adev = dev->dev_private;
1924        struct amdgpu_display_manager *dm = &adev->dm;
1925        struct drm_private_obj *obj;
1926        struct drm_private_state *new_obj_state;
1927        int i;
1928
1929        for_each_new_private_obj_in_state(state, obj, new_obj_state, i) {
1930                if (obj->funcs == dm->atomic_obj.funcs)
1931                        return to_dm_atomic_state(new_obj_state);
1932        }
1933
1934        return NULL;
1935}
1936
1937struct dm_atomic_state *
1938dm_atomic_get_old_state(struct drm_atomic_state *state)
1939{
1940        struct drm_device *dev = state->dev;
1941        struct amdgpu_device *adev = dev->dev_private;
1942        struct amdgpu_display_manager *dm = &adev->dm;
1943        struct drm_private_obj *obj;
1944        struct drm_private_state *old_obj_state;
1945        int i;
1946
1947        for_each_old_private_obj_in_state(state, obj, old_obj_state, i) {
1948                if (obj->funcs == dm->atomic_obj.funcs)
1949                        return to_dm_atomic_state(old_obj_state);
1950        }
1951
1952        return NULL;
1953}
1954
1955static struct drm_private_state *
1956dm_atomic_duplicate_state(struct drm_private_obj *obj)
1957{
1958        struct dm_atomic_state *old_state, *new_state;
1959
1960        new_state = kzalloc(sizeof(*new_state), GFP_KERNEL);
1961        if (!new_state)
1962                return NULL;
1963
1964        __drm_atomic_helper_private_obj_duplicate_state(obj, &new_state->base);
1965
1966        old_state = to_dm_atomic_state(obj->state);
1967
1968        if (old_state && old_state->context)
1969                new_state->context = dc_copy_state(old_state->context);
1970
1971        if (!new_state->context) {
1972                kfree(new_state);
1973                return NULL;
1974        }
1975
1976        return &new_state->base;
1977}
1978
1979static void dm_atomic_destroy_state(struct drm_private_obj *obj,
1980                                    struct drm_private_state *state)
1981{
1982        struct dm_atomic_state *dm_state = to_dm_atomic_state(state);
1983
1984        if (dm_state && dm_state->context)
1985                dc_release_state(dm_state->context);
1986
1987        kfree(dm_state);
1988}
1989
1990static struct drm_private_state_funcs dm_atomic_state_funcs = {
1991        .atomic_duplicate_state = dm_atomic_duplicate_state,
1992        .atomic_destroy_state = dm_atomic_destroy_state,
1993};
1994
1995static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
1996{
1997        struct dm_atomic_state *state;
1998        int r;
1999
2000        adev->mode_info.mode_config_initialized = true;
2001
2002        adev->ddev->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs;
2003        adev->ddev->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs;
2004
2005        adev->ddev->mode_config.max_width = 16384;
2006        adev->ddev->mode_config.max_height = 16384;
2007
2008        adev->ddev->mode_config.preferred_depth = 24;
2009        adev->ddev->mode_config.prefer_shadow = 1;
2010        /* indicates support for immediate flip */
2011        adev->ddev->mode_config.async_page_flip = true;
2012
2013        adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2014
2015        state = kzalloc(sizeof(*state), GFP_KERNEL);
2016        if (!state)
2017                return -ENOMEM;
2018
2019        state->context = dc_create_state(adev->dm.dc);
2020        if (!state->context) {
2021                kfree(state);
2022                return -ENOMEM;
2023        }
2024
2025        dc_resource_state_copy_construct_current(adev->dm.dc, state->context);
2026
2027        drm_atomic_private_obj_init(adev->ddev,
2028                                    &adev->dm.atomic_obj,
2029                                    &state->base,
2030                                    &dm_atomic_state_funcs);
2031
2032        r = amdgpu_display_modeset_create_props(adev);
2033        if (r)
2034                return r;
2035
2036        r = amdgpu_dm_audio_init(adev);
2037        if (r)
2038                return r;
2039
2040        return 0;
2041}
2042
2043#define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12
2044#define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255
2045
2046#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2047        defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2048
2049static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm)
2050{
2051#if defined(CONFIG_ACPI)
2052        struct amdgpu_dm_backlight_caps caps;
2053
2054        if (dm->backlight_caps.caps_valid)
2055                return;
2056
2057        amdgpu_acpi_get_backlight_caps(dm->adev, &caps);
2058        if (caps.caps_valid) {
2059                dm->backlight_caps.min_input_signal = caps.min_input_signal;
2060                dm->backlight_caps.max_input_signal = caps.max_input_signal;
2061                dm->backlight_caps.caps_valid = true;
2062        } else {
2063                dm->backlight_caps.min_input_signal =
2064                                AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2065                dm->backlight_caps.max_input_signal =
2066                                AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2067        }
2068#else
2069        dm->backlight_caps.min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT;
2070        dm->backlight_caps.max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT;
2071#endif
2072}
2073
2074static int amdgpu_dm_backlight_update_status(struct backlight_device *bd)
2075{
2076        struct amdgpu_display_manager *dm = bl_get_data(bd);
2077        struct amdgpu_dm_backlight_caps caps;
2078        uint32_t brightness = bd->props.brightness;
2079
2080        amdgpu_dm_update_backlight_caps(dm);
2081        caps = dm->backlight_caps;
2082        /*
2083         * The brightness input is in the range 0-255
2084         * It needs to be rescaled to be between the
2085         * requested min and max input signal
2086         *
2087         * It also needs to be scaled up by 0x101 to
2088         * match the DC interface which has a range of
2089         * 0 to 0xffff
2090         */
2091        brightness =
2092                brightness
2093                * 0x101
2094                * (caps.max_input_signal - caps.min_input_signal)
2095                / AMDGPU_MAX_BL_LEVEL
2096                + caps.min_input_signal * 0x101;
2097
2098        if (dc_link_set_backlight_level(dm->backlight_link,
2099                        brightness, 0))
2100                return 0;
2101        else
2102                return 1;
2103}
2104
2105static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd)
2106{
2107        struct amdgpu_display_manager *dm = bl_get_data(bd);
2108        int ret = dc_link_get_backlight_level(dm->backlight_link);
2109
2110        if (ret == DC_ERROR_UNEXPECTED)
2111                return bd->props.brightness;
2112        return ret;
2113}
2114
2115static const struct backlight_ops amdgpu_dm_backlight_ops = {
2116        .options = BL_CORE_SUSPENDRESUME,
2117        .get_brightness = amdgpu_dm_backlight_get_brightness,
2118        .update_status  = amdgpu_dm_backlight_update_status,
2119};
2120
2121static void
2122amdgpu_dm_register_backlight_device(struct amdgpu_display_manager *dm)
2123{
2124        char bl_name[16];
2125        struct backlight_properties props = { 0 };
2126
2127        amdgpu_dm_update_backlight_caps(dm);
2128
2129        props.max_brightness = AMDGPU_MAX_BL_LEVEL;
2130        props.brightness = AMDGPU_MAX_BL_LEVEL;
2131        props.type = BACKLIGHT_RAW;
2132
2133        snprintf(bl_name, sizeof(bl_name), "amdgpu_bl%d",
2134                        dm->adev->ddev->primary->index);
2135
2136        dm->backlight_dev = backlight_device_register(bl_name,
2137                        dm->adev->ddev->dev,
2138                        dm,
2139                        &amdgpu_dm_backlight_ops,
2140                        &props);
2141
2142        if (IS_ERR(dm->backlight_dev))
2143                DRM_ERROR("DM: Backlight registration failed!\n");
2144        else
2145                DRM_DEBUG_DRIVER("DM: Registered Backlight device: %s\n", bl_name);
2146}
2147
2148#endif
2149
2150static int initialize_plane(struct amdgpu_display_manager *dm,
2151                            struct amdgpu_mode_info *mode_info, int plane_id,
2152                            enum drm_plane_type plane_type,
2153                            const struct dc_plane_cap *plane_cap)
2154{
2155        struct drm_plane *plane;
2156        unsigned long possible_crtcs;
2157        int ret = 0;
2158
2159        plane = kzalloc(sizeof(struct drm_plane), GFP_KERNEL);
2160        if (!plane) {
2161                DRM_ERROR("KMS: Failed to allocate plane\n");
2162                return -ENOMEM;
2163        }
2164        plane->type = plane_type;
2165
2166        /*
2167         * HACK: IGT tests expect that the primary plane for a CRTC
2168         * can only have one possible CRTC. Only expose support for
2169         * any CRTC if they're not going to be used as a primary plane
2170         * for a CRTC - like overlay or underlay planes.
2171         */
2172        possible_crtcs = 1 << plane_id;
2173        if (plane_id >= dm->dc->caps.max_streams)
2174                possible_crtcs = 0xff;
2175
2176        ret = amdgpu_dm_plane_init(dm, plane, possible_crtcs, plane_cap);
2177
2178        if (ret) {
2179                DRM_ERROR("KMS: Failed to initialize plane\n");
2180                kfree(plane);
2181                return ret;
2182        }
2183
2184        if (mode_info)
2185                mode_info->planes[plane_id] = plane;
2186
2187        return ret;
2188}
2189
2190
2191static void register_backlight_device(struct amdgpu_display_manager *dm,
2192                                      struct dc_link *link)
2193{
2194#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
2195        defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
2196
2197        if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
2198            link->type != dc_connection_none) {
2199                /*
2200                 * Event if registration failed, we should continue with
2201                 * DM initialization because not having a backlight control
2202                 * is better then a black screen.
2203                 */
2204                amdgpu_dm_register_backlight_device(dm);
2205
2206                if (dm->backlight_dev)
2207                        dm->backlight_link = link;
2208        }
2209#endif
2210}
2211
2212
2213/*
2214 * In this architecture, the association
2215 * connector -> encoder -> crtc
2216 * id not really requried. The crtc and connector will hold the
2217 * display_index as an abstraction to use with DAL component
2218 *
2219 * Returns 0 on success
2220 */
2221static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
2222{
2223        struct amdgpu_display_manager *dm = &adev->dm;
2224        int32_t i;
2225        struct amdgpu_dm_connector *aconnector = NULL;
2226        struct amdgpu_encoder *aencoder = NULL;
2227        struct amdgpu_mode_info *mode_info = &adev->mode_info;
2228        uint32_t link_cnt;
2229        int32_t primary_planes;
2230        enum dc_connection_type new_connection_type = dc_connection_none;
2231        const struct dc_plane_cap *plane;
2232
2233        link_cnt = dm->dc->caps.max_links;
2234        if (amdgpu_dm_mode_config_init(dm->adev)) {
2235                DRM_ERROR("DM: Failed to initialize mode config\n");
2236                return -EINVAL;
2237        }
2238
2239        /* There is one primary plane per CRTC */
2240        primary_planes = dm->dc->caps.max_streams;
2241        ASSERT(primary_planes <= AMDGPU_MAX_PLANES);
2242
2243        /*
2244         * Initialize primary planes, implicit planes for legacy IOCTLS.
2245         * Order is reversed to match iteration order in atomic check.
2246         */
2247        for (i = (primary_planes - 1); i >= 0; i--) {
2248                plane = &dm->dc->caps.planes[i];
2249
2250                if (initialize_plane(dm, mode_info, i,
2251                                     DRM_PLANE_TYPE_PRIMARY, plane)) {
2252                        DRM_ERROR("KMS: Failed to initialize primary plane\n");
2253                        goto fail;
2254                }
2255        }
2256
2257        /*
2258         * Initialize overlay planes, index starting after primary planes.
2259         * These planes have a higher DRM index than the primary planes since
2260         * they should be considered as having a higher z-order.
2261         * Order is reversed to match iteration order in atomic check.
2262         *
2263         * Only support DCN for now, and only expose one so we don't encourage
2264         * userspace to use up all the pipes.
2265         */
2266        for (i = 0; i < dm->dc->caps.max_planes; ++i) {
2267                struct dc_plane_cap *plane = &dm->dc->caps.planes[i];
2268
2269                if (plane->type != DC_PLANE_TYPE_DCN_UNIVERSAL)
2270                        continue;
2271
2272                if (!plane->blends_with_above || !plane->blends_with_below)
2273                        continue;
2274
2275                if (!plane->pixel_format_support.argb8888)
2276                        continue;
2277
2278                if (initialize_plane(dm, NULL, primary_planes + i,
2279                                     DRM_PLANE_TYPE_OVERLAY, plane)) {
2280                        DRM_ERROR("KMS: Failed to initialize overlay plane\n");
2281                        goto fail;
2282                }
2283
2284                /* Only create one overlay plane. */
2285                break;
2286        }
2287
2288        for (i = 0; i < dm->dc->caps.max_streams; i++)
2289                if (amdgpu_dm_crtc_init(dm, mode_info->planes[i], i)) {
2290                        DRM_ERROR("KMS: Failed to initialize crtc\n");
2291                        goto fail;
2292                }
2293
2294        dm->display_indexes_num = dm->dc->caps.max_streams;
2295
2296        /* loops over all connectors on the board */
2297        for (i = 0; i < link_cnt; i++) {
2298                struct dc_link *link = NULL;
2299
2300                if (i > AMDGPU_DM_MAX_DISPLAY_INDEX) {
2301                        DRM_ERROR(
2302                                "KMS: Cannot support more than %d display indexes\n",
2303                                        AMDGPU_DM_MAX_DISPLAY_INDEX);
2304                        continue;
2305                }
2306
2307                aconnector = kzalloc(sizeof(*aconnector), GFP_KERNEL);
2308                if (!aconnector)
2309                        goto fail;
2310
2311                aencoder = kzalloc(sizeof(*aencoder), GFP_KERNEL);
2312                if (!aencoder)
2313                        goto fail;
2314
2315                if (amdgpu_dm_encoder_init(dm->ddev, aencoder, i)) {
2316                        DRM_ERROR("KMS: Failed to initialize encoder\n");
2317                        goto fail;
2318                }
2319
2320                if (amdgpu_dm_connector_init(dm, aconnector, i, aencoder)) {
2321                        DRM_ERROR("KMS: Failed to initialize connector\n");
2322                        goto fail;
2323                }
2324
2325                link = dc_get_link_at_index(dm->dc, i);
2326
2327                if (!dc_link_detect_sink(link, &new_connection_type))
2328                        DRM_ERROR("KMS: Failed to detect connector\n");
2329
2330                if (aconnector->base.force && new_connection_type == dc_connection_none) {
2331                        emulated_link_detect(link);
2332                        amdgpu_dm_update_connector_after_detect(aconnector);
2333
2334                } else if (dc_link_detect(link, DETECT_REASON_BOOT)) {
2335                        amdgpu_dm_update_connector_after_detect(aconnector);
2336                        register_backlight_device(dm, link);
2337                }
2338
2339
2340        }
2341
2342        /* Software is initialized. Now we can register interrupt handlers. */
2343        switch (adev->asic_type) {
2344        case CHIP_BONAIRE:
2345        case CHIP_HAWAII:
2346        case CHIP_KAVERI:
2347        case CHIP_KABINI:
2348        case CHIP_MULLINS:
2349        case CHIP_TONGA:
2350        case CHIP_FIJI:
2351        case CHIP_CARRIZO:
2352        case CHIP_STONEY:
2353        case CHIP_POLARIS11:
2354        case CHIP_POLARIS10:
2355        case CHIP_POLARIS12:
2356        case CHIP_VEGAM:
2357        case CHIP_VEGA10:
2358        case CHIP_VEGA12:
2359        case CHIP_VEGA20:
2360                if (dce110_register_irq_handlers(dm->adev)) {
2361                        DRM_ERROR("DM: Failed to initialize IRQ\n");
2362                        goto fail;
2363                }
2364                break;
2365#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2366        case CHIP_RAVEN:
2367#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2368        case CHIP_NAVI12:
2369        case CHIP_NAVI10:
2370        case CHIP_NAVI14:
2371#endif
2372#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2373        case CHIP_RENOIR:
2374#endif
2375                if (dcn10_register_irq_handlers(dm->adev)) {
2376                        DRM_ERROR("DM: Failed to initialize IRQ\n");
2377                        goto fail;
2378                }
2379                break;
2380#endif
2381        default:
2382                DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2383                goto fail;
2384        }
2385
2386        if (adev->asic_type != CHIP_CARRIZO && adev->asic_type != CHIP_STONEY)
2387                dm->dc->debug.disable_stutter = amdgpu_pp_feature_mask & PP_STUTTER_MODE ? false : true;
2388
2389        return 0;
2390fail:
2391        kfree(aencoder);
2392        kfree(aconnector);
2393
2394        return -EINVAL;
2395}
2396
2397static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm)
2398{
2399        drm_mode_config_cleanup(dm->ddev);
2400        drm_atomic_private_obj_fini(&dm->atomic_obj);
2401        return;
2402}
2403
2404/******************************************************************************
2405 * amdgpu_display_funcs functions
2406 *****************************************************************************/
2407
2408/*
2409 * dm_bandwidth_update - program display watermarks
2410 *
2411 * @adev: amdgpu_device pointer
2412 *
2413 * Calculate and program the display watermarks and line buffer allocation.
2414 */
2415static void dm_bandwidth_update(struct amdgpu_device *adev)
2416{
2417        /* TODO: implement later */
2418}
2419
2420static const struct amdgpu_display_funcs dm_display_funcs = {
2421        .bandwidth_update = dm_bandwidth_update, /* called unconditionally */
2422        .vblank_get_counter = dm_vblank_get_counter,/* called unconditionally */
2423        .backlight_set_level = NULL, /* never called for DC */
2424        .backlight_get_level = NULL, /* never called for DC */
2425        .hpd_sense = NULL,/* called unconditionally */
2426        .hpd_set_polarity = NULL, /* called unconditionally */
2427        .hpd_get_gpio_reg = NULL, /* VBIOS parsing. DAL does it. */
2428        .page_flip_get_scanoutpos =
2429                dm_crtc_get_scanoutpos,/* called unconditionally */
2430        .add_encoder = NULL, /* VBIOS parsing. DAL does it. */
2431        .add_connector = NULL, /* VBIOS parsing. DAL does it. */
2432};
2433
2434#if defined(CONFIG_DEBUG_KERNEL_DC)
2435
2436static ssize_t s3_debug_store(struct device *device,
2437                              struct device_attribute *attr,
2438                              const char *buf,
2439                              size_t count)
2440{
2441        int ret;
2442        int s3_state;
2443        struct drm_device *drm_dev = dev_get_drvdata(device);
2444        struct amdgpu_device *adev = drm_dev->dev_private;
2445
2446        ret = kstrtoint(buf, 0, &s3_state);
2447
2448        if (ret == 0) {
2449                if (s3_state) {
2450                        dm_resume(adev);
2451                        drm_kms_helper_hotplug_event(adev->ddev);
2452                } else
2453                        dm_suspend(adev);
2454        }
2455
2456        return ret == 0 ? count : 0;
2457}
2458
2459DEVICE_ATTR_WO(s3_debug);
2460
2461#endif
2462
2463static int dm_early_init(void *handle)
2464{
2465        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2466
2467        switch (adev->asic_type) {
2468        case CHIP_BONAIRE:
2469        case CHIP_HAWAII:
2470                adev->mode_info.num_crtc = 6;
2471                adev->mode_info.num_hpd = 6;
2472                adev->mode_info.num_dig = 6;
2473                break;
2474        case CHIP_KAVERI:
2475                adev->mode_info.num_crtc = 4;
2476                adev->mode_info.num_hpd = 6;
2477                adev->mode_info.num_dig = 7;
2478                break;
2479        case CHIP_KABINI:
2480        case CHIP_MULLINS:
2481                adev->mode_info.num_crtc = 2;
2482                adev->mode_info.num_hpd = 6;
2483                adev->mode_info.num_dig = 6;
2484                break;
2485        case CHIP_FIJI:
2486        case CHIP_TONGA:
2487                adev->mode_info.num_crtc = 6;
2488                adev->mode_info.num_hpd = 6;
2489                adev->mode_info.num_dig = 7;
2490                break;
2491        case CHIP_CARRIZO:
2492                adev->mode_info.num_crtc = 3;
2493                adev->mode_info.num_hpd = 6;
2494                adev->mode_info.num_dig = 9;
2495                break;
2496        case CHIP_STONEY:
2497                adev->mode_info.num_crtc = 2;
2498                adev->mode_info.num_hpd = 6;
2499                adev->mode_info.num_dig = 9;
2500                break;
2501        case CHIP_POLARIS11:
2502        case CHIP_POLARIS12:
2503                adev->mode_info.num_crtc = 5;
2504                adev->mode_info.num_hpd = 5;
2505                adev->mode_info.num_dig = 5;
2506                break;
2507        case CHIP_POLARIS10:
2508        case CHIP_VEGAM:
2509                adev->mode_info.num_crtc = 6;
2510                adev->mode_info.num_hpd = 6;
2511                adev->mode_info.num_dig = 6;
2512                break;
2513        case CHIP_VEGA10:
2514        case CHIP_VEGA12:
2515        case CHIP_VEGA20:
2516                adev->mode_info.num_crtc = 6;
2517                adev->mode_info.num_hpd = 6;
2518                adev->mode_info.num_dig = 6;
2519                break;
2520#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
2521        case CHIP_RAVEN:
2522                adev->mode_info.num_crtc = 4;
2523                adev->mode_info.num_hpd = 4;
2524                adev->mode_info.num_dig = 4;
2525                break;
2526#endif
2527#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2528        case CHIP_NAVI10:
2529        case CHIP_NAVI12:
2530                adev->mode_info.num_crtc = 6;
2531                adev->mode_info.num_hpd = 6;
2532                adev->mode_info.num_dig = 6;
2533                break;
2534        case CHIP_NAVI14:
2535                adev->mode_info.num_crtc = 5;
2536                adev->mode_info.num_hpd = 5;
2537                adev->mode_info.num_dig = 5;
2538                break;
2539#endif
2540#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2541        case CHIP_RENOIR:
2542                adev->mode_info.num_crtc = 4;
2543                adev->mode_info.num_hpd = 4;
2544                adev->mode_info.num_dig = 4;
2545                break;
2546#endif
2547        default:
2548                DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
2549                return -EINVAL;
2550        }
2551
2552        amdgpu_dm_set_irq_funcs(adev);
2553
2554        if (adev->mode_info.funcs == NULL)
2555                adev->mode_info.funcs = &dm_display_funcs;
2556
2557        /*
2558         * Note: Do NOT change adev->audio_endpt_rreg and
2559         * adev->audio_endpt_wreg because they are initialised in
2560         * amdgpu_device_init()
2561         */
2562#if defined(CONFIG_DEBUG_KERNEL_DC)
2563        device_create_file(
2564                adev->ddev->dev,
2565                &dev_attr_s3_debug);
2566#endif
2567
2568        return 0;
2569}
2570
2571static bool modeset_required(struct drm_crtc_state *crtc_state,
2572                             struct dc_stream_state *new_stream,
2573                             struct dc_stream_state *old_stream)
2574{
2575        if (!drm_atomic_crtc_needs_modeset(crtc_state))
2576                return false;
2577
2578        if (!crtc_state->enable)
2579                return false;
2580
2581        return crtc_state->active;
2582}
2583
2584static bool modereset_required(struct drm_crtc_state *crtc_state)
2585{
2586        if (!drm_atomic_crtc_needs_modeset(crtc_state))
2587                return false;
2588
2589        return !crtc_state->enable || !crtc_state->active;
2590}
2591
2592static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder)
2593{
2594        drm_encoder_cleanup(encoder);
2595        kfree(encoder);
2596}
2597
2598static const struct drm_encoder_funcs amdgpu_dm_encoder_funcs = {
2599        .destroy = amdgpu_dm_encoder_destroy,
2600};
2601
2602
2603static int fill_dc_scaling_info(const struct drm_plane_state *state,
2604                                struct dc_scaling_info *scaling_info)
2605{
2606        int scale_w, scale_h;
2607
2608        memset(scaling_info, 0, sizeof(*scaling_info));
2609
2610        /* Source is fixed 16.16 but we ignore mantissa for now... */
2611        scaling_info->src_rect.x = state->src_x >> 16;
2612        scaling_info->src_rect.y = state->src_y >> 16;
2613
2614        scaling_info->src_rect.width = state->src_w >> 16;
2615        if (scaling_info->src_rect.width == 0)
2616                return -EINVAL;
2617
2618        scaling_info->src_rect.height = state->src_h >> 16;
2619        if (scaling_info->src_rect.height == 0)
2620                return -EINVAL;
2621
2622        scaling_info->dst_rect.x = state->crtc_x;
2623        scaling_info->dst_rect.y = state->crtc_y;
2624
2625        if (state->crtc_w == 0)
2626                return -EINVAL;
2627
2628        scaling_info->dst_rect.width = state->crtc_w;
2629
2630        if (state->crtc_h == 0)
2631                return -EINVAL;
2632
2633        scaling_info->dst_rect.height = state->crtc_h;
2634
2635        /* DRM doesn't specify clipping on destination output. */
2636        scaling_info->clip_rect = scaling_info->dst_rect;
2637
2638        /* TODO: Validate scaling per-format with DC plane caps */
2639        scale_w = scaling_info->dst_rect.width * 1000 /
2640                  scaling_info->src_rect.width;
2641
2642        if (scale_w < 250 || scale_w > 16000)
2643                return -EINVAL;
2644
2645        scale_h = scaling_info->dst_rect.height * 1000 /
2646                  scaling_info->src_rect.height;
2647
2648        if (scale_h < 250 || scale_h > 16000)
2649                return -EINVAL;
2650
2651        /*
2652         * The "scaling_quality" can be ignored for now, quality = 0 has DC
2653         * assume reasonable defaults based on the format.
2654         */
2655
2656        return 0;
2657}
2658
2659static int get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb,
2660                       uint64_t *tiling_flags)
2661{
2662        struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]);
2663        int r = amdgpu_bo_reserve(rbo, false);
2664
2665        if (unlikely(r)) {
2666                /* Don't show error message when returning -ERESTARTSYS */
2667                if (r != -ERESTARTSYS)
2668                        DRM_ERROR("Unable to reserve buffer: %d\n", r);
2669                return r;
2670        }
2671
2672        if (tiling_flags)
2673                amdgpu_bo_get_tiling_flags(rbo, tiling_flags);
2674
2675        amdgpu_bo_unreserve(rbo);
2676
2677        return r;
2678}
2679
2680static inline uint64_t get_dcc_address(uint64_t address, uint64_t tiling_flags)
2681{
2682        uint32_t offset = AMDGPU_TILING_GET(tiling_flags, DCC_OFFSET_256B);
2683
2684        return offset ? (address + offset * 256) : 0;
2685}
2686
2687static int
2688fill_plane_dcc_attributes(struct amdgpu_device *adev,
2689                          const struct amdgpu_framebuffer *afb,
2690                          const enum surface_pixel_format format,
2691                          const enum dc_rotation_angle rotation,
2692                          const struct plane_size *plane_size,
2693                          const union dc_tiling_info *tiling_info,
2694                          const uint64_t info,
2695                          struct dc_plane_dcc_param *dcc,
2696                          struct dc_plane_address *address)
2697{
2698        struct dc *dc = adev->dm.dc;
2699        struct dc_dcc_surface_param input;
2700        struct dc_surface_dcc_cap output;
2701        uint32_t offset = AMDGPU_TILING_GET(info, DCC_OFFSET_256B);
2702        uint32_t i64b = AMDGPU_TILING_GET(info, DCC_INDEPENDENT_64B) != 0;
2703        uint64_t dcc_address;
2704
2705        memset(&input, 0, sizeof(input));
2706        memset(&output, 0, sizeof(output));
2707
2708        if (!offset)
2709                return 0;
2710
2711        if (format >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2712                return 0;
2713
2714        if (!dc->cap_funcs.get_dcc_compression_cap)
2715                return -EINVAL;
2716
2717        input.format = format;
2718        input.surface_size.width = plane_size->surface_size.width;
2719        input.surface_size.height = plane_size->surface_size.height;
2720        input.swizzle_mode = tiling_info->gfx9.swizzle;
2721
2722        if (rotation == ROTATION_ANGLE_0 || rotation == ROTATION_ANGLE_180)
2723                input.scan = SCAN_DIRECTION_HORIZONTAL;
2724        else if (rotation == ROTATION_ANGLE_90 || rotation == ROTATION_ANGLE_270)
2725                input.scan = SCAN_DIRECTION_VERTICAL;
2726
2727        if (!dc->cap_funcs.get_dcc_compression_cap(dc, &input, &output))
2728                return -EINVAL;
2729
2730        if (!output.capable)
2731                return -EINVAL;
2732
2733        if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0)
2734                return -EINVAL;
2735
2736        dcc->enable = 1;
2737        dcc->meta_pitch =
2738                AMDGPU_TILING_GET(info, DCC_PITCH_MAX) + 1;
2739        dcc->independent_64b_blks = i64b;
2740
2741        dcc_address = get_dcc_address(afb->address, info);
2742        address->grph.meta_addr.low_part = lower_32_bits(dcc_address);
2743        address->grph.meta_addr.high_part = upper_32_bits(dcc_address);
2744
2745        return 0;
2746}
2747
2748static int
2749fill_plane_buffer_attributes(struct amdgpu_device *adev,
2750                             const struct amdgpu_framebuffer *afb,
2751                             const enum surface_pixel_format format,
2752                             const enum dc_rotation_angle rotation,
2753                             const uint64_t tiling_flags,
2754                             union dc_tiling_info *tiling_info,
2755                             struct plane_size *plane_size,
2756                             struct dc_plane_dcc_param *dcc,
2757                             struct dc_plane_address *address)
2758{
2759        const struct drm_framebuffer *fb = &afb->base;
2760        int ret;
2761
2762        memset(tiling_info, 0, sizeof(*tiling_info));
2763        memset(plane_size, 0, sizeof(*plane_size));
2764        memset(dcc, 0, sizeof(*dcc));
2765        memset(address, 0, sizeof(*address));
2766
2767        if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
2768                plane_size->surface_size.x = 0;
2769                plane_size->surface_size.y = 0;
2770                plane_size->surface_size.width = fb->width;
2771                plane_size->surface_size.height = fb->height;
2772                plane_size->surface_pitch =
2773                        fb->pitches[0] / fb->format->cpp[0];
2774
2775                address->type = PLN_ADDR_TYPE_GRAPHICS;
2776                address->grph.addr.low_part = lower_32_bits(afb->address);
2777                address->grph.addr.high_part = upper_32_bits(afb->address);
2778        } else if (format < SURFACE_PIXEL_FORMAT_INVALID) {
2779                uint64_t chroma_addr = afb->address + fb->offsets[1];
2780
2781                plane_size->surface_size.x = 0;
2782                plane_size->surface_size.y = 0;
2783                plane_size->surface_size.width = fb->width;
2784                plane_size->surface_size.height = fb->height;
2785                plane_size->surface_pitch =
2786                        fb->pitches[0] / fb->format->cpp[0];
2787
2788                plane_size->chroma_size.x = 0;
2789                plane_size->chroma_size.y = 0;
2790                /* TODO: set these based on surface format */
2791                plane_size->chroma_size.width = fb->width / 2;
2792                plane_size->chroma_size.height = fb->height / 2;
2793
2794                plane_size->chroma_pitch =
2795                        fb->pitches[1] / fb->format->cpp[1];
2796
2797                address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
2798                address->video_progressive.luma_addr.low_part =
2799                        lower_32_bits(afb->address);
2800                address->video_progressive.luma_addr.high_part =
2801                        upper_32_bits(afb->address);
2802                address->video_progressive.chroma_addr.low_part =
2803                        lower_32_bits(chroma_addr);
2804                address->video_progressive.chroma_addr.high_part =
2805                        upper_32_bits(chroma_addr);
2806        }
2807
2808        /* Fill GFX8 params */
2809        if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) {
2810                unsigned int bankw, bankh, mtaspect, tile_split, num_banks;
2811
2812                bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2813                bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2814                mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2815                tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2816                num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2817
2818                /* XXX fix me for VI */
2819                tiling_info->gfx8.num_banks = num_banks;
2820                tiling_info->gfx8.array_mode =
2821                                DC_ARRAY_2D_TILED_THIN1;
2822                tiling_info->gfx8.tile_split = tile_split;
2823                tiling_info->gfx8.bank_width = bankw;
2824                tiling_info->gfx8.bank_height = bankh;
2825                tiling_info->gfx8.tile_aspect = mtaspect;
2826                tiling_info->gfx8.tile_mode =
2827                                DC_ADDR_SURF_MICRO_TILING_DISPLAY;
2828        } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE)
2829                        == DC_ARRAY_1D_TILED_THIN1) {
2830                tiling_info->gfx8.array_mode = DC_ARRAY_1D_TILED_THIN1;
2831        }
2832
2833        tiling_info->gfx8.pipe_config =
2834                        AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
2835
2836        if (adev->asic_type == CHIP_VEGA10 ||
2837            adev->asic_type == CHIP_VEGA12 ||
2838            adev->asic_type == CHIP_VEGA20 ||
2839#if defined(CONFIG_DRM_AMD_DC_DCN2_0)
2840            adev->asic_type == CHIP_NAVI10 ||
2841            adev->asic_type == CHIP_NAVI14 ||
2842            adev->asic_type == CHIP_NAVI12 ||
2843#endif
2844#if defined(CONFIG_DRM_AMD_DC_DCN2_1)
2845            adev->asic_type == CHIP_RENOIR ||
2846#endif
2847            adev->asic_type == CHIP_RAVEN) {
2848                /* Fill GFX9 params */
2849                tiling_info->gfx9.num_pipes =
2850                        adev->gfx.config.gb_addr_config_fields.num_pipes;
2851                tiling_info->gfx9.num_banks =
2852                        adev->gfx.config.gb_addr_config_fields.num_banks;
2853                tiling_info->gfx9.pipe_interleave =
2854                        adev->gfx.config.gb_addr_config_fields.pipe_interleave_size;
2855                tiling_info->gfx9.num_shader_engines =
2856                        adev->gfx.config.gb_addr_config_fields.num_se;
2857                tiling_info->gfx9.max_compressed_frags =
2858                        adev->gfx.config.gb_addr_config_fields.max_compress_frags;
2859                tiling_info->gfx9.num_rb_per_se =
2860                        adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
2861                tiling_info->gfx9.swizzle =
2862                        AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE);
2863                tiling_info->gfx9.shaderEnable = 1;
2864
2865                ret = fill_plane_dcc_attributes(adev, afb, format, rotation,
2866                                                plane_size, tiling_info,
2867                                                tiling_flags, dcc, address);
2868                if (ret)
2869                        return ret;
2870        }
2871
2872        return 0;
2873}
2874
2875static void
2876fill_blending_from_plane_state(const struct drm_plane_state *plane_state,
2877                               bool *per_pixel_alpha, bool *global_alpha,
2878                               int *global_alpha_value)
2879{
2880        *per_pixel_alpha = false;
2881        *global_alpha = false;
2882        *global_alpha_value = 0xff;
2883
2884        if (plane_state->plane->type != DRM_PLANE_TYPE_OVERLAY)
2885                return;
2886
2887        if (plane_state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
2888                static const uint32_t alpha_formats[] = {
2889                        DRM_FORMAT_ARGB8888,
2890                        DRM_FORMAT_RGBA8888,
2891                        DRM_FORMAT_ABGR8888,
2892                };
2893                uint32_t format = plane_state->fb->format->format;
2894                unsigned int i;
2895
2896                for (i = 0; i < ARRAY_SIZE(alpha_formats); ++i) {
2897                        if (format == alpha_formats[i]) {
2898                                *per_pixel_alpha = true;
2899                                break;
2900                        }
2901                }
2902        }
2903
2904        if (plane_state->alpha < 0xffff) {
2905                *global_alpha = true;
2906                *global_alpha_value = plane_state->alpha >> 8;
2907        }
2908}
2909
2910static int
2911fill_plane_color_attributes(const struct drm_plane_state *plane_state,
2912                            const enum surface_pixel_format format,
2913                            enum dc_color_space *color_space)
2914{
2915        bool full_range;
2916
2917        *color_space = COLOR_SPACE_SRGB;
2918
2919        /* DRM color properties only affect non-RGB formats. */
2920        if (format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
2921                return 0;
2922
2923        full_range = (plane_state->color_range == DRM_COLOR_YCBCR_FULL_RANGE);
2924
2925        switch (plane_state->color_encoding) {
2926        case DRM_COLOR_YCBCR_BT601:
2927                if (full_range)
2928                        *color_space = COLOR_SPACE_YCBCR601;
2929                else
2930                        *color_space = COLOR_SPACE_YCBCR601_LIMITED;
2931                break;
2932
2933        case DRM_COLOR_YCBCR_BT709:
2934                if (full_range)
2935                        *color_space = COLOR_SPACE_YCBCR709;
2936                else
2937                        *color_space = COLOR_SPACE_YCBCR709_LIMITED;
2938                break;
2939
2940        case DRM_COLOR_YCBCR_BT2020:
2941                if (full_range)
2942                        *color_space = COLOR_SPACE_2020_YCBCR;
2943                else
2944                        return -EINVAL;
2945                break;
2946
2947        default:
2948                return -EINVAL;
2949        }
2950
2951        return 0;
2952}
2953
2954static int
2955fill_dc_plane_info_and_addr(struct amdgpu_device *adev,
2956                            const struct drm_plane_state *plane_state,
2957                            const uint64_t tiling_flags,
2958                            struct dc_plane_info *plane_info,
2959                            struct dc_plane_address *address)
2960{
2961        const struct drm_framebuffer *fb = plane_state->fb;
2962        const struct amdgpu_framebuffer *afb =
2963                to_amdgpu_framebuffer(plane_state->fb);
2964        struct drm_format_name_buf format_name;
2965        int ret;
2966
2967        memset(plane_info, 0, sizeof(*plane_info));
2968
2969        switch (fb->format->format) {
2970        case DRM_FORMAT_C8:
2971                plane_info->format =
2972                        SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS;
2973                break;
2974        case DRM_FORMAT_RGB565:
2975                plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_RGB565;
2976                break;
2977        case DRM_FORMAT_XRGB8888:
2978        case DRM_FORMAT_ARGB8888:
2979                plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB8888;
2980                break;
2981        case DRM_FORMAT_XRGB2101010:
2982        case DRM_FORMAT_ARGB2101010:
2983                plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010;
2984                break;
2985        case DRM_FORMAT_XBGR2101010:
2986        case DRM_FORMAT_ABGR2101010:
2987                plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
2988                break;
2989        case DRM_FORMAT_XBGR8888:
2990        case DRM_FORMAT_ABGR8888:
2991                plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
2992                break;
2993        case DRM_FORMAT_NV21:
2994                plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
2995                break;
2996        case DRM_FORMAT_NV12:
2997                plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb;
2998                break;
2999        default:
3000                DRM_ERROR(
3001                        "Unsupported screen format %s\n",
3002                        drm_get_format_name(fb->format->format, &format_name));
3003                return -EINVAL;
3004        }
3005
3006        switch (plane_state->rotation & DRM_MODE_ROTATE_MASK) {
3007        case DRM_MODE_ROTATE_0:
3008                plane_info->rotation = ROTATION_ANGLE_0;
3009                break;
3010        case DRM_MODE_ROTATE_90:
3011                plane_info->rotation = ROTATION_ANGLE_90;
3012                break;
3013        case DRM_MODE_ROTATE_180:
3014                plane_info->rotation = ROTATION_ANGLE_180;
3015                break;
3016        case DRM_MODE_ROTATE_270:
3017                plane_info->rotation = ROTATION_ANGLE_270;
3018                break;
3019        default:
3020                plane_info->rotation = ROTATION_ANGLE_0;
3021                break;
3022        }
3023
3024        plane_info->visible = true;
3025        plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE;
3026
3027        plane_info->layer_index = 0;
3028
3029        ret = fill_plane_color_attributes(plane_state, plane_info->format,
3030                                          &plane_info->color_space);
3031        if (ret)
3032                return ret;
3033
3034        ret = fill_plane_buffer_attributes(adev, afb, plane_info->format,
3035                                           plane_info->rotation, tiling_flags,
3036                                           &plane_info->tiling_info,
3037                                           &plane_info->plane_size,
3038                                           &plane_info->dcc, address);
3039        if (ret)
3040                return ret;
3041
3042        fill_blending_from_plane_state(
3043                plane_state, &plane_info->per_pixel_alpha,
3044                &plane_info->global_alpha, &plane_info->global_alpha_value);
3045
3046        return 0;
3047}
3048
3049static int fill_dc_plane_attributes(struct amdgpu_device *adev,
3050                                    struct dc_plane_state *dc_plane_state,
3051                                    struct drm_plane_state *plane_state,
3052                                    struct drm_crtc_state *crtc_state)
3053{
3054        struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
3055        const struct amdgpu_framebuffer *amdgpu_fb =
3056                to_amdgpu_framebuffer(plane_state->fb);
3057        struct dc_scaling_info scaling_info;
3058        struct dc_plane_info plane_info;
3059        uint64_t tiling_flags;
3060        int ret;
3061
3062        ret = fill_dc_scaling_info(plane_state, &scaling_info);
3063        if (ret)
3064                return ret;
3065
3066        dc_plane_state->src_rect = scaling_info.src_rect;
3067        dc_plane_state->dst_rect = scaling_info.dst_rect;
3068        dc_plane_state->clip_rect = scaling_info.clip_rect;
3069        dc_plane_state->scaling_quality = scaling_info.scaling_quality;
3070
3071        ret = get_fb_info(amdgpu_fb, &tiling_flags);
3072        if (ret)
3073                return ret;
3074
3075        ret = fill_dc_plane_info_and_addr(adev, plane_state, tiling_flags,
3076                                          &plane_info,
3077                                          &dc_plane_state->address);
3078        if (ret)
3079                return ret;
3080
3081        dc_plane_state->format = plane_info.format;
3082        dc_plane_state->color_space = plane_info.color_space;
3083        dc_plane_state->format = plane_info.format;
3084        dc_plane_state->plane_size = plane_info.plane_size;
3085        dc_plane_state->rotation = plane_info.rotation;
3086        dc_plane_state->horizontal_mirror = plane_info.horizontal_mirror;
3087        dc_plane_state->stereo_format = plane_info.stereo_format;
3088        dc_plane_state->tiling_info = plane_info.tiling_info;
3089        dc_plane_state->visible = plane_info.visible;
3090        dc_plane_state->per_pixel_alpha = plane_info.per_pixel_alpha;
3091        dc_plane_state->global_alpha = plane_info.global_alpha;
3092        dc_plane_state->global_alpha_value = plane_info.global_alpha_value;
3093        dc_plane_state->dcc = plane_info.dcc;
3094        dc_plane_state->layer_index = plane_info.layer_index; // Always returns 0
3095
3096        /*
3097         * Always set input transfer function, since plane state is refreshed
3098         * every time.
3099         */
3100        ret = amdgpu_dm_update_plane_color_mgmt(dm_crtc_state, dc_plane_state);
3101        if (ret)
3102                return ret;
3103
3104        return 0;
3105}
3106
3107static void update_stream_scaling_settings(const struct drm_display_mode *mode,
3108                                           const struct dm_connector_state *dm_state,
3109                                           struct dc_stream_state *stream)
3110{
3111        enum amdgpu_rmx_type rmx_type;
3112
3113        struct rect src = { 0 }; /* viewport in composition space*/
3114        struct rect dst = { 0 }; /* stream addressable area */
3115
3116        /* no mode. nothing to be done */
3117        if (!mode)
3118                return;
3119
3120        /* Full screen scaling by default */
3121        src.width = mode->hdisplay;
3122        src.height = mode->vdisplay;
3123        dst.width = stream->timing.h_addressable;
3124        dst.height = stream->timing.v_addressable;
3125
3126        if (dm_state) {
3127                rmx_type = dm_state->scaling;
3128                if (rmx_type == RMX_ASPECT || rmx_type == RMX_OFF) {
3129                        if (src.width * dst.height <
3130                                        src.height * dst.width) {
3131                                /* height needs less upscaling/more downscaling */
3132                                dst.width = src.width *
3133                                                dst.height / src.height;
3134                        } else {
3135                                /* width needs less upscaling/more downscaling */
3136                                dst.height = src.height *
3137                                                dst.width / src.width;
3138                        }
3139                } else if (rmx_type == RMX_CENTER) {
3140                        dst = src;
3141                }
3142
3143                dst.x = (stream->timing.h_addressable - dst.width) / 2;
3144                dst.y = (stream->timing.v_addressable - dst.height) / 2;
3145
3146                if (dm_state->underscan_enable) {
3147                        dst.x += dm_state->underscan_hborder / 2;
3148                        dst.y += dm_state->underscan_vborder / 2;
3149                        dst.width -= dm_state->underscan_hborder;
3150                        dst.height -= dm_state->underscan_vborder;
3151                }
3152        }
3153
3154        stream->src = src;
3155        stream->dst = dst;
3156
3157        DRM_DEBUG_DRIVER("Destination Rectangle x:%d  y:%d  width:%d  height:%d\n",
3158                        dst.x, dst.y, dst.width, dst.height);
3159
3160}
3161
3162static enum dc_color_depth
3163convert_color_depth_from_display_info(const struct drm_connector *connector,
3164                                      const struct drm_connector_state *state)
3165{
3166        uint8_t bpc = (uint8_t)connector->display_info.bpc;
3167
3168        /* Assume 8 bpc by default if no bpc is specified. */
3169        bpc = bpc ? bpc : 8;
3170
3171        if (!state)
3172                state = connector->state;
3173
3174        if (state) {
3175                /*
3176                 * Cap display bpc based on the user requested value.
3177                 *
3178                 * The value for state->max_bpc may not correctly updated
3179                 * depending on when the connector gets added to the state
3180                 * or if this was called outside of atomic check, so it
3181                 * can't be used directly.
3182                 */
3183                bpc = min(bpc, state->max_requested_bpc);
3184
3185                /* Round down to the nearest even number. */
3186                bpc = bpc - (bpc & 1);
3187        }
3188
3189        switch (bpc) {
3190        case 0:
3191                /*
3192                 * Temporary Work around, DRM doesn't parse color depth for
3193                 * EDID revision before 1.4
3194                 * TODO: Fix edid parsing
3195                 */
3196                return COLOR_DEPTH_888;
3197        case 6:
3198                return COLOR_DEPTH_666;
3199        case 8:
3200                return COLOR_DEPTH_888;
3201        case 10:
3202                return COLOR_DEPTH_101010;
3203        case 12:
3204                return COLOR_DEPTH_121212;
3205        case 14:
3206                return COLOR_DEPTH_141414;
3207        case 16:
3208                return COLOR_DEPTH_161616;
3209        default:
3210                return COLOR_DEPTH_UNDEFINED;
3211        }
3212}
3213
3214static enum dc_aspect_ratio
3215get_aspect_ratio(const struct drm_display_mode *mode_in)
3216{
3217        /* 1-1 mapping, since both enums follow the HDMI spec. */
3218        return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio;
3219}
3220
3221static enum dc_color_space
3222get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing)
3223{
3224        enum dc_color_space color_space = COLOR_SPACE_SRGB;
3225
3226        switch (dc_crtc_timing->pixel_encoding) {
3227        case PIXEL_ENCODING_YCBCR422:
3228        case PIXEL_ENCODING_YCBCR444:
3229        case PIXEL_ENCODING_YCBCR420:
3230        {
3231                /*
3232                 * 27030khz is the separation point between HDTV and SDTV
3233                 * according to HDMI spec, we use YCbCr709 and YCbCr601
3234                 * respectively
3235                 */
3236                if (dc_crtc_timing->pix_clk_100hz > 270300) {
3237                        if (dc_crtc_timing->flags.Y_ONLY)
3238                                color_space =
3239                                        COLOR_SPACE_YCBCR709_LIMITED;
3240                        else
3241                                color_space = COLOR_SPACE_YCBCR709;
3242                } else {
3243                        if (dc_crtc_timing->flags.Y_ONLY)
3244                                color_space =
3245                                        COLOR_SPACE_YCBCR601_LIMITED;
3246                        else
3247                                color_space = COLOR_SPACE_YCBCR601;
3248                }
3249
3250        }
3251        break;
3252        case PIXEL_ENCODING_RGB:
3253                color_space = COLOR_SPACE_SRGB;
3254                break;
3255
3256        default:
3257                WARN_ON(1);
3258                break;
3259        }
3260
3261        return color_space;
3262}
3263
3264static void reduce_mode_colour_depth(struct dc_crtc_timing *timing_out)
3265{
3266        if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3267                return;
3268
3269        timing_out->display_color_depth--;
3270}
3271
3272static void adjust_colour_depth_from_display_info(struct dc_crtc_timing *timing_out,
3273                                                const struct drm_display_info *info)
3274{
3275        int normalized_clk;
3276        if (timing_out->display_color_depth <= COLOR_DEPTH_888)
3277                return;
3278        do {
3279                normalized_clk = timing_out->pix_clk_100hz / 10;
3280                /* YCbCr 4:2:0 requires additional adjustment of 1/2 */
3281                if (timing_out->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3282                        normalized_clk /= 2;
3283                /* Adjusting pix clock following on HDMI spec based on colour depth */
3284                switch (timing_out->display_color_depth) {
3285                case COLOR_DEPTH_101010:
3286                        normalized_clk = (normalized_clk * 30) / 24;
3287                        break;
3288                case COLOR_DEPTH_121212:
3289                        normalized_clk = (normalized_clk * 36) / 24;
3290                        break;
3291                case COLOR_DEPTH_161616:
3292                        normalized_clk = (normalized_clk * 48) / 24;
3293                        break;
3294                default:
3295                        return;
3296                }
3297                if (normalized_clk <= info->max_tmds_clock)
3298                        return;
3299                reduce_mode_colour_depth(timing_out);
3300
3301        } while (timing_out->display_color_depth > COLOR_DEPTH_888);
3302
3303}
3304
3305static void fill_stream_properties_from_drm_display_mode(
3306        struct dc_stream_state *stream,
3307        const struct drm_display_mode *mode_in,
3308        const struct drm_connector *connector,
3309        const struct drm_connector_state *connector_state,
3310        const struct dc_stream_state *old_stream)
3311{
3312        struct dc_crtc_timing *timing_out = &stream->timing;
3313        const struct drm_display_info *info = &connector->display_info;
3314
3315        memset(timing_out, 0, sizeof(struct dc_crtc_timing));
3316
3317        timing_out->h_border_left = 0;
3318        timing_out->h_border_right = 0;
3319        timing_out->v_border_top = 0;
3320        timing_out->v_border_bottom = 0;
3321        /* TODO: un-hardcode */
3322        if (drm_mode_is_420_only(info, mode_in)
3323                        && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3324                timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR420;
3325        else if ((connector->display_info.color_formats & DRM_COLOR_FORMAT_YCRCB444)
3326                        && stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3327                timing_out->pixel_encoding = PIXEL_ENCODING_YCBCR444;
3328        else
3329                timing_out->pixel_encoding = PIXEL_ENCODING_RGB;
3330
3331        timing_out->timing_3d_format = TIMING_3D_FORMAT_NONE;
3332        timing_out->display_color_depth = convert_color_depth_from_display_info(
3333                connector, connector_state);
3334        timing_out->scan_type = SCANNING_TYPE_NODATA;
3335        timing_out->hdmi_vic = 0;
3336
3337        if(old_stream) {
3338                timing_out->vic = old_stream->timing.vic;
3339                timing_out->flags.HSYNC_POSITIVE_POLARITY = old_stream->timing.flags.HSYNC_POSITIVE_POLARITY;
3340                timing_out->flags.VSYNC_POSITIVE_POLARITY = old_stream->timing.flags.VSYNC_POSITIVE_POLARITY;
3341        } else {
3342                timing_out->vic = drm_match_cea_mode(mode_in);
3343                if (mode_in->flags & DRM_MODE_FLAG_PHSYNC)
3344                        timing_out->flags.HSYNC_POSITIVE_POLARITY = 1;
3345                if (mode_in->flags & DRM_MODE_FLAG_PVSYNC)
3346                        timing_out->flags.VSYNC_POSITIVE_POLARITY = 1;
3347        }
3348
3349        timing_out->h_addressable = mode_in->crtc_hdisplay;
3350        timing_out->h_total = mode_in->crtc_htotal;
3351        timing_out->h_sync_width =
3352                mode_in->crtc_hsync_end - mode_in->crtc_hsync_start;
3353        timing_out->h_front_porch =
3354                mode_in->crtc_hsync_start - mode_in->crtc_hdisplay;
3355        timing_out->v_total = mode_in->crtc_vtotal;
3356        timing_out->v_addressable = mode_in->crtc_vdisplay;
3357        timing_out->v_front_porch =
3358                mode_in->crtc_vsync_start - mode_in->crtc_vdisplay;
3359        timing_out->v_sync_width =
3360                mode_in->crtc_vsync_end - mode_in->crtc_vsync_start;
3361        timing_out->pix_clk_100hz = mode_in->crtc_clock * 10;
3362        timing_out->aspect_ratio = get_aspect_ratio(mode_in);
3363
3364        stream->output_color_space = get_output_color_space(timing_out);
3365
3366        stream->out_transfer_func->type = TF_TYPE_PREDEFINED;
3367        stream->out_transfer_func->tf = TRANSFER_FUNCTION_SRGB;
3368        if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A)
3369                adjust_colour_depth_from_display_info(timing_out, info);
3370}
3371
3372static void fill_audio_info(struct audio_info *audio_info,
3373                            const struct drm_connector *drm_connector,
3374                            const struct dc_sink *dc_sink)
3375{
3376        int i = 0;
3377        int cea_revision = 0;
3378        const struct dc_edid_caps *edid_caps = &dc_sink->edid_caps;
3379
3380        audio_info->manufacture_id = edid_caps->manufacturer_id;
3381        audio_info->product_id = edid_caps->product_id;
3382
3383        cea_revision = drm_connector->display_info.cea_rev;
3384
3385        strscpy(audio_info->display_name,
3386                edid_caps->display_name,
3387                AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS);
3388
3389        if (cea_revision >= 3) {
3390                audio_info->mode_count = edid_caps->audio_mode_count;
3391
3392                for (i = 0; i < audio_info->mode_count; ++i) {
3393                        audio_info->modes[i].format_code =
3394                                        (enum audio_format_code)
3395                                        (edid_caps->audio_modes[i].format_code);
3396                        audio_info->modes[i].channel_count =
3397                                        edid_caps->audio_modes[i].channel_count;
3398                        audio_info->modes[i].sample_rates.all =
3399                                        edid_caps->audio_modes[i].sample_rate;
3400                        audio_info->modes[i].sample_size =
3401                                        edid_caps->audio_modes[i].sample_size;
3402                }
3403        }
3404
3405        audio_info->flags.all = edid_caps->speaker_flags;
3406
3407        /* TODO: We only check for the progressive mode, check for interlace mode too */
3408        if (drm_connector->latency_present[0]) {
3409                audio_info->video_latency = drm_connector->video_latency[0];
3410                audio_info->audio_latency = drm_connector->audio_latency[0];
3411        }
3412
3413        /* TODO: For DP, video and audio latency should be calculated from DPCD caps */
3414
3415}
3416
3417static void
3418copy_crtc_timing_for_drm_display_mode(const struct drm_display_mode *src_mode,
3419                                      struct drm_display_mode *dst_mode)
3420{
3421        dst_mode->crtc_hdisplay = src_mode->crtc_hdisplay;
3422        dst_mode->crtc_vdisplay = src_mode->crtc_vdisplay;
3423        dst_mode->crtc_clock = src_mode->crtc_clock;
3424        dst_mode->crtc_hblank_start = src_mode->crtc_hblank_start;
3425        dst_mode->crtc_hblank_end = src_mode->crtc_hblank_end;
3426        dst_mode->crtc_hsync_start =  src_mode->crtc_hsync_start;
3427        dst_mode->crtc_hsync_end = src_mode->crtc_hsync_end;
3428        dst_mode->crtc_htotal = src_mode->crtc_htotal;
3429        dst_mode->crtc_hskew = src_mode->crtc_hskew;
3430        dst_mode->crtc_vblank_start = src_mode->crtc_vblank_start;
3431        dst_mode->crtc_vblank_end = src_mode->crtc_vblank_end;
3432        dst_mode->crtc_vsync_start = src_mode->crtc_vsync_start;
3433        dst_mode->crtc_vsync_end = src_mode->crtc_vsync_end;
3434        dst_mode->crtc_vtotal = src_mode->crtc_vtotal;
3435}
3436
3437static void
3438decide_crtc_timing_for_drm_display_mode(struct drm_display_mode *drm_mode,
3439                                        const struct drm_display_mode *native_mode,
3440                                        bool scale_enabled)
3441{
3442        if (scale_enabled) {
3443                copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3444        } else if (native_mode->clock == drm_mode->clock &&
3445                        native_mode->htotal == drm_mode->htotal &&
3446                        native_mode->vtotal == drm_mode->vtotal) {
3447                copy_crtc_timing_for_drm_display_mode(native_mode, drm_mode);
3448        } else {
3449                /* no scaling nor amdgpu inserted, no need to patch */
3450        }
3451}
3452
3453static struct dc_sink *
3454create_fake_sink(struct amdgpu_dm_connector *aconnector)
3455{
3456        struct dc_sink_init_data sink_init_data = { 0 };
3457        struct dc_sink *sink = NULL;
3458        sink_init_data.link = aconnector->dc_link;
3459        sink_init_data.sink_signal = aconnector->dc_link->connector_signal;
3460
3461        sink = dc_sink_create(&sink_init_data);
3462        if (!sink) {
3463                DRM_ERROR("Failed to create sink!\n");
3464                return NULL;
3465        }
3466        sink->sink_signal = SIGNAL_TYPE_VIRTUAL;
3467
3468        return sink;
3469}
3470
3471static void set_multisync_trigger_params(
3472                struct dc_stream_state *stream)
3473{
3474        if (stream->triggered_crtc_reset.enabled) {
3475                stream->triggered_crtc_reset.event = CRTC_EVENT_VSYNC_RISING;
3476                stream->triggered_crtc_reset.delay = TRIGGER_DELAY_NEXT_LINE;
3477        }
3478}
3479
3480static void set_master_stream(struct dc_stream_state *stream_set[],
3481                              int stream_count)
3482{
3483        int j, highest_rfr = 0, master_stream = 0;
3484
3485        for (j = 0;  j < stream_count; j++) {
3486                if (stream_set[j] && stream_set[j]->triggered_crtc_reset.enabled) {
3487                        int refresh_rate = 0;
3488
3489                        refresh_rate = (stream_set[j]->timing.pix_clk_100hz*100)/
3490                                (stream_set[j]->timing.h_total*stream_set[j]->timing.v_total);
3491                        if (refresh_rate > highest_rfr) {
3492                                highest_rfr = refresh_rate;
3493                                master_stream = j;
3494                        }
3495                }
3496        }
3497        for (j = 0;  j < stream_count; j++) {
3498                if (stream_set[j])
3499                        stream_set[j]->triggered_crtc_reset.event_source = stream_set[master_stream];
3500        }
3501}
3502
3503static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context)
3504{
3505        int i = 0;
3506
3507        if (context->stream_count < 2)
3508                return;
3509        for (i = 0; i < context->stream_count ; i++) {
3510                if (!context->streams[i])
3511                        continue;
3512                /*
3513                 * TODO: add a function to read AMD VSDB bits and set
3514                 * crtc_sync_master.multi_sync_enabled flag
3515                 * For now it's set to false
3516                 */
3517                set_multisync_trigger_params(context->streams[i]);
3518        }
3519        set_master_stream(context->streams, context->stream_count);
3520}
3521
3522static struct dc_stream_state *
3523create_stream_for_sink(struct amdgpu_dm_connector *aconnector,
3524                       const struct drm_display_mode *drm_mode,
3525                       const struct dm_connector_state *dm_state,
3526                       const struct dc_stream_state *old_stream)
3527{
3528        struct drm_display_mode *preferred_mode = NULL;
3529        struct drm_connector *drm_connector;
3530        const struct drm_connector_state *con_state =
3531                dm_state ? &dm_state->base : NULL;
3532        struct dc_stream_state *stream = NULL;
3533        struct drm_display_mode mode = *drm_mode;
3534        bool native_mode_found = false;
3535        bool scale = dm_state ? (dm_state->scaling != RMX_OFF) : false;
3536        int mode_refresh;
3537        int preferred_refresh = 0;
3538#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3539        struct dsc_dec_dpcd_caps dsc_caps;
3540        uint32_t link_bandwidth_kbps;
3541#endif
3542
3543        struct dc_sink *sink = NULL;
3544        if (aconnector == NULL) {
3545                DRM_ERROR("aconnector is NULL!\n");
3546                return stream;
3547        }
3548
3549        drm_connector = &aconnector->base;
3550
3551        if (!aconnector->dc_sink) {
3552                sink = create_fake_sink(aconnector);
3553                if (!sink)
3554                        return stream;
3555        } else {
3556                sink = aconnector->dc_sink;
3557                dc_sink_retain(sink);
3558        }
3559
3560        stream = dc_create_stream_for_sink(sink);
3561
3562        if (stream == NULL) {
3563                DRM_ERROR("Failed to create stream for sink!\n");
3564                goto finish;
3565        }
3566
3567        stream->dm_stream_context = aconnector;
3568
3569        list_for_each_entry(preferred_mode, &aconnector->base.modes, head) {
3570                /* Search for preferred mode */
3571                if (preferred_mode->type & DRM_MODE_TYPE_PREFERRED) {
3572                        native_mode_found = true;
3573                        break;
3574                }
3575        }
3576        if (!native_mode_found)
3577                preferred_mode = list_first_entry_or_null(
3578                                &aconnector->base.modes,
3579                                struct drm_display_mode,
3580                                head);
3581
3582        mode_refresh = drm_mode_vrefresh(&mode);
3583
3584        if (preferred_mode == NULL) {
3585                /*
3586                 * This may not be an error, the use case is when we have no
3587                 * usermode calls to reset and set mode upon hotplug. In this
3588                 * case, we call set mode ourselves to restore the previous mode
3589                 * and the modelist may not be filled in in time.
3590                 */
3591                DRM_DEBUG_DRIVER("No preferred mode found\n");
3592        } else {
3593                decide_crtc_timing_for_drm_display_mode(
3594                                &mode, preferred_mode,
3595                                dm_state ? (dm_state->scaling != RMX_OFF) : false);
3596                preferred_refresh = drm_mode_vrefresh(preferred_mode);
3597        }
3598
3599        if (!dm_state)
3600                drm_mode_set_crtcinfo(&mode, 0);
3601
3602        /*
3603        * If scaling is enabled and refresh rate didn't change
3604        * we copy the vic and polarities of the old timings
3605        */
3606        if (!scale || mode_refresh != preferred_refresh)
3607                fill_stream_properties_from_drm_display_mode(stream,
3608                        &mode, &aconnector->base, con_state, NULL);
3609        else
3610                fill_stream_properties_from_drm_display_mode(stream,
3611                        &mode, &aconnector->base, con_state, old_stream);
3612
3613#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
3614        stream->timing.flags.DSC = 0;
3615
3616        if (aconnector->dc_link && sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT) {
3617                dc_dsc_parse_dsc_dpcd(aconnector->dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.raw,
3618                                      aconnector->dc_link->dpcd_caps.dsc_caps.dsc_ext_caps.raw,
3619                                      &dsc_caps);
3620                link_bandwidth_kbps = dc_link_bandwidth_kbps(aconnector->dc_link,
3621                                                             dc_link_get_link_cap(aconnector->dc_link));
3622
3623                if (dsc_caps.is_dsc_supported)
3624                        if (dc_dsc_compute_config(aconnector->dc_link->ctx->dc,
3625                                                  &dsc_caps,
3626                                                  link_bandwidth_kbps,
3627                                                  &stream->timing,
3628                                                  &stream->timing.dsc_cfg))
3629                                stream->timing.flags.DSC = 1;
3630        }
3631#endif
3632
3633        update_stream_scaling_settings(&mode, dm_state, stream);
3634
3635        fill_audio_info(
3636                &stream->audio_info,
3637                drm_connector,
3638                sink);
3639
3640        update_stream_signal(stream, sink);
3641
3642finish:
3643        dc_sink_release(sink);
3644
3645        return stream;
3646}
3647
3648static void amdgpu_dm_crtc_destroy(struct drm_crtc *crtc)
3649{
3650        drm_crtc_cleanup(crtc);
3651        kfree(crtc);
3652}
3653
3654static void dm_crtc_destroy_state(struct drm_crtc *crtc,
3655                                  struct drm_crtc_state *state)
3656{
3657        struct dm_crtc_state *cur = to_dm_crtc_state(state);
3658
3659        /* TODO Destroy dc_stream objects are stream object is flattened */
3660        if (cur->stream)
3661                dc_stream_release(cur->stream);
3662
3663
3664        __drm_atomic_helper_crtc_destroy_state(state);
3665
3666
3667        kfree(state);
3668}
3669
3670static void dm_crtc_reset_state(struct drm_crtc *crtc)
3671{
3672        struct dm_crtc_state *state;
3673
3674        if (crtc->state)
3675                dm_crtc_destroy_state(crtc, crtc->state);
3676
3677        state = kzalloc(sizeof(*state), GFP_KERNEL);
3678        if (WARN_ON(!state))
3679                return;
3680
3681        crtc->state = &state->base;
3682        crtc->state->crtc = crtc;
3683
3684}
3685
3686static struct drm_crtc_state *
3687dm_crtc_duplicate_state(struct drm_crtc *crtc)
3688{
3689        struct dm_crtc_state *state, *cur;
3690
3691        cur = to_dm_crtc_state(crtc->state);
3692
3693        if (WARN_ON(!crtc->state))
3694                return NULL;
3695
3696        state = kzalloc(sizeof(*state), GFP_KERNEL);
3697        if (!state)
3698                return NULL;
3699
3700        __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
3701
3702        if (cur->stream) {
3703                state->stream = cur->stream;
3704                dc_stream_retain(state->stream);
3705        }
3706
3707        state->active_planes = cur->active_planes;
3708        state->interrupts_enabled = cur->interrupts_enabled;
3709        state->vrr_params = cur->vrr_params;
3710        state->vrr_infopacket = cur->vrr_infopacket;
3711        state->abm_level = cur->abm_level;
3712        state->vrr_supported = cur->vrr_supported;
3713        state->freesync_config = cur->freesync_config;
3714        state->crc_src = cur->crc_src;
3715        state->cm_has_degamma = cur->cm_has_degamma;
3716        state->cm_is_degamma_srgb = cur->cm_is_degamma_srgb;
3717
3718        /* TODO Duplicate dc_stream after objects are stream object is flattened */
3719
3720        return &state->base;
3721}
3722
3723static inline int dm_set_vupdate_irq(struct drm_crtc *crtc, bool enable)
3724{
3725        enum dc_irq_source irq_source;
3726        struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3727        struct amdgpu_device *adev = crtc->dev->dev_private;
3728        int rc;
3729
3730        irq_source = IRQ_TYPE_VUPDATE + acrtc->otg_inst;
3731
3732        rc = dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3733
3734        DRM_DEBUG_DRIVER("crtc %d - vupdate irq %sabling: r=%d\n",
3735                         acrtc->crtc_id, enable ? "en" : "dis", rc);
3736        return rc;
3737}
3738
3739static inline int dm_set_vblank(struct drm_crtc *crtc, bool enable)
3740{
3741        enum dc_irq_source irq_source;
3742        struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
3743        struct amdgpu_device *adev = crtc->dev->dev_private;
3744        struct dm_crtc_state *acrtc_state = to_dm_crtc_state(crtc->state);
3745        int rc = 0;
3746
3747        if (enable) {
3748                /* vblank irq on -> Only need vupdate irq in vrr mode */
3749                if (amdgpu_dm_vrr_active(acrtc_state))
3750                        rc = dm_set_vupdate_irq(crtc, true);
3751        } else {
3752                /* vblank irq off -> vupdate irq off */
3753                rc = dm_set_vupdate_irq(crtc, false);
3754        }
3755
3756        if (rc)
3757                return rc;
3758
3759        irq_source = IRQ_TYPE_VBLANK + acrtc->otg_inst;
3760        return dc_interrupt_set(adev->dm.dc, irq_source, enable) ? 0 : -EBUSY;
3761}
3762
3763static int dm_enable_vblank(struct drm_crtc *crtc)
3764{
3765        return dm_set_vblank(crtc, true);
3766}
3767
3768static void dm_disable_vblank(struct drm_crtc *crtc)
3769{
3770        dm_set_vblank(crtc, false);
3771}
3772
3773/* Implemented only the options currently availible for the driver */
3774static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = {
3775        .reset = dm_crtc_reset_state,
3776        .destroy = amdgpu_dm_crtc_destroy,
3777        .gamma_set = drm_atomic_helper_legacy_gamma_set,
3778        .set_config = drm_atomic_helper_set_config,
3779        .page_flip = drm_atomic_helper_page_flip,
3780        .atomic_duplicate_state = dm_crtc_duplicate_state,
3781        .atomic_destroy_state = dm_crtc_destroy_state,
3782        .set_crc_source = amdgpu_dm_crtc_set_crc_source,
3783        .verify_crc_source = amdgpu_dm_crtc_verify_crc_source,
3784        .get_crc_sources = amdgpu_dm_crtc_get_crc_sources,
3785        .enable_vblank = dm_enable_vblank,
3786        .disable_vblank = dm_disable_vblank,
3787};
3788
3789static enum drm_connector_status
3790amdgpu_dm_connector_detect(struct drm_connector *connector, bool force)
3791{
3792        bool connected;
3793        struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3794
3795        /*
3796         * Notes:
3797         * 1. This interface is NOT called in context of HPD irq.
3798         * 2. This interface *is called* in context of user-mode ioctl. Which
3799         * makes it a bad place for *any* MST-related activity.
3800         */
3801
3802        if (aconnector->base.force == DRM_FORCE_UNSPECIFIED &&
3803            !aconnector->fake_enable)
3804                connected = (aconnector->dc_sink != NULL);
3805        else
3806                connected = (aconnector->base.force == DRM_FORCE_ON);
3807
3808        return (connected ? connector_status_connected :
3809                        connector_status_disconnected);
3810}
3811
3812int amdgpu_dm_connector_atomic_set_property(struct drm_connector *connector,
3813                                            struct drm_connector_state *connector_state,
3814                                            struct drm_property *property,
3815                                            uint64_t val)
3816{
3817        struct drm_device *dev = connector->dev;
3818        struct amdgpu_device *adev = dev->dev_private;
3819        struct dm_connector_state *dm_old_state =
3820                to_dm_connector_state(connector->state);
3821        struct dm_connector_state *dm_new_state =
3822                to_dm_connector_state(connector_state);
3823
3824        int ret = -EINVAL;
3825
3826        if (property == dev->mode_config.scaling_mode_property) {
3827                enum amdgpu_rmx_type rmx_type;
3828
3829                switch (val) {
3830                case DRM_MODE_SCALE_CENTER:
3831                        rmx_type = RMX_CENTER;
3832                        break;
3833                case DRM_MODE_SCALE_ASPECT:
3834                        rmx_type = RMX_ASPECT;
3835                        break;
3836                case DRM_MODE_SCALE_FULLSCREEN:
3837                        rmx_type = RMX_FULL;
3838                        break;
3839                case DRM_MODE_SCALE_NONE:
3840                default:
3841                        rmx_type = RMX_OFF;
3842                        break;
3843                }
3844
3845                if (dm_old_state->scaling == rmx_type)
3846                        return 0;
3847
3848                dm_new_state->scaling = rmx_type;
3849                ret = 0;
3850        } else if (property == adev->mode_info.underscan_hborder_property) {
3851                dm_new_state->underscan_hborder = val;
3852                ret = 0;
3853        } else if (property == adev->mode_info.underscan_vborder_property) {
3854                dm_new_state->underscan_vborder = val;
3855                ret = 0;
3856        } else if (property == adev->mode_info.underscan_property) {
3857                dm_new_state->underscan_enable = val;
3858                ret = 0;
3859        } else if (property == adev->mode_info.abm_level_property) {
3860                dm_new_state->abm_level = val;
3861                ret = 0;
3862        }
3863
3864        return ret;
3865}
3866
3867int amdgpu_dm_connector_atomic_get_property(struct drm_connector *connector,
3868                                            const struct drm_connector_state *state,
3869                                            struct drm_property *property,
3870                                            uint64_t *val)
3871{
3872        struct drm_device *dev = connector->dev;
3873        struct amdgpu_device *adev = dev->dev_private;
3874        struct dm_connector_state *dm_state =
3875                to_dm_connector_state(state);
3876        int ret = -EINVAL;
3877
3878        if (property == dev->mode_config.scaling_mode_property) {
3879                switch (dm_state->scaling) {
3880                case RMX_CENTER:
3881                        *val = DRM_MODE_SCALE_CENTER;
3882                        break;
3883                case RMX_ASPECT:
3884                        *val = DRM_MODE_SCALE_ASPECT;
3885                        break;
3886                case RMX_FULL:
3887                        *val = DRM_MODE_SCALE_FULLSCREEN;
3888                        break;
3889                case RMX_OFF:
3890                default:
3891                        *val = DRM_MODE_SCALE_NONE;
3892                        break;
3893                }
3894                ret = 0;
3895        } else if (property == adev->mode_info.underscan_hborder_property) {
3896                *val = dm_state->underscan_hborder;
3897                ret = 0;
3898        } else if (property == adev->mode_info.underscan_vborder_property) {
3899                *val = dm_state->underscan_vborder;
3900                ret = 0;
3901        } else if (property == adev->mode_info.underscan_property) {
3902                *val = dm_state->underscan_enable;
3903                ret = 0;
3904        } else if (property == adev->mode_info.abm_level_property) {
3905                *val = dm_state->abm_level;
3906                ret = 0;
3907        }
3908
3909        return ret;
3910}
3911
3912static void amdgpu_dm_connector_unregister(struct drm_connector *connector)
3913{
3914        struct amdgpu_dm_connector *amdgpu_dm_connector = to_amdgpu_dm_connector(connector);
3915
3916        drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux);
3917}
3918
3919static void amdgpu_dm_connector_destroy(struct drm_connector *connector)
3920{
3921        struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
3922        const struct dc_link *link = aconnector->dc_link;
3923        struct amdgpu_device *adev = connector->dev->dev_private;
3924        struct amdgpu_display_manager *dm = &adev->dm;
3925
3926#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) ||\
3927        defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
3928
3929        if ((link->connector_signal & (SIGNAL_TYPE_EDP | SIGNAL_TYPE_LVDS)) &&
3930            link->type != dc_connection_none &&
3931            dm->backlight_dev) {
3932                backlight_device_unregister(dm->backlight_dev);
3933                dm->backlight_dev = NULL;
3934        }
3935#endif
3936
3937        if (aconnector->dc_em_sink)
3938                dc_sink_release(aconnector->dc_em_sink);
3939        aconnector->dc_em_sink = NULL;
3940        if (aconnector->dc_sink)
3941                dc_sink_release(aconnector->dc_sink);
3942        aconnector->dc_sink = NULL;
3943
3944        drm_dp_cec_unregister_connector(&aconnector->dm_dp_aux.aux);
3945        drm_connector_unregister(connector);
3946        drm_connector_cleanup(connector);
3947        if (aconnector->i2c) {
3948                i2c_del_adapter(&aconnector->i2c->base);
3949                kfree(aconnector->i2c);
3950        }
3951
3952        kfree(connector);
3953}
3954
3955void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector)
3956{
3957        struct dm_connector_state *state =
3958                to_dm_connector_state(connector->state);
3959
3960        if (connector->state)
3961                __drm_atomic_helper_connector_destroy_state(connector->state);
3962
3963        kfree(state);
3964
3965        state = kzalloc(sizeof(*state), GFP_KERNEL);
3966
3967        if (state) {
3968                state->scaling = RMX_OFF;
3969                state->underscan_enable = false;
3970                state->underscan_hborder = 0;
3971                state->underscan_vborder = 0;
3972                state->base.max_requested_bpc = 8;
3973
3974                if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3975                        state->abm_level = amdgpu_dm_abm_level;
3976
3977                __drm_atomic_helper_connector_reset(connector, &state->base);
3978        }
3979}
3980
3981struct drm_connector_state *
3982amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector)
3983{
3984        struct dm_connector_state *state =
3985                to_dm_connector_state(connector->state);
3986
3987        struct dm_connector_state *new_state =
3988                        kmemdup(state, sizeof(*state), GFP_KERNEL);
3989
3990        if (!new_state)
3991                return NULL;
3992
3993        __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base);
3994
3995        new_state->freesync_capable = state->freesync_capable;
3996        new_state->abm_level = state->abm_level;
3997        new_state->scaling = state->scaling;
3998        new_state->underscan_enable = state->underscan_enable;
3999        new_state->underscan_hborder = state->underscan_hborder;
4000        new_state->underscan_vborder = state->underscan_vborder;
4001
4002        return &new_state->base;
4003}
4004
4005static const struct drm_connector_funcs amdgpu_dm_connector_funcs = {
4006        .reset = amdgpu_dm_connector_funcs_reset,
4007        .detect = amdgpu_dm_connector_detect,
4008        .fill_modes = drm_helper_probe_single_connector_modes,
4009        .destroy = amdgpu_dm_connector_destroy,
4010        .atomic_duplicate_state = amdgpu_dm_connector_atomic_duplicate_state,
4011        .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4012        .atomic_set_property = amdgpu_dm_connector_atomic_set_property,
4013        .atomic_get_property = amdgpu_dm_connector_atomic_get_property,
4014        .early_unregister = amdgpu_dm_connector_unregister
4015};
4016
4017static int get_modes(struct drm_connector *connector)
4018{
4019        return amdgpu_dm_connector_get_modes(connector);
4020}
4021
4022static void create_eml_sink(struct amdgpu_dm_connector *aconnector)
4023{
4024        struct dc_sink_init_data init_params = {
4025                        .link = aconnector->dc_link,
4026                        .sink_signal = SIGNAL_TYPE_VIRTUAL
4027        };
4028        struct edid *edid;
4029
4030        if (!aconnector->base.edid_blob_ptr) {
4031                DRM_ERROR("No EDID firmware found on connector: %s ,forcing to OFF!\n",
4032                                aconnector->base.name);
4033
4034                aconnector->base.force = DRM_FORCE_OFF;
4035                aconnector->base.override_edid = false;
4036                return;
4037        }
4038
4039        edid = (struct edid *) aconnector->base.edid_blob_ptr->data;
4040
4041        aconnector->edid = edid;
4042
4043        aconnector->dc_em_sink = dc_link_add_remote_sink(
4044                aconnector->dc_link,
4045                (uint8_t *)edid,
4046                (edid->extensions + 1) * EDID_LENGTH,
4047                &init_params);
4048
4049        if (aconnector->base.force == DRM_FORCE_ON) {
4050                aconnector->dc_sink = aconnector->dc_link->local_sink ?
4051                aconnector->dc_link->local_sink :
4052                aconnector->dc_em_sink;
4053                dc_sink_retain(aconnector->dc_sink);
4054        }
4055}
4056
4057static void handle_edid_mgmt(struct amdgpu_dm_connector *aconnector)
4058{
4059        struct dc_link *link = (struct dc_link *)aconnector->dc_link;
4060
4061        /*
4062         * In case of headless boot with force on for DP managed connector
4063         * Those settings have to be != 0 to get initial modeset
4064         */
4065        if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT) {
4066                link->verified_link_cap.lane_count = LANE_COUNT_FOUR;
4067                link->verified_link_cap.link_rate = LINK_RATE_HIGH2;
4068        }
4069
4070
4071        aconnector->base.override_edid = true;
4072        create_eml_sink(aconnector);
4073}
4074
4075enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connector,
4076                                   struct drm_display_mode *mode)
4077{
4078        int result = MODE_ERROR;
4079        struct dc_sink *dc_sink;
4080        struct amdgpu_device *adev = connector->dev->dev_private;
4081        /* TODO: Unhardcode stream count */
4082        struct dc_stream_state *stream;
4083        struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
4084        enum dc_status dc_result = DC_OK;
4085
4086        if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
4087                        (mode->flags & DRM_MODE_FLAG_DBLSCAN))
4088                return result;
4089
4090        /*
4091         * Only run this the first time mode_valid is called to initilialize
4092         * EDID mgmt
4093         */
4094        if (aconnector->base.force != DRM_FORCE_UNSPECIFIED &&
4095                !aconnector->dc_em_sink)
4096                handle_edid_mgmt(aconnector);
4097
4098        dc_sink = to_amdgpu_dm_connector(connector)->dc_sink;
4099
4100        if (dc_sink == NULL) {
4101                DRM_ERROR("dc_sink is NULL!\n");
4102                goto fail;
4103        }
4104
4105        stream = create_stream_for_sink(aconnector, mode, NULL, NULL);
4106        if (stream == NULL) {
4107                DRM_ERROR("Failed to create stream for sink!\n");
4108                goto fail;
4109        }
4110
4111        dc_result = dc_validate_stream(adev->dm.dc, stream);
4112
4113        if (dc_result == DC_OK)
4114                result = MODE_OK;
4115        else
4116                DRM_DEBUG_KMS("Mode %dx%d (clk %d) failed DC validation with error %d\n",
4117                              mode->vdisplay,
4118                              mode->hdisplay,
4119                              mode->clock,
4120                              dc_result);
4121
4122        dc_stream_release(stream);
4123
4124fail:
4125        /* TODO: error handling*/
4126        return result;
4127}
4128
4129static int fill_hdr_info_packet(const struct drm_connector_state *state,
4130                                struct dc_info_packet *out)
4131{
4132        struct hdmi_drm_infoframe frame;
4133        unsigned char buf[30]; /* 26 + 4 */
4134        ssize_t len;
4135        int ret, i;
4136
4137        memset(out, 0, sizeof(*out));
4138
4139        if (!state->hdr_output_metadata)
4140                return 0;
4141
4142        ret = drm_hdmi_infoframe_set_hdr_metadata(&frame, state);
4143        if (ret)
4144                return ret;
4145
4146        len = hdmi_drm_infoframe_pack_only(&frame, buf, sizeof(buf));
4147        if (len < 0)
4148                return (int)len;
4149
4150        /* Static metadata is a fixed 26 bytes + 4 byte header. */
4151        if (len != 30)
4152                return -EINVAL;
4153
4154        /* Prepare the infopacket for DC. */
4155        switch (state->connector->connector_type) {
4156        case DRM_MODE_CONNECTOR_HDMIA:
4157                out->hb0 = 0x87; /* type */
4158                out->hb1 = 0x01; /* version */
4159                out->hb2 = 0x1A; /* length */
4160                out->sb[0] = buf[3]; /* checksum */
4161                i = 1;
4162                break;
4163
4164        case DRM_MODE_CONNECTOR_DisplayPort:
4165        case DRM_MODE_CONNECTOR_eDP:
4166                out->hb0 = 0x00; /* sdp id, zero */
4167                out->hb1 = 0x87; /* type */
4168                out->hb2 = 0x1D; /* payload len - 1 */
4169                out->hb3 = (0x13 << 2); /* sdp version */
4170                out->sb[0] = 0x01; /* version */
4171                out->sb[1] = 0x1A; /* length */
4172                i = 2;
4173                break;
4174
4175        default:
4176                return -EINVAL;
4177        }
4178
4179        memcpy(&out->sb[i], &buf[4], 26);
4180        out->valid = true;
4181
4182        print_hex_dump(KERN_DEBUG, "HDR SB:", DUMP_PREFIX_NONE, 16, 1, out->sb,
4183                       sizeof(out->sb), false);
4184
4185        return 0;
4186}
4187
4188static bool
4189is_hdr_metadata_different(const struct drm_connector_state *old_state,
4190                          const struct drm_connector_state *new_state)
4191{
4192        struct drm_property_blob *old_blob = old_state->hdr_output_metadata;
4193        struct drm_property_blob *new_blob = new_state->hdr_output_metadata;
4194
4195        if (old_blob != new_blob) {
4196                if (old_blob && new_blob &&
4197                    old_blob->length == new_blob->length)
4198                        return memcmp(old_blob->data, new_blob->data,
4199                                      old_blob->length);
4200
4201                return true;
4202        }
4203
4204        return false;
4205}
4206
4207static int
4208amdgpu_dm_connector_atomic_check(struct drm_connector *conn,
4209                                 struct drm_atomic_state *state)
4210{
4211        struct drm_connector_state *new_con_state =
4212                drm_atomic_get_new_connector_state(state, conn);
4213        struct drm_connector_state *old_con_state =
4214                drm_atomic_get_old_connector_state(state, conn);
4215        struct drm_crtc *crtc = new_con_state->crtc;
4216        struct drm_crtc_state *new_crtc_state;
4217        int ret;
4218
4219        if (!crtc)
4220                return 0;
4221
4222        if (is_hdr_metadata_different(old_con_state, new_con_state)) {
4223                struct dc_info_packet hdr_infopacket;
4224
4225                ret = fill_hdr_info_packet(new_con_state, &hdr_infopacket);
4226                if (ret)
4227                        return ret;
4228
4229                new_crtc_state = drm_atomic_get_crtc_state(state, crtc);
4230                if (IS_ERR(new_crtc_state))
4231                        return PTR_ERR(new_crtc_state);
4232
4233                /*
4234                 * DC considers the stream backends changed if the
4235                 * static metadata changes. Forcing the modeset also
4236                 * gives a simple way for userspace to switch from
4237                 * 8bpc to 10bpc when setting the metadata to enter
4238                 * or exit HDR.
4239                 *
4240                 * Changing the static metadata after it's been
4241                 * set is permissible, however. So only force a
4242                 * modeset if we're entering or exiting HDR.
4243                 */
4244                new_crtc_state->mode_changed =
4245                        !old_con_state->hdr_output_metadata ||
4246                        !new_con_state->hdr_output_metadata;
4247        }
4248
4249        return 0;
4250}
4251
4252static const struct drm_connector_helper_funcs
4253amdgpu_dm_connector_helper_funcs = {
4254        /*
4255         * If hotplugging a second bigger display in FB Con mode, bigger resolution
4256         * modes will be filtered by drm_mode_validate_size(), and those modes
4257         * are missing after user start lightdm. So we need to renew modes list.
4258         * in get_modes call back, not just return the modes count
4259         */
4260        .get_modes = get_modes,
4261        .mode_valid = amdgpu_dm_connector_mode_valid,
4262        .atomic_check = amdgpu_dm_connector_atomic_check,
4263};
4264
4265static void dm_crtc_helper_disable(struct drm_crtc *crtc)
4266{
4267}
4268
4269static bool does_crtc_have_active_cursor(struct drm_crtc_state *new_crtc_state)
4270{
4271        struct drm_device *dev = new_crtc_state->crtc->dev;
4272        struct drm_plane *plane;
4273
4274        drm_for_each_plane_mask(plane, dev, new_crtc_state->plane_mask) {
4275                if (plane->type == DRM_PLANE_TYPE_CURSOR)
4276                        return true;
4277        }
4278
4279        return false;
4280}
4281
4282static int count_crtc_active_planes(struct drm_crtc_state *new_crtc_state)
4283{
4284        struct drm_atomic_state *state = new_crtc_state->state;
4285        struct drm_plane *plane;
4286        int num_active = 0;
4287
4288        drm_for_each_plane_mask(plane, state->dev, new_crtc_state->plane_mask) {
4289                struct drm_plane_state *new_plane_state;
4290
4291                /* Cursor planes are "fake". */
4292                if (plane->type == DRM_PLANE_TYPE_CURSOR)
4293                        continue;
4294
4295                new_plane_state = drm_atomic_get_new_plane_state(state, plane);
4296
4297                if (!new_plane_state) {
4298                        /*
4299                         * The plane is enable on the CRTC and hasn't changed
4300                         * state. This means that it previously passed
4301                         * validation and is therefore enabled.
4302                         */
4303                        num_active += 1;
4304                        continue;
4305                }
4306
4307                /* We need a framebuffer to be considered enabled. */
4308                num_active += (new_plane_state->fb != NULL);
4309        }
4310
4311        return num_active;
4312}
4313
4314/*
4315 * Sets whether interrupts should be enabled on a specific CRTC.
4316 * We require that the stream be enabled and that there exist active
4317 * DC planes on the stream.
4318 */
4319static void
4320dm_update_crtc_interrupt_state(struct drm_crtc *crtc,
4321                               struct drm_crtc_state *new_crtc_state)
4322{
4323        struct dm_crtc_state *dm_new_crtc_state =
4324                to_dm_crtc_state(new_crtc_state);
4325
4326        dm_new_crtc_state->active_planes = 0;
4327        dm_new_crtc_state->interrupts_enabled = false;
4328
4329        if (!dm_new_crtc_state->stream)
4330                return;
4331
4332        dm_new_crtc_state->active_planes =
4333                count_crtc_active_planes(new_crtc_state);
4334
4335        dm_new_crtc_state->interrupts_enabled =
4336                dm_new_crtc_state->active_planes > 0;
4337}
4338
4339static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
4340                                       struct drm_crtc_state *state)
4341{
4342        struct amdgpu_device *adev = crtc->dev->dev_private;
4343        struct dc *dc = adev->dm.dc;
4344        struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
4345        int ret = -EINVAL;
4346
4347        /*
4348         * Update interrupt state for the CRTC. This needs to happen whenever
4349         * the CRTC has changed or whenever any of its planes have changed.
4350         * Atomic check satisfies both of these requirements since the CRTC
4351         * is added to the state by DRM during drm_atomic_helper_check_planes.
4352         */
4353        dm_update_crtc_interrupt_state(crtc, state);
4354
4355        if (unlikely(!dm_crtc_state->stream &&
4356                     modeset_required(state, NULL, dm_crtc_state->stream))) {
4357                WARN_ON(1);
4358                return ret;
4359        }
4360
4361        /* In some use cases, like reset, no stream is attached */
4362        if (!dm_crtc_state->stream)
4363                return 0;
4364
4365        /*
4366         * We want at least one hardware plane enabled to use
4367         * the stream with a cursor enabled.
4368         */
4369        if (state->enable && state->active &&
4370            does_crtc_have_active_cursor(state) &&
4371            dm_crtc_state->active_planes == 0)
4372                return -EINVAL;
4373
4374        if (dc_validate_stream(dc, dm_crtc_state->stream) == DC_OK)
4375                return 0;
4376
4377        return ret;
4378}
4379
4380static bool dm_crtc_helper_mode_fixup(struct drm_crtc *crtc,
4381                                      const struct drm_display_mode *mode,
4382                                      struct drm_display_mode *adjusted_mode)
4383{
4384        return true;
4385}
4386
4387static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = {
4388        .disable = dm_crtc_helper_disable,
4389        .atomic_check = dm_crtc_helper_atomic_check,
4390        .mode_fixup = dm_crtc_helper_mode_fixup
4391};
4392
4393static void dm_encoder_helper_disable(struct drm_encoder *encoder)
4394{
4395
4396}
4397
4398static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
4399                                          struct drm_crtc_state *crtc_state,
4400                                          struct drm_connector_state *conn_state)
4401{
4402        return 0;
4403}
4404
4405const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = {
4406        .disable = dm_encoder_helper_disable,
4407        .atomic_check = dm_encoder_helper_atomic_check
4408};
4409
4410static void dm_drm_plane_reset(struct drm_plane *plane)
4411{
4412        struct dm_plane_state *amdgpu_state = NULL;
4413
4414        if (plane->state)
4415                plane->funcs->atomic_destroy_state(plane, plane->state);
4416
4417        amdgpu_state = kzalloc(sizeof(*amdgpu_state), GFP_KERNEL);
4418        WARN_ON(amdgpu_state == NULL);
4419
4420        if (amdgpu_state)
4421                __drm_atomic_helper_plane_reset(plane, &amdgpu_state->base);
4422}
4423
4424static struct drm_plane_state *
4425dm_drm_plane_duplicate_state(struct drm_plane *plane)
4426{
4427        struct dm_plane_state *dm_plane_state, *old_dm_plane_state;
4428
4429        old_dm_plane_state = to_dm_plane_state(plane->state);
4430        dm_plane_state = kzalloc(sizeof(*dm_plane_state), GFP_KERNEL);
4431        if (!dm_plane_state)
4432                return NULL;
4433
4434        __drm_atomic_helper_plane_duplicate_state(plane, &dm_plane_state->base);
4435
4436        if (old_dm_plane_state->dc_state) {
4437                dm_plane_state->dc_state = old_dm_plane_state->dc_state;
4438                dc_plane_state_retain(dm_plane_state->dc_state);
4439        }
4440
4441        return &dm_plane_state->base;
4442}
4443
4444void dm_drm_plane_destroy_state(struct drm_plane *plane,
4445                                struct drm_plane_state *state)
4446{
4447        struct dm_plane_state *dm_plane_state = to_dm_plane_state(state);
4448
4449        if (dm_plane_state->dc_state)
4450                dc_plane_state_release(dm_plane_state->dc_state);
4451
4452        drm_atomic_helper_plane_destroy_state(plane, state);
4453}
4454
4455static const struct drm_plane_funcs dm_plane_funcs = {
4456        .update_plane   = drm_atomic_helper_update_plane,
4457        .disable_plane  = drm_atomic_helper_disable_plane,
4458        .destroy        = drm_primary_helper_destroy,
4459        .reset = dm_drm_plane_reset,
4460        .atomic_duplicate_state = dm_drm_plane_duplicate_state,
4461        .atomic_destroy_state = dm_drm_plane_destroy_state,
4462};
4463
4464static int dm_plane_helper_prepare_fb(struct drm_plane *plane,
4465                                      struct drm_plane_state *new_state)
4466{
4467        struct amdgpu_framebuffer *afb;
4468        struct drm_gem_object *obj;
4469        struct amdgpu_device *adev;
4470        struct amdgpu_bo *rbo;
4471        struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
4472        struct list_head list;
4473        struct ttm_validate_buffer tv;
4474        struct ww_acquire_ctx ticket;
4475        uint64_t tiling_flags;
4476        uint32_t domain;
4477        int r;
4478
4479        dm_plane_state_old = to_dm_plane_state(plane->state);
4480        dm_plane_state_new = to_dm_plane_state(new_state);
4481
4482        if (!new_state->fb) {
4483                DRM_DEBUG_DRIVER("No FB bound\n");
4484                return 0;
4485        }
4486
4487        afb = to_amdgpu_framebuffer(new_state->fb);
4488        obj = new_state->fb->obj[0];
4489        rbo = gem_to_amdgpu_bo(obj);
4490        adev = amdgpu_ttm_adev(rbo->tbo.bdev);
4491        INIT_LIST_HEAD(&list);
4492
4493        tv.bo = &rbo->tbo;
4494        tv.num_shared = 1;
4495        list_add(&tv.head, &list);
4496
4497        r = ttm_eu_reserve_buffers(&ticket, &list, false, NULL, true);
4498        if (r) {
4499                dev_err(adev->dev, "fail to reserve bo (%d)\n", r);
4500                return r;
4501        }
4502
4503        if (plane->type != DRM_PLANE_TYPE_CURSOR)
4504                domain = amdgpu_display_supported_domains(adev, rbo->flags);
4505        else
4506                domain = AMDGPU_GEM_DOMAIN_VRAM;
4507
4508        r = amdgpu_bo_pin(rbo, domain);
4509        if (unlikely(r != 0)) {
4510                if (r != -ERESTARTSYS)
4511                        DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
4512                ttm_eu_backoff_reservation(&ticket, &list);
4513                return r;
4514        }
4515
4516        r = amdgpu_ttm_alloc_gart(&rbo->tbo);
4517        if (unlikely(r != 0)) {
4518                amdgpu_bo_unpin(rbo);
4519                ttm_eu_backoff_reservation(&ticket, &list);
4520                DRM_ERROR("%p bind failed\n", rbo);
4521                return r;
4522        }
4523
4524        amdgpu_bo_get_tiling_flags(rbo, &tiling_flags);
4525
4526        ttm_eu_backoff_reservation(&ticket, &list);
4527
4528        afb->address = amdgpu_bo_gpu_offset(rbo);
4529
4530        amdgpu_bo_ref(rbo);
4531
4532        if (dm_plane_state_new->dc_state &&
4533                        dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
4534                struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
4535
4536                fill_plane_buffer_attributes(
4537                        adev, afb, plane_state->format, plane_state->rotation,
4538                        tiling_flags, &plane_state->tiling_info,
4539                        &plane_state->plane_size, &plane_state->dcc,
4540                        &plane_state->address);
4541        }
4542
4543        return 0;
4544}
4545
4546static void dm_plane_helper_cleanup_fb(struct drm_plane *plane,
4547                                       struct drm_plane_state *old_state)
4548{
4549        struct amdgpu_bo *rbo;
4550        int r;
4551
4552        if (!old_state->fb)
4553                return;
4554
4555        rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]);
4556        r = amdgpu_bo_reserve(rbo, false);
4557        if (unlikely(r)) {
4558                DRM_ERROR("failed to reserve rbo before unpin\n");
4559                return;
4560        }
4561
4562        amdgpu_bo_unpin(rbo);
4563        amdgpu_bo_unreserve(rbo);
4564        amdgpu_bo_unref(&rbo);
4565}
4566
4567static int dm_plane_atomic_check(struct drm_plane *plane,
4568                                 struct drm_plane_state *state)
4569{
4570        struct amdgpu_device *adev = plane->dev->dev_private;
4571        struct dc *dc = adev->dm.dc;
4572        struct dm_plane_state *dm_plane_state;
4573        struct dc_scaling_info scaling_info;
4574        int ret;
4575
4576        dm_plane_state = to_dm_plane_state(state);
4577
4578        if (!dm_plane_state->dc_state)
4579                return 0;
4580
4581        ret = fill_dc_scaling_info(state, &scaling_info);
4582        if (ret)
4583                return ret;
4584
4585        if (dc_validate_plane(dc, dm_plane_state->dc_state) == DC_OK)
4586                return 0;
4587
4588        return -EINVAL;
4589}
4590
4591static int dm_plane_atomic_async_check(struct drm_plane *plane,
4592                                       struct drm_plane_state *new_plane_state)
4593{
4594        /* Only support async updates on cursor planes. */
4595        if (plane->type != DRM_PLANE_TYPE_CURSOR)
4596                return -EINVAL;
4597
4598        return 0;
4599}
4600
4601static void dm_plane_atomic_async_update(struct drm_plane *plane,
4602                                         struct drm_plane_state *new_state)
4603{
4604        struct drm_plane_state *old_state =
4605                drm_atomic_get_old_plane_state(new_state->state, plane);
4606
4607        swap(plane->state->fb, new_state->fb);
4608
4609        plane->state->src_x = new_state->src_x;
4610        plane->state->src_y = new_state->src_y;
4611        plane->state->src_w = new_state->src_w;
4612        plane->state->src_h = new_state->src_h;
4613        plane->state->crtc_x = new_state->crtc_x;
4614        plane->state->crtc_y = new_state->crtc_y;
4615        plane->state->crtc_w = new_state->crtc_w;
4616        plane->state->crtc_h = new_state->crtc_h;
4617
4618        handle_cursor_update(plane, old_state);
4619}
4620
4621static const struct drm_plane_helper_funcs dm_plane_helper_funcs = {
4622        .prepare_fb = dm_plane_helper_prepare_fb,
4623        .cleanup_fb = dm_plane_helper_cleanup_fb,
4624        .atomic_check = dm_plane_atomic_check,
4625        .atomic_async_check = dm_plane_atomic_async_check,
4626        .atomic_async_update = dm_plane_atomic_async_update
4627};
4628
4629/*
4630 * TODO: these are currently initialized to rgb formats only.
4631 * For future use cases we should either initialize them dynamically based on
4632 * plane capabilities, or initialize this array to all formats, so internal drm
4633 * check will succeed, and let DC implement proper check
4634 */
4635static const uint32_t rgb_formats[] = {
4636        DRM_FORMAT_XRGB8888,
4637        DRM_FORMAT_ARGB8888,
4638        DRM_FORMAT_RGBA8888,
4639        DRM_FORMAT_XRGB2101010,
4640        DRM_FORMAT_XBGR2101010,
4641        DRM_FORMAT_ARGB2101010,
4642        DRM_FORMAT_ABGR2101010,
4643        DRM_FORMAT_XBGR8888,
4644        DRM_FORMAT_ABGR8888,
4645        DRM_FORMAT_RGB565,
4646};
4647
4648static const uint32_t overlay_formats[] = {
4649        DRM_FORMAT_XRGB8888,
4650        DRM_FORMAT_ARGB8888,
4651        DRM_FORMAT_RGBA8888,
4652        DRM_FORMAT_XBGR8888,
4653        DRM_FORMAT_ABGR8888,
4654        DRM_FORMAT_RGB565
4655};
4656
4657static const u32 cursor_formats[] = {
4658        DRM_FORMAT_ARGB8888
4659};
4660
4661static int get_plane_formats(const struct drm_plane *plane,
4662                             const struct dc_plane_cap *plane_cap,
4663                             uint32_t *formats, int max_formats)
4664{
4665        int i, num_formats = 0;
4666
4667        /*
4668         * TODO: Query support for each group of formats directly from
4669         * DC plane caps. This will require adding more formats to the
4670         * caps list.
4671         */
4672
4673        switch (plane->type) {
4674        case DRM_PLANE_TYPE_PRIMARY:
4675                for (i = 0; i < ARRAY_SIZE(rgb_formats); ++i) {
4676                        if (num_formats >= max_formats)
4677                                break;
4678
4679                        formats[num_formats++] = rgb_formats[i];
4680                }
4681
4682                if (plane_cap && plane_cap->pixel_format_support.nv12)
4683                        formats[num_formats++] = DRM_FORMAT_NV12;
4684                break;
4685
4686        case DRM_PLANE_TYPE_OVERLAY:
4687                for (i = 0; i < ARRAY_SIZE(overlay_formats); ++i) {
4688                        if (num_formats >= max_formats)
4689                                break;
4690
4691                        formats[num_formats++] = overlay_formats[i];
4692                }
4693                break;
4694
4695        case DRM_PLANE_TYPE_CURSOR:
4696                for (i = 0; i < ARRAY_SIZE(cursor_formats); ++i) {
4697                        if (num_formats >= max_formats)
4698                                break;
4699
4700                        formats[num_formats++] = cursor_formats[i];
4701                }
4702                break;
4703        }
4704
4705        return num_formats;
4706}
4707
4708static int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm,
4709                                struct drm_plane *plane,
4710                                unsigned long possible_crtcs,
4711                                const struct dc_plane_cap *plane_cap)
4712{
4713        uint32_t formats[32];
4714        int num_formats;
4715        int res = -EPERM;
4716
4717        num_formats = get_plane_formats(plane, plane_cap, formats,
4718                                        ARRAY_SIZE(formats));
4719
4720        res = drm_universal_plane_init(dm->adev->ddev, plane, possible_crtcs,
4721                                       &dm_plane_funcs, formats, num_formats,
4722                                       NULL, plane->type, NULL);
4723        if (res)
4724                return res;
4725
4726        if (plane->type == DRM_PLANE_TYPE_OVERLAY &&
4727            plane_cap && plane_cap->per_pixel_alpha) {
4728                unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
4729                                          BIT(DRM_MODE_BLEND_PREMULTI);
4730
4731                drm_plane_create_alpha_property(plane);
4732                drm_plane_create_blend_mode_property(plane, blend_caps);
4733        }
4734
4735        if (plane->type == DRM_PLANE_TYPE_PRIMARY &&
4736            plane_cap && plane_cap->pixel_format_support.nv12) {
4737                /* This only affects YUV formats. */
4738                drm_plane_create_color_properties(
4739                        plane,
4740                        BIT(DRM_COLOR_YCBCR_BT601) |
4741                        BIT(DRM_COLOR_YCBCR_BT709),
4742                        BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) |
4743                        BIT(DRM_COLOR_YCBCR_FULL_RANGE),