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25
26#include <linux/slab.h>
27
28#include "dm_services.h"
29#include "atomfirmware.h"
30#include "dm_helpers.h"
31#include "dc.h"
32#include "grph_object_id.h"
33#include "gpio_service_interface.h"
34#include "core_status.h"
35#include "dc_link_dp.h"
36#include "dc_link_ddc.h"
37#include "link_hwss.h"
38#include "opp.h"
39
40#include "link_encoder.h"
41#include "hw_sequencer.h"
42#include "resource.h"
43#include "abm.h"
44#include "fixed31_32.h"
45#include "dpcd_defs.h"
46#include "dmcu.h"
47#include "hw/clk_mgr.h"
48#include "dce/dmub_psr.h"
49#include "dmub/dmub_srv.h"
50#include "inc/hw/panel_cntl.h"
51#include "inc/link_enc_cfg.h"
52#include "inc/link_dpcd.h"
53
54#define DC_LOGGER_INIT(logger)
55
56#define LINK_INFO(...) \
57 DC_LOG_HW_HOTPLUG( \
58 __VA_ARGS__)
59
60#define RETIMER_REDRIVER_INFO(...) \
61 DC_LOG_RETIMER_REDRIVER( \
62 __VA_ARGS__)
63
64
65
66
67static void dc_link_destruct(struct dc_link *link)
68{
69 int i;
70
71 if (link->hpd_gpio) {
72 dal_gpio_destroy_irq(&link->hpd_gpio);
73 link->hpd_gpio = NULL;
74 }
75
76 if (link->ddc)
77 dal_ddc_service_destroy(&link->ddc);
78
79 if (link->panel_cntl)
80 link->panel_cntl->funcs->destroy(&link->panel_cntl);
81
82 if (link->link_enc) {
83
84
85
86
87 if (link->link_id.id != CONNECTOR_ID_VIRTUAL) {
88 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = NULL;
89 link->dc->res_pool->dig_link_enc_count--;
90 }
91 link->link_enc->funcs->destroy(&link->link_enc);
92 }
93
94 if (link->local_sink)
95 dc_sink_release(link->local_sink);
96
97 for (i = 0; i < link->sink_count; ++i)
98 dc_sink_release(link->remote_sinks[i]);
99}
100
101struct gpio *get_hpd_gpio(struct dc_bios *dcb,
102 struct graphics_object_id link_id,
103 struct gpio_service *gpio_service)
104{
105 enum bp_result bp_result;
106 struct graphics_object_hpd_info hpd_info;
107 struct gpio_pin_info pin_info;
108
109 if (dcb->funcs->get_hpd_info(dcb, link_id, &hpd_info) != BP_RESULT_OK)
110 return NULL;
111
112 bp_result = dcb->funcs->get_gpio_pin_info(dcb,
113 hpd_info.hpd_int_gpio_uid, &pin_info);
114
115 if (bp_result != BP_RESULT_OK) {
116 ASSERT(bp_result == BP_RESULT_NORECORD);
117 return NULL;
118 }
119
120 return dal_gpio_service_create_irq(gpio_service,
121 pin_info.offset,
122 pin_info.mask);
123}
124
125
126
127
128
129
130
131
132
133
134
135
136
137static bool program_hpd_filter(const struct dc_link *link)
138{
139 bool result = false;
140 struct gpio *hpd;
141 int delay_on_connect_in_ms = 0;
142 int delay_on_disconnect_in_ms = 0;
143
144 if (link->is_hpd_filter_disabled)
145 return false;
146
147 switch (link->connector_signal) {
148 case SIGNAL_TYPE_DVI_SINGLE_LINK:
149 case SIGNAL_TYPE_DVI_DUAL_LINK:
150 case SIGNAL_TYPE_HDMI_TYPE_A:
151
152 delay_on_connect_in_ms = 500;
153 delay_on_disconnect_in_ms = 100;
154 break;
155 case SIGNAL_TYPE_DISPLAY_PORT:
156 case SIGNAL_TYPE_DISPLAY_PORT_MST:
157
158
159
160
161
162
163
164 delay_on_connect_in_ms = 80;
165 delay_on_disconnect_in_ms = 0;
166 break;
167 case SIGNAL_TYPE_LVDS:
168 case SIGNAL_TYPE_EDP:
169 default:
170
171 return false;
172 }
173
174
175 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
176 link->ctx->gpio_service);
177
178 if (!hpd)
179 return result;
180
181
182 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
183 struct gpio_hpd_config config;
184
185 config.delay_on_connect = delay_on_connect_in_ms;
186 config.delay_on_disconnect = delay_on_disconnect_in_ms;
187
188 dal_irq_setup_hpd_filter(hpd, &config);
189
190 dal_gpio_close(hpd);
191
192 result = true;
193 } else {
194 ASSERT_CRITICAL(false);
195 }
196
197
198 dal_gpio_destroy_irq(&hpd);
199
200 return result;
201}
202
203bool dc_link_wait_for_t12(struct dc_link *link)
204{
205 if (link->connector_signal == SIGNAL_TYPE_EDP && link->dc->hwss.edp_wait_for_T12) {
206 link->dc->hwss.edp_wait_for_T12(link);
207
208 return true;
209 }
210
211 return false;
212}
213
214
215
216
217
218
219
220
221
222bool dc_link_detect_sink(struct dc_link *link, enum dc_connection_type *type)
223{
224 uint32_t is_hpd_high = 0;
225 struct gpio *hpd_pin;
226
227 if (link->connector_signal == SIGNAL_TYPE_LVDS) {
228 *type = dc_connection_single;
229 return true;
230 }
231
232 if (link->connector_signal == SIGNAL_TYPE_EDP) {
233
234 link->dc->hwss.edp_power_control(link, true);
235 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
236 }
237
238
239 if (link->ep_type != DISPLAY_ENDPOINT_PHY) {
240 if (link->hpd_status)
241 *type = dc_connection_single;
242 else
243 *type = dc_connection_none;
244
245 return true;
246 }
247
248
249 hpd_pin = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
250 link->ctx->gpio_service);
251 if (!hpd_pin)
252 goto hpd_gpio_failure;
253
254 dal_gpio_open(hpd_pin, GPIO_MODE_INTERRUPT);
255 dal_gpio_get_value(hpd_pin, &is_hpd_high);
256 dal_gpio_close(hpd_pin);
257 dal_gpio_destroy_irq(&hpd_pin);
258
259 if (is_hpd_high) {
260 *type = dc_connection_single;
261
262 } else {
263 *type = dc_connection_none;
264 }
265
266 return true;
267
268hpd_gpio_failure:
269 return false;
270}
271
272static enum ddc_transaction_type get_ddc_transaction_type(enum signal_type sink_signal)
273{
274 enum ddc_transaction_type transaction_type = DDC_TRANSACTION_TYPE_NONE;
275
276 switch (sink_signal) {
277 case SIGNAL_TYPE_DVI_SINGLE_LINK:
278 case SIGNAL_TYPE_DVI_DUAL_LINK:
279 case SIGNAL_TYPE_HDMI_TYPE_A:
280 case SIGNAL_TYPE_LVDS:
281 case SIGNAL_TYPE_RGB:
282 transaction_type = DDC_TRANSACTION_TYPE_I2C;
283 break;
284
285 case SIGNAL_TYPE_DISPLAY_PORT:
286 case SIGNAL_TYPE_EDP:
287 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
288 break;
289
290 case SIGNAL_TYPE_DISPLAY_PORT_MST:
291
292
293
294
295 transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
296 break;
297
298 default:
299 break;
300 }
301
302 return transaction_type;
303}
304
305static enum signal_type get_basic_signal_type(struct graphics_object_id encoder,
306 struct graphics_object_id downstream)
307{
308 if (downstream.type == OBJECT_TYPE_CONNECTOR) {
309 switch (downstream.id) {
310 case CONNECTOR_ID_SINGLE_LINK_DVII:
311 switch (encoder.id) {
312 case ENCODER_ID_INTERNAL_DAC1:
313 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
314 case ENCODER_ID_INTERNAL_DAC2:
315 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
316 return SIGNAL_TYPE_RGB;
317 default:
318 return SIGNAL_TYPE_DVI_SINGLE_LINK;
319 }
320 break;
321 case CONNECTOR_ID_DUAL_LINK_DVII:
322 {
323 switch (encoder.id) {
324 case ENCODER_ID_INTERNAL_DAC1:
325 case ENCODER_ID_INTERNAL_KLDSCP_DAC1:
326 case ENCODER_ID_INTERNAL_DAC2:
327 case ENCODER_ID_INTERNAL_KLDSCP_DAC2:
328 return SIGNAL_TYPE_RGB;
329 default:
330 return SIGNAL_TYPE_DVI_DUAL_LINK;
331 }
332 }
333 break;
334 case CONNECTOR_ID_SINGLE_LINK_DVID:
335 return SIGNAL_TYPE_DVI_SINGLE_LINK;
336 case CONNECTOR_ID_DUAL_LINK_DVID:
337 return SIGNAL_TYPE_DVI_DUAL_LINK;
338 case CONNECTOR_ID_VGA:
339 return SIGNAL_TYPE_RGB;
340 case CONNECTOR_ID_HDMI_TYPE_A:
341 return SIGNAL_TYPE_HDMI_TYPE_A;
342 case CONNECTOR_ID_LVDS:
343 return SIGNAL_TYPE_LVDS;
344 case CONNECTOR_ID_DISPLAY_PORT:
345 return SIGNAL_TYPE_DISPLAY_PORT;
346 case CONNECTOR_ID_EDP:
347 return SIGNAL_TYPE_EDP;
348 default:
349 return SIGNAL_TYPE_NONE;
350 }
351 } else if (downstream.type == OBJECT_TYPE_ENCODER) {
352 switch (downstream.id) {
353 case ENCODER_ID_EXTERNAL_NUTMEG:
354 case ENCODER_ID_EXTERNAL_TRAVIS:
355 return SIGNAL_TYPE_DISPLAY_PORT;
356 default:
357 return SIGNAL_TYPE_NONE;
358 }
359 }
360
361 return SIGNAL_TYPE_NONE;
362}
363
364
365
366
367
368bool dc_link_is_dp_sink_present(struct dc_link *link)
369{
370 enum gpio_result gpio_result;
371 uint32_t clock_pin = 0;
372 uint8_t retry = 0;
373 struct ddc *ddc;
374
375 enum connector_id connector_id =
376 dal_graphics_object_id_get_connector_id(link->link_id);
377
378 bool present =
379 ((connector_id == CONNECTOR_ID_DISPLAY_PORT) ||
380 (connector_id == CONNECTOR_ID_EDP));
381
382 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
383
384 if (!ddc) {
385 BREAK_TO_DEBUGGER();
386 return present;
387 }
388
389
390
391
392
393
394
395 if (dal_ddc_open(ddc, GPIO_MODE_INPUT,
396 GPIO_DDC_CONFIG_TYPE_MODE_I2C) != GPIO_RESULT_OK) {
397 dal_ddc_close(ddc);
398
399 return present;
400 }
401
402
403
404
405
406
407
408
409
410 do {
411 gpio_result = dal_gpio_get_value(ddc->pin_clock, &clock_pin);
412 ASSERT(gpio_result == GPIO_RESULT_OK);
413 if (clock_pin)
414 udelay(1000);
415 else
416 break;
417 } while (retry++ < 3);
418
419 present = (gpio_result == GPIO_RESULT_OK) && !clock_pin;
420
421 dal_ddc_close(ddc);
422
423 return present;
424}
425
426
427
428
429
430static enum signal_type link_detect_sink(struct dc_link *link,
431 enum dc_detect_reason reason)
432{
433 enum signal_type result;
434 struct graphics_object_id enc_id;
435
436 if (link->is_dig_mapping_flexible)
437 enc_id = (struct graphics_object_id){.id = ENCODER_ID_UNKNOWN};
438 else
439 enc_id = link->link_enc->id;
440 result = get_basic_signal_type(enc_id, link->link_id);
441
442
443 if (link->ep_type != DISPLAY_ENDPOINT_PHY)
444 return result;
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459 if (link->link_id.id == CONNECTOR_ID_PCIE) {
460
461 }
462
463 switch (link->link_id.id) {
464 case CONNECTOR_ID_HDMI_TYPE_A: {
465
466
467
468 struct audio_support *aud_support =
469 &link->dc->res_pool->audio_support;
470
471 if (!aud_support->hdmi_audio_native)
472 if (link->link_id.id == CONNECTOR_ID_HDMI_TYPE_A)
473 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
474 }
475 break;
476 case CONNECTOR_ID_DISPLAY_PORT: {
477
478
479
480 if (reason != DETECT_REASON_HPDRX) {
481
482
483
484
485 if (!dm_helpers_is_dp_sink_present(link))
486 result = SIGNAL_TYPE_DVI_SINGLE_LINK;
487 }
488 }
489 break;
490 default:
491 break;
492 }
493
494 return result;
495}
496
497static enum signal_type decide_signal_from_strap_and_dongle_type(enum display_dongle_type dongle_type,
498 struct audio_support *audio_support)
499{
500 enum signal_type signal = SIGNAL_TYPE_NONE;
501
502 switch (dongle_type) {
503 case DISPLAY_DONGLE_DP_HDMI_DONGLE:
504 if (audio_support->hdmi_audio_on_dongle)
505 signal = SIGNAL_TYPE_HDMI_TYPE_A;
506 else
507 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
508 break;
509 case DISPLAY_DONGLE_DP_DVI_DONGLE:
510 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
511 break;
512 case DISPLAY_DONGLE_DP_HDMI_MISMATCHED_DONGLE:
513 if (audio_support->hdmi_audio_native)
514 signal = SIGNAL_TYPE_HDMI_TYPE_A;
515 else
516 signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
517 break;
518 default:
519 signal = SIGNAL_TYPE_NONE;
520 break;
521 }
522
523 return signal;
524}
525
526static enum signal_type dp_passive_dongle_detection(struct ddc_service *ddc,
527 struct display_sink_capability *sink_cap,
528 struct audio_support *audio_support)
529{
530 dal_ddc_service_i2c_query_dp_dual_mode_adaptor(ddc, sink_cap);
531
532 return decide_signal_from_strap_and_dongle_type(sink_cap->dongle_type,
533 audio_support);
534}
535
536static void link_disconnect_sink(struct dc_link *link)
537{
538 if (link->local_sink) {
539 dc_sink_release(link->local_sink);
540 link->local_sink = NULL;
541 }
542
543 link->dpcd_sink_count = 0;
544
545}
546
547static void link_disconnect_remap(struct dc_sink *prev_sink, struct dc_link *link)
548{
549 dc_sink_release(link->local_sink);
550 link->local_sink = prev_sink;
551}
552
553#if defined(CONFIG_DRM_AMD_DC_HDCP)
554bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal)
555{
556 bool ret = false;
557
558 switch (signal) {
559 case SIGNAL_TYPE_DISPLAY_PORT:
560 case SIGNAL_TYPE_DISPLAY_PORT_MST:
561 ret = link->hdcp_caps.bcaps.bits.HDCP_CAPABLE;
562 break;
563 case SIGNAL_TYPE_DVI_SINGLE_LINK:
564 case SIGNAL_TYPE_DVI_DUAL_LINK:
565 case SIGNAL_TYPE_HDMI_TYPE_A:
566
567
568
569
570 ret = true;
571 break;
572 default:
573 break;
574 }
575 return ret;
576}
577
578bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal)
579{
580 bool ret = false;
581
582 switch (signal) {
583 case SIGNAL_TYPE_DISPLAY_PORT:
584 case SIGNAL_TYPE_DISPLAY_PORT_MST:
585 ret = (link->hdcp_caps.bcaps.bits.HDCP_CAPABLE &&
586 link->hdcp_caps.rx_caps.fields.byte0.hdcp_capable &&
587 (link->hdcp_caps.rx_caps.fields.version == 0x2)) ? 1 : 0;
588 break;
589 case SIGNAL_TYPE_DVI_SINGLE_LINK:
590 case SIGNAL_TYPE_DVI_DUAL_LINK:
591 case SIGNAL_TYPE_HDMI_TYPE_A:
592 ret = (link->hdcp_caps.rx_caps.fields.version == 0x4) ? 1:0;
593 break;
594 default:
595 break;
596 }
597
598 return ret;
599}
600
601static void query_hdcp_capability(enum signal_type signal, struct dc_link *link)
602{
603 struct hdcp_protection_message msg22;
604 struct hdcp_protection_message msg14;
605
606 memset(&msg22, 0, sizeof(struct hdcp_protection_message));
607 memset(&msg14, 0, sizeof(struct hdcp_protection_message));
608 memset(link->hdcp_caps.rx_caps.raw, 0,
609 sizeof(link->hdcp_caps.rx_caps.raw));
610
611 if ((link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
612 link->ddc->transaction_type ==
613 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) ||
614 link->connector_signal == SIGNAL_TYPE_EDP) {
615 msg22.data = link->hdcp_caps.rx_caps.raw;
616 msg22.length = sizeof(link->hdcp_caps.rx_caps.raw);
617 msg22.msg_id = HDCP_MESSAGE_ID_RX_CAPS;
618 } else {
619 msg22.data = &link->hdcp_caps.rx_caps.fields.version;
620 msg22.length = sizeof(link->hdcp_caps.rx_caps.fields.version);
621 msg22.msg_id = HDCP_MESSAGE_ID_HDCP2VERSION;
622 }
623 msg22.version = HDCP_VERSION_22;
624 msg22.link = HDCP_LINK_PRIMARY;
625 msg22.max_retries = 5;
626 dc_process_hdcp_msg(signal, link, &msg22);
627
628 if (signal == SIGNAL_TYPE_DISPLAY_PORT || signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
629 msg14.data = &link->hdcp_caps.bcaps.raw;
630 msg14.length = sizeof(link->hdcp_caps.bcaps.raw);
631 msg14.msg_id = HDCP_MESSAGE_ID_READ_BCAPS;
632 msg14.version = HDCP_VERSION_14;
633 msg14.link = HDCP_LINK_PRIMARY;
634 msg14.max_retries = 5;
635
636 dc_process_hdcp_msg(signal, link, &msg14);
637 }
638
639}
640#endif
641
642static void read_current_link_settings_on_detect(struct dc_link *link)
643{
644 union lane_count_set lane_count_set = { {0} };
645 uint8_t link_bw_set;
646 uint8_t link_rate_set;
647 uint32_t read_dpcd_retry_cnt = 10;
648 enum dc_status status = DC_ERROR_UNEXPECTED;
649 int i;
650 union max_down_spread max_down_spread = { {0} };
651
652
653 for (i = 0; i < read_dpcd_retry_cnt; i++) {
654 status = core_link_read_dpcd(link,
655 DP_LANE_COUNT_SET,
656 &lane_count_set.raw,
657 sizeof(lane_count_set));
658
659
660
661
662
663 if (status == DC_OK) {
664 link->cur_link_settings.lane_count =
665 lane_count_set.bits.LANE_COUNT_SET;
666 break;
667 }
668
669 msleep(8);
670 }
671
672
673 core_link_read_dpcd(link, DP_LINK_BW_SET,
674 &link_bw_set, sizeof(link_bw_set));
675
676 if (link_bw_set == 0) {
677 if (link->connector_signal == SIGNAL_TYPE_EDP) {
678
679
680
681 core_link_read_dpcd(link, DP_LINK_RATE_SET,
682 &link_rate_set, sizeof(link_rate_set));
683
684
685 if (link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) {
686 link->cur_link_settings.link_rate =
687 link->dpcd_caps.edp_supported_link_rates[link_rate_set];
688 link->cur_link_settings.link_rate_set = link_rate_set;
689 link->cur_link_settings.use_link_rate_set = true;
690 }
691 } else {
692
693 ASSERT(false);
694 }
695 } else {
696 link->cur_link_settings.link_rate = link_bw_set;
697 link->cur_link_settings.use_link_rate_set = false;
698 }
699
700 core_link_read_dpcd(link, DP_MAX_DOWNSPREAD,
701 &max_down_spread.raw, sizeof(max_down_spread));
702 link->cur_link_settings.link_spread =
703 max_down_spread.bits.MAX_DOWN_SPREAD ?
704 LINK_SPREAD_05_DOWNSPREAD_30KHZ : LINK_SPREAD_DISABLED;
705}
706
707static bool detect_dp(struct dc_link *link,
708 struct display_sink_capability *sink_caps,
709 enum dc_detect_reason reason)
710{
711 struct audio_support *audio_support = &link->dc->res_pool->audio_support;
712
713 sink_caps->signal = link_detect_sink(link, reason);
714 sink_caps->transaction_type =
715 get_ddc_transaction_type(sink_caps->signal);
716
717 if (sink_caps->transaction_type == DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
718 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT;
719 if (!detect_dp_sink_caps(link))
720 return false;
721 if (is_mst_supported(link)) {
722 sink_caps->signal = SIGNAL_TYPE_DISPLAY_PORT_MST;
723 link->type = dc_connection_mst_branch;
724
725 dal_ddc_service_set_transaction_type(link->ddc,
726 sink_caps->transaction_type);
727
728#if defined(CONFIG_DRM_AMD_DC_HDCP)
729
730
731
732 query_hdcp_capability(SIGNAL_TYPE_DISPLAY_PORT_MST, link);
733#endif
734 }
735
736 if (link->type != dc_connection_mst_branch &&
737 is_dp_branch_device(link))
738
739 link->type = dc_connection_sst_branch;
740 } else {
741
742 sink_caps->signal = dp_passive_dongle_detection(link->ddc,
743 sink_caps,
744 audio_support);
745 link->dpcd_caps.dongle_type = sink_caps->dongle_type;
746 link->dpcd_caps.dpcd_rev.raw = 0;
747 }
748
749 return true;
750}
751
752static bool is_same_edid(struct dc_edid *old_edid, struct dc_edid *new_edid)
753{
754 if (old_edid->length != new_edid->length)
755 return false;
756
757 if (new_edid->length == 0)
758 return false;
759
760 return (memcmp(old_edid->raw_edid,
761 new_edid->raw_edid, new_edid->length) == 0);
762}
763
764static bool wait_for_entering_dp_alt_mode(struct dc_link *link)
765{
766
767
768
769
770 unsigned int sleep_time_in_microseconds = 500;
771 unsigned int tries_allowed = 400;
772 bool is_in_alt_mode;
773 unsigned long long enter_timestamp;
774 unsigned long long finish_timestamp;
775 unsigned long long time_taken_in_ns;
776 int tries_taken;
777
778 DC_LOGGER_INIT(link->ctx->logger);
779
780 if (!link->link_enc->funcs->is_in_alt_mode)
781 return true;
782
783 is_in_alt_mode = link->link_enc->funcs->is_in_alt_mode(link->link_enc);
784 DC_LOG_WARNING("DP Alt mode state on HPD: %d\n", is_in_alt_mode);
785
786 if (is_in_alt_mode)
787 return true;
788
789 enter_timestamp = dm_get_timestamp(link->ctx);
790
791 for (tries_taken = 0; tries_taken < tries_allowed; tries_taken++) {
792 udelay(sleep_time_in_microseconds);
793
794 if (link->link_enc->funcs->is_in_alt_mode(link->link_enc)) {
795 finish_timestamp = dm_get_timestamp(link->ctx);
796 time_taken_in_ns =
797 dm_get_elapse_time_in_ns(link->ctx,
798 finish_timestamp,
799 enter_timestamp);
800 DC_LOG_WARNING("Alt mode entered finished after %llu ms\n",
801 div_u64(time_taken_in_ns, 1000000));
802 return true;
803 }
804 }
805 finish_timestamp = dm_get_timestamp(link->ctx);
806 time_taken_in_ns = dm_get_elapse_time_in_ns(link->ctx, finish_timestamp,
807 enter_timestamp);
808 DC_LOG_WARNING("Alt mode has timed out after %llu ms\n",
809 div_u64(time_taken_in_ns, 1000000));
810 return false;
811}
812
813
814
815
816
817
818
819
820
821static bool dc_link_detect_helper(struct dc_link *link,
822 enum dc_detect_reason reason)
823{
824 struct dc_sink_init_data sink_init_data = { 0 };
825 struct display_sink_capability sink_caps = { 0 };
826 uint32_t i;
827 bool converter_disable_audio = false;
828 struct audio_support *aud_support = &link->dc->res_pool->audio_support;
829 bool same_edid = false;
830 enum dc_edid_status edid_status;
831 struct dc_context *dc_ctx = link->ctx;
832 struct dc_sink *sink = NULL;
833 struct dc_sink *prev_sink = NULL;
834 struct dpcd_caps prev_dpcd_caps;
835 enum dc_connection_type new_connection_type = dc_connection_none;
836 enum dc_connection_type pre_connection_type = dc_connection_none;
837 bool perform_dp_seamless_boot = false;
838 const uint32_t post_oui_delay = 30;
839
840 DC_LOGGER_INIT(link->ctx->logger);
841
842 if (dc_is_virtual_signal(link->connector_signal))
843 return false;
844
845 if (((link->connector_signal == SIGNAL_TYPE_LVDS ||
846 link->connector_signal == SIGNAL_TYPE_EDP) &&
847 (!link->dc->config.allow_edp_hotplug_detection)) &&
848 link->local_sink) {
849
850 if (link->connector_signal == SIGNAL_TYPE_EDP) {
851 dpcd_set_source_specific_data(link);
852 msleep(post_oui_delay);
853 dc_link_set_default_brightness_aux(link);
854
855 }
856
857 return true;
858 }
859
860 if (!dc_link_detect_sink(link, &new_connection_type)) {
861 BREAK_TO_DEBUGGER();
862 return false;
863 }
864
865 prev_sink = link->local_sink;
866 if (prev_sink) {
867 dc_sink_retain(prev_sink);
868 memcpy(&prev_dpcd_caps, &link->dpcd_caps, sizeof(struct dpcd_caps));
869 }
870
871 link_disconnect_sink(link);
872 if (new_connection_type != dc_connection_none) {
873 pre_connection_type = link->type;
874 link->type = new_connection_type;
875 link->link_state_valid = false;
876
877
878 switch (link->connector_signal) {
879 case SIGNAL_TYPE_HDMI_TYPE_A: {
880 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
881 if (aud_support->hdmi_audio_native)
882 sink_caps.signal = SIGNAL_TYPE_HDMI_TYPE_A;
883 else
884 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
885 break;
886 }
887
888 case SIGNAL_TYPE_DVI_SINGLE_LINK: {
889 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
890 sink_caps.signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
891 break;
892 }
893
894 case SIGNAL_TYPE_DVI_DUAL_LINK: {
895 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
896 sink_caps.signal = SIGNAL_TYPE_DVI_DUAL_LINK;
897 break;
898 }
899
900 case SIGNAL_TYPE_LVDS: {
901 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C;
902 sink_caps.signal = SIGNAL_TYPE_LVDS;
903 break;
904 }
905
906 case SIGNAL_TYPE_EDP: {
907 read_current_link_settings_on_detect(link);
908
909 detect_edp_sink_caps(link);
910 read_current_link_settings_on_detect(link);
911 sink_caps.transaction_type = DDC_TRANSACTION_TYPE_I2C_OVER_AUX;
912 sink_caps.signal = SIGNAL_TYPE_EDP;
913 break;
914 }
915
916 case SIGNAL_TYPE_DISPLAY_PORT: {
917
918 if (link->ep_type == DISPLAY_ENDPOINT_PHY &&
919 link->link_enc->features.flags.bits.DP_IS_USB_C == 1) {
920
921 if (!wait_for_entering_dp_alt_mode(link))
922 return false;
923 }
924
925 if (!detect_dp(link, &sink_caps, reason)) {
926 if (prev_sink)
927 dc_sink_release(prev_sink);
928 return false;
929 }
930
931 if (link->type == dc_connection_mst_branch) {
932 LINK_INFO("link=%d, mst branch is now Connected\n",
933 link->link_index);
934
935
936
937
938
939 dp_verify_mst_link_cap(link);
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966 dm_helpers_dp_update_branch_info(link->ctx, link);
967 if (dm_helpers_dp_mst_start_top_mgr(link->ctx,
968 link, reason == DETECT_REASON_BOOT)) {
969 if (prev_sink)
970 dc_sink_release(prev_sink);
971 return false;
972 } else {
973 link->type = dc_connection_sst_branch;
974 sink_caps.signal = SIGNAL_TYPE_DISPLAY_PORT;
975 }
976 }
977
978
979 if (link->type == dc_connection_sst_branch &&
980 link->dpcd_caps.sink_count.bits.SINK_COUNT == 0) {
981 if (prev_sink)
982
983 dc_sink_release(prev_sink);
984 return true;
985 }
986
987
988 if (link->type == dc_connection_sst_branch &&
989 is_dp_active_dongle(link) &&
990 (link->dpcd_caps.dongle_type !=
991 DISPLAY_DONGLE_DP_HDMI_CONVERTER))
992 converter_disable_audio = true;
993
994
995 if (pre_connection_type == dc_connection_mst_branch &&
996 link->type != dc_connection_mst_branch)
997 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
998
999
1000
1001 if (reason == DETECT_REASON_BOOT &&
1002 !dc_ctx->dc->config.power_down_display_on_boot &&
1003 link->link_status.link_active)
1004 perform_dp_seamless_boot = true;
1005
1006 if (perform_dp_seamless_boot) {
1007 read_current_link_settings_on_detect(link);
1008 link->verified_link_cap = link->reported_link_cap;
1009 }
1010
1011 break;
1012 }
1013
1014 default:
1015 DC_ERROR("Invalid connector type! signal:%d\n",
1016 link->connector_signal);
1017 if (prev_sink)
1018 dc_sink_release(prev_sink);
1019 return false;
1020 }
1021
1022 if (link->dpcd_caps.sink_count.bits.SINK_COUNT)
1023 link->dpcd_sink_count =
1024 link->dpcd_caps.sink_count.bits.SINK_COUNT;
1025 else
1026 link->dpcd_sink_count = 1;
1027
1028 dal_ddc_service_set_transaction_type(link->ddc,
1029 sink_caps.transaction_type);
1030
1031 link->aux_mode =
1032 dal_ddc_service_is_in_aux_transaction_mode(link->ddc);
1033
1034 sink_init_data.link = link;
1035 sink_init_data.sink_signal = sink_caps.signal;
1036
1037 sink = dc_sink_create(&sink_init_data);
1038 if (!sink) {
1039 DC_ERROR("Failed to create sink!\n");
1040 if (prev_sink)
1041 dc_sink_release(prev_sink);
1042 return false;
1043 }
1044
1045 sink->link->dongle_max_pix_clk = sink_caps.max_hdmi_pixel_clock;
1046 sink->converter_disable_audio = converter_disable_audio;
1047
1048
1049 link->local_sink = sink;
1050
1051 edid_status = dm_helpers_read_local_edid(link->ctx,
1052 link, sink);
1053
1054 switch (edid_status) {
1055 case EDID_BAD_CHECKSUM:
1056 DC_LOG_ERROR("EDID checksum invalid.\n");
1057 break;
1058 case EDID_NO_RESPONSE:
1059 DC_LOG_ERROR("No EDID read.\n");
1060
1061
1062
1063
1064
1065
1066
1067
1068 if (dc_is_hdmi_signal(link->connector_signal) ||
1069 dc_is_dvi_signal(link->connector_signal)) {
1070 if (prev_sink)
1071 dc_sink_release(prev_sink);
1072
1073 return false;
1074 }
1075 break;
1076 default:
1077 break;
1078 }
1079
1080
1081 if ((prev_sink) &&
1082 (edid_status == EDID_THE_SAME || edid_status == EDID_OK))
1083 same_edid = is_same_edid(&prev_sink->dc_edid,
1084 &sink->dc_edid);
1085
1086 if (sink->edid_caps.panel_patch.skip_scdc_overwrite)
1087 link->ctx->dc->debug.hdmi20_disable = true;
1088
1089 if (link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT &&
1090 sink_caps.transaction_type ==
1091 DDC_TRANSACTION_TYPE_I2C_OVER_AUX) {
1092
1093
1094
1095
1096#if defined(CONFIG_DRM_AMD_DC_HDCP)
1097 query_hdcp_capability(sink->sink_signal, link);
1098#endif
1099
1100
1101 if (!perform_dp_seamless_boot)
1102 dp_verify_link_cap_with_retries(link,
1103 &link->reported_link_cap,
1104 LINK_TRAINING_MAX_VERIFY_RETRY);
1105 } else {
1106
1107 if (same_edid) {
1108 link_disconnect_remap(prev_sink, link);
1109 sink = prev_sink;
1110 prev_sink = NULL;
1111 }
1112#if defined(CONFIG_DRM_AMD_DC_HDCP)
1113 query_hdcp_capability(sink->sink_signal, link);
1114#endif
1115 }
1116
1117
1118 if (sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A &&
1119 !sink->edid_caps.edid_hdmi)
1120 sink->sink_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1121
1122
1123 for (i = 0; i < sink->dc_edid.length / DC_EDID_BLOCK_SIZE; i++) {
1124 CONN_DATA_DETECT(link,
1125 &sink->dc_edid.raw_edid[i * DC_EDID_BLOCK_SIZE],
1126 DC_EDID_BLOCK_SIZE,
1127 "%s: [Block %d] ", sink->edid_caps.display_name, i);
1128 }
1129
1130 DC_LOG_DETECTION_EDID_PARSER("%s: "
1131 "manufacturer_id = %X, "
1132 "product_id = %X, "
1133 "serial_number = %X, "
1134 "manufacture_week = %d, "
1135 "manufacture_year = %d, "
1136 "display_name = %s, "
1137 "speaker_flag = %d, "
1138 "audio_mode_count = %d\n",
1139 __func__,
1140 sink->edid_caps.manufacturer_id,
1141 sink->edid_caps.product_id,
1142 sink->edid_caps.serial_number,
1143 sink->edid_caps.manufacture_week,
1144 sink->edid_caps.manufacture_year,
1145 sink->edid_caps.display_name,
1146 sink->edid_caps.speaker_flags,
1147 sink->edid_caps.audio_mode_count);
1148
1149 for (i = 0; i < sink->edid_caps.audio_mode_count; i++) {
1150 DC_LOG_DETECTION_EDID_PARSER("%s: mode number = %d, "
1151 "format_code = %d, "
1152 "channel_count = %d, "
1153 "sample_rate = %d, "
1154 "sample_size = %d\n",
1155 __func__,
1156 i,
1157 sink->edid_caps.audio_modes[i].format_code,
1158 sink->edid_caps.audio_modes[i].channel_count,
1159 sink->edid_caps.audio_modes[i].sample_rate,
1160 sink->edid_caps.audio_modes[i].sample_size);
1161 }
1162 } else {
1163
1164 if (link->type == dc_connection_mst_branch) {
1165 LINK_INFO("link=%d, mst branch is now Disconnected\n",
1166 link->link_index);
1167
1168 dm_helpers_dp_mst_stop_top_mgr(link->ctx, link);
1169
1170 link->mst_stream_alloc_table.stream_count = 0;
1171 memset(link->mst_stream_alloc_table.stream_allocations,
1172 0,
1173 sizeof(link->mst_stream_alloc_table.stream_allocations));
1174 }
1175
1176 link->type = dc_connection_none;
1177 sink_caps.signal = SIGNAL_TYPE_NONE;
1178
1179
1180
1181
1182
1183 link->dongle_max_pix_clk = 0;
1184 }
1185
1186 LINK_INFO("link=%d, dc_sink_in=%p is now %s prev_sink=%p edid same=%d\n",
1187 link->link_index, sink,
1188 (sink_caps.signal ==
1189 SIGNAL_TYPE_NONE ? "Disconnected" : "Connected"),
1190 prev_sink, same_edid);
1191
1192 if (prev_sink)
1193 dc_sink_release(prev_sink);
1194
1195 return true;
1196}
1197
1198bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason)
1199{
1200 const struct dc *dc = link->dc;
1201 bool ret;
1202 bool can_apply_seamless_boot = false;
1203 int i;
1204
1205 for (i = 0; i < dc->current_state->stream_count; i++) {
1206 if (dc->current_state->streams[i]->apply_seamless_boot_optimization) {
1207 can_apply_seamless_boot = true;
1208 break;
1209 }
1210 }
1211
1212
1213 if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1214 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr);
1215
1216 ret = dc_link_detect_helper(link, reason);
1217
1218
1219 if (!can_apply_seamless_boot && reason != DETECT_REASON_BOOT)
1220 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr);
1221
1222 return ret;
1223}
1224
1225bool dc_link_get_hpd_state(struct dc_link *dc_link)
1226{
1227 uint32_t state;
1228
1229 dal_gpio_lock_pin(dc_link->hpd_gpio);
1230 dal_gpio_get_value(dc_link->hpd_gpio, &state);
1231 dal_gpio_unlock_pin(dc_link->hpd_gpio);
1232
1233 return state;
1234}
1235
1236static enum hpd_source_id get_hpd_line(struct dc_link *link)
1237{
1238 struct gpio *hpd;
1239 enum hpd_source_id hpd_id = HPD_SOURCEID_UNKNOWN;
1240
1241 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1242 link->ctx->gpio_service);
1243
1244 if (hpd) {
1245 switch (dal_irq_get_source(hpd)) {
1246 case DC_IRQ_SOURCE_HPD1:
1247 hpd_id = HPD_SOURCEID1;
1248 break;
1249 case DC_IRQ_SOURCE_HPD2:
1250 hpd_id = HPD_SOURCEID2;
1251 break;
1252 case DC_IRQ_SOURCE_HPD3:
1253 hpd_id = HPD_SOURCEID3;
1254 break;
1255 case DC_IRQ_SOURCE_HPD4:
1256 hpd_id = HPD_SOURCEID4;
1257 break;
1258 case DC_IRQ_SOURCE_HPD5:
1259 hpd_id = HPD_SOURCEID5;
1260 break;
1261 case DC_IRQ_SOURCE_HPD6:
1262 hpd_id = HPD_SOURCEID6;
1263 break;
1264 default:
1265 BREAK_TO_DEBUGGER();
1266 break;
1267 }
1268
1269 dal_gpio_destroy_irq(&hpd);
1270 }
1271
1272 return hpd_id;
1273}
1274
1275static enum channel_id get_ddc_line(struct dc_link *link)
1276{
1277 struct ddc *ddc;
1278 enum channel_id channel = CHANNEL_ID_UNKNOWN;
1279
1280 ddc = dal_ddc_service_get_ddc_pin(link->ddc);
1281
1282 if (ddc) {
1283 switch (dal_ddc_get_line(ddc)) {
1284 case GPIO_DDC_LINE_DDC1:
1285 channel = CHANNEL_ID_DDC1;
1286 break;
1287 case GPIO_DDC_LINE_DDC2:
1288 channel = CHANNEL_ID_DDC2;
1289 break;
1290 case GPIO_DDC_LINE_DDC3:
1291 channel = CHANNEL_ID_DDC3;
1292 break;
1293 case GPIO_DDC_LINE_DDC4:
1294 channel = CHANNEL_ID_DDC4;
1295 break;
1296 case GPIO_DDC_LINE_DDC5:
1297 channel = CHANNEL_ID_DDC5;
1298 break;
1299 case GPIO_DDC_LINE_DDC6:
1300 channel = CHANNEL_ID_DDC6;
1301 break;
1302 case GPIO_DDC_LINE_DDC_VGA:
1303 channel = CHANNEL_ID_DDC_VGA;
1304 break;
1305 case GPIO_DDC_LINE_I2C_PAD:
1306 channel = CHANNEL_ID_I2C_PAD;
1307 break;
1308 default:
1309 BREAK_TO_DEBUGGER();
1310 break;
1311 }
1312 }
1313
1314 return channel;
1315}
1316
1317static enum transmitter translate_encoder_to_transmitter(struct graphics_object_id encoder)
1318{
1319 switch (encoder.id) {
1320 case ENCODER_ID_INTERNAL_UNIPHY:
1321 switch (encoder.enum_id) {
1322 case ENUM_ID_1:
1323 return TRANSMITTER_UNIPHY_A;
1324 case ENUM_ID_2:
1325 return TRANSMITTER_UNIPHY_B;
1326 default:
1327 return TRANSMITTER_UNKNOWN;
1328 }
1329 break;
1330 case ENCODER_ID_INTERNAL_UNIPHY1:
1331 switch (encoder.enum_id) {
1332 case ENUM_ID_1:
1333 return TRANSMITTER_UNIPHY_C;
1334 case ENUM_ID_2:
1335 return TRANSMITTER_UNIPHY_D;
1336 default:
1337 return TRANSMITTER_UNKNOWN;
1338 }
1339 break;
1340 case ENCODER_ID_INTERNAL_UNIPHY2:
1341 switch (encoder.enum_id) {
1342 case ENUM_ID_1:
1343 return TRANSMITTER_UNIPHY_E;
1344 case ENUM_ID_2:
1345 return TRANSMITTER_UNIPHY_F;
1346 default:
1347 return TRANSMITTER_UNKNOWN;
1348 }
1349 break;
1350 case ENCODER_ID_INTERNAL_UNIPHY3:
1351 switch (encoder.enum_id) {
1352 case ENUM_ID_1:
1353 return TRANSMITTER_UNIPHY_G;
1354 default:
1355 return TRANSMITTER_UNKNOWN;
1356 }
1357 break;
1358 case ENCODER_ID_EXTERNAL_NUTMEG:
1359 switch (encoder.enum_id) {
1360 case ENUM_ID_1:
1361 return TRANSMITTER_NUTMEG_CRT;
1362 default:
1363 return TRANSMITTER_UNKNOWN;
1364 }
1365 break;
1366 case ENCODER_ID_EXTERNAL_TRAVIS:
1367 switch (encoder.enum_id) {
1368 case ENUM_ID_1:
1369 return TRANSMITTER_TRAVIS_CRT;
1370 case ENUM_ID_2:
1371 return TRANSMITTER_TRAVIS_LCD;
1372 default:
1373 return TRANSMITTER_UNKNOWN;
1374 }
1375 break;
1376 default:
1377 return TRANSMITTER_UNKNOWN;
1378 }
1379}
1380
1381static bool dc_link_construct(struct dc_link *link,
1382 const struct link_init_data *init_params)
1383{
1384 uint8_t i;
1385 struct ddc_service_init_data ddc_service_init_data = { { 0 } };
1386 struct dc_context *dc_ctx = init_params->ctx;
1387 struct encoder_init_data enc_init_data = { 0 };
1388 struct panel_cntl_init_data panel_cntl_init_data = { 0 };
1389 struct integrated_info *info;
1390 struct dc_bios *bios = init_params->dc->ctx->dc_bios;
1391 const struct dc_vbios_funcs *bp_funcs = bios->funcs;
1392 struct bp_disp_connector_caps_info disp_connect_caps_info = { 0 };
1393
1394 DC_LOGGER_INIT(dc_ctx->logger);
1395
1396 info = kzalloc(sizeof(*info), GFP_KERNEL);
1397 if (!info)
1398 goto create_fail;
1399
1400 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1401 link->irq_source_hpd_rx = DC_IRQ_SOURCE_INVALID;
1402
1403 link->link_status.dpcd_caps = &link->dpcd_caps;
1404
1405 link->dc = init_params->dc;
1406 link->ctx = dc_ctx;
1407 link->link_index = init_params->link_index;
1408
1409 memset(&link->preferred_training_settings, 0,
1410 sizeof(struct dc_link_training_overrides));
1411 memset(&link->preferred_link_setting, 0,
1412 sizeof(struct dc_link_settings));
1413
1414 link->link_id =
1415 bios->funcs->get_connector_id(bios, init_params->connector_index);
1416
1417 link->ep_type = DISPLAY_ENDPOINT_PHY;
1418
1419 DC_LOG_DC("BIOS object table - link_id: %d", link->link_id.id);
1420
1421 if (bios->funcs->get_disp_connector_caps_info) {
1422 bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
1423 link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
1424 DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
1425 }
1426
1427 if (link->link_id.type != OBJECT_TYPE_CONNECTOR) {
1428 dm_output_to_console("%s: Invalid Connector ObjectID from Adapter Service for connector index:%d! type %d expected %d\n",
1429 __func__, init_params->connector_index,
1430 link->link_id.type, OBJECT_TYPE_CONNECTOR);
1431 goto create_fail;
1432 }
1433
1434 if (link->dc->res_pool->funcs->link_init)
1435 link->dc->res_pool->funcs->link_init(link);
1436
1437 link->hpd_gpio = get_hpd_gpio(link->ctx->dc_bios, link->link_id,
1438 link->ctx->gpio_service);
1439
1440 if (link->hpd_gpio) {
1441 dal_gpio_open(link->hpd_gpio, GPIO_MODE_INTERRUPT);
1442 dal_gpio_unlock_pin(link->hpd_gpio);
1443 link->irq_source_hpd = dal_irq_get_source(link->hpd_gpio);
1444
1445 DC_LOG_DC("BIOS object table - hpd_gpio id: %d", link->hpd_gpio->id);
1446 DC_LOG_DC("BIOS object table - hpd_gpio en: %d", link->hpd_gpio->en);
1447 }
1448
1449 switch (link->link_id.id) {
1450 case CONNECTOR_ID_HDMI_TYPE_A:
1451 link->connector_signal = SIGNAL_TYPE_HDMI_TYPE_A;
1452
1453 break;
1454 case CONNECTOR_ID_SINGLE_LINK_DVID:
1455 case CONNECTOR_ID_SINGLE_LINK_DVII:
1456 link->connector_signal = SIGNAL_TYPE_DVI_SINGLE_LINK;
1457 break;
1458 case CONNECTOR_ID_DUAL_LINK_DVID:
1459 case CONNECTOR_ID_DUAL_LINK_DVII:
1460 link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK;
1461 break;
1462 case CONNECTOR_ID_DISPLAY_PORT:
1463 link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT;
1464
1465 if (link->hpd_gpio)
1466 link->irq_source_hpd_rx =
1467 dal_irq_get_rx_source(link->hpd_gpio);
1468
1469 break;
1470 case CONNECTOR_ID_EDP:
1471 link->connector_signal = SIGNAL_TYPE_EDP;
1472
1473 if (link->hpd_gpio) {
1474 if (!link->dc->config.allow_edp_hotplug_detection)
1475 link->irq_source_hpd = DC_IRQ_SOURCE_INVALID;
1476 link->irq_source_hpd_rx =
1477 dal_irq_get_rx_source(link->hpd_gpio);
1478 }
1479
1480 break;
1481 case CONNECTOR_ID_LVDS:
1482 link->connector_signal = SIGNAL_TYPE_LVDS;
1483 break;
1484 default:
1485 DC_LOG_WARNING("Unsupported Connector type:%d!\n",
1486 link->link_id.id);
1487 goto create_fail;
1488 }
1489
1490
1491 LINK_INFO("Connector[%d] description:"
1492 "signal %d\n",
1493 init_params->connector_index,
1494 link->connector_signal);
1495
1496 ddc_service_init_data.ctx = link->ctx;
1497 ddc_service_init_data.id = link->link_id;
1498 ddc_service_init_data.link = link;
1499 link->ddc = dal_ddc_service_create(&ddc_service_init_data);
1500
1501 if (!link->ddc) {
1502 DC_ERROR("Failed to create ddc_service!\n");
1503 goto ddc_create_fail;
1504 }
1505
1506 if (!link->ddc->ddc_pin) {
1507 DC_ERROR("Failed to get I2C info for connector!\n");
1508 goto ddc_create_fail;
1509 }
1510
1511 link->ddc_hw_inst =
1512 dal_ddc_get_line(dal_ddc_service_get_ddc_pin(link->ddc));
1513
1514
1515 if (link->dc->res_pool->funcs->panel_cntl_create &&
1516 (link->link_id.id == CONNECTOR_ID_EDP ||
1517 link->link_id.id == CONNECTOR_ID_LVDS)) {
1518 panel_cntl_init_data.ctx = dc_ctx;
1519 panel_cntl_init_data.inst =
1520 panel_cntl_init_data.ctx->dc_edp_id_count;
1521 link->panel_cntl =
1522 link->dc->res_pool->funcs->panel_cntl_create(
1523 &panel_cntl_init_data);
1524 panel_cntl_init_data.ctx->dc_edp_id_count++;
1525
1526 if (link->panel_cntl == NULL) {
1527 DC_ERROR("Failed to create link panel_cntl!\n");
1528 goto panel_cntl_create_fail;
1529 }
1530 }
1531
1532 enc_init_data.ctx = dc_ctx;
1533 bp_funcs->get_src_obj(dc_ctx->dc_bios, link->link_id, 0,
1534 &enc_init_data.encoder);
1535 enc_init_data.connector = link->link_id;
1536 enc_init_data.channel = get_ddc_line(link);
1537 enc_init_data.hpd_source = get_hpd_line(link);
1538
1539 link->hpd_src = enc_init_data.hpd_source;
1540
1541 enc_init_data.transmitter =
1542 translate_encoder_to_transmitter(enc_init_data.encoder);
1543 link->link_enc =
1544 link->dc->res_pool->funcs->link_enc_create(&enc_init_data);
1545
1546 if (!link->link_enc) {
1547 DC_ERROR("Failed to create link encoder!\n");
1548 goto link_enc_create_fail;
1549 }
1550
1551 DC_LOG_DC("BIOS object table - DP_IS_USB_C: %d", link->link_enc->features.flags.bits.DP_IS_USB_C);
1552
1553
1554
1555
1556 link->eng_id = link->link_enc->preferred_engine;
1557 link->dc->res_pool->link_encoders[link->eng_id - ENGINE_ID_DIGA] = link->link_enc;
1558 link->dc->res_pool->dig_link_enc_count++;
1559
1560 link->link_enc_hw_inst = link->link_enc->transmitter;
1561
1562 for (i = 0; i < 4; i++) {
1563 if (bp_funcs->get_device_tag(dc_ctx->dc_bios,
1564 link->link_id, i,
1565 &link->device_tag) != BP_RESULT_OK) {
1566 DC_ERROR("Failed to find device tag!\n");
1567 goto device_tag_fail;
1568 }
1569
1570
1571
1572
1573 if (!bp_funcs->is_device_id_supported(dc_ctx->dc_bios,
1574 link->device_tag.dev_id))
1575 continue;
1576 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_CRT &&
1577 link->connector_signal != SIGNAL_TYPE_RGB)
1578 continue;
1579 if (link->device_tag.dev_id.device_type == DEVICE_TYPE_LCD &&
1580 link->connector_signal == SIGNAL_TYPE_RGB)
1581 continue;
1582
1583 DC_LOG_DC("BIOS object table - device_tag.acpi_device: %d", link->device_tag.acpi_device);
1584 DC_LOG_DC("BIOS object table - device_tag.dev_id.device_type: %d", link->device_tag.dev_id.device_type);
1585 DC_LOG_DC("BIOS object table - device_tag.dev_id.enum_id: %d", link->device_tag.dev_id.enum_id);
1586 break;
1587 }
1588
1589 if (bios->integrated_info)
1590 memcpy(info, bios->integrated_info, sizeof(*info));
1591
1592
1593 for (i = 0; i < MAX_NUMBER_OF_EXT_DISPLAY_PATH; i++) {
1594 struct external_display_path *path =
1595 &info->ext_disp_conn_info.path[i];
1596
1597 if (path->device_connector_id.enum_id == link->link_id.enum_id &&
1598 path->device_connector_id.id == link->link_id.id &&
1599 path->device_connector_id.type == link->link_id.type) {
1600 if (link->device_tag.acpi_device != 0 &&
1601 path->device_acpi_enum == link->device_tag.acpi_device) {
1602 link->ddi_channel_mapping = path->channel_mapping;
1603 link->chip_caps = path->caps;
1604 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1605 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1606 } else if (path->device_tag ==
1607 link->device_tag.dev_id.raw_device_tag) {
1608 link->ddi_channel_mapping = path->channel_mapping;
1609 link->chip_caps = path->caps;
1610 DC_LOG_DC("BIOS object table - ddi_channel_mapping: 0x%04X", link->ddi_channel_mapping.raw);
1611 DC_LOG_DC("BIOS object table - chip_caps: %d", link->chip_caps);
1612 }
1613 break;
1614 }
1615 }
1616
1617 if (bios->funcs->get_atom_dc_golden_table)
1618 bios->funcs->get_atom_dc_golden_table(bios);
1619
1620
1621
1622
1623
1624
1625
1626 program_hpd_filter(link);
1627
1628 link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
1629
1630 DC_LOG_DC("BIOS object table - %s finished successfully.\n", __func__);
1631 kfree(info);
1632 return true;
1633device_tag_fail:
1634 link->link_enc->funcs->destroy(&link->link_enc);
1635link_enc_create_fail:
1636 if (link->panel_cntl != NULL)
1637 link->panel_cntl->funcs->destroy(&link->panel_cntl);
1638panel_cntl_create_fail:
1639 dal_ddc_service_destroy(&link->ddc);
1640ddc_create_fail:
1641create_fail:
1642
1643 if (link->hpd_gpio) {
1644 dal_gpio_destroy_irq(&link->hpd_gpio);
1645 link->hpd_gpio = NULL;
1646 }
1647
1648 DC_LOG_DC("BIOS object table - %s failed.\n", __func__);
1649 kfree(info);
1650
1651 return false;
1652}
1653
1654
1655
1656
1657struct dc_link *link_create(const struct link_init_data *init_params)
1658{
1659 struct dc_link *link =
1660 kzalloc(sizeof(*link), GFP_KERNEL);
1661
1662 if (NULL == link)
1663 goto alloc_fail;
1664
1665 if (false == dc_link_construct(link, init_params))
1666 goto construct_fail;
1667
1668
1669
1670
1671
1672 link->preferred_link_setting.dpcd_source_device_specific_field_support = true;
1673
1674 return link;
1675
1676construct_fail:
1677 kfree(link);
1678
1679alloc_fail:
1680 return NULL;
1681}
1682
1683void link_destroy(struct dc_link **link)
1684{
1685 dc_link_destruct(*link);
1686 kfree(*link);
1687 *link = NULL;
1688}
1689
1690static void enable_stream_features(struct pipe_ctx *pipe_ctx)
1691{
1692 struct dc_stream_state *stream = pipe_ctx->stream;
1693
1694 if (pipe_ctx->stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) {
1695 struct dc_link *link = stream->link;
1696 union down_spread_ctrl old_downspread;
1697 union down_spread_ctrl new_downspread;
1698
1699 core_link_read_dpcd(link, DP_DOWNSPREAD_CTRL,
1700 &old_downspread.raw, sizeof(old_downspread));
1701
1702 new_downspread.raw = old_downspread.raw;
1703
1704 new_downspread.bits.IGNORE_MSA_TIMING_PARAM =
1705 (stream->ignore_msa_timing_param) ? 1 : 0;
1706
1707 if (new_downspread.raw != old_downspread.raw) {
1708 core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
1709 &new_downspread.raw, sizeof(new_downspread));
1710 }
1711
1712 } else {
1713 dm_helpers_mst_enable_stream_features(stream);
1714 }
1715}
1716
1717static enum dc_status enable_link_dp(struct dc_state *state,
1718 struct pipe_ctx *pipe_ctx)
1719{
1720 struct dc_stream_state *stream = pipe_ctx->stream;
1721 enum dc_status status;
1722 bool skip_video_pattern;
1723 struct dc_link *link = stream->link;
1724 struct dc_link_settings link_settings = {0};
1725 bool fec_enable;
1726 int i;
1727 bool apply_seamless_boot_optimization = false;
1728 uint32_t bl_oled_enable_delay = 50;
1729 const uint32_t post_oui_delay = 30;
1730
1731 bool do_fallback = false;
1732
1733
1734 for (i = 0; i < state->stream_count; i++) {
1735 if (state->streams[i]->apply_seamless_boot_optimization) {
1736 apply_seamless_boot_optimization = true;
1737 break;
1738 }
1739 }
1740
1741
1742 decide_link_settings(stream, &link_settings);
1743
1744 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) {
1745
1746 link->dc->hwss.edp_power_control(link, true);
1747 link->dc->hwss.edp_wait_for_hpd_ready(link, true);
1748 }
1749
1750 pipe_ctx->stream_res.pix_clk_params.requested_sym_clk =
1751 link_settings.link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
1752 if (state->clk_mgr && !apply_seamless_boot_optimization)
1753 state->clk_mgr->funcs->update_clocks(state->clk_mgr,
1754 state, false);
1755
1756
1757 dpcd_set_source_specific_data(link);
1758 if (link->dpcd_sink_ext_caps.raw != 0)
1759 msleep(post_oui_delay);
1760
1761 skip_video_pattern = true;
1762
1763 if (link_settings.link_rate == LINK_RATE_LOW)
1764 skip_video_pattern = false;
1765
1766 if (perform_link_training_with_retries(&link_settings,
1767 skip_video_pattern,
1768 LINK_TRAINING_ATTEMPTS,
1769 pipe_ctx,
1770 pipe_ctx->stream->signal,
1771 do_fallback)) {
1772 link->cur_link_settings = link_settings;
1773 status = DC_OK;
1774 } else {
1775 status = DC_FAIL_DP_LINK_TRAINING;
1776 }
1777
1778 if (link->preferred_training_settings.fec_enable)
1779 fec_enable = *link->preferred_training_settings.fec_enable;
1780 else
1781 fec_enable = true;
1782
1783 dp_set_fec_enable(link, fec_enable);
1784
1785
1786 if (link->dpcd_sink_ext_caps.bits.oled == 1 ||
1787 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 ||
1788 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) {
1789 dc_link_set_default_brightness_aux(link);
1790 if (link->dpcd_sink_ext_caps.bits.oled == 1)
1791 msleep(bl_oled_enable_delay);
1792 dc_link_backlight_enable_aux(link, true);
1793 }
1794
1795 return status;
1796}
1797
1798static enum dc_status enable_link_edp(
1799 struct dc_state *state,
1800 struct pipe_ctx *pipe_ctx)
1801{
1802 enum dc_status status;
1803
1804 status = enable_link_dp(state, pipe_ctx);
1805
1806 return status;
1807}
1808
1809static enum dc_status enable_link_dp_mst(
1810 struct dc_state *state,
1811 struct pipe_ctx *pipe_ctx)
1812{
1813 struct dc_link *link = pipe_ctx->stream->link;
1814
1815
1816
1817
1818 if (link->link_status.link_active)
1819 return DC_OK;
1820
1821
1822 dm_helpers_dp_mst_clear_payload_allocation_table(link->ctx, link);
1823
1824
1825
1826
1827 dm_helpers_dp_mst_poll_pending_down_reply(link->ctx, link);
1828
1829
1830 dp_enable_mst_on_sink(link, true);
1831
1832 return enable_link_dp(state, pipe_ctx);
1833}
1834
1835static bool get_ext_hdmi_settings(struct pipe_ctx *pipe_ctx,
1836 enum engine_id eng_id,
1837 struct ext_hdmi_settings *settings)
1838{
1839 bool result = false;
1840 int i = 0;
1841 struct integrated_info *integrated_info =
1842 pipe_ctx->stream->ctx->dc_bios->integrated_info;
1843
1844 if (integrated_info == NULL)
1845 return false;
1846
1847
1848
1849
1850
1851
1852
1853
1854 if (integrated_info->gpu_cap_info & 0x20) {
1855 switch (eng_id) {
1856 case ENGINE_ID_DIGA:
1857 settings->slv_addr = integrated_info->dp0_ext_hdmi_slv_addr;
1858 settings->reg_num = integrated_info->dp0_ext_hdmi_6g_reg_num;
1859 settings->reg_num_6g = integrated_info->dp0_ext_hdmi_6g_reg_num;
1860 memmove(settings->reg_settings,
1861 integrated_info->dp0_ext_hdmi_reg_settings,
1862 sizeof(integrated_info->dp0_ext_hdmi_reg_settings));
1863 memmove(settings->reg_settings_6g,
1864 integrated_info->dp0_ext_hdmi_6g_reg_settings,
1865 sizeof(integrated_info->dp0_ext_hdmi_6g_reg_settings));
1866 result = true;
1867 break;
1868 case ENGINE_ID_DIGB:
1869 settings->slv_addr = integrated_info->dp1_ext_hdmi_slv_addr;
1870 settings->reg_num = integrated_info->dp1_ext_hdmi_6g_reg_num;
1871 settings->reg_num_6g = integrated_info->dp1_ext_hdmi_6g_reg_num;
1872 memmove(settings->reg_settings,
1873 integrated_info->dp1_ext_hdmi_reg_settings,
1874 sizeof(integrated_info->dp1_ext_hdmi_reg_settings));
1875 memmove(settings->reg_settings_6g,
1876 integrated_info->dp1_ext_hdmi_6g_reg_settings,
1877 sizeof(integrated_info->dp1_ext_hdmi_6g_reg_settings));
1878 result = true;
1879 break;
1880 case ENGINE_ID_DIGC:
1881 settings->slv_addr = integrated_info->dp2_ext_hdmi_slv_addr;
1882 settings->reg_num = integrated_info->dp2_ext_hdmi_6g_reg_num;
1883 settings->reg_num_6g = integrated_info->dp2_ext_hdmi_6g_reg_num;
1884 memmove(settings->reg_settings,
1885 integrated_info->dp2_ext_hdmi_reg_settings,
1886 sizeof(integrated_info->dp2_ext_hdmi_reg_settings));
1887 memmove(settings->reg_settings_6g,
1888 integrated_info->dp2_ext_hdmi_6g_reg_settings,
1889 sizeof(integrated_info->dp2_ext_hdmi_6g_reg_settings));
1890 result = true;
1891 break;
1892 case ENGINE_ID_DIGD:
1893 settings->slv_addr = integrated_info->dp3_ext_hdmi_slv_addr;
1894 settings->reg_num = integrated_info->dp3_ext_hdmi_6g_reg_num;
1895 settings->reg_num_6g = integrated_info->dp3_ext_hdmi_6g_reg_num;
1896 memmove(settings->reg_settings,
1897 integrated_info->dp3_ext_hdmi_reg_settings,
1898 sizeof(integrated_info->dp3_ext_hdmi_reg_settings));
1899 memmove(settings->reg_settings_6g,
1900 integrated_info->dp3_ext_hdmi_6g_reg_settings,
1901 sizeof(integrated_info->dp3_ext_hdmi_6g_reg_settings));
1902 result = true;
1903 break;
1904 default:
1905 break;
1906 }
1907
1908 if (result == true) {
1909
1910 if (settings->slv_addr == 0)
1911 return false;
1912 if (settings->reg_num > 9)
1913 return false;
1914 if (settings->reg_num_6g > 3)
1915 return false;
1916
1917 for (i = 0; i < settings->reg_num; i++) {
1918 if (settings->reg_settings[i].i2c_reg_index > 0x20)
1919 return false;
1920 }
1921
1922 for (i = 0; i < settings->reg_num_6g; i++) {
1923 if (settings->reg_settings_6g[i].i2c_reg_index > 0x20)
1924 return false;
1925 }
1926 }
1927 }
1928
1929 return result;
1930}
1931
1932static bool i2c_write(struct pipe_ctx *pipe_ctx,
1933 uint8_t address, uint8_t *buffer, uint32_t length)
1934{
1935 struct i2c_command cmd = {0};
1936 struct i2c_payload payload = {0};
1937
1938 memset(&payload, 0, sizeof(payload));
1939 memset(&cmd, 0, sizeof(cmd));
1940
1941 cmd.number_of_payloads = 1;
1942 cmd.engine = I2C_COMMAND_ENGINE_DEFAULT;
1943 cmd.speed = pipe_ctx->stream->ctx->dc->caps.i2c_speed_in_khz;
1944
1945 payload.address = address;
1946 payload.data = buffer;
1947 payload.length = length;
1948 payload.write = true;
1949 cmd.payloads = &payload;
1950
1951 if (dm_helpers_submit_i2c(pipe_ctx->stream->ctx,
1952 pipe_ctx->stream->link, &cmd))
1953 return true;
1954
1955 return false;
1956}
1957
1958static void write_i2c_retimer_setting(
1959 struct pipe_ctx *pipe_ctx,
1960 bool is_vga_mode,
1961 bool is_over_340mhz,
1962 struct ext_hdmi_settings *settings)
1963{
1964 uint8_t slave_address = (settings->slv_addr >> 1);
1965 uint8_t buffer[2];
1966 const uint8_t apply_rx_tx_change = 0x4;
1967 uint8_t offset = 0xA;
1968 uint8_t value = 0;
1969 int i = 0;
1970 bool i2c_success = false;
1971 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
1972
1973 memset(&buffer, 0, sizeof(buffer));
1974
1975
1976
1977 for (i = 0; i < settings->reg_num; i++) {
1978
1979 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
1980
1981 buffer[0] = settings->reg_settings[i].i2c_reg_index;
1982 buffer[1] = settings->reg_settings[i].i2c_reg_val;
1983 i2c_success = i2c_write(pipe_ctx, slave_address,
1984 buffer, sizeof(buffer));
1985 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
1986 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
1987 slave_address, buffer[0], buffer[1], i2c_success?1:0);
1988
1989 if (!i2c_success)
1990 goto i2c_write_fail;
1991
1992
1993
1994
1995 if (settings->reg_settings[i].i2c_reg_index == 0xA ||
1996 settings->reg_settings[i].i2c_reg_index == 0xB ||
1997 settings->reg_settings[i].i2c_reg_index == 0xC) {
1998
1999
2000 if (settings->reg_settings[i].i2c_reg_index == 0xA)
2001 value = settings->reg_settings[i].i2c_reg_val;
2002 else {
2003 i2c_success =
2004 dal_ddc_service_query_ddc_data(
2005 pipe_ctx->stream->link->ddc,
2006 slave_address, &offset, 1, &value, 1);
2007 if (!i2c_success)
2008 goto i2c_write_fail;
2009 }
2010
2011 buffer[0] = offset;
2012
2013 buffer[1] = value | apply_rx_tx_change;
2014 i2c_success = i2c_write(pipe_ctx, slave_address,
2015 buffer, sizeof(buffer));
2016 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2017 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2018 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2019 if (!i2c_success)
2020 goto i2c_write_fail;
2021 }
2022 }
2023 }
2024
2025
2026 if (is_over_340mhz) {
2027 for (i = 0; i < settings->reg_num_6g; i++) {
2028
2029 if (settings->reg_settings[i].i2c_reg_index <= 0x20) {
2030
2031 buffer[0] = settings->reg_settings_6g[i].i2c_reg_index;
2032 buffer[1] = settings->reg_settings_6g[i].i2c_reg_val;
2033 i2c_success = i2c_write(pipe_ctx, slave_address,
2034 buffer, sizeof(buffer));
2035 RETIMER_REDRIVER_INFO("above 340Mhz: retimer write to slave_address = 0x%x,\
2036 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2037 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2038
2039 if (!i2c_success)
2040 goto i2c_write_fail;
2041
2042
2043
2044
2045 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA ||
2046 settings->reg_settings_6g[i].i2c_reg_index == 0xB ||
2047 settings->reg_settings_6g[i].i2c_reg_index == 0xC) {
2048
2049
2050 if (settings->reg_settings_6g[i].i2c_reg_index == 0xA)
2051 value = settings->reg_settings_6g[i].i2c_reg_val;
2052 else {
2053 i2c_success =
2054 dal_ddc_service_query_ddc_data(
2055 pipe_ctx->stream->link->ddc,
2056 slave_address, &offset, 1, &value, 1);
2057 if (!i2c_success)
2058 goto i2c_write_fail;
2059 }
2060
2061 buffer[0] = offset;
2062
2063 buffer[1] = value | apply_rx_tx_change;
2064 i2c_success = i2c_write(pipe_ctx, slave_address,
2065 buffer, sizeof(buffer));
2066 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2067 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2068 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2069 if (!i2c_success)
2070 goto i2c_write_fail;
2071 }
2072 }
2073 }
2074 }
2075
2076 if (is_vga_mode) {
2077
2078
2079
2080 buffer[0] = 0xff;
2081 buffer[1] = 0x01;
2082 i2c_success = i2c_write(pipe_ctx, slave_address,
2083 buffer, sizeof(buffer));
2084 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2085 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2086 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2087 if (!i2c_success)
2088 goto i2c_write_fail;
2089
2090
2091 buffer[0] = 0x00;
2092 buffer[1] = 0x23;
2093 i2c_success = i2c_write(pipe_ctx, slave_address,
2094 buffer, sizeof(buffer));
2095 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2096 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2097 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2098 if (!i2c_success)
2099 goto i2c_write_fail;
2100
2101
2102 buffer[0] = 0xff;
2103 buffer[1] = 0x00;
2104 i2c_success = i2c_write(pipe_ctx, slave_address,
2105 buffer, sizeof(buffer));
2106 RETIMER_REDRIVER_INFO("retimer write to slave_address = 0x%x,\
2107 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2108 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2109 if (!i2c_success)
2110 goto i2c_write_fail;
2111
2112 }
2113
2114 return;
2115
2116i2c_write_fail:
2117 DC_LOG_DEBUG("Set retimer failed");
2118}
2119
2120static void write_i2c_default_retimer_setting(
2121 struct pipe_ctx *pipe_ctx,
2122 bool is_vga_mode,
2123 bool is_over_340mhz)
2124{
2125 uint8_t slave_address = (0xBA >> 1);
2126 uint8_t buffer[2];
2127 bool i2c_success = false;
2128 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2129
2130 memset(&buffer, 0, sizeof(buffer));
2131
2132
2133
2134 buffer[0] = 0x0A;
2135 buffer[1] = 0x13;
2136 i2c_success = i2c_write(pipe_ctx, slave_address,
2137 buffer, sizeof(buffer));
2138 RETIMER_REDRIVER_INFO("retimer writes default setting to slave_address = 0x%x,\
2139 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2140 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2141 if (!i2c_success)
2142 goto i2c_write_fail;
2143
2144
2145 buffer[0] = 0x0A;
2146 buffer[1] = 0x17;
2147 i2c_success = i2c_write(pipe_ctx, slave_address,
2148 buffer, sizeof(buffer));
2149 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2150 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2151 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2152 if (!i2c_success)
2153 goto i2c_write_fail;
2154
2155
2156 buffer[0] = 0x0B;
2157 buffer[1] = is_over_340mhz ? 0xDA : 0xD8;
2158 i2c_success = i2c_write(pipe_ctx, slave_address,
2159 buffer, sizeof(buffer));
2160 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2161 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2162 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2163 if (!i2c_success)
2164 goto i2c_write_fail;
2165
2166
2167 buffer[0] = 0x0A;
2168 buffer[1] = 0x17;
2169 i2c_success = i2c_write(pipe_ctx, slave_address,
2170 buffer, sizeof(buffer));
2171 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2172 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2173 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2174 if (!i2c_success)
2175 goto i2c_write_fail;
2176
2177
2178 buffer[0] = 0x0C;
2179 buffer[1] = is_over_340mhz ? 0x1D : 0x91;
2180 i2c_success = i2c_write(pipe_ctx, slave_address,
2181 buffer, sizeof(buffer));
2182 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2183 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2184 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2185 if (!i2c_success)
2186 goto i2c_write_fail;
2187
2188
2189 buffer[0] = 0x0A;
2190 buffer[1] = 0x17;
2191 i2c_success = i2c_write(pipe_ctx, slave_address,
2192 buffer, sizeof(buffer));
2193 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2194 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2195 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2196 if (!i2c_success)
2197 goto i2c_write_fail;
2198
2199
2200 if (is_vga_mode) {
2201
2202
2203
2204 buffer[0] = 0xff;
2205 buffer[1] = 0x01;
2206 i2c_success = i2c_write(pipe_ctx, slave_address,
2207 buffer, sizeof(buffer));
2208 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2209 offset = 0x%x, reg_val = 0x%x, i2c_success = %d\n",
2210 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2211 if (!i2c_success)
2212 goto i2c_write_fail;
2213
2214
2215 buffer[0] = 0x00;
2216 buffer[1] = 0x23;
2217 i2c_success = i2c_write(pipe_ctx, slave_address,
2218 buffer, sizeof(buffer));
2219 RETIMER_REDRIVER_INFO("retimer write to slave_addr = 0x%x,\
2220 offset = 0x%x, reg_val= 0x%x, i2c_success = %d\n",
2221 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2222 if (!i2c_success)
2223 goto i2c_write_fail;
2224
2225
2226 buffer[0] = 0xff;
2227 buffer[1] = 0x00;
2228 i2c_success = i2c_write(pipe_ctx, slave_address,
2229 buffer, sizeof(buffer));
2230 RETIMER_REDRIVER_INFO("retimer write default setting to slave_addr = 0x%x,\
2231 offset = 0x%x, reg_val= 0x%x, i2c_success = %d end here\n",
2232 slave_address, buffer[0], buffer[1], i2c_success?1:0);
2233 if (!i2c_success)
2234 goto i2c_write_fail;
2235 }
2236
2237 return;
2238
2239i2c_write_fail:
2240 DC_LOG_DEBUG("Set default retimer failed");
2241}
2242
2243static void write_i2c_redriver_setting(
2244 struct pipe_ctx *pipe_ctx,
2245 bool is_over_340mhz)
2246{
2247 uint8_t slave_address = (0xF0 >> 1);
2248 uint8_t buffer[16];
2249 bool i2c_success = false;
2250 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
2251
2252 memset(&buffer, 0, sizeof(buffer));
2253
2254
2255 buffer[3] = 0x4E;
2256 buffer[4] = 0x4E;
2257 buffer[5] = 0x4E;
2258 buffer[6] = is_over_340mhz ? 0x4E : 0x4A;
2259
2260 i2c_success = i2c_write(pipe_ctx, slave_address,
2261 buffer, sizeof(buffer));
2262 RETIMER_REDRIVER_INFO("redriver write 0 to all 16 reg offset expect following:\n\
2263 \t slave_addr = 0x%x, offset[3] = 0x%x, offset[4] = 0x%x,\
2264 offset[5] = 0x%x,offset[6] is_over_340mhz = 0x%x,\
2265 i2c_success = %d\n",
2266 slave_address, buffer[3], buffer[4], buffer[5], buffer[6], i2c_success?1:0);
2267
2268 if (!i2c_success)
2269 DC_LOG_DEBUG("Set redriver failed");
2270}
2271
2272static void disable_link(struct dc_link *link, enum signal_type signal)
2273{
2274
2275
2276
2277
2278
2279
2280
2281
2282
2283
2284
2285 if (dc_is_dp_signal(signal)) {
2286
2287 if (dc_is_dp_sst_signal(signal))
2288 dp_disable_link_phy(link, signal);
2289 else
2290 dp_disable_link_phy_mst(link, signal);
2291
2292 if (dc_is_dp_sst_signal(signal) ||
2293 link->mst_stream_alloc_table.stream_count == 0) {
2294 dp_set_fec_enable(link, false);
2295 dp_set_fec_ready(link, false);
2296 }
2297 } else {
2298 if (signal != SIGNAL_TYPE_VIRTUAL)
2299 link->link_enc->funcs->disable_output(link->link_enc, signal);
2300 }
2301
2302 if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
2303
2304 if (link->mst_stream_alloc_table.stream_count <= 0)
2305 link->link_status.link_active = false;
2306 } else {
2307 link->link_status.link_active = false;
2308 }
2309}
2310
2311static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
2312{
2313 struct dc_stream_state *stream = pipe_ctx->stream;
2314 struct dc_link *link = stream->link;
2315 enum dc_color_depth display_color_depth;
2316 enum engine_id eng_id;
2317 struct ext_hdmi_settings settings = {0};
2318 bool is_over_340mhz = false;
2319 bool is_vga_mode = (stream->timing.h_addressable == 640)
2320 && (stream->timing.v_addressable == 480);
2321
2322 if (stream->phy_pix_clk == 0)
2323 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2324 if (stream->phy_pix_clk > 340000)
2325 is_over_340mhz = true;
2326
2327 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
2328 unsigned short masked_chip_caps = pipe_ctx->stream->link->chip_caps &
2329 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
2330 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
2331
2332 eng_id = pipe_ctx->stream_res.stream_enc->id;
2333
2334 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings)) {
2335 write_i2c_retimer_setting(pipe_ctx,
2336 is_vga_mode, is_over_340mhz, &settings);
2337 } else {
2338 write_i2c_default_retimer_setting(pipe_ctx,
2339 is_vga_mode, is_over_340mhz);
2340 }
2341 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
2342
2343 write_i2c_redriver_setting(pipe_ctx, is_over_340mhz);
2344 }
2345 }
2346
2347 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2348 dal_ddc_service_write_scdc_data(
2349 stream->link->ddc,
2350 stream->phy_pix_clk,
2351 stream->timing.flags.LTE_340MCSC_SCRAMBLE);
2352
2353 memset(&stream->link->cur_link_settings, 0,
2354 sizeof(struct dc_link_settings));
2355
2356 display_color_depth = stream->timing.display_color_depth;
2357 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
2358 display_color_depth = COLOR_DEPTH_888;
2359
2360 link->link_enc->funcs->enable_tmds_output(
2361 link->link_enc,
2362 pipe_ctx->clock_source->id,
2363 display_color_depth,
2364 pipe_ctx->stream->signal,
2365 stream->phy_pix_clk);
2366
2367 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
2368 dal_ddc_service_read_scdc_data(link->ddc);
2369}
2370
2371static void enable_link_lvds(struct pipe_ctx *pipe_ctx)
2372{
2373 struct dc_stream_state *stream = pipe_ctx->stream;
2374 struct dc_link *link = stream->link;
2375
2376 if (stream->phy_pix_clk == 0)
2377 stream->phy_pix_clk = stream->timing.pix_clk_100hz / 10;
2378
2379 memset(&stream->link->cur_link_settings, 0,
2380 sizeof(struct dc_link_settings));
2381
2382 link->link_enc->funcs->enable_lvds_output(
2383 link->link_enc,
2384 pipe_ctx->clock_source->id,
2385 stream->phy_pix_clk);
2386
2387}
2388
2389
2390static enum dc_status enable_link(
2391 struct dc_state *state,
2392 struct pipe_ctx *pipe_ctx)
2393{
2394 enum dc_status status = DC_ERROR_UNEXPECTED;
2395 struct dc_stream_state *stream = pipe_ctx->stream;
2396 struct dc_link *link = stream->link;
2397
2398
2399
2400
2401
2402
2403
2404 if (link->link_status.link_active) {
2405 disable_link(link, pipe_ctx->stream->signal);
2406 }
2407
2408 switch (pipe_ctx->stream->signal) {
2409 case SIGNAL_TYPE_DISPLAY_PORT:
2410 status = enable_link_dp(state, pipe_ctx);
2411 break;
2412 case SIGNAL_TYPE_EDP:
2413 status = enable_link_edp(state, pipe_ctx);
2414 break;
2415 case SIGNAL_TYPE_DISPLAY_PORT_MST:
2416 status = enable_link_dp_mst(state, pipe_ctx);
2417 msleep(200);
2418 break;
2419 case SIGNAL_TYPE_DVI_SINGLE_LINK:
2420 case SIGNAL_TYPE_DVI_DUAL_LINK:
2421 case SIGNAL_TYPE_HDMI_TYPE_A:
2422 enable_link_hdmi(pipe_ctx);
2423 status = DC_OK;
2424 break;
2425 case SIGNAL_TYPE_LVDS:
2426 enable_link_lvds(pipe_ctx);
2427 status = DC_OK;
2428 break;
2429 case SIGNAL_TYPE_VIRTUAL:
2430 status = DC_OK;
2431 break;
2432 default:
2433 break;
2434 }
2435
2436 if (status == DC_OK)
2437 pipe_ctx->stream->link->link_status.link_active = true;
2438
2439 return status;
2440}
2441
2442static uint32_t get_timing_pixel_clock_100hz(const struct dc_crtc_timing *timing)
2443{
2444
2445 uint32_t pxl_clk = timing->pix_clk_100hz;
2446
2447 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
2448 pxl_clk /= 2;
2449 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
2450 pxl_clk = pxl_clk * 2 / 3;
2451
2452 if (timing->display_color_depth == COLOR_DEPTH_101010)
2453 pxl_clk = pxl_clk * 10 / 8;
2454 else if (timing->display_color_depth == COLOR_DEPTH_121212)
2455 pxl_clk = pxl_clk * 12 / 8;
2456
2457 return pxl_clk;
2458}
2459
2460static bool dp_active_dongle_validate_timing(
2461 const struct dc_crtc_timing *timing,
2462 const struct dpcd_caps *dpcd_caps)
2463{
2464 const struct dc_dongle_caps *dongle_caps = &dpcd_caps->dongle_caps;
2465
2466 switch (dpcd_caps->dongle_type) {
2467 case DISPLAY_DONGLE_DP_VGA_CONVERTER:
2468 case DISPLAY_DONGLE_DP_DVI_CONVERTER:
2469 case DISPLAY_DONGLE_DP_DVI_DONGLE:
2470 if (timing->pixel_encoding == PIXEL_ENCODING_RGB)
2471 return true;
2472 else
2473 return false;
2474 default:
2475 break;
2476 }
2477
2478 if (dpcd_caps->dongle_type != DISPLAY_DONGLE_DP_HDMI_CONVERTER ||
2479 dongle_caps->extendedCapValid == false)
2480 return true;
2481
2482
2483 switch (timing->pixel_encoding) {
2484 case PIXEL_ENCODING_RGB:
2485 case PIXEL_ENCODING_YCBCR444:
2486 break;
2487 case PIXEL_ENCODING_YCBCR422:
2488 if (!dongle_caps->is_dp_hdmi_ycbcr422_pass_through)
2489 return false;
2490 break;
2491 case PIXEL_ENCODING_YCBCR420:
2492 if (!dongle_caps->is_dp_hdmi_ycbcr420_pass_through)
2493 return false;
2494 break;
2495 default:
2496
2497 return false;
2498 }
2499
2500 switch (timing->display_color_depth) {
2501 case COLOR_DEPTH_666:
2502 case COLOR_DEPTH_888:
2503
2504 break;
2505 case COLOR_DEPTH_101010:
2506 if (dongle_caps->dp_hdmi_max_bpc < 10)
2507 return false;
2508 break;
2509 case COLOR_DEPTH_121212:
2510 if (dongle_caps->dp_hdmi_max_bpc < 12)
2511 return false;
2512 break;
2513 case COLOR_DEPTH_141414:
2514 case COLOR_DEPTH_161616:
2515 default:
2516
2517 return false;
2518 }
2519
2520 if (get_timing_pixel_clock_100hz(timing) > (dongle_caps->dp_hdmi_max_pixel_clk_in_khz * 10))
2521 return false;
2522
2523 return true;
2524}
2525
2526enum dc_status dc_link_validate_mode_timing(
2527 const struct dc_stream_state *stream,
2528 struct dc_link *link,
2529 const struct dc_crtc_timing *timing)
2530{
2531 uint32_t max_pix_clk = stream->link->dongle_max_pix_clk * 10;
2532 struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
2533
2534
2535
2536
2537 if (link->remote_sinks[0] && link->remote_sinks[0]->sink_signal == SIGNAL_TYPE_VIRTUAL)
2538 return DC_OK;
2539
2540
2541 if (max_pix_clk != 0 && get_timing_pixel_clock_100hz(timing) > max_pix_clk)
2542 return DC_EXCEED_DONGLE_CAP;
2543
2544
2545 if (!dp_active_dongle_validate_timing(timing, dpcd_caps))
2546 return DC_EXCEED_DONGLE_CAP;
2547
2548 switch (stream->signal) {
2549 case SIGNAL_TYPE_EDP:
2550 case SIGNAL_TYPE_DISPLAY_PORT:
2551 if (!dp_validate_mode_timing(
2552 link,
2553 timing))
2554 return DC_NO_DP_LINK_BANDWIDTH;
2555 break;
2556
2557 default:
2558 break;
2559 }
2560
2561 return DC_OK;
2562}
2563
2564static struct abm *get_abm_from_stream_res(const struct dc_link *link)
2565{
2566 int i;
2567 struct dc *dc = NULL;
2568 struct abm *abm = NULL;
2569
2570 if (!link || !link->ctx)
2571 return NULL;
2572
2573 dc = link->ctx->dc;
2574
2575 for (i = 0; i < MAX_PIPES; i++) {
2576 struct pipe_ctx pipe_ctx = dc->current_state->res_ctx.pipe_ctx[i];
2577 struct dc_stream_state *stream = pipe_ctx.stream;
2578
2579 if (stream && stream->link == link) {
2580 abm = pipe_ctx.stream_res.abm;
2581 break;
2582 }
2583 }
2584 return abm;
2585}
2586
2587int dc_link_get_backlight_level(const struct dc_link *link)
2588{
2589 struct abm *abm = get_abm_from_stream_res(link);
2590 struct panel_cntl *panel_cntl = link->panel_cntl;
2591 struct dc *dc = link->ctx->dc;
2592 struct dmcu *dmcu = dc->res_pool->dmcu;
2593 bool fw_set_brightness = true;
2594
2595 if (dmcu)
2596 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu);
2597
2598 if (!fw_set_brightness && panel_cntl->funcs->get_current_backlight)
2599 return panel_cntl->funcs->get_current_backlight(panel_cntl);
2600 else if (abm != NULL && abm->funcs->get_current_backlight != NULL)
2601 return (int) abm->funcs->get_current_backlight(abm);
2602 else
2603 return DC_ERROR_UNEXPECTED;
2604}
2605
2606int dc_link_get_target_backlight_pwm(const struct dc_link *link)
2607{
2608 struct abm *abm = get_abm_from_stream_res(link);
2609
2610 if (abm == NULL || abm->funcs->get_target_backlight == NULL)
2611 return DC_ERROR_UNEXPECTED;
2612
2613 return (int) abm->funcs->get_target_backlight(abm);
2614}
2615
2616static struct pipe_ctx *get_pipe_from_link(const struct dc_link *link)
2617{
2618 int i;
2619 struct dc *dc = link->ctx->dc;
2620 struct pipe_ctx *pipe_ctx = NULL;
2621
2622 for (i = 0; i < MAX_PIPES; i++) {
2623 if (dc->current_state->res_ctx.pipe_ctx[i].stream) {
2624 if (dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
2625 pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
2626 break;
2627 }
2628 }
2629 }
2630
2631 return pipe_ctx;
2632}
2633
2634bool dc_link_set_backlight_level(const struct dc_link *link,
2635 uint32_t backlight_pwm_u16_16,
2636 uint32_t frame_ramp)
2637{
2638 struct dc *dc = link->ctx->dc;
2639
2640 DC_LOGGER_INIT(link->ctx->logger);
2641 DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n",
2642 backlight_pwm_u16_16, backlight_pwm_u16_16);
2643
2644 if (dc_is_embedded_signal(link->connector_signal)) {
2645 struct pipe_ctx *pipe_ctx = get_pipe_from_link(link);
2646
2647 if (pipe_ctx) {
2648
2649
2650
2651 if (pipe_ctx->plane_state == NULL)
2652 frame_ramp = 0;
2653 } else {
2654 return false;
2655 }
2656
2657 dc->hwss.set_backlight_level(
2658 pipe_ctx,
2659 backlight_pwm_u16_16,
2660 frame_ramp);
2661 }
2662 return true;
2663}
2664
2665bool dc_link_set_psr_allow_active(struct dc_link *link, bool allow_active,
2666 bool wait, bool force_static)
2667{
2668 struct dc *dc = link->ctx->dc;
2669 struct dmcu *dmcu = dc->res_pool->dmcu;
2670 struct dmub_psr *psr = dc->res_pool->psr;
2671 unsigned int panel_inst;
2672
2673 if (psr == NULL && force_static)
2674 return false;
2675
2676 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2677 return false;
2678
2679 link->psr_settings.psr_allow_active = allow_active;
2680#if defined(CONFIG_DRM_AMD_DC_DCN)
2681 if (!allow_active)
2682 dc_z10_restore(dc);
2683#endif
2684
2685 if (psr != NULL && link->psr_settings.psr_feature_enabled) {
2686 if (force_static && psr->funcs->psr_force_static)
2687 psr->funcs->psr_force_static(psr, panel_inst);
2688 psr->funcs->psr_enable(psr, allow_active, wait, panel_inst);
2689 } else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) && link->psr_settings.psr_feature_enabled)
2690 dmcu->funcs->set_psr_enable(dmcu, allow_active, wait);
2691 else
2692 return false;
2693
2694 return true;
2695}
2696
2697bool dc_link_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
2698{
2699 struct dc *dc = link->ctx->dc;
2700 struct dmcu *dmcu = dc->res_pool->dmcu;
2701 struct dmub_psr *psr = dc->res_pool->psr;
2702 unsigned int panel_inst;
2703
2704 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2705 return false;
2706
2707 if (psr != NULL && link->psr_settings.psr_feature_enabled)
2708 psr->funcs->psr_get_state(psr, state, panel_inst);
2709 else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
2710 dmcu->funcs->get_psr_state(dmcu, state);
2711
2712 return true;
2713}
2714
2715static inline enum physical_phy_id
2716transmitter_to_phy_id(enum transmitter transmitter_value)
2717{
2718 switch (transmitter_value) {
2719 case TRANSMITTER_UNIPHY_A:
2720 return PHYLD_0;
2721 case TRANSMITTER_UNIPHY_B:
2722 return PHYLD_1;
2723 case TRANSMITTER_UNIPHY_C:
2724 return PHYLD_2;
2725 case TRANSMITTER_UNIPHY_D:
2726 return PHYLD_3;
2727 case TRANSMITTER_UNIPHY_E:
2728 return PHYLD_4;
2729 case TRANSMITTER_UNIPHY_F:
2730 return PHYLD_5;
2731 case TRANSMITTER_NUTMEG_CRT:
2732 return PHYLD_6;
2733 case TRANSMITTER_TRAVIS_CRT:
2734 return PHYLD_7;
2735 case TRANSMITTER_TRAVIS_LCD:
2736 return PHYLD_8;
2737 case TRANSMITTER_UNIPHY_G:
2738 return PHYLD_9;
2739 case TRANSMITTER_COUNT:
2740 return PHYLD_COUNT;
2741 case TRANSMITTER_UNKNOWN:
2742 return PHYLD_UNKNOWN;
2743 default:
2744 WARN_ONCE(1, "Unknown transmitter value %d\n",
2745 transmitter_value);
2746 return PHYLD_UNKNOWN;
2747 }
2748}
2749
2750bool dc_link_setup_psr(struct dc_link *link,
2751 const struct dc_stream_state *stream, struct psr_config *psr_config,
2752 struct psr_context *psr_context)
2753{
2754 struct dc *dc;
2755 struct dmcu *dmcu;
2756 struct dmub_psr *psr;
2757 int i;
2758 unsigned int panel_inst;
2759
2760 union dpcd_psr_configuration psr_configuration;
2761
2762 psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
2763
2764 if (!link)
2765 return false;
2766
2767 dc = link->ctx->dc;
2768 dmcu = dc->res_pool->dmcu;
2769 psr = dc->res_pool->psr;
2770
2771 if (!dmcu && !psr)
2772 return false;
2773
2774 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2775 return false;
2776
2777
2778 memset(&psr_configuration, 0, sizeof(psr_configuration));
2779
2780 psr_configuration.bits.ENABLE = 1;
2781 psr_configuration.bits.CRC_VERIFICATION = 1;
2782 psr_configuration.bits.FRAME_CAPTURE_INDICATION =
2783 psr_config->psr_frame_capture_indication_req;
2784
2785
2786 if (psr_config->psr_version == 0x2) {
2787
2788
2789
2790
2791
2792 psr_configuration.bits.LINE_CAPTURE_INDICATION = 0;
2793
2794
2795
2796 psr_configuration.bits.IRQ_HPD_WITH_CRC_ERROR = 1;
2797 }
2798
2799 dm_helpers_dp_write_dpcd(
2800 link->ctx,
2801 link,
2802 368,
2803 &psr_configuration.raw,
2804 sizeof(psr_configuration.raw));
2805
2806 psr_context->channel = link->ddc->ddc_pin->hw_info.ddc_channel;
2807 psr_context->transmitterId = link->link_enc->transmitter;
2808 psr_context->engineId = link->link_enc->preferred_engine;
2809
2810 for (i = 0; i < MAX_PIPES; i++) {
2811 if (dc->current_state->res_ctx.pipe_ctx[i].stream
2812 == stream) {
2813
2814
2815
2816 psr_context->controllerId =
2817 dc->current_state->res_ctx.
2818 pipe_ctx[i].stream_res.tg->inst + 1;
2819 break;
2820 }
2821 }
2822
2823
2824 psr_context->phyType = PHY_TYPE_UNIPHY;
2825
2826 psr_context->smuPhyId =
2827 transmitter_to_phy_id(link->link_enc->transmitter);
2828
2829 psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
2830 psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
2831 timing.pix_clk_100hz * 100),
2832 stream->timing.v_total),
2833 stream->timing.h_total);
2834
2835 psr_context->psrSupportedDisplayConfig = true;
2836 psr_context->psrExitLinkTrainingRequired =
2837 psr_config->psr_exit_link_training_required;
2838 psr_context->sdpTransmitLineNumDeadline =
2839 psr_config->psr_sdp_transmit_line_num_deadline;
2840 psr_context->psrFrameCaptureIndicationReq =
2841 psr_config->psr_frame_capture_indication_req;
2842
2843 psr_context->skipPsrWaitForPllLock = 0;
2844
2845 psr_context->numberOfControllers =
2846 link->dc->res_pool->timing_generator_count;
2847
2848 psr_context->rfb_update_auto_en = true;
2849
2850
2851 psr_context->timehyst_frames = 2;
2852
2853
2854
2855 psr_context->hyst_lines = stream->timing.v_total / 2 / 100;
2856 psr_context->aux_repeats = 10;
2857
2858 psr_context->psr_level.u32all = 0;
2859
2860
2861#if defined(CONFIG_DRM_AMD_DC_DCN)
2862 if (link->ctx->asic_id.chip_family >= FAMILY_RV) {
2863 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2864 if (link->ctx->asic_id.chip_family == FAMILY_YELLOW_CARP && !dc->debug.disable_z10)
2865 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = false;
2866 }
2867#else
2868 if (link->ctx->asic_id.chip_family >= FAMILY_RV)
2869 psr_context->psr_level.bits.SKIP_CRTC_DISABLE = true;
2870#endif
2871
2872
2873
2874
2875
2876
2877 psr_context->allow_smu_optimizations = psr_config->allow_smu_optimizations;
2878 psr_context->allow_multi_disp_optimizations = psr_config->allow_multi_disp_optimizations;
2879
2880
2881
2882
2883 psr_context->psr_level.bits.DISABLE_PSR_ENTRY_ABORT = 1;
2884
2885
2886
2887
2888 psr_context->frame_delay = 0;
2889
2890 if (psr)
2891 link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
2892 link, psr_context, panel_inst);
2893 else
2894 link->psr_settings.psr_feature_enabled = dmcu->funcs->setup_psr(dmcu, link, psr_context);
2895
2896
2897
2898
2899 if (link->psr_settings.psr_feature_enabled == 0)
2900 ASSERT(0);
2901
2902 return true;
2903
2904}
2905
2906void dc_link_get_psr_residency(const struct dc_link *link, uint32_t *residency)
2907{
2908 struct dc *dc = link->ctx->dc;
2909 struct dmub_psr *psr = dc->res_pool->psr;
2910 unsigned int panel_inst;
2911
2912 if (!dc_get_edp_link_panel_inst(dc, link, &panel_inst))
2913 return;
2914
2915
2916 if (psr != NULL && link->psr_settings.psr_feature_enabled)
2917 psr->funcs->psr_get_residency(psr, residency, panel_inst);
2918 else
2919 *residency = 0;
2920}
2921
2922const struct dc_link_status *dc_link_get_status(const struct dc_link *link)
2923{
2924 return &link->link_status;
2925}
2926
2927void core_link_resume(struct dc_link *link)
2928{
2929 if (link->connector_signal != SIGNAL_TYPE_VIRTUAL)
2930 program_hpd_filter(link);
2931}
2932
2933static struct fixed31_32 get_pbn_per_slot(struct dc_stream_state *stream)
2934{
2935 struct fixed31_32 mbytes_per_sec;
2936 uint32_t link_rate_in_mbytes_per_sec = dc_link_bandwidth_kbps(stream->link,
2937 &stream->link->cur_link_settings);
2938 link_rate_in_mbytes_per_sec /= 8000;
2939
2940 mbytes_per_sec = dc_fixpt_from_int(link_rate_in_mbytes_per_sec);
2941
2942 return dc_fixpt_div_int(mbytes_per_sec, 54);
2943}
2944
2945static struct fixed31_32 get_pbn_from_bw_in_kbps(uint64_t kbps)
2946{
2947 struct fixed31_32 peak_kbps;
2948 uint32_t numerator = 0;
2949 uint32_t denominator = 1;
2950
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962 numerator = 64 * PEAK_FACTOR_X1000;
2963 denominator = 54 * 8 * 1000 * 1000;
2964 kbps *= numerator;
2965 peak_kbps = dc_fixpt_from_fraction(kbps, denominator);
2966
2967 return peak_kbps;
2968}
2969
2970static struct fixed31_32 get_pbn_from_timing(struct pipe_ctx *pipe_ctx)
2971{
2972 uint64_t kbps;
2973
2974 kbps = dc_bandwidth_in_kbps_from_timing(&pipe_ctx->stream->timing);
2975 return get_pbn_from_bw_in_kbps(kbps);
2976}
2977
2978static void update_mst_stream_alloc_table(
2979 struct dc_link *link,
2980 struct stream_encoder *stream_enc,
2981 const struct dp_mst_stream_allocation_table *proposed_table)
2982{
2983 struct link_mst_stream_allocation work_table[MAX_CONTROLLER_NUM] = {
2984 { 0 } };
2985 struct link_mst_stream_allocation *dc_alloc;
2986
2987 int i;
2988 int j;
2989
2990
2991 ASSERT(proposed_table->stream_count -
2992 link->mst_stream_alloc_table.stream_count < 2);
2993
2994
2995 for (i = 0; i < proposed_table->stream_count; i++) {
2996
2997 for (j = 0; j < link->mst_stream_alloc_table.stream_count; j++) {
2998 dc_alloc =
2999 &link->mst_stream_alloc_table.stream_allocations[j];
3000
3001 if (dc_alloc->vcp_id ==
3002 proposed_table->stream_allocations[i].vcp_id) {
3003
3004 work_table[i] = *dc_alloc;
3005 work_table[i].slot_count = proposed_table->stream_allocations[i].slot_count;
3006 break;
3007 }
3008 }
3009
3010
3011 if (j == link->mst_stream_alloc_table.stream_count) {
3012 work_table[i].vcp_id =
3013 proposed_table->stream_allocations[i].vcp_id;
3014 work_table[i].slot_count =
3015 proposed_table->stream_allocations[i].slot_count;
3016 work_table[i].stream_enc = stream_enc;
3017 }
3018 }
3019
3020
3021 link->mst_stream_alloc_table.stream_count =
3022 proposed_table->stream_count;
3023 for (i = 0; i < MAX_CONTROLLER_NUM; i++)
3024 link->mst_stream_alloc_table.stream_allocations[i] =
3025 work_table[i];
3026}
3027
3028
3029
3030
3031enum dc_status dc_link_allocate_mst_payload(struct pipe_ctx *pipe_ctx)
3032{
3033 struct dc_stream_state *stream = pipe_ctx->stream;
3034 struct dc_link *link = stream->link;
3035 struct link_encoder *link_encoder = link->link_enc;
3036 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3037 struct dp_mst_stream_allocation_table proposed_table = {0};
3038 struct fixed31_32 avg_time_slots_per_mtp;
3039 struct fixed31_32 pbn;
3040 struct fixed31_32 pbn_per_slot;
3041 uint8_t i;
3042 enum act_return_status ret;
3043 DC_LOGGER_INIT(link->ctx->logger);
3044
3045
3046
3047
3048
3049
3050
3051 if (dm_helpers_dp_mst_write_payload_allocation_table(
3052 stream->ctx,
3053 stream,
3054 &proposed_table,
3055 true)) {
3056 update_mst_stream_alloc_table(
3057 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3058 }
3059 else
3060 DC_LOG_WARNING("Failed to update"
3061 "MST allocation table for"
3062 "pipe idx:%d\n",
3063 pipe_ctx->pipe_idx);
3064
3065 DC_LOG_MST("%s "
3066 "stream_count: %d: \n ",
3067 __func__,
3068 link->mst_stream_alloc_table.stream_count);
3069
3070 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3071 DC_LOG_MST("stream_enc[%d]: %p "
3072 "stream[%d].vcp_id: %d "
3073 "stream[%d].slot_count: %d\n",
3074 i,
3075 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3076 i,
3077 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3078 i,
3079 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3080 }
3081
3082 ASSERT(proposed_table.stream_count > 0);
3083
3084
3085 link_encoder->funcs->update_mst_stream_allocation_table(
3086 link_encoder,
3087 &link->mst_stream_alloc_table);
3088
3089
3090 ret = dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3091 stream->ctx,
3092 stream);
3093
3094 if (ret != ACT_LINK_LOST) {
3095 dm_helpers_dp_mst_send_payload_allocation(
3096 stream->ctx,
3097 stream,
3098 true);
3099 }
3100
3101
3102 pbn_per_slot = get_pbn_per_slot(stream);
3103 if (pbn_per_slot.value == 0) {
3104 DC_LOG_ERROR("Failure: pbn_per_slot==0 not allowed. Cannot continue, returning DC_UNSUPPORTED_VALUE.\n");
3105 return DC_UNSUPPORTED_VALUE;
3106 }
3107 pbn = get_pbn_from_timing(pipe_ctx);
3108 avg_time_slots_per_mtp = dc_fixpt_div(pbn, pbn_per_slot);
3109
3110 stream_encoder->funcs->set_throttled_vcp_size(
3111 stream_encoder,
3112 avg_time_slots_per_mtp);
3113
3114 return DC_OK;
3115
3116}
3117
3118static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
3119{
3120 struct dc_stream_state *stream = pipe_ctx->stream;
3121 struct dc_link *link = stream->link;
3122 struct link_encoder *link_encoder = link->link_enc;
3123 struct stream_encoder *stream_encoder = pipe_ctx->stream_res.stream_enc;
3124 struct dp_mst_stream_allocation_table proposed_table = {0};
3125 struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0);
3126 uint8_t i;
3127 bool mst_mode = (link->type == dc_connection_mst_branch);
3128 DC_LOGGER_INIT(link->ctx->logger);
3129
3130
3131
3132
3133
3134
3135
3136
3137
3138 stream_encoder->funcs->set_throttled_vcp_size(
3139 stream_encoder,
3140 avg_time_slots_per_mtp);
3141
3142
3143 if (mst_mode) {
3144 if (dm_helpers_dp_mst_write_payload_allocation_table(
3145 stream->ctx,
3146 stream,
3147 &proposed_table,
3148 false)) {
3149
3150 update_mst_stream_alloc_table(
3151 link, pipe_ctx->stream_res.stream_enc, &proposed_table);
3152 }
3153 else {
3154 DC_LOG_WARNING("Failed to update"
3155 "MST allocation table for"
3156 "pipe idx:%d\n",
3157 pipe_ctx->pipe_idx);
3158 }
3159 }
3160
3161 DC_LOG_MST("%s"
3162 "stream_count: %d: ",
3163 __func__,
3164 link->mst_stream_alloc_table.stream_count);
3165
3166 for (i = 0; i < MAX_CONTROLLER_NUM; i++) {
3167 DC_LOG_MST("stream_enc[%d]: %p "
3168 "stream[%d].vcp_id: %d "
3169 "stream[%d].slot_count: %d\n",
3170 i,
3171 (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc,
3172 i,
3173 link->mst_stream_alloc_table.stream_allocations[i].vcp_id,
3174 i,
3175 link->mst_stream_alloc_table.stream_allocations[i].slot_count);
3176 }
3177
3178 link_encoder->funcs->update_mst_stream_allocation_table(
3179 link_encoder,
3180 &link->mst_stream_alloc_table);
3181
3182 if (mst_mode) {
3183 dm_helpers_dp_mst_poll_for_allocation_change_trigger(
3184 stream->ctx,
3185 stream);
3186
3187 dm_helpers_dp_mst_send_payload_allocation(
3188 stream->ctx,
3189 stream,
3190 false);
3191 }
3192
3193 return DC_OK;
3194}
3195
3196
3197#if defined(CONFIG_DRM_AMD_DC_HDCP)
3198static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
3199{
3200 struct cp_psp *cp_psp = &pipe_ctx->stream->ctx->cp_psp;
3201 if (cp_psp && cp_psp->funcs.update_stream_config) {
3202 struct cp_psp_stream_config config = {0};
3203 enum dp_panel_mode panel_mode =
3204 dp_get_panel_mode(pipe_ctx->stream->link);
3205
3206 config.otg_inst = (uint8_t) pipe_ctx->stream_res.tg->inst;
3207
3208 config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
3209 config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
3210#if defined(CONFIG_DRM_AMD_DC_DCN)
3211 config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
3212 config.link_enc_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3213 config.phy_idx = pipe_ctx->stream->link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
3214#endif
3215 config.dpms_off = dpms_off;
3216 config.dm_stream_ctx = pipe_ctx->stream->dm_stream_context;
3217 config.assr_enabled = (panel_mode == DP_PANEL_MODE_EDP);
3218 config.mst_enabled = (pipe_ctx->stream->signal ==
3219 SIGNAL_TYPE_DISPLAY_PORT_MST);
3220 cp_psp->funcs.update_stream_config(cp_psp->handle, &config);
3221 }
3222}
3223#endif
3224
3225void core_link_enable_stream(
3226 struct dc_state *state,
3227 struct pipe_ctx *pipe_ctx)
3228{
3229 struct dc *dc = pipe_ctx->stream->ctx->dc;
3230 struct dc_stream_state *stream = pipe_ctx->stream;
3231 enum dc_status status;
3232#if defined(CONFIG_DRM_AMD_DC_DCN)
3233 enum otg_out_mux_dest otg_out_dest = OUT_MUX_DIO;
3234#endif
3235 DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger);
3236
3237 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3238 dc_is_virtual_signal(pipe_ctx->stream->signal))
3239 return;
3240
3241 if (!dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3242 stream->link->link_enc->funcs->setup(
3243 stream->link->link_enc,
3244 pipe_ctx->stream->signal);
3245 pipe_ctx->stream_res.stream_enc->funcs->setup_stereo_sync(
3246 pipe_ctx->stream_res.stream_enc,
3247 pipe_ctx->stream_res.tg->inst,
3248 stream->timing.timing_3d_format != TIMING_3D_FORMAT_NONE);
3249 }
3250
3251 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3252 pipe_ctx->stream_res.stream_enc->funcs->dp_set_stream_attribute(
3253 pipe_ctx->stream_res.stream_enc,
3254 &stream->timing,
3255 stream->output_color_space,
3256 stream->use_vsc_sdp_for_colorimetry,
3257 stream->link->dpcd_caps.dprx_feature.bits.SST_SPLIT_SDP_CAP);
3258
3259 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal))
3260 pipe_ctx->stream_res.stream_enc->funcs->hdmi_set_stream_attribute(
3261 pipe_ctx->stream_res.stream_enc,
3262 &stream->timing,
3263 stream->phy_pix_clk,
3264 pipe_ctx->stream_res.audio != NULL);
3265
3266 pipe_ctx->stream->link->link_state_valid = true;
3267
3268#if defined(CONFIG_DRM_AMD_DC_DCN)
3269 if (pipe_ctx->stream_res.tg->funcs->set_out_mux)
3270 pipe_ctx->stream_res.tg->funcs->set_out_mux(pipe_ctx->stream_res.tg, otg_out_dest);
3271#endif
3272
3273 if (dc_is_dvi_signal(pipe_ctx->stream->signal))
3274 pipe_ctx->stream_res.stream_enc->funcs->dvi_set_stream_attribute(
3275 pipe_ctx->stream_res.stream_enc,
3276 &stream->timing,
3277 (pipe_ctx->stream->signal == SIGNAL_TYPE_DVI_DUAL_LINK) ?
3278 true : false);
3279
3280 if (dc_is_lvds_signal(pipe_ctx->stream->signal))
3281 pipe_ctx->stream_res.stream_enc->funcs->lvds_set_stream_attribute(
3282 pipe_ctx->stream_res.stream_enc,
3283 &stream->timing);
3284
3285 if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {
3286 bool apply_edp_fast_boot_optimization =
3287 pipe_ctx->stream->apply_edp_fast_boot_optimization;
3288
3289 pipe_ctx->stream->apply_edp_fast_boot_optimization = false;
3290
3291 resource_build_info_frame(pipe_ctx);
3292 dc->hwss.update_info_frame(pipe_ctx);
3293
3294
3295 if (pipe_ctx->stream->apply_seamless_boot_optimization) {
3296 pipe_ctx->stream->dpms_off = false;
3297
3298
3299 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT) {
3300 enable_stream_features(pipe_ctx);
3301 if (pipe_ctx->stream_res.audio != NULL) {
3302 pipe_ctx->stream_res.stream_enc->funcs->dp_audio_enable(pipe_ctx->stream_res.stream_enc);
3303 dc->hwss.enable_audio_stream(pipe_ctx);
3304 }
3305 }
3306
3307#if defined(CONFIG_DRM_AMD_DC_HDCP)
3308 update_psp_stream_config(pipe_ctx, false);
3309#endif
3310 return;
3311 }
3312
3313
3314 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP &&
3315 apply_edp_fast_boot_optimization &&
3316 !pipe_ctx->stream->timing.flags.DSC) {
3317 pipe_ctx->stream->dpms_off = false;
3318#if defined(CONFIG_DRM_AMD_DC_HDCP)
3319 update_psp_stream_config(pipe_ctx, false);
3320#endif
3321 return;
3322 }
3323
3324 if (pipe_ctx->stream->dpms_off)
3325 return;
3326
3327
3328
3329
3330
3331
3332
3333 if (pipe_ctx->stream->timing.flags.DSC) {
3334 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3335 dc_is_virtual_signal(pipe_ctx->stream->signal))
3336 dp_set_dsc_enable(pipe_ctx, true);
3337 }
3338
3339 status = enable_link(state, pipe_ctx);
3340
3341 if (status != DC_OK) {
3342 DC_LOG_WARNING("enabling link %u failed: %d\n",
3343 pipe_ctx->stream->link->link_index,
3344 status);
3345
3346
3347
3348
3349
3350
3351 if (status != DC_FAIL_DP_LINK_TRAINING ||
3352 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
3353 BREAK_TO_DEBUGGER();
3354 return;
3355 }
3356 }
3357
3358
3359 if (pipe_ctx->stream_res.tg->funcs->set_test_pattern)
3360 pipe_ctx->stream_res.tg->funcs->set_test_pattern(pipe_ctx->stream_res.tg,
3361 CONTROLLER_DP_TEST_PATTERN_VIDEOMODE,
3362 COLOR_DEPTH_UNDEFINED);
3363
3364
3365
3366
3367
3368 if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
3369 stream->link->link_enc->funcs->setup(
3370 stream->link->link_enc,
3371 pipe_ctx->stream->signal);
3372
3373 dc->hwss.enable_stream(pipe_ctx);
3374
3375
3376 if (pipe_ctx->stream->timing.flags.DSC) {
3377 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3378 dc_is_virtual_signal(pipe_ctx->stream->signal)) {
3379 dp_set_dsc_on_rx(pipe_ctx, true);
3380 dp_set_dsc_pps_sdp(pipe_ctx, true);
3381 }
3382 }
3383
3384 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3385 dc_link_allocate_mst_payload(pipe_ctx);
3386
3387 dc->hwss.unblank_stream(pipe_ctx,
3388 &pipe_ctx->stream->link->cur_link_settings);
3389
3390 if (stream->sink_patches.delay_ignore_msa > 0)
3391 msleep(stream->sink_patches.delay_ignore_msa);
3392
3393 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3394 enable_stream_features(pipe_ctx);
3395#if defined(CONFIG_DRM_AMD_DC_HDCP)
3396 update_psp_stream_config(pipe_ctx, false);
3397#endif
3398
3399 dc->hwss.enable_audio_stream(pipe_ctx);
3400
3401 } else {
3402 if (dc_is_dp_signal(pipe_ctx->stream->signal) ||
3403 dc_is_virtual_signal(pipe_ctx->stream->signal))
3404 dp_set_dsc_enable(pipe_ctx, true);
3405
3406 }
3407
3408 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) {
3409 core_link_set_avmute(pipe_ctx, false);
3410 }
3411}
3412
3413void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
3414{
3415 struct dc *dc = pipe_ctx->stream->ctx->dc;
3416 struct dc_stream_state *stream = pipe_ctx->stream;
3417 struct dc_link *link = stream->sink->link;
3418
3419 if (!IS_DIAG_DC(dc->ctx->dce_environment) &&
3420 dc_is_virtual_signal(pipe_ctx->stream->signal))
3421 return;
3422
3423 if (!pipe_ctx->stream->sink->edid_caps.panel_patch.skip_avmute) {
3424 if (dc_is_hdmi_signal(pipe_ctx->stream->signal))
3425 core_link_set_avmute(pipe_ctx, true);
3426 }
3427
3428 dc->hwss.disable_audio_stream(pipe_ctx);
3429
3430#if defined(CONFIG_DRM_AMD_DC_HDCP)
3431 update_psp_stream_config(pipe_ctx, true);
3432#endif
3433 dc->hwss.blank_stream(pipe_ctx);
3434
3435 if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
3436 deallocate_mst_payload(pipe_ctx);
3437
3438 if (dc_is_hdmi_signal(pipe_ctx->stream->signal)) {
3439 struct ext_hdmi_settings settings = {0};
3440 enum engine_id eng_id = pipe_ctx->stream_res.stream_enc->id;
3441
3442 unsigned short masked_chip_caps = link->chip_caps &
3443 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK;
3444
3445 dal_ddc_service_write_scdc_data(
3446 link->ddc,
3447 165000,
3448 false);
3449 if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_TISN65DP159RSBT) {
3450
3451 if (get_ext_hdmi_settings(pipe_ctx, eng_id, &settings))
3452 write_i2c_retimer_setting(pipe_ctx,
3453 false, false, &settings);
3454 else
3455 write_i2c_default_retimer_setting(pipe_ctx,
3456 false, false);
3457 } else if (masked_chip_caps == EXT_DISPLAY_PATH_CAPS__HDMI20_PI3EQX1204) {
3458
3459 write_i2c_redriver_setting(pipe_ctx, false);
3460 }
3461 }
3462
3463 disable_link(pipe_ctx->stream->link, pipe_ctx->stream->signal);
3464
3465 dc->hwss.disable_stream(pipe_ctx);
3466
3467 if (pipe_ctx->stream->timing.flags.DSC) {
3468 if (dc_is_dp_signal(pipe_ctx->stream->signal))
3469 dp_set_dsc_enable(pipe_ctx, false);
3470 }
3471}
3472
3473void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
3474{
3475 struct dc *dc = pipe_ctx->stream->ctx->dc;
3476
3477 if (!dc_is_hdmi_signal(pipe_ctx->stream->signal))
3478 return;
3479
3480 dc->hwss.set_avmute(pipe_ctx, enable);
3481}
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494
3495void dc_link_enable_hpd_filter(struct dc_link *link, bool enable)
3496{
3497 struct gpio *hpd;
3498
3499 if (enable) {
3500 link->is_hpd_filter_disabled = false;
3501 program_hpd_filter(link);
3502 } else {
3503 link->is_hpd_filter_disabled = true;
3504
3505 hpd = get_hpd_gpio(link->ctx->dc_bios, link->link_id, link->ctx->gpio_service);
3506
3507 if (!hpd)
3508 return;
3509
3510
3511 if (dal_gpio_open(hpd, GPIO_MODE_INTERRUPT) == GPIO_RESULT_OK) {
3512 struct gpio_hpd_config config;
3513
3514 config.delay_on_connect = 0;
3515 config.delay_on_disconnect = 0;
3516
3517 dal_irq_setup_hpd_filter(hpd, &config);
3518
3519 dal_gpio_close(hpd);
3520 } else {
3521 ASSERT_CRITICAL(false);
3522 }
3523
3524 dal_gpio_destroy_irq(&hpd);
3525 }
3526}
3527
3528void dc_link_set_drive_settings(struct dc *dc,
3529 struct link_training_settings *lt_settings,
3530 const struct dc_link *link)
3531{
3532
3533 int i;
3534
3535 for (i = 0; i < dc->link_count; i++) {
3536 if (dc->links[i] == link)
3537 break;
3538 }
3539
3540 if (i >= dc->link_count)
3541 ASSERT_CRITICAL(false);
3542
3543 dc_link_dp_set_drive_settings(dc->links[i], lt_settings);
3544}
3545
3546void dc_link_set_preferred_link_settings(struct dc *dc,
3547 struct dc_link_settings *link_setting,
3548 struct dc_link *link)
3549{
3550 int i;
3551 struct pipe_ctx *pipe;
3552 struct dc_stream_state *link_stream;
3553 struct dc_link_settings store_settings = *link_setting;
3554
3555 link->preferred_link_setting = store_settings;
3556
3557
3558
3559
3560
3561 if (!dc_is_dp_signal(link->connector_signal) ||
3562 link->dongle_max_pix_clk > 0)
3563 return;
3564
3565 for (i = 0; i < MAX_PIPES; i++) {
3566 pipe = &dc->current_state->res_ctx.pipe_ctx[i];
3567 if (pipe->stream && pipe->stream->link) {
3568 if (pipe->stream->link == link) {
3569 link_stream = pipe->stream;
3570 break;
3571 }
3572 }
3573 }
3574
3575
3576 if (i == MAX_PIPES)
3577 return;
3578
3579
3580 if (link_stream->dpms_off)
3581 return;
3582
3583 decide_link_settings(link_stream, &store_settings);
3584
3585 if ((store_settings.lane_count != LANE_COUNT_UNKNOWN) &&
3586 (store_settings.link_rate != LINK_RATE_UNKNOWN))
3587 dp_retrain_link_dp_test(link, &store_settings, false);
3588}
3589
3590void dc_link_set_preferred_training_settings(struct dc *dc,
3591 struct dc_link_settings *link_setting,
3592 struct dc_link_training_overrides *lt_overrides,
3593 struct dc_link *link,
3594 bool skip_immediate_retrain)
3595{
3596 if (lt_overrides != NULL)
3597 link->preferred_training_settings = *lt_overrides;
3598 else
3599 memset(&link->preferred_training_settings, 0, sizeof(link->preferred_training_settings));
3600
3601 if (link_setting != NULL) {
3602 link->preferred_link_setting = *link_setting;
3603 } else {
3604 link->preferred_link_setting.lane_count = LANE_COUNT_UNKNOWN;
3605 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN;
3606 }
3607
3608
3609 if (skip_immediate_retrain == false)
3610 dc_link_set_preferred_link_settings(dc, &link->preferred_link_setting, link);
3611}
3612
3613void dc_link_enable_hpd(const struct dc_link *link)
3614{
3615 dc_link_dp_enable_hpd(link);
3616}
3617
3618void dc_link_disable_hpd(const struct dc_link *link)
3619{
3620 dc_link_dp_disable_hpd(link);
3621}
3622
3623void dc_link_set_test_pattern(struct dc_link *link,
3624 enum dp_test_pattern test_pattern,
3625 enum dp_test_pattern_color_space test_pattern_color_space,
3626 const struct link_training_settings *p_link_settings,
3627 const unsigned char *p_custom_pattern,
3628 unsigned int cust_pattern_size)
3629{
3630 if (link != NULL)
3631 dc_link_dp_set_test_pattern(
3632 link,
3633 test_pattern,
3634 test_pattern_color_space,
3635 p_link_settings,
3636 p_custom_pattern,
3637 cust_pattern_size);
3638}
3639
3640uint32_t dc_link_bandwidth_kbps(
3641 const struct dc_link *link,
3642 const struct dc_link_settings *link_setting)
3643{
3644 uint32_t link_bw_kbps =
3645 link_setting->link_rate * LINK_RATE_REF_FREQ_IN_KHZ;
3646
3647 link_bw_kbps *= 8;
3648 link_bw_kbps *= link_setting->lane_count;
3649
3650 if (dc_link_should_enable_fec(link)) {
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671 long long fec_link_bw_kbps = link_bw_kbps * 970LL;
3672 link_bw_kbps = (uint32_t)(div64_s64(fec_link_bw_kbps, 1000LL));
3673 }
3674
3675 return link_bw_kbps;
3676
3677}
3678
3679const struct dc_link_settings *dc_link_get_link_cap(
3680 const struct dc_link *link)
3681{
3682 if (link->preferred_link_setting.lane_count != LANE_COUNT_UNKNOWN &&
3683 link->preferred_link_setting.link_rate != LINK_RATE_UNKNOWN)
3684 return &link->preferred_link_setting;
3685 return &link->verified_link_cap;
3686}
3687
3688void dc_link_overwrite_extended_receiver_cap(
3689 struct dc_link *link)
3690{
3691 dp_overwrite_extended_receiver_cap(link);
3692}
3693
3694bool dc_link_is_fec_supported(const struct dc_link *link)
3695{
3696 struct link_encoder *link_enc = NULL;
3697
3698
3699
3700
3701 if (link->is_dig_mapping_flexible &&
3702 link->dc->res_pool->funcs->link_encs_assign) {
3703 link_enc = link_enc_cfg_get_link_enc_used_by_link(link->dc->current_state, link);
3704 if (link_enc == NULL)
3705 link_enc = link_enc_cfg_get_next_avail_link_enc(link->dc, link->dc->current_state);
3706 } else
3707 link_enc = link->link_enc;
3708 ASSERT(link_enc);
3709
3710 return (dc_is_dp_signal(link->connector_signal) &&
3711 link_enc->features.fec_supported &&
3712 link->dpcd_caps.fec_cap.bits.FEC_CAPABLE &&
3713 !IS_FPGA_MAXIMUS_DC(link->ctx->dce_environment));
3714}
3715
3716bool dc_link_should_enable_fec(const struct dc_link *link)
3717{
3718 bool is_fec_disable = false;
3719 bool ret = false;
3720
3721 if ((link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT_MST &&
3722 link->local_sink &&
3723 link->local_sink->edid_caps.panel_patch.disable_fec) ||
3724 (link->connector_signal == SIGNAL_TYPE_EDP &&
3725 link->dc->debug.force_enable_edp_fec == false))
3726 is_fec_disable = true;
3727
3728 if (dc_link_is_fec_supported(link) && !link->dc->debug.disable_fec && !is_fec_disable)
3729 ret = true;
3730
3731 return ret;
3732}
3733
3734uint32_t dc_bandwidth_in_kbps_from_timing(
3735 const struct dc_crtc_timing *timing)
3736{
3737 uint32_t bits_per_channel = 0;
3738 uint32_t kbps;
3739
3740#if defined(CONFIG_DRM_AMD_DC_DCN)
3741 if (timing->flags.DSC)
3742 return dc_dsc_stream_bandwidth_in_kbps(timing,
3743 timing->dsc_cfg.bits_per_pixel,
3744 timing->dsc_cfg.num_slices_h,
3745 timing->dsc_cfg.is_dp);
3746#endif
3747
3748 switch (timing->display_color_depth) {
3749 case COLOR_DEPTH_666:
3750 bits_per_channel = 6;
3751 break;
3752 case COLOR_DEPTH_888:
3753 bits_per_channel = 8;
3754 break;
3755 case COLOR_DEPTH_101010:
3756 bits_per_channel = 10;
3757 break;
3758 case COLOR_DEPTH_121212:
3759 bits_per_channel = 12;
3760 break;
3761 case COLOR_DEPTH_141414:
3762 bits_per_channel = 14;
3763 break;
3764 case COLOR_DEPTH_161616:
3765 bits_per_channel = 16;
3766 break;
3767 default:
3768 ASSERT(bits_per_channel != 0);
3769 bits_per_channel = 8;
3770 break;
3771 }
3772
3773 kbps = timing->pix_clk_100hz / 10;
3774 kbps *= bits_per_channel;
3775
3776 if (timing->flags.Y_ONLY != 1) {
3777
3778 kbps *= 3;
3779 if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420)
3780 kbps /= 2;
3781 else if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR422)
3782 kbps = kbps * 2 / 3;
3783 }
3784
3785 return kbps;
3786
3787}
3788