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25#ifndef DC_TYPES_H_
26#define DC_TYPES_H_
27
28
29
30
31
32#include "os_types.h"
33#include "fixed31_32.h"
34#include "irq_types.h"
35#include "dc_dp_types.h"
36#include "dc_hw_types.h"
37#include "dal_types.h"
38#include "grph_object_defs.h"
39
40#ifdef CONFIG_DRM_AMD_DC_HDCP
41#include "dm_cp_psp.h"
42#endif
43
44
45struct dc_plane_state;
46struct dc_stream_state;
47struct dc_link;
48struct dc_sink;
49struct dal;
50struct dc_dmub_srv;
51
52
53
54
55enum dce_environment {
56 DCE_ENV_PRODUCTION_DRV = 0,
57
58
59
60 DCE_ENV_FPGA_MAXIMUS,
61
62
63 DCE_ENV_DIAG,
64
65
66
67
68 DCE_ENV_VIRTUAL_HW
69};
70
71
72#define IS_FPGA_MAXIMUS_DC(dce_environment) \
73 (dce_environment == DCE_ENV_FPGA_MAXIMUS)
74
75#define IS_DIAG_DC(dce_environment) \
76 (IS_FPGA_MAXIMUS_DC(dce_environment) || (dce_environment == DCE_ENV_DIAG))
77
78struct dc_perf_trace {
79 unsigned long read_count;
80 unsigned long write_count;
81 unsigned long last_entry_read;
82 unsigned long last_entry_write;
83};
84
85#define DC_MAX_EDID_BUFFER_SIZE 2048
86#define DC_EDID_BLOCK_SIZE 128
87#define MAX_SURFACE_NUM 4
88#define NUM_PIXEL_FORMATS 10
89#define MAX_REPEATER_CNT 8
90
91#include "dc_ddc_types.h"
92
93enum tiling_mode {
94 TILING_MODE_INVALID,
95 TILING_MODE_LINEAR,
96 TILING_MODE_TILED,
97 TILING_MODE_COUNT
98};
99
100enum view_3d_format {
101 VIEW_3D_FORMAT_NONE = 0,
102 VIEW_3D_FORMAT_FRAME_SEQUENTIAL,
103 VIEW_3D_FORMAT_SIDE_BY_SIDE,
104 VIEW_3D_FORMAT_TOP_AND_BOTTOM,
105 VIEW_3D_FORMAT_COUNT,
106 VIEW_3D_FORMAT_FIRST = VIEW_3D_FORMAT_FRAME_SEQUENTIAL
107};
108
109enum plane_stereo_format {
110 PLANE_STEREO_FORMAT_NONE = 0,
111 PLANE_STEREO_FORMAT_SIDE_BY_SIDE = 1,
112 PLANE_STEREO_FORMAT_TOP_AND_BOTTOM = 2,
113 PLANE_STEREO_FORMAT_FRAME_ALTERNATE = 3,
114 PLANE_STEREO_FORMAT_ROW_INTERLEAVED = 5,
115 PLANE_STEREO_FORMAT_COLUMN_INTERLEAVED = 6,
116 PLANE_STEREO_FORMAT_CHECKER_BOARD = 7
117};
118
119
120
121
122
123
124enum dc_edid_connector_type {
125 DC_EDID_CONNECTOR_UNKNOWN = 0,
126 DC_EDID_CONNECTOR_ANALOG = 1,
127 DC_EDID_CONNECTOR_DIGITAL = 10,
128 DC_EDID_CONNECTOR_DVI = 11,
129 DC_EDID_CONNECTOR_HDMIA = 12,
130 DC_EDID_CONNECTOR_MDDI = 14,
131 DC_EDID_CONNECTOR_DISPLAYPORT = 15
132};
133
134enum dc_edid_status {
135 EDID_OK,
136 EDID_BAD_INPUT,
137 EDID_NO_RESPONSE,
138 EDID_BAD_CHECKSUM,
139 EDID_THE_SAME,
140 EDID_FALL_BACK,
141};
142
143enum act_return_status {
144 ACT_SUCCESS,
145 ACT_LINK_LOST,
146 ACT_FAILED
147};
148
149
150struct dc_cea_audio_mode {
151 uint8_t format_code;
152 uint8_t channel_count;
153 uint8_t sample_rate;
154 union {
155 uint8_t sample_size;
156
157 uint8_t max_bit_rate;
158 uint8_t audio_codec_vendor_specific;
159 };
160};
161
162struct dc_edid {
163 uint32_t length;
164 uint8_t raw_edid[DC_MAX_EDID_BUFFER_SIZE];
165};
166
167
168
169
170#define DEFAULT_SPEAKER_LOCATION 5
171
172#define DC_MAX_AUDIO_DESC_COUNT 16
173
174#define AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS 20
175
176union display_content_support {
177 unsigned int raw;
178 struct {
179 unsigned int valid_content_type :1;
180 unsigned int game_content :1;
181 unsigned int cinema_content :1;
182 unsigned int photo_content :1;
183 unsigned int graphics_content :1;
184 unsigned int reserved :27;
185 } bits;
186};
187
188struct dc_panel_patch {
189 unsigned int dppowerup_delay;
190 unsigned int extra_t12_ms;
191 unsigned int extra_delay_backlight_off;
192 unsigned int extra_t7_ms;
193 unsigned int skip_scdc_overwrite;
194 unsigned int delay_ignore_msa;
195 unsigned int disable_fec;
196 unsigned int extra_t3_ms;
197 unsigned int max_dsc_target_bpp_limit;
198 unsigned int skip_avmute;
199};
200
201struct dc_edid_caps {
202
203 uint16_t manufacturer_id;
204 uint16_t product_id;
205 uint32_t serial_number;
206 uint8_t manufacture_week;
207 uint8_t manufacture_year;
208 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
209
210
211 uint8_t speaker_flags;
212 uint32_t audio_mode_count;
213 struct dc_cea_audio_mode audio_modes[DC_MAX_AUDIO_DESC_COUNT];
214 uint32_t audio_latency;
215 uint32_t video_latency;
216
217 union display_content_support content_support;
218
219 uint8_t qs_bit;
220 uint8_t qy_bit;
221
222 uint32_t max_tmds_clk_mhz;
223
224
225 bool lte_340mcsc_scramble;
226
227 bool edid_hdmi;
228 bool hdr_supported;
229
230 struct dc_panel_patch panel_patch;
231};
232
233struct dc_mode_flags {
234
235 uint32_t INTERLACE :1;
236
237 uint32_t NATIVE :1;
238
239 uint32_t PREFERRED :1;
240
241
242 uint32_t REDUCED_BLANKING :1;
243
244 uint32_t VIDEO_OPTIMIZED_RATE :1;
245
246 uint32_t PACKED_PIXEL_FORMAT :1;
247
248 uint32_t PREFERRED_VIEW :1;
249
250 uint32_t TILED_MODE :1;
251 uint32_t DSE_MODE :1;
252
253
254
255
256 uint32_t MIRACAST_REFRESH_DIVIDER;
257};
258
259
260enum dc_timing_source {
261 TIMING_SOURCE_UNDEFINED,
262
263
264 TIMING_SOURCE_USER_FORCED,
265 TIMING_SOURCE_USER_OVERRIDE,
266 TIMING_SOURCE_CUSTOM,
267 TIMING_SOURCE_EXPLICIT,
268
269
270 TIMING_SOURCE_EDID_CEA_SVD_3D,
271 TIMING_SOURCE_EDID_CEA_SVD_PREFERRED,
272 TIMING_SOURCE_EDID_CEA_SVD_420,
273 TIMING_SOURCE_EDID_DETAILED,
274 TIMING_SOURCE_EDID_ESTABLISHED,
275 TIMING_SOURCE_EDID_STANDARD,
276 TIMING_SOURCE_EDID_CEA_SVD,
277 TIMING_SOURCE_EDID_CVT_3BYTE,
278 TIMING_SOURCE_EDID_4BYTE,
279 TIMING_SOURCE_VBIOS,
280 TIMING_SOURCE_CV,
281 TIMING_SOURCE_TV,
282 TIMING_SOURCE_HDMI_VIC,
283
284
285 TIMING_SOURCE_DEFAULT,
286
287
288 TIMING_SOURCE_CUSTOM_BASE,
289
290
291 TIMING_SOURCE_RANGELIMIT,
292 TIMING_SOURCE_OS_FORCED,
293 TIMING_SOURCE_IMPLICIT,
294
295
296 TIMING_SOURCE_BASICMODE,
297
298 TIMING_SOURCE_COUNT
299};
300
301
302struct stereo_3d_features {
303 bool supported ;
304 bool allTimings ;
305 bool cloneMode ;
306 bool scaling ;
307 bool singleFrameSWPacked;
308};
309
310enum dc_timing_support_method {
311 TIMING_SUPPORT_METHOD_UNDEFINED,
312 TIMING_SUPPORT_METHOD_EXPLICIT,
313 TIMING_SUPPORT_METHOD_IMPLICIT,
314 TIMING_SUPPORT_METHOD_NATIVE
315};
316
317struct dc_mode_info {
318 uint32_t pixel_width;
319 uint32_t pixel_height;
320 uint32_t field_rate;
321
322
323
324 enum dc_timing_standard timing_standard;
325 enum dc_timing_source timing_source;
326 struct dc_mode_flags flags;
327};
328
329enum dc_power_state {
330 DC_POWER_STATE_ON = 1,
331 DC_POWER_STATE_STANDBY,
332 DC_POWER_STATE_SUSPEND,
333 DC_POWER_STATE_OFF
334};
335
336
337enum dc_video_power_state {
338 DC_VIDEO_POWER_UNSPECIFIED = 0,
339 DC_VIDEO_POWER_ON = 1,
340 DC_VIDEO_POWER_STANDBY,
341 DC_VIDEO_POWER_SUSPEND,
342 DC_VIDEO_POWER_OFF,
343 DC_VIDEO_POWER_HIBERNATE,
344 DC_VIDEO_POWER_SHUTDOWN,
345 DC_VIDEO_POWER_ULPS,
346 DC_VIDEO_POWER_AFTER_RESET,
347 DC_VIDEO_POWER_MAXIMUM
348};
349
350enum dc_acpi_cm_power_state {
351 DC_ACPI_CM_POWER_STATE_D0 = 1,
352 DC_ACPI_CM_POWER_STATE_D1 = 2,
353 DC_ACPI_CM_POWER_STATE_D2 = 4,
354 DC_ACPI_CM_POWER_STATE_D3 = 8
355};
356
357enum dc_connection_type {
358 dc_connection_none,
359 dc_connection_single,
360 dc_connection_mst_branch,
361 dc_connection_sst_branch
362};
363
364struct dc_csc_adjustments {
365 struct fixed31_32 contrast;
366 struct fixed31_32 saturation;
367 struct fixed31_32 brightness;
368 struct fixed31_32 hue;
369};
370
371enum dpcd_downstream_port_max_bpc {
372 DOWN_STREAM_MAX_8BPC = 0,
373 DOWN_STREAM_MAX_10BPC,
374 DOWN_STREAM_MAX_12BPC,
375 DOWN_STREAM_MAX_16BPC
376};
377
378
379enum link_training_offset {
380 DPRX = 0,
381 LTTPR_PHY_REPEATER1 = 1,
382 LTTPR_PHY_REPEATER2 = 2,
383 LTTPR_PHY_REPEATER3 = 3,
384 LTTPR_PHY_REPEATER4 = 4,
385 LTTPR_PHY_REPEATER5 = 5,
386 LTTPR_PHY_REPEATER6 = 6,
387 LTTPR_PHY_REPEATER7 = 7,
388 LTTPR_PHY_REPEATER8 = 8
389};
390
391struct dc_lttpr_caps {
392 union dpcd_rev revision;
393 uint8_t mode;
394 uint8_t max_lane_count;
395 uint8_t max_link_rate;
396 uint8_t phy_repeater_cnt;
397 uint8_t max_ext_timeout;
398 uint8_t aux_rd_interval[MAX_REPEATER_CNT - 1];
399};
400
401struct dc_dongle_caps {
402
403 enum display_dongle_type dongle_type;
404 bool extendedCapValid;
405
406
407 bool is_dp_hdmi_s3d_converter;
408 bool is_dp_hdmi_ycbcr422_pass_through;
409 bool is_dp_hdmi_ycbcr420_pass_through;
410 bool is_dp_hdmi_ycbcr422_converter;
411 bool is_dp_hdmi_ycbcr420_converter;
412 uint32_t dp_hdmi_max_bpc;
413 uint32_t dp_hdmi_max_pixel_clk_in_khz;
414};
415
416enum scaling_transformation {
417 SCALING_TRANSFORMATION_UNINITIALIZED,
418 SCALING_TRANSFORMATION_IDENTITY = 0x0001,
419 SCALING_TRANSFORMATION_CENTER_TIMING = 0x0002,
420 SCALING_TRANSFORMATION_FULL_SCREEN_SCALE = 0x0004,
421 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE = 0x0008,
422 SCALING_TRANSFORMATION_DAL_DECIDE = 0x0010,
423 SCALING_TRANSFORMATION_INVALID = 0x80000000,
424
425
426 SCALING_TRANSFORMATION_BEGING = SCALING_TRANSFORMATION_IDENTITY,
427 SCALING_TRANSFORMATION_END =
428 SCALING_TRANSFORMATION_PRESERVE_ASPECT_RATIO_SCALE
429};
430
431enum display_content_type {
432 DISPLAY_CONTENT_TYPE_NO_DATA = 0,
433 DISPLAY_CONTENT_TYPE_GRAPHICS = 1,
434 DISPLAY_CONTENT_TYPE_PHOTO = 2,
435 DISPLAY_CONTENT_TYPE_CINEMA = 4,
436 DISPLAY_CONTENT_TYPE_GAME = 8
437};
438
439enum cm_gamut_adjust_type {
440 CM_GAMUT_ADJUST_TYPE_BYPASS = 0,
441 CM_GAMUT_ADJUST_TYPE_HW,
442 CM_GAMUT_ADJUST_TYPE_SW
443};
444
445struct cm_grph_csc_adjustment {
446 struct fixed31_32 temperature_matrix[12];
447 enum cm_gamut_adjust_type gamut_adjust_type;
448 enum cm_gamut_coef_format gamut_coef_format;
449};
450
451
452struct dwb_stereo_params {
453 bool stereo_enabled;
454 enum dwb_stereo_type stereo_type;
455 bool stereo_polarity;
456 enum dwb_stereo_eye_select stereo_eye_select;
457};
458
459struct dc_dwb_cnv_params {
460 unsigned int src_width;
461 unsigned int src_height;
462 unsigned int crop_width;
463 bool crop_en;
464 unsigned int crop_height;
465 unsigned int crop_x;
466 unsigned int crop_y;
467 enum dwb_cnv_out_bpc cnv_out_bpc;
468 enum dwb_out_format fc_out_format;
469 enum dwb_out_denorm out_denorm_mode;
470 unsigned int out_max_pix_val;
471 unsigned int out_min_pix_val;
472};
473
474struct dc_dwb_params {
475 unsigned int dwbscl_black_color;
476 unsigned int hdr_mult;
477 struct cm_grph_csc_adjustment csc_params;
478 struct dwb_stereo_params stereo_params;
479 struct dc_dwb_cnv_params cnv_params;
480 unsigned int dest_width;
481 unsigned int dest_height;
482 enum dwb_scaler_mode out_format;
483 enum dwb_output_depth output_depth;
484 enum dwb_capture_rate capture_rate;
485 struct scaling_taps scaler_taps;
486 enum dwb_subsample_position subsample_position;
487 struct dc_transfer_func *out_transfer_func;
488};
489
490
491
492union audio_sample_rates {
493 struct sample_rates {
494 uint8_t RATE_32:1;
495 uint8_t RATE_44_1:1;
496 uint8_t RATE_48:1;
497 uint8_t RATE_88_2:1;
498 uint8_t RATE_96:1;
499 uint8_t RATE_176_4:1;
500 uint8_t RATE_192:1;
501 } rate;
502
503 uint8_t all;
504};
505
506struct audio_speaker_flags {
507 uint32_t FL_FR:1;
508 uint32_t LFE:1;
509 uint32_t FC:1;
510 uint32_t RL_RR:1;
511 uint32_t RC:1;
512 uint32_t FLC_FRC:1;
513 uint32_t RLC_RRC:1;
514 uint32_t SUPPORT_AI:1;
515};
516
517struct audio_speaker_info {
518 uint32_t ALLSPEAKERS:7;
519 uint32_t SUPPORT_AI:1;
520};
521
522
523struct audio_info_flags {
524
525 union {
526
527 struct audio_speaker_flags speaker_flags;
528 struct audio_speaker_info info;
529
530 uint8_t all;
531 };
532};
533
534enum audio_format_code {
535 AUDIO_FORMAT_CODE_FIRST = 1,
536 AUDIO_FORMAT_CODE_LINEARPCM = AUDIO_FORMAT_CODE_FIRST,
537
538 AUDIO_FORMAT_CODE_AC3,
539
540 AUDIO_FORMAT_CODE_MPEG1,
541
542 AUDIO_FORMAT_CODE_MP3,
543
544 AUDIO_FORMAT_CODE_MPEG2,
545 AUDIO_FORMAT_CODE_AAC,
546 AUDIO_FORMAT_CODE_DTS,
547 AUDIO_FORMAT_CODE_ATRAC,
548 AUDIO_FORMAT_CODE_1BITAUDIO,
549 AUDIO_FORMAT_CODE_DOLBYDIGITALPLUS,
550 AUDIO_FORMAT_CODE_DTS_HD,
551 AUDIO_FORMAT_CODE_MAT_MLP,
552 AUDIO_FORMAT_CODE_DST,
553 AUDIO_FORMAT_CODE_WMAPRO,
554 AUDIO_FORMAT_CODE_LAST,
555 AUDIO_FORMAT_CODE_COUNT =
556 AUDIO_FORMAT_CODE_LAST - AUDIO_FORMAT_CODE_FIRST
557};
558
559struct audio_mode {
560
561 enum audio_format_code format_code;
562
563 uint8_t channel_count;
564
565 union audio_sample_rates sample_rates;
566 union {
567
568 uint8_t sample_size;
569
570 uint8_t max_bit_rate;
571
572 uint8_t vendor_specific;
573 };
574};
575
576struct audio_info {
577 struct audio_info_flags flags;
578 uint32_t video_latency;
579 uint32_t audio_latency;
580 uint32_t display_index;
581 uint8_t display_name[AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS];
582 uint32_t manufacture_id;
583 uint32_t product_id;
584
585 uint32_t port_id[2];
586 uint32_t mode_count;
587
588 struct audio_mode modes[DC_MAX_AUDIO_DESC_COUNT];
589};
590struct audio_check {
591 unsigned int audio_packet_type;
592 unsigned int max_audiosample_rate;
593 unsigned int acat;
594};
595enum dc_infoframe_type {
596 DC_HDMI_INFOFRAME_TYPE_VENDOR = 0x81,
597 DC_HDMI_INFOFRAME_TYPE_AVI = 0x82,
598 DC_HDMI_INFOFRAME_TYPE_SPD = 0x83,
599 DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84,
600 DC_DP_INFOFRAME_TYPE_PPS = 0x10,
601};
602
603struct dc_info_packet {
604 bool valid;
605 uint8_t hb0;
606 uint8_t hb1;
607 uint8_t hb2;
608 uint8_t hb3;
609 uint8_t sb[32];
610};
611
612struct dc_info_packet_128 {
613 bool valid;
614 uint8_t hb0;
615 uint8_t hb1;
616 uint8_t hb2;
617 uint8_t hb3;
618 uint8_t sb[128];
619};
620
621#define DC_PLANE_UPDATE_TIMES_MAX 10
622
623struct dc_plane_flip_time {
624 unsigned int time_elapsed_in_us[DC_PLANE_UPDATE_TIMES_MAX];
625 unsigned int index;
626 unsigned int prev_update_time_in_us;
627};
628
629enum dc_psr_state {
630 PSR_STATE0 = 0x0,
631 PSR_STATE1,
632 PSR_STATE1a,
633 PSR_STATE2,
634 PSR_STATE2a,
635 PSR_STATE3,
636 PSR_STATE3Init,
637 PSR_STATE4,
638 PSR_STATE4a,
639 PSR_STATE4b,
640 PSR_STATE4c,
641 PSR_STATE4d,
642 PSR_STATE5,
643 PSR_STATE5a,
644 PSR_STATE5b,
645 PSR_STATE5c,
646 PSR_STATE_INVALID = 0xFF
647};
648
649struct psr_config {
650 unsigned char psr_version;
651 unsigned int psr_rfb_setup_time;
652 bool psr_exit_link_training_required;
653 bool psr_frame_capture_indication_req;
654 unsigned int psr_sdp_transmit_line_num_deadline;
655 bool allow_smu_optimizations;
656 bool allow_multi_disp_optimizations;
657};
658
659union dmcu_psr_level {
660 struct {
661 unsigned int SKIP_CRC:1;
662 unsigned int SKIP_DP_VID_STREAM_DISABLE:1;
663 unsigned int SKIP_PHY_POWER_DOWN:1;
664 unsigned int SKIP_AUX_ACK_CHECK:1;
665 unsigned int SKIP_CRTC_DISABLE:1;
666 unsigned int SKIP_AUX_RFB_CAPTURE_CHECK:1;
667 unsigned int SKIP_SMU_NOTIFICATION:1;
668 unsigned int SKIP_AUTO_STATE_ADVANCE:1;
669 unsigned int DISABLE_PSR_ENTRY_ABORT:1;
670 unsigned int SKIP_SINGLE_OTG_DISABLE:1;
671 unsigned int RESERVED:22;
672 } bits;
673 unsigned int u32all;
674};
675
676enum physical_phy_id {
677 PHYLD_0,
678 PHYLD_1,
679 PHYLD_2,
680 PHYLD_3,
681 PHYLD_4,
682 PHYLD_5,
683 PHYLD_6,
684 PHYLD_7,
685 PHYLD_8,
686 PHYLD_9,
687 PHYLD_COUNT,
688 PHYLD_UNKNOWN = (-1L)
689};
690
691enum phy_type {
692 PHY_TYPE_UNKNOWN = 1,
693 PHY_TYPE_PCIE_PHY = 2,
694 PHY_TYPE_UNIPHY = 3,
695};
696
697struct psr_context {
698
699 enum channel_id channel;
700
701 enum transmitter transmitterId;
702
703 enum engine_id engineId;
704
705 enum controller_id controllerId;
706
707 enum phy_type phyType;
708
709 enum physical_phy_id smuPhyId;
710
711
712
713
714
715 unsigned int crtcTimingVerticalTotal;
716
717
718
719 bool psrSupportedDisplayConfig;
720
721 bool psrExitLinkTrainingRequired;
722
723
724
725
726
727
728 bool psrFrameCaptureIndicationReq;
729
730
731
732 unsigned int sdpTransmitLineNumDeadline;
733
734
735
736 unsigned int vsync_rate_hz;
737 unsigned int skipPsrWaitForPllLock;
738 unsigned int numberOfControllers;
739
740
741
742
743 bool rfb_update_auto_en;
744
745 unsigned int timehyst_frames;
746
747 unsigned int hyst_lines;
748
749
750
751 unsigned int aux_repeats;
752
753 union dmcu_psr_level psr_level;
754
755
756
757 unsigned int frame_delay;
758 bool allow_smu_optimizations;
759 bool allow_multi_disp_optimizations;
760};
761
762struct colorspace_transform {
763 struct fixed31_32 matrix[12];
764 bool enable_remap;
765};
766
767enum i2c_mot_mode {
768 I2C_MOT_UNDEF,
769 I2C_MOT_TRUE,
770 I2C_MOT_FALSE
771};
772
773struct AsicStateEx {
774 unsigned int memoryClock;
775 unsigned int displayClock;
776 unsigned int engineClock;
777 unsigned int maxSupportedDppClock;
778 unsigned int dppClock;
779 unsigned int socClock;
780 unsigned int dcfClockDeepSleep;
781 unsigned int fClock;
782 unsigned int phyClock;
783};
784
785
786enum dc_clock_type {
787 DC_CLOCK_TYPE_DISPCLK = 0,
788 DC_CLOCK_TYPE_DPPCLK = 1,
789};
790
791struct dc_clock_config {
792 uint32_t max_clock_khz;
793 uint32_t min_clock_khz;
794 uint32_t bw_requirequired_clock_khz;
795 uint32_t current_clock_khz;
796};
797
798struct hw_asic_id {
799 uint32_t chip_id;
800 uint32_t chip_family;
801 uint32_t pci_revision_id;
802 uint32_t hw_internal_rev;
803 uint32_t vram_type;
804 uint32_t vram_width;
805 uint32_t feature_flags;
806 uint32_t fake_paths_num;
807 void *atombios_base_address;
808};
809
810struct dc_context {
811 struct dc *dc;
812
813 void *driver_context;
814 struct dc_perf_trace *perf_trace;
815 void *cgs_device;
816
817 enum dce_environment dce_environment;
818 struct hw_asic_id asic_id;
819
820
821
822
823 enum dce_version dce_version;
824 struct dc_bios *dc_bios;
825 bool created_bios;
826 struct gpio_service *gpio_service;
827 uint32_t dc_sink_id_count;
828 uint32_t dc_stream_id_count;
829 uint32_t dc_edp_id_count;
830 uint64_t fbc_gpu_addr;
831 struct dc_dmub_srv *dmub_srv;
832#ifdef CONFIG_DRM_AMD_DC_HDCP
833 struct cp_psp cp_psp;
834#endif
835
836};
837
838
839union dsc_slice_caps1 {
840 struct {
841 uint8_t NUM_SLICES_1 : 1;
842 uint8_t NUM_SLICES_2 : 1;
843 uint8_t RESERVED : 1;
844 uint8_t NUM_SLICES_4 : 1;
845 uint8_t NUM_SLICES_6 : 1;
846 uint8_t NUM_SLICES_8 : 1;
847 uint8_t NUM_SLICES_10 : 1;
848 uint8_t NUM_SLICES_12 : 1;
849 } bits;
850 uint8_t raw;
851};
852
853union dsc_slice_caps2 {
854 struct {
855 uint8_t NUM_SLICES_16 : 1;
856 uint8_t NUM_SLICES_20 : 1;
857 uint8_t NUM_SLICES_24 : 1;
858 uint8_t RESERVED : 5;
859 } bits;
860 uint8_t raw;
861};
862
863union dsc_color_formats {
864 struct {
865 uint8_t RGB : 1;
866 uint8_t YCBCR_444 : 1;
867 uint8_t YCBCR_SIMPLE_422 : 1;
868 uint8_t YCBCR_NATIVE_422 : 1;
869 uint8_t YCBCR_NATIVE_420 : 1;
870 uint8_t RESERVED : 3;
871 } bits;
872 uint8_t raw;
873};
874
875union dsc_color_depth {
876 struct {
877 uint8_t RESERVED1 : 1;
878 uint8_t COLOR_DEPTH_8_BPC : 1;
879 uint8_t COLOR_DEPTH_10_BPC : 1;
880 uint8_t COLOR_DEPTH_12_BPC : 1;
881 uint8_t RESERVED2 : 3;
882 } bits;
883 uint8_t raw;
884};
885
886struct dsc_dec_dpcd_caps {
887 bool is_dsc_supported;
888 uint8_t dsc_version;
889 int32_t rc_buffer_size;
890 union dsc_slice_caps1 slice_caps1;
891 union dsc_slice_caps2 slice_caps2;
892 int32_t lb_bit_depth;
893 bool is_block_pred_supported;
894 int32_t edp_max_bits_per_pixel;
895 union dsc_color_formats color_formats;
896 union dsc_color_depth color_depth;
897 int32_t throughput_mode_0_mps;
898 int32_t throughput_mode_1_mps;
899 int32_t max_slice_width;
900 uint32_t bpp_increment_div;
901
902
903 uint32_t branch_overall_throughput_0_mps;
904 uint32_t branch_overall_throughput_1_mps;
905 uint32_t branch_max_line_width;
906 bool is_dp;
907};
908
909struct dc_golden_table {
910 uint16_t dc_golden_table_ver;
911 uint32_t aux_dphy_rx_control0_val;
912 uint32_t aux_dphy_tx_control_val;
913 uint32_t aux_dphy_rx_control1_val;
914 uint32_t dc_gpio_aux_ctrl_0_val;
915 uint32_t dc_gpio_aux_ctrl_1_val;
916 uint32_t dc_gpio_aux_ctrl_2_val;
917 uint32_t dc_gpio_aux_ctrl_3_val;
918 uint32_t dc_gpio_aux_ctrl_4_val;
919 uint32_t dc_gpio_aux_ctrl_5_val;
920};
921
922enum dc_gpu_mem_alloc_type {
923 DC_MEM_ALLOC_TYPE_GART,
924 DC_MEM_ALLOC_TYPE_FRAME_BUFFER,
925 DC_MEM_ALLOC_TYPE_INVISIBLE_FRAME_BUFFER,
926 DC_MEM_ALLOC_TYPE_AGP
927};
928
929enum dc_psr_version {
930 DC_PSR_VERSION_1 = 0,
931 DC_PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
932};
933
934
935enum display_endpoint_type {
936 DISPLAY_ENDPOINT_PHY = 0,
937 DISPLAY_ENDPOINT_UNKNOWN = -1
938};
939
940
941
942
943
944struct display_endpoint_id {
945 struct graphics_object_id link_id;
946 enum display_endpoint_type ep_type;
947};
948
949#endif
950