LXR linux/drivers/gpu/drm/amd/display/dc/dce/dce

   1/*
   2 * Copyright 2012-16 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26
  27#ifndef _DCE_ABM_H_
  28#define _DCE_ABM_H_
  29
  30#include "abm.h"
  31
  32#define ABM_COMMON_REG_LIST_DCE_BASE() \
  33        SR(MASTER_COMM_CNTL_REG), \
  34        SR(MASTER_COMM_CMD_REG), \
  35        SR(MASTER_COMM_DATA_REG1)
  36
  37#define ABM_DCE110_COMMON_REG_LIST() \
  38        ABM_COMMON_REG_LIST_DCE_BASE(), \
  39        SR(DC_ABM1_HG_SAMPLE_RATE), \
  40        SR(DC_ABM1_LS_SAMPLE_RATE), \
  41        SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
  42        SR(DC_ABM1_HG_MISC_CTRL), \
  43        SR(DC_ABM1_IPCSC_COEFF_SEL), \
  44        SR(BL1_PWM_CURRENT_ABM_LEVEL), \
  45        SR(BL1_PWM_TARGET_ABM_LEVEL), \
  46        SR(BL1_PWM_USER_LEVEL), \
  47        SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
  48        SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
  49        SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
  50        SR(DC_ABM1_ACE_THRES_12), \
  51        SR(BIOS_SCRATCH_2)
  52
  53#define ABM_DCN10_REG_LIST(id)\
  54        ABM_COMMON_REG_LIST_DCE_BASE(), \
  55        SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
  56        SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
  57        SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
  58        SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
  59        SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
  60        SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
  61        SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
  62        SRI(BL1_PWM_USER_LEVEL, ABM, id), \
  63        SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
  64        SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
  65        SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
  66        SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
  67        NBIO_SR(BIOS_SCRATCH_2)
  68
  69#define ABM_DCN20_REG_LIST() \
  70        ABM_COMMON_REG_LIST_DCE_BASE(), \
  71        SR(DC_ABM1_HG_SAMPLE_RATE), \
  72        SR(DC_ABM1_LS_SAMPLE_RATE), \
  73        SR(BL1_PWM_BL_UPDATE_SAMPLE_RATE), \
  74        SR(DC_ABM1_HG_MISC_CTRL), \
  75        SR(DC_ABM1_IPCSC_COEFF_SEL), \
  76        SR(BL1_PWM_CURRENT_ABM_LEVEL), \
  77        SR(BL1_PWM_TARGET_ABM_LEVEL), \
  78        SR(BL1_PWM_USER_LEVEL), \
  79        SR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES), \
  80        SR(DC_ABM1_HGLS_REG_READ_PROGRESS), \
  81        SR(DC_ABM1_ACE_OFFSET_SLOPE_0), \
  82        SR(DC_ABM1_ACE_THRES_12), \
  83        NBIO_SR(BIOS_SCRATCH_2)
  84
  85#define ABM_DCN301_REG_LIST(id)\
  86        ABM_COMMON_REG_LIST_DCE_BASE(), \
  87        SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
  88        SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
  89        SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
  90        SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
  91        SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
  92        SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
  93        SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
  94        SRI(BL1_PWM_USER_LEVEL, ABM, id), \
  95        SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
  96        SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
  97        NBIO_SR(BIOS_SCRATCH_2)
  98
  99#define ABM_DCN30_REG_LIST(id)\
 100        ABM_COMMON_REG_LIST_DCE_BASE(), \
 101        SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
 102        SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
 103        SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
 104        SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
 105        SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
 106        SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
 107        SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
 108        SRI(BL1_PWM_USER_LEVEL, ABM, id), \
 109        SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
 110        SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
 111        SRI(DC_ABM1_ACE_OFFSET_SLOPE_0, ABM, id), \
 112        SRI(DC_ABM1_ACE_THRES_12, ABM, id), \
 113        NBIO_SR(BIOS_SCRATCH_2)
 114
 115#define ABM_SF(reg_name, field_name, post_fix)\
 116        .field_name = reg_name ## __ ## field_name ## post_fix
 117
 118#define ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
 119        ABM_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
 120        ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
 121        ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
 122        ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
 123
 124#define ABM_MASK_SH_LIST_DCE110(mask_sh) \
 125        ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 126        ABM_SF(DC_ABM1_HG_MISC_CTRL, \
 127                        ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
 128        ABM_SF(DC_ABM1_HG_MISC_CTRL, \
 129                        ABM1_HG_VMAX_SEL, mask_sh), \
 130        ABM_SF(DC_ABM1_HG_MISC_CTRL, \
 131                        ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
 132        ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
 133                        ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
 134        ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
 135                        ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
 136        ABM_SF(DC_ABM1_IPCSC_COEFF_SEL, \
 137                        ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
 138        ABM_SF(BL1_PWM_CURRENT_ABM_LEVEL, \
 139                        BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
 140        ABM_SF(BL1_PWM_TARGET_ABM_LEVEL, \
 141                        BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
 142        ABM_SF(BL1_PWM_USER_LEVEL, \
 143                        BL1_PWM_USER_LEVEL, mask_sh), \
 144        ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 145                        ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
 146        ABM_SF(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 147                        ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
 148        ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 149                        ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 150        ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 151                        ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 152        ABM_SF(DC_ABM1_HGLS_REG_READ_PROGRESS, \
 153                        ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 154
 155#define ABM_MASK_SH_LIST_DCN10(mask_sh) \
 156        ABM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
 157        ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 158                        ABM1_HG_NUM_OF_BINS_SEL, mask_sh), \
 159        ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 160                        ABM1_HG_VMAX_SEL, mask_sh), \
 161        ABM_SF(ABM0_DC_ABM1_HG_MISC_CTRL, \
 162                        ABM1_HG_BIN_BITWIDTH_SIZE_SEL, mask_sh), \
 163        ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
 164                        ABM1_IPCSC_COEFF_SEL_R, mask_sh), \
 165        ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
 166                        ABM1_IPCSC_COEFF_SEL_G, mask_sh), \
 167        ABM_SF(ABM0_DC_ABM1_IPCSC_COEFF_SEL, \
 168                        ABM1_IPCSC_COEFF_SEL_B, mask_sh), \
 169        ABM_SF(ABM0_BL1_PWM_CURRENT_ABM_LEVEL, \
 170                        BL1_PWM_CURRENT_ABM_LEVEL, mask_sh), \
 171        ABM_SF(ABM0_BL1_PWM_TARGET_ABM_LEVEL, \
 172                        BL1_PWM_TARGET_ABM_LEVEL, mask_sh), \
 173        ABM_SF(ABM0_BL1_PWM_USER_LEVEL, \
 174                        BL1_PWM_USER_LEVEL, mask_sh), \
 175        ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 176                        ABM1_LS_MIN_PIXEL_VALUE_THRES, mask_sh), \
 177        ABM_SF(ABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, \
 178                        ABM1_LS_MAX_PIXEL_VALUE_THRES, mask_sh), \
 179        ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 180                        ABM1_HG_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 181        ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 182                        ABM1_LS_REG_READ_MISSED_FRAME_CLEAR, mask_sh), \
 183        ABM_SF(ABM0_DC_ABM1_HGLS_REG_READ_PROGRESS, \
 184                        ABM1_BL_REG_READ_MISSED_FRAME_CLEAR, mask_sh)
 185
 186#define ABM_MASK_SH_LIST_DCN20(mask_sh) ABM_MASK_SH_LIST_DCE110(mask_sh)
 187
 188#define ABM_MASK_SH_LIST_DCN30(mask_sh) ABM_MASK_SH_LIST_DCN10(mask_sh)
 189
 190#define ABM_REG_FIELD_LIST(type) \
 191        type ABM1_HG_NUM_OF_BINS_SEL; \
 192        type ABM1_HG_VMAX_SEL; \
 193        type ABM1_HG_BIN_BITWIDTH_SIZE_SEL; \
 194        type ABM1_IPCSC_COEFF_SEL_R; \
 195        type ABM1_IPCSC_COEFF_SEL_G; \
 196        type ABM1_IPCSC_COEFF_SEL_B; \
 197        type BL1_PWM_CURRENT_ABM_LEVEL; \
 198        type BL1_PWM_TARGET_ABM_LEVEL; \
 199        type BL1_PWM_USER_LEVEL; \
 200        type ABM1_LS_MIN_PIXEL_VALUE_THRES; \
 201        type ABM1_LS_MAX_PIXEL_VALUE_THRES; \
 202        type ABM1_HG_REG_READ_MISSED_FRAME_CLEAR; \
 203        type ABM1_LS_REG_READ_MISSED_FRAME_CLEAR; \
 204        type ABM1_BL_REG_READ_MISSED_FRAME_CLEAR; \
 205        type MASTER_COMM_INTERRUPT; \
 206        type MASTER_COMM_CMD_REG_BYTE0; \
 207        type MASTER_COMM_CMD_REG_BYTE1; \
 208        type MASTER_COMM_CMD_REG_BYTE2
 209
 210struct dce_abm_shift {
 211        ABM_REG_FIELD_LIST(uint8_t);
 212};
 213
 214struct dce_abm_mask {
 215        ABM_REG_FIELD_LIST(uint32_t);
 216};
 217
 218struct dce_abm_registers {
 219        uint32_t DC_ABM1_HG_SAMPLE_RATE;
 220        uint32_t DC_ABM1_LS_SAMPLE_RATE;
 221        uint32_t BL1_PWM_BL_UPDATE_SAMPLE_RATE;
 222        uint32_t DC_ABM1_HG_MISC_CTRL;
 223        uint32_t DC_ABM1_IPCSC_COEFF_SEL;
 224        uint32_t BL1_PWM_CURRENT_ABM_LEVEL;
 225        uint32_t BL1_PWM_TARGET_ABM_LEVEL;
 226        uint32_t BL1_PWM_USER_LEVEL;
 227        uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
 228        uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
 229        uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
 230        uint32_t DC_ABM1_ACE_THRES_12;
 231        uint32_t MASTER_COMM_CNTL_REG;
 232        uint32_t MASTER_COMM_CMD_REG;
 233        uint32_t MASTER_COMM_DATA_REG1;
 234        uint32_t BIOS_SCRATCH_2;
 235};
 236
 237struct dce_abm {
 238        struct abm base;
 239        const struct dce_abm_registers *regs;
 240        const struct dce_abm_shift *abm_shift;
 241        const struct dce_abm_mask *abm_mask;
 242};
 243
 244struct abm *dce_abm_create(
 245        struct dc_context *ctx,
 246        const struct dce_abm_registers *regs,
 247        const struct dce_abm_shift *abm_shift,
 248        const struct dce_abm_mask *abm_mask);
 249
 250void dce_abm_destroy(struct abm **abm);
 251
 252#endif /* _DCE_ABM_H_ */
 253