LXR linux/drivers/gpu/drm/amd/display/dc/dce/dce

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25#ifndef __DAL_AUDIO_DCE_110_H__
  26#define __DAL_AUDIO_DCE_110_H__
  27
  28#include "audio.h"
  29
  30#define AUD_COMMON_REG_LIST(id)\
  31        SRI(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZF0ENDPOINT, id),\
  32        SRI(AZALIA_F0_CODEC_ENDPOINT_DATA, AZF0ENDPOINT, id),\
  33        SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS),\
  34        SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES),\
  35        SR(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES),\
  36        SR(DCCG_AUDIO_DTO_SOURCE),\
  37        SR(DCCG_AUDIO_DTO0_MODULE),\
  38        SR(DCCG_AUDIO_DTO0_PHASE),\
  39        SR(DCCG_AUDIO_DTO1_MODULE),\
  40        SR(DCCG_AUDIO_DTO1_PHASE)
  41
  42
  43 /* set field name */
  44#define SF(reg_name, field_name, post_fix)\
  45        .field_name = reg_name ## __ ## field_name ## post_fix
  46
  47
  48#define AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)\
  49                SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
  50                SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
  51                SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO2_USE_512FBR_DTO, mask_sh),\
  52                SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_USE_512FBR_DTO, mask_sh),\
  53                SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO1_USE_512FBR_DTO, mask_sh),\
  54                SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
  55                SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
  56                SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
  57                SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
  58                SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
  59                SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
  60                SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh)
  61
  62#define AUD_COMMON_MASK_SH_LIST(mask_sh)\
  63                AUD_COMMON_MASK_SH_LIST_BASE(mask_sh),\
  64                SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
  65                SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
  66
  67#if defined(CONFIG_DRM_AMD_DC_SI)
  68#define AUD_DCE60_MASK_SH_LIST(mask_sh)\
  69                SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL, mask_sh),\
  70                SF(DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO_SEL, mask_sh),\
  71                SF(DCCG_AUDIO_DTO0_MODULE, DCCG_AUDIO_DTO0_MODULE, mask_sh),\
  72                SF(DCCG_AUDIO_DTO0_PHASE, DCCG_AUDIO_DTO0_PHASE, mask_sh),\
  73                SF(DCCG_AUDIO_DTO1_MODULE, DCCG_AUDIO_DTO1_MODULE, mask_sh),\
  74                SF(DCCG_AUDIO_DTO1_PHASE, DCCG_AUDIO_DTO1_PHASE, mask_sh),\
  75                SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES, AUDIO_RATE_CAPABILITIES, mask_sh),\
  76                SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, CLKSTOP, mask_sh),\
  77                SF(AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES, EPSS, mask_sh), \
  78                SF(AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
  79                SF(AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh)
  80#endif
  81
  82struct dce_audio_registers {
  83        uint32_t AZALIA_F0_CODEC_ENDPOINT_INDEX;
  84        uint32_t AZALIA_F0_CODEC_ENDPOINT_DATA;
  85
  86        uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS;
  87        uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES;
  88        uint32_t AZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES;
  89
  90        uint32_t DCCG_AUDIO_DTO_SOURCE;
  91        uint32_t DCCG_AUDIO_DTO0_MODULE;
  92        uint32_t DCCG_AUDIO_DTO0_PHASE;
  93        uint32_t DCCG_AUDIO_DTO1_MODULE;
  94        uint32_t DCCG_AUDIO_DTO1_PHASE;
  95
  96        uint32_t AUDIO_RATE_CAPABILITIES;
  97};
  98
  99struct dce_audio_shift {
 100        uint8_t AZALIA_ENDPOINT_REG_INDEX;
 101        uint8_t AZALIA_ENDPOINT_REG_DATA;
 102
 103        uint8_t AUDIO_RATE_CAPABILITIES;
 104        uint8_t CLKSTOP;
 105        uint8_t EPSS;
 106
 107        uint8_t DCCG_AUDIO_DTO0_SOURCE_SEL;
 108        uint8_t DCCG_AUDIO_DTO_SEL;
 109        uint8_t DCCG_AUDIO_DTO0_MODULE;
 110        uint8_t DCCG_AUDIO_DTO0_PHASE;
 111        uint8_t DCCG_AUDIO_DTO1_MODULE;
 112        uint8_t DCCG_AUDIO_DTO1_PHASE;
 113        uint8_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
 114        uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
 115        uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
 116};
 117
 118struct dce_audio_mask {
 119        uint32_t AZALIA_ENDPOINT_REG_INDEX;
 120        uint32_t AZALIA_ENDPOINT_REG_DATA;
 121
 122        uint32_t AUDIO_RATE_CAPABILITIES;
 123        uint32_t CLKSTOP;
 124        uint32_t EPSS;
 125
 126        uint32_t DCCG_AUDIO_DTO0_SOURCE_SEL;
 127        uint32_t DCCG_AUDIO_DTO_SEL;
 128        uint32_t DCCG_AUDIO_DTO0_MODULE;
 129        uint32_t DCCG_AUDIO_DTO0_PHASE;
 130        uint32_t DCCG_AUDIO_DTO1_MODULE;
 131        uint32_t DCCG_AUDIO_DTO1_PHASE;
 132        uint32_t DCCG_AUDIO_DTO2_USE_512FBR_DTO;
 133        uint32_t DCCG_AUDIO_DTO0_USE_512FBR_DTO;
 134        uint32_t DCCG_AUDIO_DTO1_USE_512FBR_DTO;
 135
 136};
 137
 138struct dce_audio {
 139        struct audio base;
 140        const struct dce_audio_registers *regs;
 141        const struct dce_audio_shift *shifts;
 142        const struct dce_audio_mask *masks;
 143};
 144
 145struct audio *dce_audio_create(
 146                struct dc_context *ctx,
 147                unsigned int inst,
 148                const struct dce_audio_registers *reg,
 149                const struct dce_audio_shift *shifts,
 150                const struct dce_audio_mask *masks);
 151
 152#if defined(CONFIG_DRM_AMD_DC_SI)
 153struct audio *dce60_audio_create(
 154                struct dc_context *ctx,
 155                unsigned int inst,
 156                const struct dce_audio_registers *reg,
 157                const struct dce_audio_shift *shifts,
 158                const struct dce_audio_mask *masks);
 159#endif
 160
 161void dce_aud_destroy(struct audio **audio);
 162
 163void dce_aud_hw_init(struct audio *audio);
 164
 165void dce_aud_az_enable(struct audio *audio);
 166void dce_aud_az_disable(struct audio *audio);
 167
 168void dce_aud_az_configure(struct audio *audio,
 169        enum signal_type signal,
 170        const struct audio_crtc_info *crtc_info,
 171        const struct audio_info *audio_info);
 172
 173void dce_aud_wall_dto_setup(struct audio *audio,
 174        enum signal_type signal,
 175        const struct audio_crtc_info *crtc_info,
 176        const struct audio_pll_info *pll_info);
 177
 178#endif   /*__DAL_AUDIO_DCE_110_H__*/
 179