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27#ifndef _DCE_DMCU_H_
28#define _DCE_DMCU_H_
29
30#include "dmcu.h"
31
32#define DMCU_COMMON_REG_LIST_DCE_BASE() \
33 SR(DMCU_CTRL), \
34 SR(DMCU_STATUS), \
35 SR(DMCU_RAM_ACCESS_CTRL), \
36 SR(DMCU_IRAM_WR_CTRL), \
37 SR(DMCU_IRAM_WR_DATA), \
38 SR(MASTER_COMM_DATA_REG1), \
39 SR(MASTER_COMM_DATA_REG2), \
40 SR(MASTER_COMM_DATA_REG3), \
41 SR(MASTER_COMM_CMD_REG), \
42 SR(MASTER_COMM_CNTL_REG), \
43 SR(SLAVE_COMM_DATA_REG1), \
44 SR(SLAVE_COMM_DATA_REG2), \
45 SR(SLAVE_COMM_DATA_REG3), \
46 SR(SLAVE_COMM_CMD_REG), \
47 SR(DMCU_IRAM_RD_CTRL), \
48 SR(DMCU_IRAM_RD_DATA), \
49 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
50 SR(SMU_INTERRUPT_CONTROL), \
51 SR(DC_DMCU_SCRATCH)
52
53#if defined(CONFIG_DRM_AMD_DC_SI)
54#define DMCU_DCE60_REG_LIST() \
55 SR(DMCU_CTRL), \
56 SR(DMCU_STATUS), \
57 SR(DMCU_RAM_ACCESS_CTRL), \
58 SR(DMCU_IRAM_WR_CTRL), \
59 SR(DMCU_IRAM_WR_DATA), \
60 SR(MASTER_COMM_DATA_REG1), \
61 SR(MASTER_COMM_DATA_REG2), \
62 SR(MASTER_COMM_DATA_REG3), \
63 SR(MASTER_COMM_CMD_REG), \
64 SR(MASTER_COMM_CNTL_REG), \
65 SR(DMCU_IRAM_RD_CTRL), \
66 SR(DMCU_IRAM_RD_DATA), \
67 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
68 SR(DC_DMCU_SCRATCH)
69#endif
70
71#define DMCU_DCE80_REG_LIST() \
72 SR(DMCU_CTRL), \
73 SR(DMCU_STATUS), \
74 SR(DMCU_RAM_ACCESS_CTRL), \
75 SR(DMCU_IRAM_WR_CTRL), \
76 SR(DMCU_IRAM_WR_DATA), \
77 SR(MASTER_COMM_DATA_REG1), \
78 SR(MASTER_COMM_DATA_REG2), \
79 SR(MASTER_COMM_DATA_REG3), \
80 SR(MASTER_COMM_CMD_REG), \
81 SR(MASTER_COMM_CNTL_REG), \
82 SR(DMCU_IRAM_RD_CTRL), \
83 SR(DMCU_IRAM_RD_DATA), \
84 SR(DMCU_INTERRUPT_TO_UC_EN_MASK), \
85 SR(SMU_INTERRUPT_CONTROL), \
86 SR(DC_DMCU_SCRATCH)
87
88#define DMCU_DCE110_COMMON_REG_LIST() \
89 DMCU_COMMON_REG_LIST_DCE_BASE(), \
90 SR(DCI_MEM_PWR_STATUS)
91
92#define DMCU_DCN10_REG_LIST()\
93 DMCU_COMMON_REG_LIST_DCE_BASE(), \
94 SR(DMU_MEM_PWR_CNTL)
95
96#define DMCU_DCN20_REG_LIST()\
97 DMCU_DCN10_REG_LIST(), \
98 SR(DMCUB_SCRATCH15)
99
100#define DMCU_SF(reg_name, field_name, post_fix)\
101 .field_name = reg_name ## __ ## field_name ## post_fix
102
103#define DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
104 DMCU_SF(DMCU_CTRL, \
105 DMCU_ENABLE, mask_sh), \
106 DMCU_SF(DMCU_STATUS, \
107 UC_IN_STOP_MODE, mask_sh), \
108 DMCU_SF(DMCU_STATUS, \
109 UC_IN_RESET, mask_sh), \
110 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
111 IRAM_HOST_ACCESS_EN, mask_sh), \
112 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
113 IRAM_WR_ADDR_AUTO_INC, mask_sh), \
114 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
115 IRAM_RD_ADDR_AUTO_INC, mask_sh), \
116 DMCU_SF(MASTER_COMM_CMD_REG, \
117 MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
118 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
119 DMCU_SF(SLAVE_COMM_CNTL_REG, SLAVE_COMM_INTERRUPT, mask_sh), \
120 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
121 STATIC_SCREEN1_INT_TO_UC_EN, mask_sh), \
122 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
123 STATIC_SCREEN2_INT_TO_UC_EN, mask_sh), \
124 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
125 STATIC_SCREEN3_INT_TO_UC_EN, mask_sh), \
126 DMCU_SF(DMCU_INTERRUPT_TO_UC_EN_MASK, \
127 STATIC_SCREEN4_INT_TO_UC_EN, mask_sh), \
128 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
129
130#if defined(CONFIG_DRM_AMD_DC_SI)
131#define DMCU_MASK_SH_LIST_DCE60(mask_sh) \
132 DMCU_SF(DMCU_CTRL, \
133 DMCU_ENABLE, mask_sh), \
134 DMCU_SF(DMCU_STATUS, \
135 UC_IN_STOP_MODE, mask_sh), \
136 DMCU_SF(DMCU_STATUS, \
137 UC_IN_RESET, mask_sh), \
138 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
139 IRAM_HOST_ACCESS_EN, mask_sh), \
140 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
141 IRAM_WR_ADDR_AUTO_INC, mask_sh), \
142 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
143 IRAM_RD_ADDR_AUTO_INC, mask_sh), \
144 DMCU_SF(MASTER_COMM_CMD_REG, \
145 MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
146 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh)
147#endif
148
149#define DMCU_MASK_SH_LIST_DCE80(mask_sh) \
150 DMCU_SF(DMCU_CTRL, \
151 DMCU_ENABLE, mask_sh), \
152 DMCU_SF(DMCU_STATUS, \
153 UC_IN_STOP_MODE, mask_sh), \
154 DMCU_SF(DMCU_STATUS, \
155 UC_IN_RESET, mask_sh), \
156 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
157 IRAM_HOST_ACCESS_EN, mask_sh), \
158 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
159 IRAM_WR_ADDR_AUTO_INC, mask_sh), \
160 DMCU_SF(DMCU_RAM_ACCESS_CTRL, \
161 IRAM_RD_ADDR_AUTO_INC, mask_sh), \
162 DMCU_SF(MASTER_COMM_CMD_REG, \
163 MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
164 DMCU_SF(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, mask_sh), \
165 DMCU_SF(SMU_INTERRUPT_CONTROL, DC_SMU_INT_ENABLE, mask_sh)
166
167#define DMCU_MASK_SH_LIST_DCE110(mask_sh) \
168 DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
169 DMCU_SF(DCI_MEM_PWR_STATUS, \
170 DMCU_IRAM_MEM_PWR_STATE, mask_sh)
171
172#define DMCU_MASK_SH_LIST_DCN10(mask_sh) \
173 DMCU_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
174 DMCU_SF(DMU_MEM_PWR_CNTL, \
175 DMCU_IRAM_MEM_PWR_STATE, mask_sh)
176
177#define DMCU_REG_FIELD_LIST(type) \
178 type DMCU_IRAM_MEM_PWR_STATE; \
179 type IRAM_HOST_ACCESS_EN; \
180 type IRAM_WR_ADDR_AUTO_INC; \
181 type IRAM_RD_ADDR_AUTO_INC; \
182 type DMCU_ENABLE; \
183 type UC_IN_STOP_MODE; \
184 type UC_IN_RESET; \
185 type MASTER_COMM_CMD_REG_BYTE0; \
186 type MASTER_COMM_INTERRUPT; \
187 type SLAVE_COMM_INTERRUPT; \
188 type DPHY_RX_FAST_TRAINING_CAPABLE; \
189 type DPHY_LOAD_BS_COUNT; \
190 type STATIC_SCREEN1_INT_TO_UC_EN; \
191 type STATIC_SCREEN2_INT_TO_UC_EN; \
192 type STATIC_SCREEN3_INT_TO_UC_EN; \
193 type STATIC_SCREEN4_INT_TO_UC_EN; \
194 type DP_SEC_GSP0_LINE_NUM; \
195 type DP_SEC_GSP0_PRIORITY; \
196 type DC_SMU_INT_ENABLE
197
198struct dce_dmcu_shift {
199 DMCU_REG_FIELD_LIST(uint8_t);
200};
201
202struct dce_dmcu_mask {
203 DMCU_REG_FIELD_LIST(uint32_t);
204};
205
206struct dce_dmcu_registers {
207 uint32_t DMCU_CTRL;
208 uint32_t DMCU_STATUS;
209 uint32_t DMCU_RAM_ACCESS_CTRL;
210 uint32_t DCI_MEM_PWR_STATUS;
211 uint32_t DMU_MEM_PWR_CNTL;
212 uint32_t DMCU_IRAM_WR_CTRL;
213 uint32_t DMCU_IRAM_WR_DATA;
214
215 uint32_t MASTER_COMM_DATA_REG1;
216 uint32_t MASTER_COMM_DATA_REG2;
217 uint32_t MASTER_COMM_DATA_REG3;
218 uint32_t MASTER_COMM_CMD_REG;
219 uint32_t MASTER_COMM_CNTL_REG;
220 uint32_t SLAVE_COMM_DATA_REG1;
221 uint32_t SLAVE_COMM_DATA_REG2;
222 uint32_t SLAVE_COMM_DATA_REG3;
223 uint32_t SLAVE_COMM_CMD_REG;
224 uint32_t SLAVE_COMM_CNTL_REG;
225 uint32_t DMCU_IRAM_RD_CTRL;
226 uint32_t DMCU_IRAM_RD_DATA;
227 uint32_t DMCU_INTERRUPT_TO_UC_EN_MASK;
228 uint32_t SMU_INTERRUPT_CONTROL;
229 uint32_t DC_DMCU_SCRATCH;
230 uint32_t DMCUB_SCRATCH15;
231};
232
233struct dce_dmcu {
234 struct dmcu base;
235 const struct dce_dmcu_registers *regs;
236 const struct dce_dmcu_shift *dmcu_shift;
237 const struct dce_dmcu_mask *dmcu_mask;
238};
239
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252
253union dce_dmcu_psr_config_data_reg1 {
254 struct {
255 unsigned int timehyst_frames:8;
256 unsigned int hyst_lines:7;
257 unsigned int rfb_update_auto_en:1;
258 unsigned int dp_port_num:3;
259 unsigned int dcp_sel:3;
260 unsigned int phy_type:1;
261 unsigned int frame_cap_ind:1;
262 unsigned int aux_chan:3;
263 unsigned int aux_repeat:4;
264 unsigned int allow_smu_optimizations:1;
265 } bits;
266 unsigned int u32All;
267};
268
269
270
271
272union dce_dmcu_psr_config_data_reg2 {
273 struct {
274 unsigned int dig_fe:3;
275 unsigned int dig_be:3;
276 unsigned int skip_wait_for_pll_lock:1;
277 unsigned int reserved:9;
278 unsigned int frame_delay:8;
279 unsigned int smu_phy_id:4;
280 unsigned int num_of_controllers:4;
281 } bits;
282 unsigned int u32All;
283};
284
285
286
287
288union dce_dmcu_psr_config_data_reg3 {
289 struct {
290 unsigned int psr_level:16;
291 unsigned int link_rate:4;
292 unsigned int reserved:12;
293 } bits;
294 unsigned int u32All;
295};
296
297union dce_dmcu_psr_config_data_wait_loop_reg1 {
298 struct {
299 unsigned int wait_loop:16;
300 unsigned int reserved:16;
301 } bits;
302 unsigned int u32;
303};
304
305struct dmcu *dce_dmcu_create(
306 struct dc_context *ctx,
307 const struct dce_dmcu_registers *regs,
308 const struct dce_dmcu_shift *dmcu_shift,
309 const struct dce_dmcu_mask *dmcu_mask);
310
311struct dmcu *dcn10_dmcu_create(
312 struct dc_context *ctx,
313 const struct dce_dmcu_registers *regs,
314 const struct dce_dmcu_shift *dmcu_shift,
315 const struct dce_dmcu_mask *dmcu_mask);
316
317struct dmcu *dcn20_dmcu_create(
318 struct dc_context *ctx,
319 const struct dce_dmcu_registers *regs,
320 const struct dce_dmcu_shift *dmcu_shift,
321 const struct dce_dmcu_mask *dmcu_mask);
322
323struct dmcu *dcn21_dmcu_create(
324 struct dc_context *ctx,
325 const struct dce_dmcu_registers *regs,
326 const struct dce_dmcu_shift *dmcu_shift,
327 const struct dce_dmcu_mask *dmcu_mask);
328
329void dce_dmcu_destroy(struct dmcu **dmcu);
330
331#endif
332