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26#ifndef _DCE_DCE_TRANSFORM_H_
27#define _DCE_DCE_TRANSFORM_H_
28
29
30#include "transform.h"
31
32#define TO_DCE_TRANSFORM(transform)\
33 container_of(transform, struct dce_transform, base)
34
35#define LB_TOTAL_NUMBER_OF_ENTRIES 1712
36#define LB_BITS_PER_ENTRY 144
37
38#define XFM_COMMON_REG_LIST_DCE_BASE(id) \
39 SRI(LB_DATA_FORMAT, LB, id), \
40 SRI(GAMUT_REMAP_CONTROL, DCP, id), \
41 SRI(GAMUT_REMAP_C11_C12, DCP, id), \
42 SRI(GAMUT_REMAP_C13_C14, DCP, id), \
43 SRI(GAMUT_REMAP_C21_C22, DCP, id), \
44 SRI(GAMUT_REMAP_C23_C24, DCP, id), \
45 SRI(GAMUT_REMAP_C31_C32, DCP, id), \
46 SRI(GAMUT_REMAP_C33_C34, DCP, id), \
47 SRI(OUTPUT_CSC_C11_C12, DCP, id), \
48 SRI(OUTPUT_CSC_C13_C14, DCP, id), \
49 SRI(OUTPUT_CSC_C21_C22, DCP, id), \
50 SRI(OUTPUT_CSC_C23_C24, DCP, id), \
51 SRI(OUTPUT_CSC_C31_C32, DCP, id), \
52 SRI(OUTPUT_CSC_C33_C34, DCP, id), \
53 SRI(OUTPUT_CSC_CONTROL, DCP, id), \
54 SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
55 SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
56 SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
57 SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
58 SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
59 SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
60 SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
61 SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
62 SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
63 SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
64 SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
65 SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
66 SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
67 SRI(REGAMMA_LUT_INDEX, DCP, id), \
68 SRI(REGAMMA_LUT_DATA, DCP, id), \
69 SRI(REGAMMA_CONTROL, DCP, id), \
70 SRI(DENORM_CONTROL, DCP, id), \
71 SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
72 SRI(OUT_ROUND_CONTROL, DCP, id), \
73 SRI(OUT_CLAMP_CONTROL_R_CR, DCP, id), \
74 SRI(OUT_CLAMP_CONTROL_G_Y, DCP, id), \
75 SRI(OUT_CLAMP_CONTROL_B_CB, DCP, id), \
76 SRI(SCL_MODE, SCL, id), \
77 SRI(SCL_TAP_CONTROL, SCL, id), \
78 SRI(SCL_CONTROL, SCL, id), \
79 SRI(SCL_BYPASS_CONTROL, SCL, id), \
80 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
81 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
82 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
83 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
84 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
85 SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
86 SRI(VIEWPORT_START, SCL, id), \
87 SRI(VIEWPORT_SIZE, SCL, id), \
88 SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
89 SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
90 SRI(SCL_HORZ_FILTER_INIT, SCL, id), \
91 SRI(SCL_VERT_FILTER_INIT, SCL, id), \
92 SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
93 SRI(LB_MEMORY_CTRL, LB, id), \
94 SRI(SCL_UPDATE, SCL, id), \
95 SRI(SCL_F_SHARP_CONTROL, SCL, id)
96
97#define XFM_COMMON_REG_LIST_DCE80(id) \
98 XFM_COMMON_REG_LIST_DCE_BASE(id), \
99 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
100
101#define XFM_COMMON_REG_LIST_DCE100(id) \
102 XFM_COMMON_REG_LIST_DCE_BASE(id), \
103 SRI(DCFE_MEM_PWR_CTRL, CRTC, id), \
104 SRI(DCFE_MEM_PWR_STATUS, CRTC, id)
105
106#define XFM_COMMON_REG_LIST_DCE110(id) \
107 XFM_COMMON_REG_LIST_DCE_BASE(id), \
108 SRI(DCFE_MEM_PWR_CTRL, DCFE, id), \
109 SRI(DCFE_MEM_PWR_STATUS, DCFE, id)
110
111#if defined(CONFIG_DRM_AMD_DC_SI)
112#define XFM_COMMON_REG_LIST_DCE60_BASE(id) \
113 SRI(DATA_FORMAT, LB, id), \
114 SRI(GAMUT_REMAP_CONTROL, DCP, id), \
115 SRI(GAMUT_REMAP_C11_C12, DCP, id), \
116 SRI(GAMUT_REMAP_C13_C14, DCP, id), \
117 SRI(GAMUT_REMAP_C21_C22, DCP, id), \
118 SRI(GAMUT_REMAP_C23_C24, DCP, id), \
119 SRI(GAMUT_REMAP_C31_C32, DCP, id), \
120 SRI(GAMUT_REMAP_C33_C34, DCP, id), \
121 SRI(OUTPUT_CSC_C11_C12, DCP, id), \
122 SRI(OUTPUT_CSC_C13_C14, DCP, id), \
123 SRI(OUTPUT_CSC_C21_C22, DCP, id), \
124 SRI(OUTPUT_CSC_C23_C24, DCP, id), \
125 SRI(OUTPUT_CSC_C31_C32, DCP, id), \
126 SRI(OUTPUT_CSC_C33_C34, DCP, id), \
127 SRI(OUTPUT_CSC_CONTROL, DCP, id), \
128 SRI(REGAMMA_CNTLA_START_CNTL, DCP, id), \
129 SRI(REGAMMA_CNTLA_SLOPE_CNTL, DCP, id), \
130 SRI(REGAMMA_CNTLA_END_CNTL1, DCP, id), \
131 SRI(REGAMMA_CNTLA_END_CNTL2, DCP, id), \
132 SRI(REGAMMA_CNTLA_REGION_0_1, DCP, id), \
133 SRI(REGAMMA_CNTLA_REGION_2_3, DCP, id), \
134 SRI(REGAMMA_CNTLA_REGION_4_5, DCP, id), \
135 SRI(REGAMMA_CNTLA_REGION_6_7, DCP, id), \
136 SRI(REGAMMA_CNTLA_REGION_8_9, DCP, id), \
137 SRI(REGAMMA_CNTLA_REGION_10_11, DCP, id), \
138 SRI(REGAMMA_CNTLA_REGION_12_13, DCP, id), \
139 SRI(REGAMMA_CNTLA_REGION_14_15, DCP, id), \
140 SRI(REGAMMA_LUT_WRITE_EN_MASK, DCP, id), \
141 SRI(REGAMMA_LUT_INDEX, DCP, id), \
142 SRI(REGAMMA_LUT_DATA, DCP, id), \
143 SRI(REGAMMA_CONTROL, DCP, id), \
144 SRI(DENORM_CONTROL, DCP, id), \
145 SRI(DCP_SPATIAL_DITHER_CNTL, DCP, id), \
146 SRI(OUT_ROUND_CONTROL, DCP, id), \
147 SRI(SCL_TAP_CONTROL, SCL, id), \
148 SRI(SCL_CONTROL, SCL, id), \
149 SRI(SCL_BYPASS_CONTROL, SCL, id), \
150 SRI(EXT_OVERSCAN_LEFT_RIGHT, SCL, id), \
151 SRI(EXT_OVERSCAN_TOP_BOTTOM, SCL, id), \
152 SRI(SCL_VERT_FILTER_CONTROL, SCL, id), \
153 SRI(SCL_HORZ_FILTER_CONTROL, SCL, id), \
154 SRI(SCL_COEF_RAM_SELECT, SCL, id), \
155 SRI(SCL_COEF_RAM_TAP_DATA, SCL, id), \
156 SRI(VIEWPORT_START, SCL, id), \
157 SRI(VIEWPORT_SIZE, SCL, id), \
158 SRI(SCL_HORZ_FILTER_SCALE_RATIO, SCL, id), \
159 SRI(SCL_VERT_FILTER_SCALE_RATIO, SCL, id), \
160 SRI(SCL_VERT_FILTER_INIT, SCL, id), \
161 SRI(SCL_AUTOMATIC_MODE_CONTROL, SCL, id), \
162 SRI(DC_LB_MEMORY_SPLIT, LB, id), \
163 SRI(DC_LB_MEM_SIZE, LB, id), \
164 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id), \
165 SRI(SCL_UPDATE, SCL, id), \
166 SRI(SCL_F_SHARP_CONTROL, SCL, id)
167
168#define XFM_COMMON_REG_LIST_DCE60(id) \
169 XFM_COMMON_REG_LIST_DCE60_BASE(id), \
170 SRI(DCFE_MEM_LIGHT_SLEEP_CNTL, CRTC, id)
171#endif
172
173#define XFM_SF(reg_name, field_name, post_fix)\
174 .field_name = reg_name ## __ ## field_name ## post_fix
175
176#define XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh) \
177 XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
178 XFM_SF(OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
179 XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
180 XFM_SF(OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
181 XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
182 XFM_SF(OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
183 XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
184 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
185 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
186 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
187 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
188 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
189 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
190 XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
191 XFM_SF(LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
192 XFM_SF(LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
193 XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
194 XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
195 XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
196 XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
197 XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
198 XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
199 XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
200 XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
201 XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
202 XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
203 XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
204 XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
205 XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
206 XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
207 XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
208 XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
209 XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
210 XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
211 XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
212 XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
213 XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
214 XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
215 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
216 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
217 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
218 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
219 XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
220 XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
221 XFM_SF(SCL_MODE, SCL_MODE, mask_sh), \
222 XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
223 XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
224 XFM_SF(SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
225 XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
226 XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
227 XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
228 XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
229 XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
230 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
231 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
232 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
233 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
234 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
235 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
236 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
237 XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
238 XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
239 XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
240 XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
241 XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
242 XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
243 XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
244 XFM_SF(SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
245 XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
246 XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
247 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
248 XFM_SF(LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
249 XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
250 XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
251 XFM_SF(SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
252 XFM_SF(LB_DATA_FORMAT, ALPHA_EN, mask_sh)
253
254#define XFM_COMMON_MASK_SH_LIST_DCE80(mask_sh) \
255 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
256 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
257 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
258 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
259
260#define XFM_COMMON_MASK_SH_LIST_DCE110(mask_sh) \
261 XFM_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(mask_sh), \
262 XFM_SF(DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
263 XFM_SF(DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
264 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
265 XFM_SF(DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
266 XFM_SF(DCFE_MEM_PWR_STATUS, DCP_REGAMMA_MEM_PWR_STATE, mask_sh),\
267 XFM_SF(SCL_MODE, SCL_PSCL_EN, mask_sh)
268
269#if defined(CONFIG_DRM_AMD_DC_SI)
270#define XFM_COMMON_MASK_SH_LIST_DCE60(mask_sh) \
271 XFM_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh), \
272 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_LIGHT_SLEEP_DIS, mask_sh),\
273 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, DCP_LUT_LIGHT_SLEEP_DIS, mask_sh),\
274 OPP_SF(DCFE_MEM_LIGHT_SLEEP_CNTL, REGAMMA_LUT_MEM_PWR_STATE, mask_sh)
275
276#define XFM_COMMON_MASK_SH_LIST_DCE60_COMMON_BASE(mask_sh) \
277 XFM_SF(OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
278 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
279 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
280 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
281 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
282 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
283 XFM_SF(DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
284 XFM_SF(DENORM_CONTROL, DENORM_MODE, mask_sh), \
285 XFM_SF(DATA_FORMAT, INTERLEAVE_EN, mask_sh), \
286 XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
287 XFM_SF(GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
288 XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
289 XFM_SF(GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
290 XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
291 XFM_SF(GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
292 XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
293 XFM_SF(GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
294 XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
295 XFM_SF(GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
296 XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
297 XFM_SF(GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
298 XFM_SF(GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
299 XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
300 XFM_SF(OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
301 XFM_SF(OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
302 XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
303 XFM_SF(REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
304 XFM_SF(REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
305 XFM_SF(REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
306 XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
307 XFM_SF(REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
308 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
309 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
310 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
311 XFM_SF(REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
312 XFM_SF(REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
313 XFM_SF(REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
314 XFM_SF(SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
315 XFM_SF(SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
316 XFM_SF(SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
317 XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
318 XFM_SF(EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
319 XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
320 XFM_SF(EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
321 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
322 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
323 XFM_SF(SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
324 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
325 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
326 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
327 XFM_SF(SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
328 XFM_SF(VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
329 XFM_SF(VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
330 XFM_SF(VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
331 XFM_SF(VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
332 XFM_SF(SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
333 XFM_SF(SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
334 XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_INT_RGB_Y, mask_sh), \
335 XFM_SF(SCL_HORZ_FILTER_INIT_RGB_LUMA, SCL_H_INIT_FRAC_RGB_Y, mask_sh), \
336 XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_INT_CBCR, mask_sh), \
337 XFM_SF(SCL_HORZ_FILTER_INIT_CHROMA, SCL_H_INIT_FRAC_CBCR, mask_sh), \
338 XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
339 XFM_SF(SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
340 XFM_SF(SCL_HORZ_FILTER_CONTROL, SCL_H_FILTER_PICK_NEAREST, mask_sh), \
341 XFM_SF(SCL_VERT_FILTER_CONTROL, SCL_V_FILTER_PICK_NEAREST, mask_sh), \
342 XFM_SF(DC_LB_MEMORY_SPLIT, DC_LB_MEMORY_CONFIG, mask_sh), \
343 XFM_SF(DC_LB_MEM_SIZE, DC_LB_MEM_SIZE, mask_sh)
344#endif
345
346#define XFM_COMMON_MASK_SH_LIST_SOC_BASE(mask_sh) \
347 XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MIN_B_CB, mask_sh), \
348 XFM_SF(DCP0_OUT_CLAMP_CONTROL_B_CB, OUT_CLAMP_MAX_B_CB, mask_sh), \
349 XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MIN_G_Y, mask_sh), \
350 XFM_SF(DCP0_OUT_CLAMP_CONTROL_G_Y, OUT_CLAMP_MAX_G_Y, mask_sh), \
351 XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MIN_R_CR, mask_sh), \
352 XFM_SF(DCP0_OUT_CLAMP_CONTROL_R_CR, OUT_CLAMP_MAX_R_CR, mask_sh), \
353 XFM_SF(DCP0_OUT_ROUND_CONTROL, OUT_ROUND_TRUNC_MODE, mask_sh), \
354 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_EN, mask_sh), \
355 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_MODE, mask_sh), \
356 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_SPATIAL_DITHER_DEPTH, mask_sh), \
357 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_FRAME_RANDOM_ENABLE, mask_sh), \
358 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_RGB_RANDOM_ENABLE, mask_sh), \
359 XFM_SF(DCP0_DCP_SPATIAL_DITHER_CNTL, DCP_HIGHPASS_RANDOM_ENABLE, mask_sh), \
360 XFM_SF(DCP0_DENORM_CONTROL, DENORM_MODE, mask_sh), \
361 XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_DEPTH, mask_sh), \
362 XFM_SF(LB0_LB_DATA_FORMAT, PIXEL_EXPAN_MODE, mask_sh), \
363 XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C11, mask_sh), \
364 XFM_SF(DCP0_GAMUT_REMAP_C11_C12, GAMUT_REMAP_C12, mask_sh), \
365 XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C13, mask_sh), \
366 XFM_SF(DCP0_GAMUT_REMAP_C13_C14, GAMUT_REMAP_C14, mask_sh), \
367 XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C21, mask_sh), \
368 XFM_SF(DCP0_GAMUT_REMAP_C21_C22, GAMUT_REMAP_C22, mask_sh), \
369 XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C23, mask_sh), \
370 XFM_SF(DCP0_GAMUT_REMAP_C23_C24, GAMUT_REMAP_C24, mask_sh), \
371 XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C31, mask_sh), \
372 XFM_SF(DCP0_GAMUT_REMAP_C31_C32, GAMUT_REMAP_C32, mask_sh), \
373 XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C33, mask_sh), \
374 XFM_SF(DCP0_GAMUT_REMAP_C33_C34, GAMUT_REMAP_C34, mask_sh), \
375 XFM_SF(DCP0_GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, mask_sh), \
376 XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C11, mask_sh),\
377 XFM_SF(DCP0_OUTPUT_CSC_C11_C12, OUTPUT_CSC_C12, mask_sh),\
378 XFM_SF(DCP0_OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, mask_sh),\
379 XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START, mask_sh),\
380 XFM_SF(DCP0_REGAMMA_CNTLA_START_CNTL, REGAMMA_CNTLA_EXP_REGION_START_SEGMENT, mask_sh),\
381 XFM_SF(DCP0_REGAMMA_CNTLA_SLOPE_CNTL, REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE, mask_sh),\
382 XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL1, REGAMMA_CNTLA_EXP_REGION_END, mask_sh),\
383 XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_BASE, mask_sh),\
384 XFM_SF(DCP0_REGAMMA_CNTLA_END_CNTL2, REGAMMA_CNTLA_EXP_REGION_END_SLOPE, mask_sh),\
385 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET, mask_sh),\
386 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS, mask_sh),\
387 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET, mask_sh),\
388 XFM_SF(DCP0_REGAMMA_CNTLA_REGION_0_1, REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS, mask_sh),\
389 XFM_SF(DCP0_REGAMMA_CONTROL, GRPH_REGAMMA_MODE, mask_sh),\
390 XFM_SF(DCP0_REGAMMA_LUT_WRITE_EN_MASK, REGAMMA_LUT_WRITE_EN_MASK, mask_sh),\
391 XFM_SF(SCL0_SCL_MODE, SCL_MODE, mask_sh), \
392 XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_H_NUM_OF_TAPS, mask_sh), \
393 XFM_SF(SCL0_SCL_TAP_CONTROL, SCL_V_NUM_OF_TAPS, mask_sh), \
394 XFM_SF(SCL0_SCL_CONTROL, SCL_BOUNDARY_MODE, mask_sh), \
395 XFM_SF(SCL0_SCL_BYPASS_CONTROL, SCL_BYPASS_MODE, mask_sh), \
396 XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_LEFT, mask_sh), \
397 XFM_SF(SCL0_EXT_OVERSCAN_LEFT_RIGHT, EXT_OVERSCAN_RIGHT, mask_sh), \
398 XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_TOP, mask_sh), \
399 XFM_SF(SCL0_EXT_OVERSCAN_TOP_BOTTOM, EXT_OVERSCAN_BOTTOM, mask_sh), \
400 XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_FILTER_TYPE, mask_sh), \
401 XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_PHASE, mask_sh), \
402 XFM_SF(SCL0_SCL_COEF_RAM_SELECT, SCL_C_RAM_TAP_PAIR_IDX, mask_sh), \
403 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF_EN, mask_sh), \
404 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_EVEN_TAP_COEF, mask_sh), \
405 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF_EN, mask_sh), \
406 XFM_SF(SCL0_SCL_COEF_RAM_TAP_DATA, SCL_C_RAM_ODD_TAP_COEF, mask_sh), \
407 XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_X_START, mask_sh), \
408 XFM_SF(SCL0_VIEWPORT_START, VIEWPORT_Y_START, mask_sh), \
409 XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT, mask_sh), \
410 XFM_SF(SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH, mask_sh), \
411 XFM_SF(SCL0_SCL_HORZ_FILTER_SCALE_RATIO, SCL_H_SCALE_RATIO, mask_sh), \
412 XFM_SF(SCL0_SCL_VERT_FILTER_SCALE_RATIO, SCL_V_SCALE_RATIO, mask_sh), \
413 XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_INT, mask_sh), \
414 XFM_SF(SCL0_SCL_HORZ_FILTER_INIT, SCL_H_INIT_FRAC, mask_sh), \
415 XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_INT, mask_sh), \
416 XFM_SF(SCL0_SCL_VERT_FILTER_INIT, SCL_V_INIT_FRAC, mask_sh), \
417 XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mask_sh), \
418 XFM_SF(LB0_LB_MEMORY_CTRL, LB_MEMORY_SIZE, mask_sh), \
419 XFM_SF(SCL0_SCL_VERT_FILTER_CONTROL, SCL_V_2TAP_HARDCODE_COEF_EN, mask_sh), \
420 XFM_SF(SCL0_SCL_HORZ_FILTER_CONTROL, SCL_H_2TAP_HARDCODE_COEF_EN, mask_sh), \
421 XFM_SF(SCL0_SCL_UPDATE, SCL_COEF_UPDATE_COMPLETE, mask_sh), \
422 XFM_SF(LB0_LB_DATA_FORMAT, ALPHA_EN, mask_sh), \
423 XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, SCL_COEFF_MEM_PWR_DIS, mask_sh), \
424 XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_REGAMMA_MEM_PWR_DIS, mask_sh),\
425 XFM_SF(DCFE0_DCFE_MEM_PWR_CTRL, DCP_LUT_MEM_PWR_DIS, mask_sh),\
426 XFM_SF(DCFE0_DCFE_MEM_PWR_STATUS, SCL_COEFF_MEM_PWR_STATE, mask_sh), \
427 XFM_SF(SCL0_SCL_MODE, SCL_PSCL_EN, mask_sh)
428
429#define XFM_REG_FIELD_LIST(type) \
430 type OUT_CLAMP_MIN_B_CB; \
431 type OUT_CLAMP_MAX_B_CB; \
432 type OUT_CLAMP_MIN_G_Y; \
433 type OUT_CLAMP_MAX_G_Y; \
434 type OUT_CLAMP_MIN_R_CR; \
435 type OUT_CLAMP_MAX_R_CR; \
436 type OUT_ROUND_TRUNC_MODE; \
437 type DCP_SPATIAL_DITHER_EN; \
438 type DCP_SPATIAL_DITHER_MODE; \
439 type DCP_SPATIAL_DITHER_DEPTH; \
440 type DCP_FRAME_RANDOM_ENABLE; \
441 type DCP_RGB_RANDOM_ENABLE; \
442 type DCP_HIGHPASS_RANDOM_ENABLE; \
443 type DENORM_MODE; \
444 type INTERLEAVE_EN; \
445 type PIXEL_DEPTH; \
446 type PIXEL_EXPAN_MODE; \
447 type GAMUT_REMAP_C11; \
448 type GAMUT_REMAP_C12; \
449 type GAMUT_REMAP_C13; \
450 type GAMUT_REMAP_C14; \
451 type GAMUT_REMAP_C21; \
452 type GAMUT_REMAP_C22; \
453 type GAMUT_REMAP_C23; \
454 type GAMUT_REMAP_C24; \
455 type GAMUT_REMAP_C31; \
456 type GAMUT_REMAP_C32; \
457 type GAMUT_REMAP_C33; \
458 type GAMUT_REMAP_C34; \
459 type GRPH_GAMUT_REMAP_MODE; \
460 type OUTPUT_CSC_C11; \
461 type OUTPUT_CSC_C12; \
462 type OUTPUT_CSC_GRPH_MODE; \
463 type DCP_REGAMMA_MEM_PWR_DIS; \
464 type DCP_LUT_MEM_PWR_DIS; \
465 type REGAMMA_LUT_LIGHT_SLEEP_DIS; \
466 type DCP_LUT_LIGHT_SLEEP_DIS; \
467 type REGAMMA_CNTLA_EXP_REGION_START; \
468 type REGAMMA_CNTLA_EXP_REGION_START_SEGMENT; \
469 type REGAMMA_CNTLA_EXP_REGION_LINEAR_SLOPE; \
470 type REGAMMA_CNTLA_EXP_REGION_END; \
471 type REGAMMA_CNTLA_EXP_REGION_END_BASE; \
472 type REGAMMA_CNTLA_EXP_REGION_END_SLOPE; \
473 type REGAMMA_CNTLA_EXP_REGION0_LUT_OFFSET; \
474 type REGAMMA_CNTLA_EXP_REGION0_NUM_SEGMENTS; \
475 type REGAMMA_CNTLA_EXP_REGION1_LUT_OFFSET; \
476 type REGAMMA_CNTLA_EXP_REGION1_NUM_SEGMENTS; \
477 type DCP_REGAMMA_MEM_PWR_STATE; \
478 type REGAMMA_LUT_MEM_PWR_STATE; \
479 type REGAMMA_LUT_WRITE_EN_MASK; \
480 type GRPH_REGAMMA_MODE; \
481 type SCL_MODE; \
482 type SCL_BYPASS_MODE; \
483 type SCL_PSCL_EN; \
484 type SCL_H_NUM_OF_TAPS; \
485 type SCL_V_NUM_OF_TAPS; \
486 type SCL_BOUNDARY_MODE; \
487 type EXT_OVERSCAN_LEFT; \
488 type EXT_OVERSCAN_RIGHT; \
489 type EXT_OVERSCAN_TOP; \
490 type EXT_OVERSCAN_BOTTOM; \
491 type SCL_COEFF_MEM_PWR_DIS; \
492 type SCL_COEFF_MEM_PWR_STATE; \
493 type SCL_C_RAM_FILTER_TYPE; \
494 type SCL_C_RAM_PHASE; \
495 type SCL_C_RAM_TAP_PAIR_IDX; \
496 type SCL_C_RAM_EVEN_TAP_COEF_EN; \
497 type SCL_C_RAM_EVEN_TAP_COEF; \
498 type SCL_C_RAM_ODD_TAP_COEF_EN; \
499 type SCL_C_RAM_ODD_TAP_COEF; \
500 type VIEWPORT_X_START; \
501 type VIEWPORT_Y_START; \
502 type VIEWPORT_HEIGHT; \
503 type VIEWPORT_WIDTH; \
504 type SCL_H_SCALE_RATIO; \
505 type SCL_V_SCALE_RATIO; \
506 type SCL_H_INIT_INT; \
507 type SCL_H_INIT_FRAC; \
508 type SCL_H_INIT_INT_RGB_Y; \
509 type SCL_H_INIT_FRAC_RGB_Y; \
510 type SCL_H_INIT_INT_CBCR; \
511 type SCL_H_INIT_FRAC_CBCR; \
512 type SCL_V_INIT_INT; \
513 type SCL_V_INIT_FRAC; \
514 type DC_LB_MEMORY_CONFIG; \
515 type DC_LB_MEM_SIZE; \
516 type LB_MEMORY_CONFIG; \
517 type LB_MEMORY_SIZE; \
518 type SCL_V_2TAP_HARDCODE_COEF_EN; \
519 type SCL_H_2TAP_HARDCODE_COEF_EN; \
520 type SCL_V_FILTER_PICK_NEAREST; \
521 type SCL_H_FILTER_PICK_NEAREST; \
522 type SCL_COEF_UPDATE_COMPLETE; \
523 type ALPHA_EN
524
525struct dce_transform_shift {
526 XFM_REG_FIELD_LIST(uint8_t);
527};
528
529struct dce_transform_mask {
530 XFM_REG_FIELD_LIST(uint32_t);
531};
532
533struct dce_transform_registers {
534#if defined(CONFIG_DRM_AMD_DC_SI)
535 uint32_t DATA_FORMAT;
536#endif
537 uint32_t LB_DATA_FORMAT;
538 uint32_t GAMUT_REMAP_CONTROL;
539 uint32_t GAMUT_REMAP_C11_C12;
540 uint32_t GAMUT_REMAP_C13_C14;
541 uint32_t GAMUT_REMAP_C21_C22;
542 uint32_t GAMUT_REMAP_C23_C24;
543 uint32_t GAMUT_REMAP_C31_C32;
544 uint32_t GAMUT_REMAP_C33_C34;
545 uint32_t OUTPUT_CSC_C11_C12;
546 uint32_t OUTPUT_CSC_C13_C14;
547 uint32_t OUTPUT_CSC_C21_C22;
548 uint32_t OUTPUT_CSC_C23_C24;
549 uint32_t OUTPUT_CSC_C31_C32;
550 uint32_t OUTPUT_CSC_C33_C34;
551 uint32_t OUTPUT_CSC_CONTROL;
552 uint32_t DCFE_MEM_LIGHT_SLEEP_CNTL;
553 uint32_t REGAMMA_CNTLA_START_CNTL;
554 uint32_t REGAMMA_CNTLA_SLOPE_CNTL;
555 uint32_t REGAMMA_CNTLA_END_CNTL1;
556 uint32_t REGAMMA_CNTLA_END_CNTL2;
557 uint32_t REGAMMA_CNTLA_REGION_0_1;
558 uint32_t REGAMMA_CNTLA_REGION_2_3;
559 uint32_t REGAMMA_CNTLA_REGION_4_5;
560 uint32_t REGAMMA_CNTLA_REGION_6_7;
561 uint32_t REGAMMA_CNTLA_REGION_8_9;
562 uint32_t REGAMMA_CNTLA_REGION_10_11;
563 uint32_t REGAMMA_CNTLA_REGION_12_13;
564 uint32_t REGAMMA_CNTLA_REGION_14_15;
565 uint32_t REGAMMA_LUT_WRITE_EN_MASK;
566 uint32_t REGAMMA_LUT_INDEX;
567 uint32_t REGAMMA_LUT_DATA;
568 uint32_t REGAMMA_CONTROL;
569 uint32_t DENORM_CONTROL;
570 uint32_t DCP_SPATIAL_DITHER_CNTL;
571 uint32_t OUT_ROUND_CONTROL;
572 uint32_t OUT_CLAMP_CONTROL_R_CR;
573 uint32_t OUT_CLAMP_CONTROL_G_Y;
574 uint32_t OUT_CLAMP_CONTROL_B_CB;
575 uint32_t SCL_MODE;
576 uint32_t SCL_TAP_CONTROL;
577 uint32_t SCL_CONTROL;
578 uint32_t SCL_BYPASS_CONTROL;
579 uint32_t EXT_OVERSCAN_LEFT_RIGHT;
580 uint32_t EXT_OVERSCAN_TOP_BOTTOM;
581 uint32_t SCL_VERT_FILTER_CONTROL;
582 uint32_t SCL_HORZ_FILTER_CONTROL;
583 uint32_t DCFE_MEM_PWR_CTRL;
584 uint32_t DCFE_MEM_PWR_STATUS;
585 uint32_t SCL_COEF_RAM_SELECT;
586 uint32_t SCL_COEF_RAM_TAP_DATA;
587 uint32_t VIEWPORT_START;
588 uint32_t VIEWPORT_SIZE;
589 uint32_t SCL_HORZ_FILTER_SCALE_RATIO;
590 uint32_t SCL_VERT_FILTER_SCALE_RATIO;
591 uint32_t SCL_HORZ_FILTER_INIT;
592#if defined(CONFIG_DRM_AMD_DC_SI)
593 uint32_t SCL_HORZ_FILTER_INIT_RGB_LUMA;
594 uint32_t SCL_HORZ_FILTER_INIT_CHROMA;
595#endif
596 uint32_t SCL_VERT_FILTER_INIT;
597 uint32_t SCL_AUTOMATIC_MODE_CONTROL;
598#if defined(CONFIG_DRM_AMD_DC_SI)
599 uint32_t DC_LB_MEMORY_SPLIT;
600 uint32_t DC_LB_MEM_SIZE;
601#endif
602 uint32_t LB_MEMORY_CTRL;
603 uint32_t SCL_UPDATE;
604 uint32_t SCL_F_SHARP_CONTROL;
605};
606
607struct init_int_and_frac {
608 uint32_t integer;
609 uint32_t fraction;
610};
611
612struct scl_ratios_inits {
613 uint32_t h_int_scale_ratio;
614 uint32_t v_int_scale_ratio;
615 struct init_int_and_frac h_init;
616 struct init_int_and_frac v_init;
617};
618
619#if defined(CONFIG_DRM_AMD_DC_SI)
620struct sclh_ratios_inits {
621 uint32_t h_int_scale_ratio;
622 uint32_t v_int_scale_ratio;
623 struct init_int_and_frac h_init_luma;
624 struct init_int_and_frac h_init_chroma;
625 struct init_int_and_frac v_init;
626};
627#endif
628
629enum ram_filter_type {
630 FILTER_TYPE_RGB_Y_VERTICAL = 0,
631 FILTER_TYPE_CBCR_VERTICAL = 1,
632 FILTER_TYPE_RGB_Y_HORIZONTAL = 2,
633 FILTER_TYPE_CBCR_HORIZONTAL = 3,
634 FILTER_TYPE_ALPHA_VERTICAL = 4,
635 FILTER_TYPE_ALPHA_HORIZONTAL = 5,
636};
637
638struct dce_transform {
639 struct transform base;
640 const struct dce_transform_registers *regs;
641 const struct dce_transform_shift *xfm_shift;
642 const struct dce_transform_mask *xfm_mask;
643
644 const uint16_t *filter_v;
645 const uint16_t *filter_h;
646 const uint16_t *filter_v_c;
647 const uint16_t *filter_h_c;
648 int lb_pixel_depth_supported;
649 int lb_memory_size;
650 int lb_bits_per_entry;
651 bool prescaler_on;
652};
653
654void dce_transform_construct(struct dce_transform *xfm_dce,
655 struct dc_context *ctx,
656 uint32_t inst,
657 const struct dce_transform_registers *regs,
658 const struct dce_transform_shift *xfm_shift,
659 const struct dce_transform_mask *xfm_mask);
660
661#if defined(CONFIG_DRM_AMD_DC_SI)
662void dce60_transform_construct(struct dce_transform *xfm_dce,
663 struct dc_context *ctx,
664 uint32_t inst,
665 const struct dce_transform_registers *regs,
666 const struct dce_transform_shift *xfm_shift,
667 const struct dce_transform_mask *xfm_mask);
668#endif
669
670bool dce_transform_get_optimal_number_of_taps(
671 struct transform *xfm,
672 struct scaler_data *scl_data,
673 const struct scaling_taps *in_taps);
674
675void dce110_opp_set_csc_adjustment(
676 struct transform *xfm,
677 const struct out_csc_color_matrix *tbl_entry);
678
679void dce110_opp_set_csc_default(
680 struct transform *xfm,
681 const struct default_adjustment *default_adjust);
682
683
684void dce110_opp_power_on_regamma_lut(
685 struct transform *xfm,
686 bool power_on);
687
688void dce110_opp_program_regamma_pwl(
689 struct transform *xfm,
690 const struct pwl_params *params);
691
692void dce110_opp_set_regamma_mode(struct transform *xfm,
693 enum opp_regamma mode);
694
695#endif
696
