LXR linux/drivers/gpu/drm/amd/display/dc/dce80/dce80_hw

   1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#include "dm_services.h"
  27#include "dc.h"
  28#include "core_types.h"
  29#include "dce80_hw_sequencer.h"
  30
  31#include "dce/dce_hwseq.h"
  32#include "dce110/dce110_hw_sequencer.h"
  33#include "dce100/dce100_hw_sequencer.h"
  34
  35/* include DCE8 register header files */
  36#include "dce/dce_8_0_d.h"
  37#include "dce/dce_8_0_sh_mask.h"
  38
  39/*******************************************************************************
  40 * Private definitions
  41 ******************************************************************************/
  42
  43/***************************PIPE_CONTROL***********************************/
  44
  45void dce80_hw_sequencer_construct(struct dc *dc)
  46{
  47        dce110_hw_sequencer_construct(dc);
  48
  49        dc->hwseq->funcs.enable_display_power_gating = dce100_enable_display_power_gating;
  50        dc->hwss.pipe_control_lock = dce_pipe_control_lock;
  51        dc->hwss.prepare_bandwidth = dce100_prepare_bandwidth;
  52        dc->hwss.optimize_bandwidth = dce100_optimize_bandwidth;
  53}
  54
  55