1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26#include "dm_services.h"
27
28#include "core_types.h"
29
30#include "reg_helper.h"
31#include "dcn10_dpp.h"
32#include "basics/conversion.h"
33
34#define NUM_PHASES 64
35#define HORZ_MAX_TAPS 8
36#define VERT_MAX_TAPS 8
37
38#define BLACK_OFFSET_RGB_Y 0x0
39#define BLACK_OFFSET_CBCR 0x8000
40
41#define REG(reg)\
42 dpp->tf_regs->reg
43
44#define CTX \
45 dpp->base.ctx
46
47#undef FN
48#define FN(reg_name, field_name) \
49 dpp->tf_shift->field_name, dpp->tf_mask->field_name
50
51enum pixel_format_description {
52 PIXEL_FORMAT_FIXED = 0,
53 PIXEL_FORMAT_FIXED16,
54 PIXEL_FORMAT_FLOAT
55
56};
57
58enum dcn10_coef_filter_type_sel {
59 SCL_COEF_LUMA_VERT_FILTER = 0,
60 SCL_COEF_LUMA_HORZ_FILTER = 1,
61 SCL_COEF_CHROMA_VERT_FILTER = 2,
62 SCL_COEF_CHROMA_HORZ_FILTER = 3,
63 SCL_COEF_ALPHA_VERT_FILTER = 4,
64 SCL_COEF_ALPHA_HORZ_FILTER = 5
65};
66
67enum dscl_autocal_mode {
68 AUTOCAL_MODE_OFF = 0,
69
70
71
72
73 AUTOCAL_MODE_AUTOSCALE = 1,
74
75
76
77 AUTOCAL_MODE_AUTOCENTER = 2,
78
79
80
81 AUTOCAL_MODE_AUTOREPLICATE = 3
82};
83
84enum dscl_mode_sel {
85 DSCL_MODE_SCALING_444_BYPASS = 0,
86 DSCL_MODE_SCALING_444_RGB_ENABLE = 1,
87 DSCL_MODE_SCALING_444_YCBCR_ENABLE = 2,
88 DSCL_MODE_SCALING_420_YCBCR_ENABLE = 3,
89 DSCL_MODE_SCALING_420_LUMA_BYPASS = 4,
90 DSCL_MODE_SCALING_420_CHROMA_BYPASS = 5,
91 DSCL_MODE_DSCL_BYPASS = 6
92};
93
94void dpp_read_state(struct dpp *dpp_base,
95 struct dcn_dpp_state *s)
96{
97 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
98
99 REG_GET(DPP_CONTROL,
100 DPP_CLOCK_ENABLE, &s->is_enabled);
101 REG_GET(CM_IGAM_CONTROL,
102 CM_IGAM_LUT_MODE, &s->igam_lut_mode);
103 REG_GET(CM_IGAM_CONTROL,
104 CM_IGAM_INPUT_FORMAT, &s->igam_input_format);
105 REG_GET(CM_DGAM_CONTROL,
106 CM_DGAM_LUT_MODE, &s->dgam_lut_mode);
107 REG_GET(CM_RGAM_CONTROL,
108 CM_RGAM_LUT_MODE, &s->rgam_lut_mode);
109 REG_GET(CM_GAMUT_REMAP_CONTROL,
110 CM_GAMUT_REMAP_MODE, &s->gamut_remap_mode);
111
112 if (s->gamut_remap_mode) {
113 s->gamut_remap_c11_c12 = REG_READ(CM_GAMUT_REMAP_C11_C12);
114 s->gamut_remap_c13_c14 = REG_READ(CM_GAMUT_REMAP_C13_C14);
115 s->gamut_remap_c21_c22 = REG_READ(CM_GAMUT_REMAP_C21_C22);
116 s->gamut_remap_c23_c24 = REG_READ(CM_GAMUT_REMAP_C23_C24);
117 s->gamut_remap_c31_c32 = REG_READ(CM_GAMUT_REMAP_C31_C32);
118 s->gamut_remap_c33_c34 = REG_READ(CM_GAMUT_REMAP_C33_C34);
119 }
120}
121
122
123void dpp_set_gamut_remap_bypass(struct dcn10_dpp *dpp)
124{
125 REG_SET(CM_GAMUT_REMAP_CONTROL, 0,
126 CM_GAMUT_REMAP_MODE, 0);
127
128}
129
130#define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19))
131
132bool dpp1_get_optimal_number_of_taps(
133 struct dpp *dpp,
134 struct scaler_data *scl_data,
135 const struct scaling_taps *in_taps)
136{
137
138 if (scl_data->format == PIXEL_FORMAT_FP16 &&
139 dpp->caps->dscl_data_proc_format == DSCL_DATA_PRCESSING_FIXED_FORMAT &&
140 scl_data->ratios.horz.value != dc_fixpt_one.value &&
141 scl_data->ratios.vert.value != dc_fixpt_one.value)
142 return false;
143
144 if (scl_data->viewport.width > scl_data->h_active &&
145 dpp->ctx->dc->debug.max_downscale_src_width != 0 &&
146 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width)
147 return false;
148
149
150
151
152 if (scl_data->ratios.horz.value == (4ll << 32))
153 scl_data->ratios.horz.value--;
154 if (scl_data->ratios.vert.value == (4ll << 32))
155 scl_data->ratios.vert.value--;
156 if (scl_data->ratios.horz_c.value == (4ll << 32))
157 scl_data->ratios.horz_c.value--;
158 if (scl_data->ratios.vert_c.value == (4ll << 32))
159 scl_data->ratios.vert_c.value--;
160
161
162 if (in_taps->h_taps == 0)
163 scl_data->taps.h_taps = 4;
164 else
165 scl_data->taps.h_taps = in_taps->h_taps;
166 if (in_taps->v_taps == 0)
167 scl_data->taps.v_taps = 4;
168 else
169 scl_data->taps.v_taps = in_taps->v_taps;
170 if (in_taps->v_taps_c == 0)
171 scl_data->taps.v_taps_c = 2;
172 else
173 scl_data->taps.v_taps_c = in_taps->v_taps_c;
174 if (in_taps->h_taps_c == 0)
175 scl_data->taps.h_taps_c = 2;
176
177 else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1)
178 scl_data->taps.h_taps_c = in_taps->h_taps_c - 1;
179 else
180 scl_data->taps.h_taps_c = in_taps->h_taps_c;
181
182 if (!dpp->ctx->dc->debug.always_scale) {
183 if (IDENTITY_RATIO(scl_data->ratios.horz))
184 scl_data->taps.h_taps = 1;
185 if (IDENTITY_RATIO(scl_data->ratios.vert))
186 scl_data->taps.v_taps = 1;
187 if (IDENTITY_RATIO(scl_data->ratios.horz_c))
188 scl_data->taps.h_taps_c = 1;
189 if (IDENTITY_RATIO(scl_data->ratios.vert_c))
190 scl_data->taps.v_taps_c = 1;
191 }
192
193 return true;
194}
195
196void dpp_reset(struct dpp *dpp_base)
197{
198 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
199
200 dpp->filter_h_c = NULL;
201 dpp->filter_v_c = NULL;
202 dpp->filter_h = NULL;
203 dpp->filter_v = NULL;
204
205 memset(&dpp->scl_data, 0, sizeof(dpp->scl_data));
206 memset(&dpp->pwl_data, 0, sizeof(dpp->pwl_data));
207}
208
209
210
211static void dpp1_cm_set_regamma_pwl(
212 struct dpp *dpp_base, const struct pwl_params *params, enum opp_regamma mode)
213{
214 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
215 uint32_t re_mode = 0;
216
217 switch (mode) {
218 case OPP_REGAMMA_BYPASS:
219 re_mode = 0;
220 break;
221 case OPP_REGAMMA_SRGB:
222 re_mode = 1;
223 break;
224 case OPP_REGAMMA_XVYCC:
225 re_mode = 2;
226 break;
227 case OPP_REGAMMA_USER:
228 re_mode = dpp->is_write_to_ram_a_safe ? 4 : 3;
229 if (memcmp(&dpp->pwl_data, params, sizeof(*params)) == 0)
230 break;
231
232 dpp1_cm_power_on_regamma_lut(dpp_base, true);
233 dpp1_cm_configure_regamma_lut(dpp_base, dpp->is_write_to_ram_a_safe);
234
235 if (dpp->is_write_to_ram_a_safe)
236 dpp1_cm_program_regamma_luta_settings(dpp_base, params);
237 else
238 dpp1_cm_program_regamma_lutb_settings(dpp_base, params);
239
240 dpp1_cm_program_regamma_lut(dpp_base, params->rgb_resulted,
241 params->hw_points_num);
242 dpp->pwl_data = *params;
243
244 re_mode = dpp->is_write_to_ram_a_safe ? 3 : 4;
245 dpp->is_write_to_ram_a_safe = !dpp->is_write_to_ram_a_safe;
246 break;
247 default:
248 break;
249 }
250 REG_SET(CM_RGAM_CONTROL, 0, CM_RGAM_LUT_MODE, re_mode);
251}
252
253static void dpp1_setup_format_flags(enum surface_pixel_format input_format,\
254 enum pixel_format_description *fmt)
255{
256
257 if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F ||
258 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F)
259 *fmt = PIXEL_FORMAT_FLOAT;
260 else if (input_format == SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616 ||
261 input_format == SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616)
262 *fmt = PIXEL_FORMAT_FIXED16;
263 else
264 *fmt = PIXEL_FORMAT_FIXED;
265}
266
267static void dpp1_set_degamma_format_float(
268 struct dpp *dpp_base,
269 bool is_float)
270{
271 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
272
273 if (is_float) {
274 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 3);
275 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 1);
276 } else {
277 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_INPUT_FORMAT, 2);
278 REG_UPDATE(CM_IGAM_CONTROL, CM_IGAM_LUT_MODE, 0);
279 }
280}
281
282void dpp1_cnv_setup (
283 struct dpp *dpp_base,
284 enum surface_pixel_format format,
285 enum expansion_mode mode,
286 struct dc_csc_transform input_csc_color_matrix,
287 enum dc_color_space input_color_space,
288 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
289{
290 uint32_t pixel_format;
291 uint32_t alpha_en;
292 enum pixel_format_description fmt ;
293 enum dc_color_space color_space;
294 enum dcn10_input_csc_select select;
295 bool is_float;
296 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
297 bool force_disable_cursor = false;
298 struct out_csc_color_matrix tbl_entry;
299 int i = 0;
300
301 dpp1_setup_format_flags(format, &fmt);
302 alpha_en = 1;
303 pixel_format = 0;
304 color_space = COLOR_SPACE_SRGB;
305 select = INPUT_CSC_SELECT_BYPASS;
306 is_float = false;
307
308 switch (fmt) {
309 case PIXEL_FORMAT_FIXED:
310 case PIXEL_FORMAT_FIXED16:
311
312 REG_SET_3(FORMAT_CONTROL, 0,
313 CNVC_BYPASS, 0,
314 FORMAT_EXPANSION_MODE, mode,
315 OUTPUT_FP, 0);
316 break;
317 case PIXEL_FORMAT_FLOAT:
318 REG_SET_3(FORMAT_CONTROL, 0,
319 CNVC_BYPASS, 0,
320 FORMAT_EXPANSION_MODE, mode,
321 OUTPUT_FP, 1);
322 is_float = true;
323 break;
324 default:
325
326 break;
327 }
328
329 dpp1_set_degamma_format_float(dpp_base, is_float);
330
331 switch (format) {
332 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
333 pixel_format = 1;
334 break;
335 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
336 pixel_format = 3;
337 alpha_en = 0;
338 break;
339 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
340 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
341 pixel_format = 8;
342 break;
343 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
344 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
345 pixel_format = 10;
346 break;
347 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
348 force_disable_cursor = false;
349 pixel_format = 65;
350 color_space = COLOR_SPACE_YCBCR709;
351 select = INPUT_CSC_SELECT_ICSC;
352 break;
353 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
354 force_disable_cursor = true;
355 pixel_format = 64;
356 color_space = COLOR_SPACE_YCBCR709;
357 select = INPUT_CSC_SELECT_ICSC;
358 break;
359 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
360 force_disable_cursor = true;
361 pixel_format = 67;
362 color_space = COLOR_SPACE_YCBCR709;
363 select = INPUT_CSC_SELECT_ICSC;
364 break;
365 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
366 force_disable_cursor = true;
367 pixel_format = 66;
368 color_space = COLOR_SPACE_YCBCR709;
369 select = INPUT_CSC_SELECT_ICSC;
370 break;
371 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
372 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
373 pixel_format = 26;
374 break;
375 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
376 pixel_format = 24;
377 break;
378 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
379 pixel_format = 25;
380 break;
381 default:
382 break;
383 }
384
385
386 color_space = input_color_space ? input_color_space : color_space;
387
388 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0,
389 CNVC_SURFACE_PIXEL_FORMAT, pixel_format);
390 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
391
392
393
394 if (input_csc_color_matrix.enable_adjustment
395 == true) {
396 for (i = 0; i < 12; i++)
397 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
398
399 tbl_entry.color_space = color_space;
400
401 if (color_space >= COLOR_SPACE_YCBCR601)
402 select = INPUT_CSC_SELECT_ICSC;
403 else
404 select = INPUT_CSC_SELECT_BYPASS;
405
406 dpp1_program_input_csc(dpp_base, color_space, select, &tbl_entry);
407 } else
408 dpp1_program_input_csc(dpp_base, color_space, select, NULL);
409
410 if (force_disable_cursor) {
411 REG_UPDATE(CURSOR_CONTROL,
412 CURSOR_ENABLE, 0);
413 REG_UPDATE(CURSOR0_CONTROL,
414 CUR0_ENABLE, 0);
415 }
416}
417
418void dpp1_set_cursor_attributes(
419 struct dpp *dpp_base,
420 struct dc_cursor_attributes *cursor_attributes)
421{
422 enum dc_cursor_color_format color_format = cursor_attributes->color_format;
423 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
424
425 REG_UPDATE_2(CURSOR0_CONTROL,
426 CUR0_MODE, color_format,
427 CUR0_EXPANSION_MODE, 0);
428
429 if (color_format == CURSOR_MODE_MONO) {
430
431 REG_UPDATE(CURSOR0_COLOR0,
432 CUR0_COLOR0, 0x00000000);
433 REG_UPDATE(CURSOR0_COLOR1,
434 CUR0_COLOR1, 0xFFFFFFFF);
435 }
436}
437
438
439void dpp1_set_cursor_position(
440 struct dpp *dpp_base,
441 const struct dc_cursor_position *pos,
442 const struct dc_cursor_mi_param *param,
443 uint32_t width,
444 uint32_t height)
445{
446 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
447 int src_x_offset = pos->x - pos->x_hotspot - param->viewport.x;
448 int src_y_offset = pos->y - pos->y_hotspot - param->viewport.y;
449 uint32_t cur_en = pos->enable ? 1 : 0;
450
451
452 if (param->rotation == ROTATION_ANGLE_90 || param->rotation == ROTATION_ANGLE_270) {
453 swap(width, height);
454 if (param->rotation == ROTATION_ANGLE_90) {
455 src_x_offset = pos->x - pos->y_hotspot - param->viewport.x;
456 src_y_offset = pos->y - pos->x_hotspot - param->viewport.y;
457 }
458 } else if (param->rotation == ROTATION_ANGLE_180) {
459 src_x_offset = pos->x - param->viewport.x;
460 src_y_offset = pos->y - param->viewport.y;
461 }
462
463
464 if (src_x_offset >= (int)param->viewport.width)
465 cur_en = 0;
466
467 if (src_x_offset + (int)width <= 0)
468 cur_en = 0;
469
470 if (src_y_offset >= (int)param->viewport.height)
471 cur_en = 0;
472
473 if (src_y_offset + (int)height <= 0)
474 cur_en = 0;
475
476 REG_UPDATE(CURSOR0_CONTROL,
477 CUR0_ENABLE, cur_en);
478
479}
480
481void dpp1_cnv_set_optional_cursor_attributes(
482 struct dpp *dpp_base,
483 struct dpp_cursor_attributes *attr)
484{
485 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
486
487 if (attr) {
488 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_BIAS, attr->bias);
489 REG_UPDATE(CURSOR0_FP_SCALE_BIAS, CUR0_FP_SCALE, attr->scale);
490 }
491}
492
493void dpp1_dppclk_control(
494 struct dpp *dpp_base,
495 bool dppclk_div,
496 bool enable)
497{
498 struct dcn10_dpp *dpp = TO_DCN10_DPP(dpp_base);
499
500 if (enable) {
501 if (dpp->tf_mask->DPPCLK_RATE_CONTROL)
502 REG_UPDATE_2(DPP_CONTROL,
503 DPPCLK_RATE_CONTROL, dppclk_div,
504 DPP_CLOCK_ENABLE, 1);
505 else
506 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 1);
507 } else
508 REG_UPDATE(DPP_CONTROL, DPP_CLOCK_ENABLE, 0);
509}
510
511static const struct dpp_funcs dcn10_dpp_funcs = {
512 .dpp_read_state = dpp_read_state,
513 .dpp_reset = dpp_reset,
514 .dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
515 .dpp_get_optimal_number_of_taps = dpp1_get_optimal_number_of_taps,
516 .dpp_set_gamut_remap = dpp1_cm_set_gamut_remap,
517 .dpp_set_csc_adjustment = dpp1_cm_set_output_csc_adjustment,
518 .dpp_set_csc_default = dpp1_cm_set_output_csc_default,
519 .dpp_power_on_regamma_lut = dpp1_cm_power_on_regamma_lut,
520 .dpp_program_regamma_lut = dpp1_cm_program_regamma_lut,
521 .dpp_configure_regamma_lut = dpp1_cm_configure_regamma_lut,
522 .dpp_program_regamma_lutb_settings = dpp1_cm_program_regamma_lutb_settings,
523 .dpp_program_regamma_luta_settings = dpp1_cm_program_regamma_luta_settings,
524 .dpp_program_regamma_pwl = dpp1_cm_set_regamma_pwl,
525 .dpp_program_bias_and_scale = dpp1_program_bias_and_scale,
526 .dpp_set_degamma = dpp1_set_degamma,
527 .dpp_program_input_lut = dpp1_program_input_lut,
528 .dpp_program_degamma_pwl = dpp1_set_degamma_pwl,
529 .dpp_setup = dpp1_cnv_setup,
530 .dpp_full_bypass = dpp1_full_bypass,
531 .set_cursor_attributes = dpp1_set_cursor_attributes,
532 .set_cursor_position = dpp1_set_cursor_position,
533 .set_optional_cursor_attributes = dpp1_cnv_set_optional_cursor_attributes,
534 .dpp_dppclk_control = dpp1_dppclk_control,
535 .dpp_set_hdr_multiplier = dpp1_set_hdr_multiplier,
536 .dpp_program_blnd_lut = NULL,
537 .dpp_program_shaper_lut = NULL,
538 .dpp_program_3dlut = NULL
539};
540
541static struct dpp_caps dcn10_dpp_cap = {
542 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FIXED_FORMAT,
543 .dscl_calc_lb_num_partitions = dpp1_dscl_calc_lb_num_partitions,
544};
545
546
547
548
549
550void dpp1_construct(
551 struct dcn10_dpp *dpp,
552 struct dc_context *ctx,
553 uint32_t inst,
554 const struct dcn_dpp_registers *tf_regs,
555 const struct dcn_dpp_shift *tf_shift,
556 const struct dcn_dpp_mask *tf_mask)
557{
558 dpp->base.ctx = ctx;
559
560 dpp->base.inst = inst;
561 dpp->base.funcs = &dcn10_dpp_funcs;
562 dpp->base.caps = &dcn10_dpp_cap;
563
564 dpp->tf_regs = tf_regs;
565 dpp->tf_shift = tf_shift;
566 dpp->tf_mask = tf_mask;
567
568 dpp->lb_pixel_depth_supported =
569 LB_PIXEL_DEPTH_18BPP |
570 LB_PIXEL_DEPTH_24BPP |
571 LB_PIXEL_DEPTH_30BPP |
572 LB_PIXEL_DEPTH_36BPP;
573
574 dpp->lb_bits_per_entry = LB_BITS_PER_ENTRY;
575 dpp->lb_memory_size = LB_TOTAL_NUMBER_OF_ENTRIES;
576}
577
