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27#include <linux/slab.h>
28
29#include "dm_services.h"
30#include "dc.h"
31
32#include "dcn21_init.h"
33
34#include "resource.h"
35#include "include/irq_service_interface.h"
36#include "dcn20/dcn20_resource.h"
37
38#include "dml/dcn2x/dcn2x.h"
39
40#include "clk_mgr.h"
41#include "dcn10/dcn10_hubp.h"
42#include "dcn10/dcn10_ipp.h"
43#include "dcn20/dcn20_hubbub.h"
44#include "dcn20/dcn20_mpc.h"
45#include "dcn20/dcn20_hubp.h"
46#include "dcn21_hubp.h"
47#include "irq/dcn21/irq_service_dcn21.h"
48#include "dcn20/dcn20_dpp.h"
49#include "dcn20/dcn20_optc.h"
50#include "dcn21/dcn21_hwseq.h"
51#include "dce110/dce110_hw_sequencer.h"
52#include "dcn20/dcn20_opp.h"
53#include "dcn20/dcn20_dsc.h"
54#include "dcn21/dcn21_link_encoder.h"
55#include "dcn20/dcn20_stream_encoder.h"
56#include "dce/dce_clock_source.h"
57#include "dce/dce_audio.h"
58#include "dce/dce_hwseq.h"
59#include "virtual/virtual_stream_encoder.h"
60#include "dml/display_mode_vba.h"
61#include "dcn20/dcn20_dccg.h"
62#include "dcn21/dcn21_dccg.h"
63#include "dcn21_hubbub.h"
64#include "dcn10/dcn10_resource.h"
65#include "dce/dce_panel_cntl.h"
66
67#include "dcn20/dcn20_dwb.h"
68#include "dcn20/dcn20_mmhubbub.h"
69#include "dpcs/dpcs_2_1_0_offset.h"
70#include "dpcs/dpcs_2_1_0_sh_mask.h"
71
72#include "renoir_ip_offset.h"
73#include "dcn/dcn_2_1_0_offset.h"
74#include "dcn/dcn_2_1_0_sh_mask.h"
75
76#include "nbio/nbio_7_0_offset.h"
77
78#include "mmhub/mmhub_2_0_0_offset.h"
79#include "mmhub/mmhub_2_0_0_sh_mask.h"
80
81#include "reg_helper.h"
82#include "dce/dce_abm.h"
83#include "dce/dce_dmcu.h"
84#include "dce/dce_aux.h"
85#include "dce/dce_i2c.h"
86#include "dcn21_resource.h"
87#include "vm_helper.h"
88#include "dcn20/dcn20_vmid.h"
89#include "dce/dmub_psr.h"
90#include "dce/dmub_abm.h"
91
92#define DC_LOGGER_INIT(logger)
93
94
95struct _vcs_dpi_ip_params_st dcn2_1_ip = {
96 .odm_capable = 1,
97 .gpuvm_enable = 1,
98 .hostvm_enable = 1,
99 .gpuvm_max_page_table_levels = 1,
100 .hostvm_max_page_table_levels = 4,
101 .hostvm_cached_page_table_levels = 2,
102 .num_dsc = 3,
103 .rob_buffer_size_kbytes = 168,
104 .det_buffer_size_kbytes = 164,
105 .dpte_buffer_size_in_pte_reqs_luma = 44,
106 .dpte_buffer_size_in_pte_reqs_chroma = 42,
107 .dpp_output_buffer_pixels = 2560,
108 .opp_output_buffer_lines = 1,
109 .pixel_chunk_size_kbytes = 8,
110 .pte_enable = 1,
111 .max_page_table_levels = 4,
112 .pte_chunk_size_kbytes = 2,
113 .meta_chunk_size_kbytes = 2,
114 .min_meta_chunk_size_bytes = 256,
115 .writeback_chunk_size_kbytes = 2,
116 .line_buffer_size_bits = 789504,
117 .is_line_buffer_bpp_fixed = 0,
118 .line_buffer_fixed_bpp = 0,
119 .dcc_supported = true,
120 .max_line_buffer_lines = 12,
121 .writeback_luma_buffer_size_kbytes = 12,
122 .writeback_chroma_buffer_size_kbytes = 8,
123 .writeback_chroma_line_buffer_width_pixels = 4,
124 .writeback_max_hscl_ratio = 1,
125 .writeback_max_vscl_ratio = 1,
126 .writeback_min_hscl_ratio = 1,
127 .writeback_min_vscl_ratio = 1,
128 .writeback_max_hscl_taps = 12,
129 .writeback_max_vscl_taps = 12,
130 .writeback_line_buffer_luma_buffer_size = 0,
131 .writeback_line_buffer_chroma_buffer_size = 14643,
132 .cursor_buffer_size = 8,
133 .cursor_chunk_size = 2,
134 .max_num_otg = 4,
135 .max_num_dpp = 4,
136 .max_num_wb = 1,
137 .max_dchub_pscl_bw_pix_per_clk = 4,
138 .max_pscl_lb_bw_pix_per_clk = 2,
139 .max_lb_vscl_bw_pix_per_clk = 4,
140 .max_vscl_hscl_bw_pix_per_clk = 4,
141 .max_hscl_ratio = 4,
142 .max_vscl_ratio = 4,
143 .hscl_mults = 4,
144 .vscl_mults = 4,
145 .max_hscl_taps = 8,
146 .max_vscl_taps = 8,
147 .dispclk_ramp_margin_percent = 1,
148 .underscan_factor = 1.10,
149 .min_vblank_lines = 32,
150 .dppclk_delay_subtotal = 77,
151 .dppclk_delay_scl_lb_only = 16,
152 .dppclk_delay_scl = 50,
153 .dppclk_delay_cnvc_formatter = 8,
154 .dppclk_delay_cnvc_cursor = 6,
155 .dispclk_delay_subtotal = 87,
156 .dcfclk_cstate_latency = 10,
157 .max_inter_dcn_tile_repeaters = 8,
158
159 .xfc_supported = false,
160 .xfc_fill_bw_overhead_percent = 10.0,
161 .xfc_fill_constant_bytes = 0,
162 .ptoi_supported = 0,
163 .number_of_cursors = 1,
164};
165
166struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
167 .clock_limits = {
168 {
169 .state = 0,
170 .dcfclk_mhz = 400.0,
171 .fabricclk_mhz = 400.0,
172 .dispclk_mhz = 600.0,
173 .dppclk_mhz = 400.00,
174 .phyclk_mhz = 600.0,
175 .socclk_mhz = 278.0,
176 .dscclk_mhz = 205.67,
177 .dram_speed_mts = 1600.0,
178 },
179 {
180 .state = 1,
181 .dcfclk_mhz = 464.52,
182 .fabricclk_mhz = 800.0,
183 .dispclk_mhz = 654.55,
184 .dppclk_mhz = 626.09,
185 .phyclk_mhz = 600.0,
186 .socclk_mhz = 278.0,
187 .dscclk_mhz = 205.67,
188 .dram_speed_mts = 1600.0,
189 },
190 {
191 .state = 2,
192 .dcfclk_mhz = 514.29,
193 .fabricclk_mhz = 933.0,
194 .dispclk_mhz = 757.89,
195 .dppclk_mhz = 685.71,
196 .phyclk_mhz = 600.0,
197 .socclk_mhz = 278.0,
198 .dscclk_mhz = 287.67,
199 .dram_speed_mts = 1866.0,
200 },
201 {
202 .state = 3,
203 .dcfclk_mhz = 576.00,
204 .fabricclk_mhz = 1067.0,
205 .dispclk_mhz = 847.06,
206 .dppclk_mhz = 757.89,
207 .phyclk_mhz = 600.0,
208 .socclk_mhz = 715.0,
209 .dscclk_mhz = 318.334,
210 .dram_speed_mts = 2134.0,
211 },
212 {
213 .state = 4,
214 .dcfclk_mhz = 626.09,
215 .fabricclk_mhz = 1200.0,
216 .dispclk_mhz = 900.00,
217 .dppclk_mhz = 847.06,
218 .phyclk_mhz = 810.0,
219 .socclk_mhz = 953.0,
220 .dscclk_mhz = 489.0,
221 .dram_speed_mts = 2400.0,
222 },
223 {
224 .state = 5,
225 .dcfclk_mhz = 685.71,
226 .fabricclk_mhz = 1333.0,
227 .dispclk_mhz = 1028.57,
228 .dppclk_mhz = 960.00,
229 .phyclk_mhz = 810.0,
230 .socclk_mhz = 278.0,
231 .dscclk_mhz = 287.67,
232 .dram_speed_mts = 2666.0,
233 },
234 {
235 .state = 6,
236 .dcfclk_mhz = 757.89,
237 .fabricclk_mhz = 1467.0,
238 .dispclk_mhz = 1107.69,
239 .dppclk_mhz = 1028.57,
240 .phyclk_mhz = 810.0,
241 .socclk_mhz = 715.0,
242 .dscclk_mhz = 318.334,
243 .dram_speed_mts = 3200.0,
244 },
245 {
246 .state = 7,
247 .dcfclk_mhz = 847.06,
248 .fabricclk_mhz = 1600.0,
249 .dispclk_mhz = 1395.0,
250 .dppclk_mhz = 1285.00,
251 .phyclk_mhz = 1325.0,
252 .socclk_mhz = 953.0,
253 .dscclk_mhz = 489.0,
254 .dram_speed_mts = 4266.0,
255 },
256
257 {
258 .state = 8,
259 .dcfclk_mhz = 847.06,
260 .fabricclk_mhz = 1600.0,
261 .dispclk_mhz = 1395.0,
262 .dppclk_mhz = 1285.0,
263 .phyclk_mhz = 1325.0,
264 .socclk_mhz = 953.0,
265 .dscclk_mhz = 489.0,
266 .dram_speed_mts = 4266.0,
267 },
268
269 },
270
271 .sr_exit_time_us = 12.5,
272 .sr_enter_plus_exit_time_us = 17.0,
273 .urgent_latency_us = 4.0,
274 .urgent_latency_pixel_data_only_us = 4.0,
275 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
276 .urgent_latency_vm_data_only_us = 4.0,
277 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
278 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
279 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
280 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
281 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
282 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
283 .max_avg_sdp_bw_use_normal_percent = 60.0,
284 .max_avg_dram_bw_use_normal_percent = 100.0,
285 .writeback_latency_us = 12.0,
286 .max_request_size_bytes = 256,
287 .dram_channel_width_bytes = 4,
288 .fabric_datapath_to_dcn_data_return_bytes = 32,
289 .dcn_downspread_percent = 0.5,
290 .downspread_percent = 0.38,
291 .dram_page_open_time_ns = 50.0,
292 .dram_rw_turnaround_time_ns = 17.5,
293 .dram_return_buffer_per_channel_bytes = 8192,
294 .round_trip_ping_latency_dcfclk_cycles = 128,
295 .urgent_out_of_order_return_per_channel_bytes = 4096,
296 .channel_interleave_bytes = 256,
297 .num_banks = 8,
298 .num_chans = 4,
299 .vmm_page_size_bytes = 4096,
300 .dram_clock_change_latency_us = 23.84,
301 .return_bus_width_bytes = 64,
302 .dispclk_dppclk_vco_speed_mhz = 3600,
303 .xfc_bus_transport_time_us = 4,
304 .xfc_xbuf_latency_tolerance_us = 4,
305 .use_urgent_burst_bw = 1,
306 .num_states = 8
307};
308
309#ifndef MAX
310#define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
311#endif
312#ifndef MIN
313#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
314#endif
315
316
317
318
319
320
321#undef BASE_INNER
322#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
323
324#define BASE(seg) BASE_INNER(seg)
325
326#define SR(reg_name)\
327 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
328 mm ## reg_name
329
330#define SRI(reg_name, block, id)\
331 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
332 mm ## block ## id ## _ ## reg_name
333
334#define SRIR(var_name, reg_name, block, id)\
335 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
336 mm ## block ## id ## _ ## reg_name
337
338#define SRII(reg_name, block, id)\
339 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
340 mm ## block ## id ## _ ## reg_name
341
342#define DCCG_SRII(reg_name, block, id)\
343 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
344 mm ## block ## id ## _ ## reg_name
345
346#define VUPDATE_SRII(reg_name, block, id)\
347 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
348 mm ## reg_name ## _ ## block ## id
349
350
351#define NBIO_BASE_INNER(seg) \
352 NBIF0_BASE__INST0_SEG ## seg
353
354#define NBIO_BASE(seg) \
355 NBIO_BASE_INNER(seg)
356
357#define NBIO_SR(reg_name)\
358 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
359 mm ## reg_name
360
361
362#define MMHUB_BASE_INNER(seg) \
363 MMHUB_BASE__INST0_SEG ## seg
364
365#define MMHUB_BASE(seg) \
366 MMHUB_BASE_INNER(seg)
367
368#define MMHUB_SR(reg_name)\
369 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
370 mmMM ## reg_name
371
372#define clk_src_regs(index, pllid)\
373[index] = {\
374 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
375}
376
377static const struct dce110_clk_src_regs clk_src_regs[] = {
378 clk_src_regs(0, A),
379 clk_src_regs(1, B),
380 clk_src_regs(2, C),
381 clk_src_regs(3, D),
382 clk_src_regs(4, E),
383};
384
385static const struct dce110_clk_src_shift cs_shift = {
386 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
387};
388
389static const struct dce110_clk_src_mask cs_mask = {
390 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
391};
392
393static const struct bios_registers bios_regs = {
394 NBIO_SR(BIOS_SCRATCH_3),
395 NBIO_SR(BIOS_SCRATCH_6)
396};
397
398static const struct dce_dmcu_registers dmcu_regs = {
399 DMCU_DCN20_REG_LIST()
400};
401
402static const struct dce_dmcu_shift dmcu_shift = {
403 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
404};
405
406static const struct dce_dmcu_mask dmcu_mask = {
407 DMCU_MASK_SH_LIST_DCN10(_MASK)
408};
409
410static const struct dce_abm_registers abm_regs = {
411 ABM_DCN20_REG_LIST()
412};
413
414static const struct dce_abm_shift abm_shift = {
415 ABM_MASK_SH_LIST_DCN20(__SHIFT)
416};
417
418static const struct dce_abm_mask abm_mask = {
419 ABM_MASK_SH_LIST_DCN20(_MASK)
420};
421
422#define audio_regs(id)\
423[id] = {\
424 AUD_COMMON_REG_LIST(id)\
425}
426
427static const struct dce_audio_registers audio_regs[] = {
428 audio_regs(0),
429 audio_regs(1),
430 audio_regs(2),
431 audio_regs(3),
432 audio_regs(4),
433 audio_regs(5),
434};
435
436#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
437 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
438 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
439 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
440
441static const struct dce_audio_shift audio_shift = {
442 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
443};
444
445static const struct dce_audio_mask audio_mask = {
446 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
447};
448
449static const struct dccg_registers dccg_regs = {
450 DCCG_COMMON_REG_LIST_DCN_BASE()
451};
452
453static const struct dccg_shift dccg_shift = {
454 DCCG_MASK_SH_LIST_DCN2_1(__SHIFT)
455};
456
457static const struct dccg_mask dccg_mask = {
458 DCCG_MASK_SH_LIST_DCN2_1(_MASK)
459};
460
461#define opp_regs(id)\
462[id] = {\
463 OPP_REG_LIST_DCN20(id),\
464}
465
466static const struct dcn20_opp_registers opp_regs[] = {
467 opp_regs(0),
468 opp_regs(1),
469 opp_regs(2),
470 opp_regs(3),
471 opp_regs(4),
472 opp_regs(5),
473};
474
475static const struct dcn20_opp_shift opp_shift = {
476 OPP_MASK_SH_LIST_DCN20(__SHIFT)
477};
478
479static const struct dcn20_opp_mask opp_mask = {
480 OPP_MASK_SH_LIST_DCN20(_MASK)
481};
482
483#define tg_regs(id)\
484[id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
485
486static const struct dcn_optc_registers tg_regs[] = {
487 tg_regs(0),
488 tg_regs(1),
489 tg_regs(2),
490 tg_regs(3)
491};
492
493static const struct dcn_optc_shift tg_shift = {
494 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
495};
496
497static const struct dcn_optc_mask tg_mask = {
498 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
499};
500
501static const struct dcn20_mpc_registers mpc_regs = {
502 MPC_REG_LIST_DCN2_0(0),
503 MPC_REG_LIST_DCN2_0(1),
504 MPC_REG_LIST_DCN2_0(2),
505 MPC_REG_LIST_DCN2_0(3),
506 MPC_REG_LIST_DCN2_0(4),
507 MPC_REG_LIST_DCN2_0(5),
508 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
509 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
510 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
511 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
512 MPC_DBG_REG_LIST_DCN2_0()
513};
514
515static const struct dcn20_mpc_shift mpc_shift = {
516 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
517 MPC_DEBUG_REG_LIST_SH_DCN20
518};
519
520static const struct dcn20_mpc_mask mpc_mask = {
521 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
522 MPC_DEBUG_REG_LIST_MASK_DCN20
523};
524
525#define hubp_regs(id)\
526[id] = {\
527 HUBP_REG_LIST_DCN21(id)\
528}
529
530static const struct dcn_hubp2_registers hubp_regs[] = {
531 hubp_regs(0),
532 hubp_regs(1),
533 hubp_regs(2),
534 hubp_regs(3)
535};
536
537static const struct dcn_hubp2_shift hubp_shift = {
538 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
539};
540
541static const struct dcn_hubp2_mask hubp_mask = {
542 HUBP_MASK_SH_LIST_DCN21(_MASK)
543};
544
545static const struct dcn_hubbub_registers hubbub_reg = {
546 HUBBUB_REG_LIST_DCN21()
547};
548
549static const struct dcn_hubbub_shift hubbub_shift = {
550 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
551};
552
553static const struct dcn_hubbub_mask hubbub_mask = {
554 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
555};
556
557
558#define vmid_regs(id)\
559[id] = {\
560 DCN20_VMID_REG_LIST(id)\
561}
562
563static const struct dcn_vmid_registers vmid_regs[] = {
564 vmid_regs(0),
565 vmid_regs(1),
566 vmid_regs(2),
567 vmid_regs(3),
568 vmid_regs(4),
569 vmid_regs(5),
570 vmid_regs(6),
571 vmid_regs(7),
572 vmid_regs(8),
573 vmid_regs(9),
574 vmid_regs(10),
575 vmid_regs(11),
576 vmid_regs(12),
577 vmid_regs(13),
578 vmid_regs(14),
579 vmid_regs(15)
580};
581
582static const struct dcn20_vmid_shift vmid_shifts = {
583 DCN20_VMID_MASK_SH_LIST(__SHIFT)
584};
585
586static const struct dcn20_vmid_mask vmid_masks = {
587 DCN20_VMID_MASK_SH_LIST(_MASK)
588};
589
590#define dsc_regsDCN20(id)\
591[id] = {\
592 DSC_REG_LIST_DCN20(id)\
593}
594
595static const struct dcn20_dsc_registers dsc_regs[] = {
596 dsc_regsDCN20(0),
597 dsc_regsDCN20(1),
598 dsc_regsDCN20(2),
599 dsc_regsDCN20(3),
600 dsc_regsDCN20(4),
601 dsc_regsDCN20(5)
602};
603
604static const struct dcn20_dsc_shift dsc_shift = {
605 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
606};
607
608static const struct dcn20_dsc_mask dsc_mask = {
609 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
610};
611
612#define ipp_regs(id)\
613[id] = {\
614 IPP_REG_LIST_DCN20(id),\
615}
616
617static const struct dcn10_ipp_registers ipp_regs[] = {
618 ipp_regs(0),
619 ipp_regs(1),
620 ipp_regs(2),
621 ipp_regs(3),
622};
623
624static const struct dcn10_ipp_shift ipp_shift = {
625 IPP_MASK_SH_LIST_DCN20(__SHIFT)
626};
627
628static const struct dcn10_ipp_mask ipp_mask = {
629 IPP_MASK_SH_LIST_DCN20(_MASK),
630};
631
632#define opp_regs(id)\
633[id] = {\
634 OPP_REG_LIST_DCN20(id),\
635}
636
637
638#define aux_engine_regs(id)\
639[id] = {\
640 AUX_COMMON_REG_LIST0(id), \
641 .AUXN_IMPCAL = 0, \
642 .AUXP_IMPCAL = 0, \
643 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
644}
645
646static const struct dce110_aux_registers aux_engine_regs[] = {
647 aux_engine_regs(0),
648 aux_engine_regs(1),
649 aux_engine_regs(2),
650 aux_engine_regs(3),
651 aux_engine_regs(4),
652};
653
654#define tf_regs(id)\
655[id] = {\
656 TF_REG_LIST_DCN20(id),\
657 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
658}
659
660static const struct dcn2_dpp_registers tf_regs[] = {
661 tf_regs(0),
662 tf_regs(1),
663 tf_regs(2),
664 tf_regs(3),
665};
666
667static const struct dcn2_dpp_shift tf_shift = {
668 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
669 TF_DEBUG_REG_LIST_SH_DCN20
670};
671
672static const struct dcn2_dpp_mask tf_mask = {
673 TF_REG_LIST_SH_MASK_DCN20(_MASK),
674 TF_DEBUG_REG_LIST_MASK_DCN20
675};
676
677#define stream_enc_regs(id)\
678[id] = {\
679 SE_DCN2_REG_LIST(id)\
680}
681
682static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
683 stream_enc_regs(0),
684 stream_enc_regs(1),
685 stream_enc_regs(2),
686 stream_enc_regs(3),
687 stream_enc_regs(4),
688};
689
690static const struct dce110_aux_registers_shift aux_shift = {
691 DCN_AUX_MASK_SH_LIST(__SHIFT)
692};
693
694static const struct dce110_aux_registers_mask aux_mask = {
695 DCN_AUX_MASK_SH_LIST(_MASK)
696};
697
698static const struct dcn10_stream_encoder_shift se_shift = {
699 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
700};
701
702static const struct dcn10_stream_encoder_mask se_mask = {
703 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
704};
705
706static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
707
708static int dcn21_populate_dml_pipes_from_context(
709 struct dc *dc,
710 struct dc_state *context,
711 display_e2e_pipe_params_st *pipes,
712 bool fast_validate);
713
714static struct input_pixel_processor *dcn21_ipp_create(
715 struct dc_context *ctx, uint32_t inst)
716{
717 struct dcn10_ipp *ipp =
718 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
719
720 if (!ipp) {
721 BREAK_TO_DEBUGGER();
722 return NULL;
723 }
724
725 dcn20_ipp_construct(ipp, ctx, inst,
726 &ipp_regs[inst], &ipp_shift, &ipp_mask);
727 return &ipp->base;
728}
729
730static struct dpp *dcn21_dpp_create(
731 struct dc_context *ctx,
732 uint32_t inst)
733{
734 struct dcn20_dpp *dpp =
735 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
736
737 if (!dpp)
738 return NULL;
739
740 if (dpp2_construct(dpp, ctx, inst,
741 &tf_regs[inst], &tf_shift, &tf_mask))
742 return &dpp->base;
743
744 BREAK_TO_DEBUGGER();
745 kfree(dpp);
746 return NULL;
747}
748
749static struct dce_aux *dcn21_aux_engine_create(
750 struct dc_context *ctx,
751 uint32_t inst)
752{
753 struct aux_engine_dce110 *aux_engine =
754 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
755
756 if (!aux_engine)
757 return NULL;
758
759 dce110_aux_engine_construct(aux_engine, ctx, inst,
760 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
761 &aux_engine_regs[inst],
762 &aux_mask,
763 &aux_shift,
764 ctx->dc->caps.extended_aux_timeout_support);
765
766 return &aux_engine->base;
767}
768
769#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
770
771static const struct dce_i2c_registers i2c_hw_regs[] = {
772 i2c_inst_regs(1),
773 i2c_inst_regs(2),
774 i2c_inst_regs(3),
775 i2c_inst_regs(4),
776 i2c_inst_regs(5),
777};
778
779static const struct dce_i2c_shift i2c_shifts = {
780 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
781};
782
783static const struct dce_i2c_mask i2c_masks = {
784 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
785};
786
787struct dce_i2c_hw *dcn21_i2c_hw_create(
788 struct dc_context *ctx,
789 uint32_t inst)
790{
791 struct dce_i2c_hw *dce_i2c_hw =
792 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
793
794 if (!dce_i2c_hw)
795 return NULL;
796
797 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
798 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
799
800 return dce_i2c_hw;
801}
802
803static const struct resource_caps res_cap_rn = {
804 .num_timing_generator = 4,
805 .num_opp = 4,
806 .num_video_plane = 4,
807 .num_audio = 4,
808 .num_stream_encoder = 5,
809 .num_pll = 5,
810 .num_dwb = 1,
811 .num_ddc = 5,
812 .num_vmid = 16,
813 .num_dsc = 3,
814};
815
816#ifdef DIAGS_BUILD
817static const struct resource_caps res_cap_rn_FPGA_4pipe = {
818 .num_timing_generator = 4,
819 .num_opp = 4,
820 .num_video_plane = 4,
821 .num_audio = 7,
822 .num_stream_encoder = 4,
823 .num_pll = 4,
824 .num_dwb = 1,
825 .num_ddc = 4,
826 .num_dsc = 0,
827};
828
829static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
830 .num_timing_generator = 2,
831 .num_opp = 2,
832 .num_video_plane = 2,
833 .num_audio = 7,
834 .num_stream_encoder = 2,
835 .num_pll = 4,
836 .num_dwb = 1,
837 .num_ddc = 4,
838 .num_dsc = 2,
839};
840#endif
841
842static const struct dc_plane_cap plane_cap = {
843 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
844 .blends_with_above = true,
845 .blends_with_below = true,
846 .per_pixel_alpha = true,
847
848 .pixel_format_support = {
849 .argb8888 = true,
850 .nv12 = true,
851 .fp16 = true,
852 .p010 = true
853 },
854
855 .max_upscale_factor = {
856 .argb8888 = 16000,
857 .nv12 = 16000,
858 .fp16 = 16000
859 },
860
861 .max_downscale_factor = {
862 .argb8888 = 250,
863 .nv12 = 250,
864 .fp16 = 250
865 },
866 64,
867 64
868};
869
870static const struct dc_debug_options debug_defaults_drv = {
871 .disable_dmcu = false,
872 .force_abm_enable = false,
873 .timing_trace = false,
874 .clock_trace = true,
875 .disable_pplib_clock_request = true,
876 .min_disp_clk_khz = 100000,
877 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
878 .force_single_disp_pipe_split = false,
879 .disable_dcc = DCC_ENABLE,
880 .vsr_support = true,
881 .performance_trace = false,
882 .max_downscale_src_width = 4096,
883 .disable_pplib_wm_range = false,
884 .scl_reset_length10 = true,
885 .sanity_checks = true,
886 .disable_48mhz_pwrdwn = false,
887 .usbc_combo_phy_reset_wa = true,
888 .dmub_command_table = true,
889 .use_max_lb = true,
890 .optimize_edp_link_rate = true
891};
892
893static const struct dc_debug_options debug_defaults_diags = {
894 .disable_dmcu = false,
895 .force_abm_enable = false,
896 .timing_trace = true,
897 .clock_trace = true,
898 .disable_dpp_power_gate = true,
899 .disable_hubp_power_gate = true,
900 .disable_clock_gate = true,
901 .disable_pplib_clock_request = true,
902 .disable_pplib_wm_range = true,
903 .disable_stutter = true,
904 .disable_48mhz_pwrdwn = true,
905 .disable_psr = true,
906 .enable_tri_buf = true,
907 .use_max_lb = true
908};
909
910enum dcn20_clk_src_array_id {
911 DCN20_CLK_SRC_PLL0,
912 DCN20_CLK_SRC_PLL1,
913 DCN20_CLK_SRC_PLL2,
914 DCN20_CLK_SRC_PLL3,
915 DCN20_CLK_SRC_PLL4,
916 DCN20_CLK_SRC_TOTAL_DCN21
917};
918
919static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
920{
921 unsigned int i;
922
923 for (i = 0; i < pool->base.stream_enc_count; i++) {
924 if (pool->base.stream_enc[i] != NULL) {
925 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
926 pool->base.stream_enc[i] = NULL;
927 }
928 }
929
930 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
931 if (pool->base.dscs[i] != NULL)
932 dcn20_dsc_destroy(&pool->base.dscs[i]);
933 }
934
935 if (pool->base.mpc != NULL) {
936 kfree(TO_DCN20_MPC(pool->base.mpc));
937 pool->base.mpc = NULL;
938 }
939 if (pool->base.hubbub != NULL) {
940 kfree(pool->base.hubbub);
941 pool->base.hubbub = NULL;
942 }
943 for (i = 0; i < pool->base.pipe_count; i++) {
944 if (pool->base.dpps[i] != NULL)
945 dcn20_dpp_destroy(&pool->base.dpps[i]);
946
947 if (pool->base.ipps[i] != NULL)
948 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
949
950 if (pool->base.hubps[i] != NULL) {
951 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
952 pool->base.hubps[i] = NULL;
953 }
954
955 if (pool->base.irqs != NULL) {
956 dal_irq_service_destroy(&pool->base.irqs);
957 }
958 }
959
960 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
961 if (pool->base.engines[i] != NULL)
962 dce110_engine_destroy(&pool->base.engines[i]);
963 if (pool->base.hw_i2cs[i] != NULL) {
964 kfree(pool->base.hw_i2cs[i]);
965 pool->base.hw_i2cs[i] = NULL;
966 }
967 if (pool->base.sw_i2cs[i] != NULL) {
968 kfree(pool->base.sw_i2cs[i]);
969 pool->base.sw_i2cs[i] = NULL;
970 }
971 }
972
973 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
974 if (pool->base.opps[i] != NULL)
975 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
976 }
977
978 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
979 if (pool->base.timing_generators[i] != NULL) {
980 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
981 pool->base.timing_generators[i] = NULL;
982 }
983 }
984
985 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
986 if (pool->base.dwbc[i] != NULL) {
987 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
988 pool->base.dwbc[i] = NULL;
989 }
990 if (pool->base.mcif_wb[i] != NULL) {
991 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
992 pool->base.mcif_wb[i] = NULL;
993 }
994 }
995
996 for (i = 0; i < pool->base.audio_count; i++) {
997 if (pool->base.audios[i])
998 dce_aud_destroy(&pool->base.audios[i]);
999 }
1000
1001 for (i = 0; i < pool->base.clk_src_count; i++) {
1002 if (pool->base.clock_sources[i] != NULL) {
1003 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1004 pool->base.clock_sources[i] = NULL;
1005 }
1006 }
1007
1008 if (pool->base.dp_clock_source != NULL) {
1009 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1010 pool->base.dp_clock_source = NULL;
1011 }
1012
1013 if (pool->base.abm != NULL) {
1014 if (pool->base.abm->ctx->dc->config.disable_dmcu)
1015 dmub_abm_destroy(&pool->base.abm);
1016 else
1017 dce_abm_destroy(&pool->base.abm);
1018 }
1019
1020 if (pool->base.dmcu != NULL)
1021 dce_dmcu_destroy(&pool->base.dmcu);
1022
1023 if (pool->base.psr != NULL)
1024 dmub_psr_destroy(&pool->base.psr);
1025
1026 if (pool->base.dccg != NULL)
1027 dcn_dccg_destroy(&pool->base.dccg);
1028
1029 if (pool->base.pp_smu != NULL)
1030 dcn21_pp_smu_destroy(&pool->base.pp_smu);
1031}
1032
1033
1034static void calculate_wm_set_for_vlevel(
1035 int vlevel,
1036 struct wm_range_table_entry *table_entry,
1037 struct dcn_watermarks *wm_set,
1038 struct display_mode_lib *dml,
1039 display_e2e_pipe_params_st *pipes,
1040 int pipe_cnt)
1041{
1042 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1043
1044 ASSERT(vlevel < dml->soc.num_states);
1045
1046 pipes[0].clks_cfg.voltage = vlevel;
1047 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1048 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1049
1050 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1051 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1052 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1053
1054 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1055 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1056 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1057 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1058 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1059 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1060 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1061 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1062 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1063
1064}
1065
1066static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1067{
1068 int i;
1069
1070 if (dc->bb_overrides.sr_exit_time_ns) {
1071 for (i = 0; i < WM_SET_COUNT; i++) {
1072 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1073 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1074 }
1075 }
1076
1077 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1078 for (i = 0; i < WM_SET_COUNT; i++) {
1079 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1080 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1081 }
1082 }
1083
1084 if (dc->bb_overrides.urgent_latency_ns) {
1085 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1086 }
1087
1088 if (dc->bb_overrides.dram_clock_change_latency_ns) {
1089 for (i = 0; i < WM_SET_COUNT; i++) {
1090 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1091 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1092 }
1093 }
1094}
1095
1096void dcn21_calculate_wm(
1097 struct dc *dc, struct dc_state *context,
1098 display_e2e_pipe_params_st *pipes,
1099 int *out_pipe_cnt,
1100 int *pipe_split_from,
1101 int vlevel_req,
1102 bool fast_validate)
1103{
1104 int pipe_cnt, i, pipe_idx;
1105 int vlevel, vlevel_max;
1106 struct wm_range_table_entry *table_entry;
1107 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1108
1109 ASSERT(bw_params);
1110
1111 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1112
1113 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1114 if (!context->res_ctx.pipe_ctx[i].stream)
1115 continue;
1116
1117 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1118 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1119
1120 if (pipe_split_from[i] < 0) {
1121 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1122 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1123 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1124 pipes[pipe_cnt].pipe.dest.odm_combine =
1125 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1126 else
1127 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1128 pipe_idx++;
1129 } else {
1130 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1131 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1132 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1133 pipes[pipe_cnt].pipe.dest.odm_combine =
1134 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1135 else
1136 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1137 }
1138 pipe_cnt++;
1139 }
1140
1141 if (pipe_cnt != pipe_idx) {
1142 if (dc->res_pool->funcs->populate_dml_pipes)
1143 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1144 context, pipes, fast_validate);
1145 else
1146 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1147 context, pipes, fast_validate);
1148 }
1149
1150 *out_pipe_cnt = pipe_cnt;
1151
1152 vlevel_max = bw_params->clk_table.num_entries - 1;
1153
1154
1155
1156 table_entry = &bw_params->wm_table.entries[WM_D];
1157 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1158 vlevel = 0;
1159 else
1160 vlevel = vlevel_max;
1161 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1162 &context->bw_ctx.dml, pipes, pipe_cnt);
1163
1164 table_entry = &bw_params->wm_table.entries[WM_C];
1165 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
1166 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1167 &context->bw_ctx.dml, pipes, pipe_cnt);
1168
1169 table_entry = &bw_params->wm_table.entries[WM_B];
1170 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1171 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1172 &context->bw_ctx.dml, pipes, pipe_cnt);
1173
1174
1175 table_entry = &bw_params->wm_table.entries[WM_A];
1176 vlevel = MIN(vlevel_req, vlevel_max);
1177 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1178 &context->bw_ctx.dml, pipes, pipe_cnt);
1179}
1180
1181
1182static bool dcn21_fast_validate_bw(
1183 struct dc *dc,
1184 struct dc_state *context,
1185 display_e2e_pipe_params_st *pipes,
1186 int *pipe_cnt_out,
1187 int *pipe_split_from,
1188 int *vlevel_out,
1189 bool fast_validate)
1190{
1191 bool out = false;
1192 int split[MAX_PIPES] = { 0 };
1193 int pipe_cnt, i, pipe_idx, vlevel;
1194
1195 ASSERT(pipes);
1196 if (!pipes)
1197 return false;
1198
1199 dcn20_merge_pipes_for_validate(dc, context);
1200
1201 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1202
1203 *pipe_cnt_out = pipe_cnt;
1204
1205 if (!pipe_cnt) {
1206 out = true;
1207 goto validate_out;
1208 }
1209
1210
1211
1212
1213
1214 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1215 dm_allow_self_refresh_and_mclk_switch;
1216 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1217
1218 if (vlevel > context->bw_ctx.dml.soc.num_states) {
1219
1220
1221
1222
1223
1224
1225
1226 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1227 dm_allow_self_refresh;
1228 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1229 if (vlevel > context->bw_ctx.dml.soc.num_states)
1230 goto validate_fail;
1231 }
1232
1233 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
1234
1235 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1236 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1237 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1238 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1239
1240 if (!pipe->stream)
1241 continue;
1242
1243
1244 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1245 && pipe->plane_state && mpo_pipe
1246 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1247 &pipe->plane_res.scl_data.recout,
1248 sizeof(struct rect)) != 0) {
1249 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1250 goto validate_fail;
1251 }
1252 pipe_idx++;
1253 }
1254
1255
1256 for (i = 0; i < MAX_PIPES; i++)
1257 pipe_split_from[i] = -1;
1258
1259 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1260 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1261 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1262
1263 if (!pipe->stream || pipe_split_from[i] >= 0)
1264 continue;
1265
1266 pipe_idx++;
1267
1268 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
1269 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
1270 ASSERT(hsplit_pipe);
1271 if (!dcn20_split_stream_for_odm(
1272 dc, &context->res_ctx,
1273 pipe, hsplit_pipe))
1274 goto validate_fail;
1275 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1276 dcn20_build_mapped_resource(dc, context, pipe->stream);
1277 }
1278
1279 if (!pipe->plane_state)
1280 continue;
1281
1282 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
1283 continue;
1284
1285 if (split[i] == 2) {
1286 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
1287
1288 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
1289 ASSERT(hsplit_pipe);
1290 if (!hsplit_pipe) {
1291 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
1292 continue;
1293 }
1294 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
1295 if (!dcn20_split_stream_for_odm(
1296 dc, &context->res_ctx,
1297 pipe, hsplit_pipe))
1298 goto validate_fail;
1299 dcn20_build_mapped_resource(dc, context, pipe->stream);
1300 } else {
1301 dcn20_split_stream_for_mpc(
1302 &context->res_ctx, dc->res_pool,
1303 pipe, hsplit_pipe);
1304 resource_build_scaling_params(pipe);
1305 resource_build_scaling_params(hsplit_pipe);
1306 }
1307 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1308 }
1309 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1310
1311 ASSERT(0);
1312 }
1313 }
1314
1315 if (!dcn20_validate_dsc(dc, context)) {
1316 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
1317 DML_FAIL_DSC_VALIDATION_FAILURE;
1318 goto validate_fail;
1319 }
1320
1321 *vlevel_out = vlevel;
1322
1323 out = true;
1324 goto validate_out;
1325
1326validate_fail:
1327 out = false;
1328
1329validate_out:
1330 return out;
1331}
1332
1333static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc,
1334 struct dc_state *context, bool fast_validate)
1335{
1336 bool out = false;
1337
1338 BW_VAL_TRACE_SETUP();
1339
1340 int vlevel = 0;
1341 int pipe_split_from[MAX_PIPES];
1342 int pipe_cnt = 0;
1343 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
1344 DC_LOGGER_INIT(dc->ctx->logger);
1345
1346 BW_VAL_TRACE_COUNT();
1347
1348
1349 ASSERT(context != dc->current_state);
1350
1351 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1352
1353 if (pipe_cnt == 0)
1354 goto validate_out;
1355
1356 if (!out)
1357 goto validate_fail;
1358
1359 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1360
1361 if (fast_validate) {
1362 BW_VAL_TRACE_SKIP(fast);
1363 goto validate_out;
1364 }
1365
1366 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1367 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1368
1369 BW_VAL_TRACE_END_WATERMARKS();
1370
1371 goto validate_out;
1372
1373validate_fail:
1374 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1375 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1376
1377 BW_VAL_TRACE_SKIP(fail);
1378 out = false;
1379
1380validate_out:
1381 kfree(pipes);
1382
1383 BW_VAL_TRACE_FINISH();
1384
1385 return out;
1386}
1387
1388
1389
1390
1391
1392
1393bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1394 bool fast_validate)
1395{
1396 bool voltage_supported;
1397 DC_FP_START();
1398 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate);
1399 DC_FP_END();
1400 return voltage_supported;
1401}
1402
1403static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1404{
1405 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1406
1407 dcn21_resource_destruct(dcn21_pool);
1408 kfree(dcn21_pool);
1409 *pool = NULL;
1410}
1411
1412static struct clock_source *dcn21_clock_source_create(
1413 struct dc_context *ctx,
1414 struct dc_bios *bios,
1415 enum clock_source_id id,
1416 const struct dce110_clk_src_regs *regs,
1417 bool dp_clk_src)
1418{
1419 struct dce110_clk_src *clk_src =
1420 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1421
1422 if (!clk_src)
1423 return NULL;
1424
1425 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1426 regs, &cs_shift, &cs_mask)) {
1427 clk_src->base.dp_clk_src = dp_clk_src;
1428 return &clk_src->base;
1429 }
1430
1431 BREAK_TO_DEBUGGER();
1432 return NULL;
1433}
1434
1435static struct hubp *dcn21_hubp_create(
1436 struct dc_context *ctx,
1437 uint32_t inst)
1438{
1439 struct dcn21_hubp *hubp21 =
1440 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1441
1442 if (!hubp21)
1443 return NULL;
1444
1445 if (hubp21_construct(hubp21, ctx, inst,
1446 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1447 return &hubp21->base;
1448
1449 BREAK_TO_DEBUGGER();
1450 kfree(hubp21);
1451 return NULL;
1452}
1453
1454static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1455{
1456 int i;
1457
1458 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1459 GFP_KERNEL);
1460
1461 if (!hubbub)
1462 return NULL;
1463
1464 hubbub21_construct(hubbub, ctx,
1465 &hubbub_reg,
1466 &hubbub_shift,
1467 &hubbub_mask);
1468
1469 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1470 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1471
1472 vmid->ctx = ctx;
1473
1474 vmid->regs = &vmid_regs[i];
1475 vmid->shifts = &vmid_shifts;
1476 vmid->masks = &vmid_masks;
1477 }
1478 hubbub->num_vmid = res_cap_rn.num_vmid;
1479
1480 return &hubbub->base;
1481}
1482
1483struct output_pixel_processor *dcn21_opp_create(
1484 struct dc_context *ctx, uint32_t inst)
1485{
1486 struct dcn20_opp *opp =
1487 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1488
1489 if (!opp) {
1490 BREAK_TO_DEBUGGER();
1491 return NULL;
1492 }
1493
1494 dcn20_opp_construct(opp, ctx, inst,
1495 &opp_regs[inst], &opp_shift, &opp_mask);
1496 return &opp->base;
1497}
1498
1499struct timing_generator *dcn21_timing_generator_create(
1500 struct dc_context *ctx,
1501 uint32_t instance)
1502{
1503 struct optc *tgn10 =
1504 kzalloc(sizeof(struct optc), GFP_KERNEL);
1505
1506 if (!tgn10)
1507 return NULL;
1508
1509 tgn10->base.inst = instance;
1510 tgn10->base.ctx = ctx;
1511
1512 tgn10->tg_regs = &tg_regs[instance];
1513 tgn10->tg_shift = &tg_shift;
1514 tgn10->tg_mask = &tg_mask;
1515
1516 dcn20_timing_generator_init(tgn10);
1517
1518 return &tgn10->base;
1519}
1520
1521struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1522{
1523 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1524 GFP_KERNEL);
1525
1526 if (!mpc20)
1527 return NULL;
1528
1529 dcn20_mpc_construct(mpc20, ctx,
1530 &mpc_regs,
1531 &mpc_shift,
1532 &mpc_mask,
1533 6);
1534
1535 return &mpc20->base;
1536}
1537
1538static void read_dce_straps(
1539 struct dc_context *ctx,
1540 struct resource_straps *straps)
1541{
1542 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1543 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1544
1545}
1546
1547
1548struct display_stream_compressor *dcn21_dsc_create(
1549 struct dc_context *ctx, uint32_t inst)
1550{
1551 struct dcn20_dsc *dsc =
1552 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1553
1554 if (!dsc) {
1555 BREAK_TO_DEBUGGER();
1556 return NULL;
1557 }
1558
1559 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1560 return &dsc->base;
1561}
1562
1563static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
1564{
1565 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
1566 int i;
1567
1568 low_pstate_lvl.state = 1;
1569 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1570 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1571 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
1572 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1573
1574 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
1575 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
1576 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
1577 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
1578 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
1579 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
1580 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
1581
1582 for (i = clk_table->num_entries; i > 1; i--)
1583 clk_table->entries[i] = clk_table->entries[i-1];
1584 clk_table->entries[1] = clk_table->entries[0];
1585 clk_table->num_entries++;
1586
1587 return low_pstate_lvl;
1588}
1589
1590static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1591{
1592 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1593 struct clk_limit_table *clk_table = &bw_params->clk_table;
1594 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1595 unsigned int i, closest_clk_lvl = 0, k = 0;
1596 int j;
1597
1598 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1599 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1600 dcn2_1_soc.num_chans = bw_params->num_channels;
1601
1602 ASSERT(clk_table->num_entries);
1603
1604 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
1605 clock_limits[i] = dcn2_1_soc.clock_limits[i];
1606 }
1607
1608 for (i = 0; i < clk_table->num_entries; i++) {
1609
1610 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
1611 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1612 closest_clk_lvl = j;
1613 break;
1614 }
1615 }
1616
1617
1618 if (i == 1)
1619 k++;
1620
1621 clock_limits[k].state = k;
1622 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1623 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1624 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1625 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1626
1627 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1628 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1629 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1630 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1631 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1632 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1633 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1634
1635 k++;
1636 }
1637 for (i = 0; i < clk_table->num_entries + 1; i++)
1638 dcn2_1_soc.clock_limits[i] = clock_limits[i];
1639 if (clk_table->num_entries) {
1640 dcn2_1_soc.num_states = clk_table->num_entries + 1;
1641
1642 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
1643
1644 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1645 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1646 }
1647
1648 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1649}
1650
1651static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1652{
1653 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1654
1655 if (!pp_smu)
1656 return pp_smu;
1657
1658 dm_pp_get_funcs(ctx, pp_smu);
1659
1660 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1661 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1662
1663
1664 return pp_smu;
1665}
1666
1667static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1668{
1669 if (pp_smu && *pp_smu) {
1670 kfree(*pp_smu);
1671 *pp_smu = NULL;
1672 }
1673}
1674
1675static struct audio *dcn21_create_audio(
1676 struct dc_context *ctx, unsigned int inst)
1677{
1678 return dce_audio_create(ctx, inst,
1679 &audio_regs[inst], &audio_shift, &audio_mask);
1680}
1681
1682static struct dc_cap_funcs cap_funcs = {
1683 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1684};
1685
1686struct stream_encoder *dcn21_stream_encoder_create(
1687 enum engine_id eng_id,
1688 struct dc_context *ctx)
1689{
1690 struct dcn10_stream_encoder *enc1 =
1691 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1692
1693 if (!enc1)
1694 return NULL;
1695
1696 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1697 &stream_enc_regs[eng_id],
1698 &se_shift, &se_mask);
1699
1700 return &enc1->base;
1701}
1702
1703static const struct dce_hwseq_registers hwseq_reg = {
1704 HWSEQ_DCN21_REG_LIST()
1705};
1706
1707static const struct dce_hwseq_shift hwseq_shift = {
1708 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1709};
1710
1711static const struct dce_hwseq_mask hwseq_mask = {
1712 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1713};
1714
1715static struct dce_hwseq *dcn21_hwseq_create(
1716 struct dc_context *ctx)
1717{
1718 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1719
1720 if (hws) {
1721 hws->ctx = ctx;
1722 hws->regs = &hwseq_reg;
1723 hws->shifts = &hwseq_shift;
1724 hws->masks = &hwseq_mask;
1725 hws->wa.DEGVIDCN21 = true;
1726 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1727 }
1728 return hws;
1729}
1730
1731static const struct resource_create_funcs res_create_funcs = {
1732 .read_dce_straps = read_dce_straps,
1733 .create_audio = dcn21_create_audio,
1734 .create_stream_encoder = dcn21_stream_encoder_create,
1735 .create_hwseq = dcn21_hwseq_create,
1736};
1737
1738static const struct resource_create_funcs res_create_maximus_funcs = {
1739 .read_dce_straps = NULL,
1740 .create_audio = NULL,
1741 .create_stream_encoder = NULL,
1742 .create_hwseq = dcn21_hwseq_create,
1743};
1744
1745static const struct encoder_feature_support link_enc_feature = {
1746 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1747 .max_hdmi_pixel_clock = 600000,
1748 .hdmi_ycbcr420_supported = true,
1749 .dp_ycbcr420_supported = true,
1750 .fec_supported = true,
1751 .flags.bits.IS_HBR2_CAPABLE = true,
1752 .flags.bits.IS_HBR3_CAPABLE = true,
1753 .flags.bits.IS_TPS3_CAPABLE = true,
1754 .flags.bits.IS_TPS4_CAPABLE = true
1755};
1756
1757
1758#define link_regs(id, phyid)\
1759[id] = {\
1760 LE_DCN2_REG_LIST(id), \
1761 UNIPHY_DCN2_REG_LIST(phyid), \
1762 DPCS_DCN21_REG_LIST(id), \
1763 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1764}
1765
1766static const struct dcn10_link_enc_registers link_enc_regs[] = {
1767 link_regs(0, A),
1768 link_regs(1, B),
1769 link_regs(2, C),
1770 link_regs(3, D),
1771 link_regs(4, E),
1772};
1773
1774static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1775 { DCN_PANEL_CNTL_REG_LIST() }
1776};
1777
1778static const struct dce_panel_cntl_shift panel_cntl_shift = {
1779 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1780};
1781
1782static const struct dce_panel_cntl_mask panel_cntl_mask = {
1783 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1784};
1785
1786#define aux_regs(id)\
1787[id] = {\
1788 DCN2_AUX_REG_LIST(id)\
1789}
1790
1791static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1792 aux_regs(0),
1793 aux_regs(1),
1794 aux_regs(2),
1795 aux_regs(3),
1796 aux_regs(4)
1797};
1798
1799#define hpd_regs(id)\
1800[id] = {\
1801 HPD_REG_LIST(id)\
1802}
1803
1804static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1805 hpd_regs(0),
1806 hpd_regs(1),
1807 hpd_regs(2),
1808 hpd_regs(3),
1809 hpd_regs(4)
1810};
1811
1812static const struct dcn10_link_enc_shift le_shift = {
1813 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1814 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1815};
1816
1817static const struct dcn10_link_enc_mask le_mask = {
1818 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1819 DPCS_DCN21_MASK_SH_LIST(_MASK)
1820};
1821
1822static int map_transmitter_id_to_phy_instance(
1823 enum transmitter transmitter)
1824{
1825 switch (transmitter) {
1826 case TRANSMITTER_UNIPHY_A:
1827 return 0;
1828 break;
1829 case TRANSMITTER_UNIPHY_B:
1830 return 1;
1831 break;
1832 case TRANSMITTER_UNIPHY_C:
1833 return 2;
1834 break;
1835 case TRANSMITTER_UNIPHY_D:
1836 return 3;
1837 break;
1838 case TRANSMITTER_UNIPHY_E:
1839 return 4;
1840 break;
1841 default:
1842 ASSERT(0);
1843 return 0;
1844 }
1845}
1846
1847static struct link_encoder *dcn21_link_encoder_create(
1848 const struct encoder_init_data *enc_init_data)
1849{
1850 struct dcn21_link_encoder *enc21 =
1851 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1852 int link_regs_id;
1853
1854 if (!enc21)
1855 return NULL;
1856
1857 link_regs_id =
1858 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1859
1860 dcn21_link_encoder_construct(enc21,
1861 enc_init_data,
1862 &link_enc_feature,
1863 &link_enc_regs[link_regs_id],
1864 &link_enc_aux_regs[enc_init_data->channel - 1],
1865 &link_enc_hpd_regs[enc_init_data->hpd_source],
1866 &le_shift,
1867 &le_mask);
1868
1869 return &enc21->enc10.base;
1870}
1871
1872static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1873{
1874 struct dce_panel_cntl *panel_cntl =
1875 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1876
1877 if (!panel_cntl)
1878 return NULL;
1879
1880 dce_panel_cntl_construct(panel_cntl,
1881 init_data,
1882 &panel_cntl_regs[init_data->inst],
1883 &panel_cntl_shift,
1884 &panel_cntl_mask);
1885
1886 return &panel_cntl->base;
1887}
1888
1889#define CTX ctx
1890
1891#define REG(reg_name) \
1892 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1893
1894static uint32_t read_pipe_fuses(struct dc_context *ctx)
1895{
1896 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1897
1898 value = value & 0xf;
1899 return value;
1900}
1901
1902static int dcn21_populate_dml_pipes_from_context(
1903 struct dc *dc,
1904 struct dc_state *context,
1905 display_e2e_pipe_params_st *pipes,
1906 bool fast_validate)
1907{
1908 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1909 int i;
1910
1911 for (i = 0; i < pipe_cnt; i++) {
1912
1913 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1914 pipes[i].pipe.src.gpuvm = 1;
1915 }
1916
1917 return pipe_cnt;
1918}
1919
1920enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1921{
1922 enum dc_status result = DC_OK;
1923
1924 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1925 plane_state->dcc.enable = 1;
1926
1927 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1928 }
1929 result = dcn20_patch_unknown_plane_state(plane_state);
1930 return result;
1931}
1932
1933static const struct resource_funcs dcn21_res_pool_funcs = {
1934 .destroy = dcn21_destroy_resource_pool,
1935 .link_enc_create = dcn21_link_encoder_create,
1936 .panel_cntl_create = dcn21_panel_cntl_create,
1937 .validate_bandwidth = dcn21_validate_bandwidth,
1938 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1939 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1940 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1941 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1942 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1943 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1944 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1945 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1946 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1947 .update_bw_bounding_box = update_bw_bounding_box
1948};
1949
1950static bool dcn21_resource_construct(
1951 uint8_t num_virtual_links,
1952 struct dc *dc,
1953 struct dcn21_resource_pool *pool)
1954{
1955 int i, j;
1956 struct dc_context *ctx = dc->ctx;
1957 struct irq_service_init_data init_data;
1958 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1959 uint32_t num_pipes;
1960
1961 ctx->dc_bios->regs = &bios_regs;
1962
1963 pool->base.res_cap = &res_cap_rn;
1964#ifdef DIAGS_BUILD
1965 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1966
1967 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1968#endif
1969
1970 pool->base.funcs = &dcn21_res_pool_funcs;
1971
1972
1973
1974
1975 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1976
1977
1978 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1979
1980 dc->caps.max_downscale_ratio = 200;
1981 dc->caps.i2c_speed_in_khz = 100;
1982 dc->caps.i2c_speed_in_khz_hdcp = 5;
1983 dc->caps.max_cursor_size = 256;
1984 dc->caps.min_horizontal_blanking_period = 80;
1985 dc->caps.dmdata_alloc_size = 2048;
1986
1987 dc->caps.max_slave_planes = 1;
1988 dc->caps.max_slave_yuv_planes = 1;
1989 dc->caps.max_slave_rgb_planes = 1;
1990 dc->caps.post_blend_color_processing = true;
1991 dc->caps.force_dp_tps4_for_cp2520 = true;
1992 dc->caps.extended_aux_timeout_support = true;
1993 dc->caps.dmcub_support = true;
1994 dc->caps.is_apu = true;
1995
1996
1997 dc->caps.color.dpp.dcn_arch = 1;
1998 dc->caps.color.dpp.input_lut_shared = 0;
1999 dc->caps.color.dpp.icsc = 1;
2000 dc->caps.color.dpp.dgam_ram = 1;
2001 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
2002 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
2003 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
2004 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
2005 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
2006 dc->caps.color.dpp.post_csc = 0;
2007 dc->caps.color.dpp.gamma_corr = 0;
2008 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
2009
2010 dc->caps.color.dpp.hw_3d_lut = 1;
2011 dc->caps.color.dpp.ogam_ram = 1;
2012
2013 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2014 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2015 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2016 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2017 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2018 dc->caps.color.dpp.ocsc = 0;
2019
2020 dc->caps.color.mpc.gamut_remap = 0;
2021 dc->caps.color.mpc.num_3dluts = 0;
2022 dc->caps.color.mpc.shared_3d_lut = 0;
2023 dc->caps.color.mpc.ogam_ram = 1;
2024 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2025 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2026 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2027 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2028 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2029 dc->caps.color.mpc.ocsc = 1;
2030
2031 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2032 dc->debug = debug_defaults_drv;
2033 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2034 pool->base.pipe_count = 4;
2035 dc->debug = debug_defaults_diags;
2036 } else
2037 dc->debug = debug_defaults_diags;
2038
2039
2040 if (dc->vm_helper)
2041 vm_helper_init(dc->vm_helper, 16);
2042
2043
2044
2045
2046
2047 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2048 dcn21_clock_source_create(ctx, ctx->dc_bios,
2049 CLOCK_SOURCE_COMBO_PHY_PLL0,
2050 &clk_src_regs[0], false);
2051 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2052 dcn21_clock_source_create(ctx, ctx->dc_bios,
2053 CLOCK_SOURCE_COMBO_PHY_PLL1,
2054 &clk_src_regs[1], false);
2055 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2056 dcn21_clock_source_create(ctx, ctx->dc_bios,
2057 CLOCK_SOURCE_COMBO_PHY_PLL2,
2058 &clk_src_regs[2], false);
2059 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2060 dcn21_clock_source_create(ctx, ctx->dc_bios,
2061 CLOCK_SOURCE_COMBO_PHY_PLL3,
2062 &clk_src_regs[3], false);
2063 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2064 dcn21_clock_source_create(ctx, ctx->dc_bios,
2065 CLOCK_SOURCE_COMBO_PHY_PLL4,
2066 &clk_src_regs[4], false);
2067
2068 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
2069
2070
2071 pool->base.dp_clock_source =
2072 dcn21_clock_source_create(ctx, ctx->dc_bios,
2073 CLOCK_SOURCE_ID_DP_DTO,
2074 &clk_src_regs[0], true);
2075
2076 for (i = 0; i < pool->base.clk_src_count; i++) {
2077 if (pool->base.clock_sources[i] == NULL) {
2078 dm_error("DC: failed to create clock sources!\n");
2079 BREAK_TO_DEBUGGER();
2080 goto create_fail;
2081 }
2082 }
2083
2084 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2085 if (pool->base.dccg == NULL) {
2086 dm_error("DC: failed to create dccg!\n");
2087 BREAK_TO_DEBUGGER();
2088 goto create_fail;
2089 }
2090
2091 if (!dc->config.disable_dmcu) {
2092 pool->base.dmcu = dcn21_dmcu_create(ctx,
2093 &dmcu_regs,
2094 &dmcu_shift,
2095 &dmcu_mask);
2096 if (pool->base.dmcu == NULL) {
2097 dm_error("DC: failed to create dmcu!\n");
2098 BREAK_TO_DEBUGGER();
2099 goto create_fail;
2100 }
2101
2102 dc->debug.dmub_command_table = false;
2103 }
2104
2105 if (dc->config.disable_dmcu) {
2106 pool->base.psr = dmub_psr_create(ctx);
2107
2108 if (pool->base.psr == NULL) {
2109 dm_error("DC: failed to create psr obj!\n");
2110 BREAK_TO_DEBUGGER();
2111 goto create_fail;
2112 }
2113 }
2114
2115 if (dc->config.disable_dmcu)
2116 pool->base.abm = dmub_abm_create(ctx,
2117 &abm_regs,
2118 &abm_shift,
2119 &abm_mask);
2120 else
2121 pool->base.abm = dce_abm_create(ctx,
2122 &abm_regs,
2123 &abm_shift,
2124 &abm_mask);
2125
2126 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
2127
2128 num_pipes = dcn2_1_ip.max_num_dpp;
2129
2130 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
2131 if (pipe_fuses & 1 << i)
2132 num_pipes--;
2133 dcn2_1_ip.max_num_dpp = num_pipes;
2134 dcn2_1_ip.max_num_otg = num_pipes;
2135
2136 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2137
2138 init_data.ctx = dc->ctx;
2139 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
2140 if (!pool->base.irqs)
2141 goto create_fail;
2142
2143 j = 0;
2144
2145 for (i = 0; i < pool->base.pipe_count; i++) {
2146
2147
2148
2149 if ((pipe_fuses & (1 << i)) != 0)
2150 continue;
2151
2152 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
2153 if (pool->base.hubps[j] == NULL) {
2154 BREAK_TO_DEBUGGER();
2155 dm_error(
2156 "DC: failed to create memory input!\n");
2157 goto create_fail;
2158 }
2159
2160 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
2161 if (pool->base.ipps[j] == NULL) {
2162 BREAK_TO_DEBUGGER();
2163 dm_error(
2164 "DC: failed to create input pixel processor!\n");
2165 goto create_fail;
2166 }
2167
2168 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
2169 if (pool->base.dpps[j] == NULL) {
2170 BREAK_TO_DEBUGGER();
2171 dm_error(
2172 "DC: failed to create dpps!\n");
2173 goto create_fail;
2174 }
2175
2176 pool->base.opps[j] = dcn21_opp_create(ctx, i);
2177 if (pool->base.opps[j] == NULL) {
2178 BREAK_TO_DEBUGGER();
2179 dm_error(
2180 "DC: failed to create output pixel processor!\n");
2181 goto create_fail;
2182 }
2183
2184 pool->base.timing_generators[j] = dcn21_timing_generator_create(
2185 ctx, i);
2186 if (pool->base.timing_generators[j] == NULL) {
2187 BREAK_TO_DEBUGGER();
2188 dm_error("DC: failed to create tg!\n");
2189 goto create_fail;
2190 }
2191 j++;
2192 }
2193
2194 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2195 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
2196 if (pool->base.engines[i] == NULL) {
2197 BREAK_TO_DEBUGGER();
2198 dm_error(
2199 "DC:failed to create aux engine!!\n");
2200 goto create_fail;
2201 }
2202 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
2203 if (pool->base.hw_i2cs[i] == NULL) {
2204 BREAK_TO_DEBUGGER();
2205 dm_error(
2206 "DC:failed to create hw i2c!!\n");
2207 goto create_fail;
2208 }
2209 pool->base.sw_i2cs[i] = NULL;
2210 }
2211
2212 pool->base.timing_generator_count = j;
2213 pool->base.pipe_count = j;
2214 pool->base.mpcc_count = j;
2215
2216 pool->base.mpc = dcn21_mpc_create(ctx);
2217 if (pool->base.mpc == NULL) {
2218 BREAK_TO_DEBUGGER();
2219 dm_error("DC: failed to create mpc!\n");
2220 goto create_fail;
2221 }
2222
2223 pool->base.hubbub = dcn21_hubbub_create(ctx);
2224 if (pool->base.hubbub == NULL) {
2225 BREAK_TO_DEBUGGER();
2226 dm_error("DC: failed to create hubbub!\n");
2227 goto create_fail;
2228 }
2229
2230 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2231 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
2232 if (pool->base.dscs[i] == NULL) {
2233 BREAK_TO_DEBUGGER();
2234 dm_error("DC: failed to create display stream compressor %d!\n", i);
2235 goto create_fail;
2236 }
2237 }
2238
2239 if (!dcn20_dwbc_create(ctx, &pool->base)) {
2240 BREAK_TO_DEBUGGER();
2241 dm_error("DC: failed to create dwbc!\n");
2242 goto create_fail;
2243 }
2244 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2245 BREAK_TO_DEBUGGER();
2246 dm_error("DC: failed to create mcif_wb!\n");
2247 goto create_fail;
2248 }
2249
2250 if (!resource_construct(num_virtual_links, dc, &pool->base,
2251 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2252 &res_create_funcs : &res_create_maximus_funcs)))
2253 goto create_fail;
2254
2255 dcn21_hw_sequencer_construct(dc);
2256
2257 dc->caps.max_planes = pool->base.pipe_count;
2258
2259 for (i = 0; i < dc->caps.max_planes; ++i)
2260 dc->caps.planes[i] = plane_cap;
2261
2262 dc->cap_funcs = cap_funcs;
2263
2264 return true;
2265
2266create_fail:
2267
2268 dcn21_resource_destruct(pool);
2269
2270 return false;
2271}
2272
2273struct resource_pool *dcn21_create_resource_pool(
2274 const struct dc_init_data *init_data,
2275 struct dc *dc)
2276{
2277 struct dcn21_resource_pool *pool =
2278 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2279
2280 if (!pool)
2281 return NULL;
2282
2283 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
2284 return &pool->base;
2285
2286 BREAK_TO_DEBUGGER();
2287 kfree(pool);
2288 return NULL;
2289}
2290