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27#include "dm_services.h"
28#include "dc.h"
29
30#include "dcn301_init.h"
31
32#include "resource.h"
33#include "include/irq_service_interface.h"
34#include "dcn30/dcn30_resource.h"
35#include "dcn301_resource.h"
36
37#include "dcn20/dcn20_resource.h"
38
39#include "dcn10/dcn10_ipp.h"
40#include "dcn301/dcn301_hubbub.h"
41#include "dcn30/dcn30_mpc.h"
42#include "dcn30/dcn30_hubp.h"
43#include "irq/dcn30/irq_service_dcn30.h"
44#include "dcn30/dcn30_dpp.h"
45#include "dcn30/dcn30_optc.h"
46#include "dcn20/dcn20_hwseq.h"
47#include "dcn30/dcn30_hwseq.h"
48#include "dce110/dce110_hw_sequencer.h"
49#include "dcn30/dcn30_opp.h"
50#include "dcn20/dcn20_dsc.h"
51#include "dcn30/dcn30_vpg.h"
52#include "dcn30/dcn30_afmt.h"
53#include "dce/dce_clock_source.h"
54#include "dce/dce_audio.h"
55#include "dce/dce_hwseq.h"
56#include "clk_mgr.h"
57#include "virtual/virtual_stream_encoder.h"
58#include "dce110/dce110_resource.h"
59#include "dml/display_mode_vba.h"
60#include "dcn301/dcn301_dccg.h"
61#include "dcn10/dcn10_resource.h"
62#include "dcn30/dcn30_dio_stream_encoder.h"
63#include "dcn301/dcn301_dio_link_encoder.h"
64#include "dcn301_panel_cntl.h"
65
66#include "vangogh_ip_offset.h"
67
68#include "dcn30/dcn30_dwb.h"
69#include "dcn30/dcn30_mmhubbub.h"
70
71#include "dcn/dcn_3_0_1_offset.h"
72#include "dcn/dcn_3_0_1_sh_mask.h"
73
74#include "nbio/nbio_7_2_0_offset.h"
75
76#include "dcn/dpcs_3_0_0_offset.h"
77#include "dcn/dpcs_3_0_0_sh_mask.h"
78
79#include "reg_helper.h"
80#include "dce/dmub_abm.h"
81#include "dce/dce_aux.h"
82#include "dce/dce_i2c.h"
83
84#include "dml/dcn30/display_mode_vba_30.h"
85#include "vm_helper.h"
86#include "dcn20/dcn20_vmid.h"
87#include "amdgpu_socbb.h"
88
89#define TO_DCN301_RES_POOL(pool)\
90 container_of(pool, struct dcn301_resource_pool, base)
91
92#define DC_LOGGER_INIT(logger)
93
94struct _vcs_dpi_ip_params_st dcn3_01_ip = {
95 .odm_capable = 1,
96 .gpuvm_enable = 1,
97 .hostvm_enable = 1,
98 .gpuvm_max_page_table_levels = 1,
99 .hostvm_max_page_table_levels = 2,
100 .hostvm_cached_page_table_levels = 0,
101 .pte_group_size_bytes = 2048,
102 .num_dsc = 3,
103 .rob_buffer_size_kbytes = 184,
104 .det_buffer_size_kbytes = 184,
105 .dpte_buffer_size_in_pte_reqs_luma = 64,
106 .dpte_buffer_size_in_pte_reqs_chroma = 32,
107 .pde_proc_buffer_size_64k_reqs = 48,
108 .dpp_output_buffer_pixels = 2560,
109 .opp_output_buffer_lines = 1,
110 .pixel_chunk_size_kbytes = 8,
111 .meta_chunk_size_kbytes = 2,
112 .writeback_chunk_size_kbytes = 8,
113 .line_buffer_size_bits = 789504,
114 .is_line_buffer_bpp_fixed = 0,
115 .line_buffer_fixed_bpp = 48,
116 .dcc_supported = true,
117 .writeback_interface_buffer_size_kbytes = 90,
118 .writeback_line_buffer_buffer_size = 656640,
119 .max_line_buffer_lines = 12,
120 .writeback_luma_buffer_size_kbytes = 12,
121 .writeback_chroma_buffer_size_kbytes = 8,
122 .writeback_chroma_line_buffer_width_pixels = 4,
123 .writeback_max_hscl_ratio = 1,
124 .writeback_max_vscl_ratio = 1,
125 .writeback_min_hscl_ratio = 1,
126 .writeback_min_vscl_ratio = 1,
127 .writeback_max_hscl_taps = 1,
128 .writeback_max_vscl_taps = 1,
129 .writeback_line_buffer_luma_buffer_size = 0,
130 .writeback_line_buffer_chroma_buffer_size = 14643,
131 .cursor_buffer_size = 8,
132 .cursor_chunk_size = 2,
133 .max_num_otg = 4,
134 .max_num_dpp = 4,
135 .max_num_wb = 1,
136 .max_dchub_pscl_bw_pix_per_clk = 4,
137 .max_pscl_lb_bw_pix_per_clk = 2,
138 .max_lb_vscl_bw_pix_per_clk = 4,
139 .max_vscl_hscl_bw_pix_per_clk = 4,
140 .max_hscl_ratio = 6,
141 .max_vscl_ratio = 6,
142 .hscl_mults = 4,
143 .vscl_mults = 4,
144 .max_hscl_taps = 8,
145 .max_vscl_taps = 8,
146 .dispclk_ramp_margin_percent = 1,
147 .underscan_factor = 1.11,
148 .min_vblank_lines = 32,
149 .dppclk_delay_subtotal = 46,
150 .dynamic_metadata_vm_enabled = true,
151 .dppclk_delay_scl_lb_only = 16,
152 .dppclk_delay_scl = 50,
153 .dppclk_delay_cnvc_formatter = 27,
154 .dppclk_delay_cnvc_cursor = 6,
155 .dispclk_delay_subtotal = 119,
156 .dcfclk_cstate_latency = 5.2,
157 .max_inter_dcn_tile_repeaters = 8,
158 .max_num_hdmi_frl_outputs = 0,
159 .odm_combine_4to1_supported = true,
160
161 .xfc_supported = false,
162 .xfc_fill_bw_overhead_percent = 10.0,
163 .xfc_fill_constant_bytes = 0,
164 .gfx7_compat_tiling_supported = 0,
165 .number_of_cursors = 1,
166};
167
168struct _vcs_dpi_soc_bounding_box_st dcn3_01_soc = {
169 .clock_limits = {
170 {
171 .state = 0,
172 .dram_speed_mts = 2400.0,
173 .fabricclk_mhz = 600,
174 .socclk_mhz = 278.0,
175 .dcfclk_mhz = 400.0,
176 .dscclk_mhz = 206.0,
177 .dppclk_mhz = 1015.0,
178 .dispclk_mhz = 1015.0,
179 .phyclk_mhz = 600.0,
180 },
181 {
182 .state = 1,
183 .dram_speed_mts = 2400.0,
184 .fabricclk_mhz = 688,
185 .socclk_mhz = 278.0,
186 .dcfclk_mhz = 400.0,
187 .dscclk_mhz = 206.0,
188 .dppclk_mhz = 1015.0,
189 .dispclk_mhz = 1015.0,
190 .phyclk_mhz = 600.0,
191 },
192 {
193 .state = 2,
194 .dram_speed_mts = 4267.0,
195 .fabricclk_mhz = 1067,
196 .socclk_mhz = 278.0,
197 .dcfclk_mhz = 608.0,
198 .dscclk_mhz = 296.0,
199 .dppclk_mhz = 1015.0,
200 .dispclk_mhz = 1015.0,
201 .phyclk_mhz = 810.0,
202 },
203
204 {
205 .state = 3,
206 .dram_speed_mts = 4267.0,
207 .fabricclk_mhz = 1067,
208 .socclk_mhz = 715.0,
209 .dcfclk_mhz = 676.0,
210 .dscclk_mhz = 338.0,
211 .dppclk_mhz = 1015.0,
212 .dispclk_mhz = 1015.0,
213 .phyclk_mhz = 810.0,
214 },
215
216 {
217 .state = 4,
218 .dram_speed_mts = 4267.0,
219 .fabricclk_mhz = 1067,
220 .socclk_mhz = 953.0,
221 .dcfclk_mhz = 810.0,
222 .dscclk_mhz = 338.0,
223 .dppclk_mhz = 1015.0,
224 .dispclk_mhz = 1015.0,
225 .phyclk_mhz = 810.0,
226 },
227 },
228
229 .sr_exit_time_us = 9.0,
230 .sr_enter_plus_exit_time_us = 11.0,
231 .urgent_latency_us = 4.0,
232 .urgent_latency_pixel_data_only_us = 4.0,
233 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
234 .urgent_latency_vm_data_only_us = 4.0,
235 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
236 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
237 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
238 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
239 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
240 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
241 .max_avg_sdp_bw_use_normal_percent = 60.0,
242 .max_avg_dram_bw_use_normal_percent = 60.0,
243 .writeback_latency_us = 12.0,
244 .max_request_size_bytes = 256,
245 .dram_channel_width_bytes = 4,
246 .fabric_datapath_to_dcn_data_return_bytes = 32,
247 .dcn_downspread_percent = 0.5,
248 .downspread_percent = 0.38,
249 .dram_page_open_time_ns = 50.0,
250 .dram_rw_turnaround_time_ns = 17.5,
251 .dram_return_buffer_per_channel_bytes = 8192,
252 .round_trip_ping_latency_dcfclk_cycles = 191,
253 .urgent_out_of_order_return_per_channel_bytes = 4096,
254 .channel_interleave_bytes = 256,
255 .num_banks = 8,
256 .num_chans = 4,
257 .gpuvm_min_page_size_bytes = 4096,
258 .hostvm_min_page_size_bytes = 4096,
259 .dram_clock_change_latency_us = 23.84,
260 .writeback_dram_clock_change_latency_us = 23.0,
261 .return_bus_width_bytes = 64,
262 .dispclk_dppclk_vco_speed_mhz = 3550,
263 .xfc_bus_transport_time_us = 20,
264 .xfc_xbuf_latency_tolerance_us = 4,
265 .use_urgent_burst_bw = 1,
266 .num_states = 5,
267 .do_urgent_latency_adjustment = false,
268 .urgent_latency_adjustment_fabric_clock_component_us = 0,
269 .urgent_latency_adjustment_fabric_clock_reference_mhz = 0,
270};
271
272enum dcn301_clk_src_array_id {
273 DCN301_CLK_SRC_PLL0,
274 DCN301_CLK_SRC_PLL1,
275 DCN301_CLK_SRC_PLL2,
276 DCN301_CLK_SRC_PLL3,
277 DCN301_CLK_SRC_TOTAL
278};
279
280
281
282
283
284
285
286#undef BASE_INNER
287#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
288
289#define BASE(seg) BASE_INNER(seg)
290
291#define SR(reg_name)\
292 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
293 mm ## reg_name
294
295#define SRI(reg_name, block, id)\
296 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
297 mm ## block ## id ## _ ## reg_name
298
299#define SRI2(reg_name, block, id)\
300 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
301 mm ## reg_name
302
303#define SRIR(var_name, reg_name, block, id)\
304 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
305 mm ## block ## id ## _ ## reg_name
306
307#define SRII(reg_name, block, id)\
308 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
309 mm ## block ## id ## _ ## reg_name
310
311#define SRII2(reg_name_pre, reg_name_post, id)\
312 .reg_name_pre ## _ ## reg_name_post[id] = BASE(mm ## reg_name_pre \
313 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
314 mm ## reg_name_pre ## id ## _ ## reg_name_post
315
316#define SRII_MPC_RMU(reg_name, block, id)\
317 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
318 mm ## block ## id ## _ ## reg_name
319
320#define SRII_DWB(reg_name, temp_name, block, id)\
321 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
322 mm ## block ## id ## _ ## temp_name
323
324#define DCCG_SRII(reg_name, block, id)\
325 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
326 mm ## block ## id ## _ ## reg_name
327
328#define VUPDATE_SRII(reg_name, block, id)\
329 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
330 mm ## reg_name ## _ ## block ## id
331
332
333#define NBIO_BASE_INNER(seg) \
334 NBIO_BASE__INST0_SEG ## seg
335
336#define NBIO_BASE(seg) \
337 NBIO_BASE_INNER(seg)
338
339#define NBIO_SR(reg_name)\
340 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
341 regBIF_BX0_ ## reg_name
342
343
344#define MMHUB_BASE_INNER(seg) \
345 MMHUB_BASE__INST0_SEG ## seg
346
347#define MMHUB_BASE(seg) \
348 MMHUB_BASE_INNER(seg)
349
350#define MMHUB_SR(reg_name)\
351 .reg_name = MMHUB_BASE(regMM ## reg_name ## _BASE_IDX) + \
352 regMM ## reg_name
353
354
355#define CLK_BASE_INNER(seg) \
356 CLK_BASE__INST0_SEG ## seg
357
358#define CLK_BASE(seg) \
359 CLK_BASE_INNER(seg)
360
361#define CLK_SRI(reg_name, block, inst)\
362 .reg_name = CLK_BASE(mm ## block ## _ ## inst ## _ ## reg_name ## _BASE_IDX) + \
363 mm ## block ## _ ## inst ## _ ## reg_name
364
365static const struct bios_registers bios_regs = {
366 NBIO_SR(BIOS_SCRATCH_3),
367 NBIO_SR(BIOS_SCRATCH_6)
368};
369
370#define clk_src_regs(index, pllid)\
371[index] = {\
372 CS_COMMON_REG_LIST_DCN3_01(index, pllid),\
373}
374
375static const struct dce110_clk_src_regs clk_src_regs[] = {
376 clk_src_regs(0, A),
377 clk_src_regs(1, B),
378 clk_src_regs(2, C),
379 clk_src_regs(3, D)
380};
381
382static const struct dce110_clk_src_shift cs_shift = {
383 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
384};
385
386static const struct dce110_clk_src_mask cs_mask = {
387 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
388};
389
390#define abm_regs(id)\
391[id] = {\
392 ABM_DCN301_REG_LIST(id)\
393}
394
395static const struct dce_abm_registers abm_regs[] = {
396 abm_regs(0),
397 abm_regs(1),
398 abm_regs(2),
399 abm_regs(3),
400};
401
402static const struct dce_abm_shift abm_shift = {
403 ABM_MASK_SH_LIST_DCN30(__SHIFT)
404};
405
406static const struct dce_abm_mask abm_mask = {
407 ABM_MASK_SH_LIST_DCN30(_MASK)
408};
409
410#define audio_regs(id)\
411[id] = {\
412 AUD_COMMON_REG_LIST(id)\
413}
414
415static const struct dce_audio_registers audio_regs[] = {
416 audio_regs(0),
417 audio_regs(1),
418 audio_regs(2),
419 audio_regs(3),
420 audio_regs(4),
421 audio_regs(5),
422 audio_regs(6)
423};
424
425#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
426 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
427 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
428 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
429
430static const struct dce_audio_shift audio_shift = {
431 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
432};
433
434static const struct dce_audio_mask audio_mask = {
435 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
436};
437
438#define vpg_regs(id)\
439[id] = {\
440 VPG_DCN3_REG_LIST(id)\
441}
442
443static const struct dcn30_vpg_registers vpg_regs[] = {
444 vpg_regs(0),
445 vpg_regs(1),
446 vpg_regs(2),
447 vpg_regs(3),
448};
449
450static const struct dcn30_vpg_shift vpg_shift = {
451 DCN3_VPG_MASK_SH_LIST(__SHIFT)
452};
453
454static const struct dcn30_vpg_mask vpg_mask = {
455 DCN3_VPG_MASK_SH_LIST(_MASK)
456};
457
458#define afmt_regs(id)\
459[id] = {\
460 AFMT_DCN3_REG_LIST(id)\
461}
462
463static const struct dcn30_afmt_registers afmt_regs[] = {
464 afmt_regs(0),
465 afmt_regs(1),
466 afmt_regs(2),
467 afmt_regs(3),
468};
469
470static const struct dcn30_afmt_shift afmt_shift = {
471 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
472};
473
474static const struct dcn30_afmt_mask afmt_mask = {
475 DCN3_AFMT_MASK_SH_LIST(_MASK)
476};
477
478#define stream_enc_regs(id)\
479[id] = {\
480 SE_DCN3_REG_LIST(id)\
481}
482
483static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
484 stream_enc_regs(0),
485 stream_enc_regs(1),
486 stream_enc_regs(2),
487 stream_enc_regs(3),
488};
489
490static const struct dcn10_stream_encoder_shift se_shift = {
491 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
492};
493
494static const struct dcn10_stream_encoder_mask se_mask = {
495 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
496};
497
498
499#define aux_regs(id)\
500[id] = {\
501 DCN2_AUX_REG_LIST(id)\
502}
503
504static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
505 aux_regs(0),
506 aux_regs(1),
507 aux_regs(2),
508 aux_regs(3),
509};
510
511#define hpd_regs(id)\
512[id] = {\
513 HPD_REG_LIST(id)\
514}
515
516static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
517 hpd_regs(0),
518 hpd_regs(1),
519 hpd_regs(2),
520 hpd_regs(3),
521};
522
523
524#define link_regs(id, phyid)\
525[id] = {\
526 LE_DCN301_REG_LIST(id), \
527 UNIPHY_DCN2_REG_LIST(phyid), \
528 DPCS_DCN2_REG_LIST(id), \
529 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
530}
531
532static const struct dce110_aux_registers_shift aux_shift = {
533 DCN_AUX_MASK_SH_LIST(__SHIFT)
534};
535
536static const struct dce110_aux_registers_mask aux_mask = {
537 DCN_AUX_MASK_SH_LIST(_MASK)
538};
539
540static const struct dcn10_link_enc_registers link_enc_regs[] = {
541 link_regs(0, A),
542 link_regs(1, B),
543 link_regs(2, C),
544 link_regs(3, D),
545};
546
547static const struct dcn10_link_enc_shift le_shift = {
548 LINK_ENCODER_MASK_SH_LIST_DCN301(__SHIFT),\
549 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
550};
551
552static const struct dcn10_link_enc_mask le_mask = {
553 LINK_ENCODER_MASK_SH_LIST_DCN301(_MASK),\
554 DPCS_DCN2_MASK_SH_LIST(_MASK)
555};
556
557#define panel_cntl_regs(id)\
558[id] = {\
559 DCN301_PANEL_CNTL_REG_LIST(id),\
560}
561
562static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
563 panel_cntl_regs(0),
564 panel_cntl_regs(1),
565};
566
567static const struct dcn301_panel_cntl_shift panel_cntl_shift = {
568 DCN301_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
569};
570
571static const struct dcn301_panel_cntl_mask panel_cntl_mask = {
572 DCN301_PANEL_CNTL_MASK_SH_LIST(_MASK)
573};
574
575#define dpp_regs(id)\
576[id] = {\
577 DPP_REG_LIST_DCN30(id),\
578}
579
580static const struct dcn3_dpp_registers dpp_regs[] = {
581 dpp_regs(0),
582 dpp_regs(1),
583 dpp_regs(2),
584 dpp_regs(3),
585};
586
587static const struct dcn3_dpp_shift tf_shift = {
588 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
589};
590
591static const struct dcn3_dpp_mask tf_mask = {
592 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
593};
594
595#define opp_regs(id)\
596[id] = {\
597 OPP_REG_LIST_DCN30(id),\
598}
599
600static const struct dcn20_opp_registers opp_regs[] = {
601 opp_regs(0),
602 opp_regs(1),
603 opp_regs(2),
604 opp_regs(3),
605};
606
607static const struct dcn20_opp_shift opp_shift = {
608 OPP_MASK_SH_LIST_DCN20(__SHIFT)
609};
610
611static const struct dcn20_opp_mask opp_mask = {
612 OPP_MASK_SH_LIST_DCN20(_MASK)
613};
614
615#define aux_engine_regs(id)\
616[id] = {\
617 AUX_COMMON_REG_LIST0(id), \
618 .AUXN_IMPCAL = 0, \
619 .AUXP_IMPCAL = 0, \
620 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
621}
622
623static const struct dce110_aux_registers aux_engine_regs[] = {
624 aux_engine_regs(0),
625 aux_engine_regs(1),
626 aux_engine_regs(2),
627 aux_engine_regs(3),
628};
629
630#define dwbc_regs_dcn3(id)\
631[id] = {\
632 DWBC_COMMON_REG_LIST_DCN30(id),\
633}
634
635static const struct dcn30_dwbc_registers dwbc30_regs[] = {
636 dwbc_regs_dcn3(0),
637};
638
639static const struct dcn30_dwbc_shift dwbc30_shift = {
640 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
641};
642
643static const struct dcn30_dwbc_mask dwbc30_mask = {
644 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
645};
646
647#define mcif_wb_regs_dcn3(id)\
648[id] = {\
649 MCIF_WB_COMMON_REG_LIST_DCN30(id),\
650}
651
652static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
653 mcif_wb_regs_dcn3(0)
654};
655
656static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
657 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
658};
659
660static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
661 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
662};
663
664#define dsc_regsDCN20(id)\
665[id] = {\
666 DSC_REG_LIST_DCN20(id)\
667}
668
669static const struct dcn20_dsc_registers dsc_regs[] = {
670 dsc_regsDCN20(0),
671 dsc_regsDCN20(1),
672 dsc_regsDCN20(2),
673};
674
675static const struct dcn20_dsc_shift dsc_shift = {
676 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
677};
678
679static const struct dcn20_dsc_mask dsc_mask = {
680 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
681};
682
683static const struct dcn30_mpc_registers mpc_regs = {
684 MPC_REG_LIST_DCN3_0(0),
685 MPC_REG_LIST_DCN3_0(1),
686 MPC_REG_LIST_DCN3_0(2),
687 MPC_REG_LIST_DCN3_0(3),
688 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
689 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
690 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
691 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
692 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
693 MPC_RMU_REG_LIST_DCN3AG(0),
694 MPC_RMU_REG_LIST_DCN3AG(1),
695 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
696};
697
698static const struct dcn30_mpc_shift mpc_shift = {
699 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
700};
701
702static const struct dcn30_mpc_mask mpc_mask = {
703 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
704};
705
706#define optc_regs(id)\
707[id] = {OPTC_COMMON_REG_LIST_DCN3_0(id)}
708
709
710static const struct dcn_optc_registers optc_regs[] = {
711 optc_regs(0),
712 optc_regs(1),
713 optc_regs(2),
714 optc_regs(3),
715};
716
717static const struct dcn_optc_shift optc_shift = {
718 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
719};
720
721static const struct dcn_optc_mask optc_mask = {
722 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
723};
724
725#define hubp_regs(id)\
726[id] = {\
727 HUBP_REG_LIST_DCN30(id)\
728}
729
730static const struct dcn_hubp2_registers hubp_regs[] = {
731 hubp_regs(0),
732 hubp_regs(1),
733 hubp_regs(2),
734 hubp_regs(3),
735};
736
737static const struct dcn_hubp2_shift hubp_shift = {
738 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
739};
740
741static const struct dcn_hubp2_mask hubp_mask = {
742 HUBP_MASK_SH_LIST_DCN30(_MASK)
743};
744
745static const struct dcn_hubbub_registers hubbub_reg = {
746 HUBBUB_REG_LIST_DCN301(0)
747};
748
749static const struct dcn_hubbub_shift hubbub_shift = {
750 HUBBUB_MASK_SH_LIST_DCN301(__SHIFT)
751};
752
753static const struct dcn_hubbub_mask hubbub_mask = {
754 HUBBUB_MASK_SH_LIST_DCN301(_MASK)
755};
756
757static const struct dccg_registers dccg_regs = {
758 DCCG_REG_LIST_DCN301()
759};
760
761static const struct dccg_shift dccg_shift = {
762 DCCG_MASK_SH_LIST_DCN301(__SHIFT)
763};
764
765static const struct dccg_mask dccg_mask = {
766 DCCG_MASK_SH_LIST_DCN301(_MASK)
767};
768
769static const struct dce_hwseq_registers hwseq_reg = {
770 HWSEQ_DCN301_REG_LIST()
771};
772
773static const struct dce_hwseq_shift hwseq_shift = {
774 HWSEQ_DCN301_MASK_SH_LIST(__SHIFT)
775};
776
777static const struct dce_hwseq_mask hwseq_mask = {
778 HWSEQ_DCN301_MASK_SH_LIST(_MASK)
779};
780#define vmid_regs(id)\
781[id] = {\
782 DCN20_VMID_REG_LIST(id)\
783}
784
785static const struct dcn_vmid_registers vmid_regs[] = {
786 vmid_regs(0),
787 vmid_regs(1),
788 vmid_regs(2),
789 vmid_regs(3),
790 vmid_regs(4),
791 vmid_regs(5),
792 vmid_regs(6),
793 vmid_regs(7),
794 vmid_regs(8),
795 vmid_regs(9),
796 vmid_regs(10),
797 vmid_regs(11),
798 vmid_regs(12),
799 vmid_regs(13),
800 vmid_regs(14),
801 vmid_regs(15)
802};
803
804static const struct dcn20_vmid_shift vmid_shifts = {
805 DCN20_VMID_MASK_SH_LIST(__SHIFT)
806};
807
808static const struct dcn20_vmid_mask vmid_masks = {
809 DCN20_VMID_MASK_SH_LIST(_MASK)
810};
811
812static const struct resource_caps res_cap_dcn301 = {
813 .num_timing_generator = 4,
814 .num_opp = 4,
815 .num_video_plane = 4,
816 .num_audio = 4,
817 .num_stream_encoder = 4,
818 .num_pll = 4,
819 .num_dwb = 1,
820 .num_ddc = 4,
821 .num_vmid = 16,
822 .num_mpc_3dlut = 2,
823 .num_dsc = 3,
824};
825
826static const struct dc_plane_cap plane_cap = {
827 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
828 .blends_with_above = true,
829 .blends_with_below = true,
830 .per_pixel_alpha = true,
831
832 .pixel_format_support = {
833 .argb8888 = true,
834 .nv12 = true,
835 .fp16 = true,
836 .p010 = false,
837 .ayuv = false,
838 },
839
840 .max_upscale_factor = {
841 .argb8888 = 16000,
842 .nv12 = 16000,
843 .fp16 = 16000
844 },
845
846
847 .max_downscale_factor = {
848 .argb8888 = 167,
849 .nv12 = 167,
850 .fp16 = 167
851 },
852 64,
853 64
854};
855
856static const struct dc_debug_options debug_defaults_drv = {
857 .disable_dmcu = true,
858 .force_abm_enable = false,
859 .timing_trace = false,
860 .clock_trace = true,
861 .disable_dpp_power_gate = false,
862 .disable_hubp_power_gate = false,
863 .disable_clock_gate = true,
864 .disable_pplib_clock_request = true,
865 .disable_pplib_wm_range = true,
866 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
867 .force_single_disp_pipe_split = false,
868 .disable_dcc = DCC_ENABLE,
869 .vsr_support = true,
870 .performance_trace = false,
871 .max_downscale_src_width = 7680,
872 .scl_reset_length10 = true,
873 .sanity_checks = false,
874 .underflow_assert_delay_us = 0xFFFFFFFF,
875 .dwb_fi_phase = -1,
876 .dmub_command_table = true,
877 .use_max_lb = false,
878};
879
880static const struct dc_debug_options debug_defaults_diags = {
881 .disable_dmcu = true,
882 .force_abm_enable = false,
883 .timing_trace = true,
884 .clock_trace = true,
885 .disable_dpp_power_gate = false,
886 .disable_hubp_power_gate = false,
887 .disable_clock_gate = true,
888 .disable_pplib_clock_request = true,
889 .disable_pplib_wm_range = true,
890 .disable_stutter = true,
891 .scl_reset_length10 = true,
892 .dwb_fi_phase = -1,
893 .dmub_command_table = true,
894 .use_max_lb = false,
895};
896
897void dcn301_dpp_destroy(struct dpp **dpp)
898{
899 kfree(TO_DCN20_DPP(*dpp));
900 *dpp = NULL;
901}
902
903struct dpp *dcn301_dpp_create(
904 struct dc_context *ctx,
905 uint32_t inst)
906{
907 struct dcn3_dpp *dpp =
908 kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
909
910 if (!dpp)
911 return NULL;
912
913 if (dpp3_construct(dpp, ctx, inst,
914 &dpp_regs[inst], &tf_shift, &tf_mask))
915 return &dpp->base;
916
917 BREAK_TO_DEBUGGER();
918 kfree(dpp);
919 return NULL;
920}
921struct output_pixel_processor *dcn301_opp_create(
922 struct dc_context *ctx, uint32_t inst)
923{
924 struct dcn20_opp *opp =
925 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
926
927 if (!opp) {
928 BREAK_TO_DEBUGGER();
929 return NULL;
930 }
931
932 dcn20_opp_construct(opp, ctx, inst,
933 &opp_regs[inst], &opp_shift, &opp_mask);
934 return &opp->base;
935}
936
937struct dce_aux *dcn301_aux_engine_create(
938 struct dc_context *ctx,
939 uint32_t inst)
940{
941 struct aux_engine_dce110 *aux_engine =
942 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
943
944 if (!aux_engine)
945 return NULL;
946
947 dce110_aux_engine_construct(aux_engine, ctx, inst,
948 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
949 &aux_engine_regs[inst],
950 &aux_mask,
951 &aux_shift,
952 ctx->dc->caps.extended_aux_timeout_support);
953
954 return &aux_engine->base;
955}
956#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
957
958static const struct dce_i2c_registers i2c_hw_regs[] = {
959 i2c_inst_regs(1),
960 i2c_inst_regs(2),
961 i2c_inst_regs(3),
962 i2c_inst_regs(4),
963};
964
965static const struct dce_i2c_shift i2c_shifts = {
966 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
967};
968
969static const struct dce_i2c_mask i2c_masks = {
970 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
971};
972
973struct dce_i2c_hw *dcn301_i2c_hw_create(
974 struct dc_context *ctx,
975 uint32_t inst)
976{
977 struct dce_i2c_hw *dce_i2c_hw =
978 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
979
980 if (!dce_i2c_hw)
981 return NULL;
982
983 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
984 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
985
986 return dce_i2c_hw;
987}
988static struct mpc *dcn301_mpc_create(
989 struct dc_context *ctx,
990 int num_mpcc,
991 int num_rmu)
992{
993 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc),
994 GFP_KERNEL);
995
996 if (!mpc30)
997 return NULL;
998
999 dcn30_mpc_construct(mpc30, ctx,
1000 &mpc_regs,
1001 &mpc_shift,
1002 &mpc_mask,
1003 num_mpcc,
1004 num_rmu);
1005
1006 return &mpc30->base;
1007}
1008
1009struct hubbub *dcn301_hubbub_create(struct dc_context *ctx)
1010{
1011 int i;
1012
1013 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub),
1014 GFP_KERNEL);
1015
1016 if (!hubbub3)
1017 return NULL;
1018
1019 hubbub301_construct(hubbub3, ctx,
1020 &hubbub_reg,
1021 &hubbub_shift,
1022 &hubbub_mask);
1023
1024
1025 for (i = 0; i < res_cap_dcn301.num_vmid; i++) {
1026 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
1027
1028 vmid->ctx = ctx;
1029
1030 vmid->regs = &vmid_regs[i];
1031 vmid->shifts = &vmid_shifts;
1032 vmid->masks = &vmid_masks;
1033 }
1034
1035 hubbub3->num_vmid = res_cap_dcn301.num_vmid;
1036
1037 return &hubbub3->base;
1038}
1039
1040struct timing_generator *dcn301_timing_generator_create(
1041 struct dc_context *ctx,
1042 uint32_t instance)
1043{
1044 struct optc *tgn10 =
1045 kzalloc(sizeof(struct optc), GFP_KERNEL);
1046
1047 if (!tgn10)
1048 return NULL;
1049
1050 tgn10->base.inst = instance;
1051 tgn10->base.ctx = ctx;
1052
1053 tgn10->tg_regs = &optc_regs[instance];
1054 tgn10->tg_shift = &optc_shift;
1055 tgn10->tg_mask = &optc_mask;
1056
1057 dcn30_timing_generator_init(tgn10);
1058
1059 return &tgn10->base;
1060}
1061
1062static const struct encoder_feature_support link_enc_feature = {
1063 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1064 .max_hdmi_pixel_clock = 600000,
1065 .hdmi_ycbcr420_supported = true,
1066 .dp_ycbcr420_supported = true,
1067 .fec_supported = true,
1068 .flags.bits.IS_HBR2_CAPABLE = true,
1069 .flags.bits.IS_HBR3_CAPABLE = true,
1070 .flags.bits.IS_TPS3_CAPABLE = true,
1071 .flags.bits.IS_TPS4_CAPABLE = true
1072};
1073
1074struct link_encoder *dcn301_link_encoder_create(
1075 const struct encoder_init_data *enc_init_data)
1076{
1077 struct dcn20_link_encoder *enc20 =
1078 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1079
1080 if (!enc20)
1081 return NULL;
1082
1083 dcn301_link_encoder_construct(enc20,
1084 enc_init_data,
1085 &link_enc_feature,
1086 &link_enc_regs[enc_init_data->transmitter],
1087 &link_enc_aux_regs[enc_init_data->channel - 1],
1088 &link_enc_hpd_regs[enc_init_data->hpd_source],
1089 &le_shift,
1090 &le_mask);
1091
1092 return &enc20->enc10.base;
1093}
1094
1095struct panel_cntl *dcn301_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1096{
1097 struct dcn301_panel_cntl *panel_cntl =
1098 kzalloc(sizeof(struct dcn301_panel_cntl), GFP_KERNEL);
1099
1100 if (!panel_cntl)
1101 return NULL;
1102
1103 dcn301_panel_cntl_construct(panel_cntl,
1104 init_data,
1105 &panel_cntl_regs[init_data->inst],
1106 &panel_cntl_shift,
1107 &panel_cntl_mask);
1108
1109 return &panel_cntl->base;
1110}
1111
1112
1113#define CTX ctx
1114
1115#define REG(reg_name) \
1116 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1117
1118static uint32_t read_pipe_fuses(struct dc_context *ctx)
1119{
1120 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1121
1122 value = value & 0xf;
1123 return value;
1124}
1125
1126
1127static void read_dce_straps(
1128 struct dc_context *ctx,
1129 struct resource_straps *straps)
1130{
1131 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1132 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1133
1134}
1135
1136static struct audio *dcn301_create_audio(
1137 struct dc_context *ctx, unsigned int inst)
1138{
1139 return dce_audio_create(ctx, inst,
1140 &audio_regs[inst], &audio_shift, &audio_mask);
1141}
1142
1143static struct vpg *dcn301_vpg_create(
1144 struct dc_context *ctx,
1145 uint32_t inst)
1146{
1147 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
1148
1149 if (!vpg3)
1150 return NULL;
1151
1152 vpg3_construct(vpg3, ctx, inst,
1153 &vpg_regs[inst],
1154 &vpg_shift,
1155 &vpg_mask);
1156
1157 return &vpg3->base;
1158}
1159
1160static struct afmt *dcn301_afmt_create(
1161 struct dc_context *ctx,
1162 uint32_t inst)
1163{
1164 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1165
1166 if (!afmt3)
1167 return NULL;
1168
1169 afmt3_construct(afmt3, ctx, inst,
1170 &afmt_regs[inst],
1171 &afmt_shift,
1172 &afmt_mask);
1173
1174 return &afmt3->base;
1175}
1176
1177struct stream_encoder *dcn301_stream_encoder_create(
1178 enum engine_id eng_id,
1179 struct dc_context *ctx)
1180{
1181 struct dcn10_stream_encoder *enc1;
1182 struct vpg *vpg;
1183 struct afmt *afmt;
1184 int vpg_inst;
1185 int afmt_inst;
1186
1187
1188 if (eng_id <= ENGINE_ID_DIGF) {
1189 vpg_inst = eng_id;
1190 afmt_inst = eng_id;
1191 } else
1192 return NULL;
1193
1194 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1195 vpg = dcn301_vpg_create(ctx, vpg_inst);
1196 afmt = dcn301_afmt_create(ctx, afmt_inst);
1197
1198 if (!enc1 || !vpg || !afmt)
1199 return NULL;
1200
1201 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1202 eng_id, vpg, afmt,
1203 &stream_enc_regs[eng_id],
1204 &se_shift, &se_mask);
1205
1206 return &enc1->base;
1207}
1208
1209struct dce_hwseq *dcn301_hwseq_create(
1210 struct dc_context *ctx)
1211{
1212 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1213
1214 if (hws) {
1215 hws->ctx = ctx;
1216 hws->regs = &hwseq_reg;
1217 hws->shifts = &hwseq_shift;
1218 hws->masks = &hwseq_mask;
1219 }
1220 return hws;
1221}
1222static const struct resource_create_funcs res_create_funcs = {
1223 .read_dce_straps = read_dce_straps,
1224 .create_audio = dcn301_create_audio,
1225 .create_stream_encoder = dcn301_stream_encoder_create,
1226 .create_hwseq = dcn301_hwseq_create,
1227};
1228
1229static const struct resource_create_funcs res_create_maximus_funcs = {
1230 .read_dce_straps = NULL,
1231 .create_audio = NULL,
1232 .create_stream_encoder = NULL,
1233 .create_hwseq = dcn301_hwseq_create,
1234};
1235
1236static void dcn301_destruct(struct dcn301_resource_pool *pool)
1237{
1238 unsigned int i;
1239
1240 for (i = 0; i < pool->base.stream_enc_count; i++) {
1241 if (pool->base.stream_enc[i] != NULL) {
1242 if (pool->base.stream_enc[i]->vpg != NULL) {
1243 kfree(DCN30_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1244 pool->base.stream_enc[i]->vpg = NULL;
1245 }
1246 if (pool->base.stream_enc[i]->afmt != NULL) {
1247 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1248 pool->base.stream_enc[i]->afmt = NULL;
1249 }
1250 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1251 pool->base.stream_enc[i] = NULL;
1252 }
1253 }
1254
1255 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1256 if (pool->base.dscs[i] != NULL)
1257 dcn20_dsc_destroy(&pool->base.dscs[i]);
1258 }
1259
1260 if (pool->base.mpc != NULL) {
1261 kfree(TO_DCN20_MPC(pool->base.mpc));
1262 pool->base.mpc = NULL;
1263 }
1264 if (pool->base.hubbub != NULL) {
1265 kfree(pool->base.hubbub);
1266 pool->base.hubbub = NULL;
1267 }
1268 for (i = 0; i < pool->base.pipe_count; i++) {
1269 if (pool->base.dpps[i] != NULL)
1270 dcn301_dpp_destroy(&pool->base.dpps[i]);
1271
1272 if (pool->base.ipps[i] != NULL)
1273 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1274
1275 if (pool->base.hubps[i] != NULL) {
1276 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1277 pool->base.hubps[i] = NULL;
1278 }
1279
1280 if (pool->base.irqs != NULL) {
1281 dal_irq_service_destroy(&pool->base.irqs);
1282 }
1283 }
1284
1285 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1286 if (pool->base.engines[i] != NULL)
1287 dce110_engine_destroy(&pool->base.engines[i]);
1288 if (pool->base.hw_i2cs[i] != NULL) {
1289 kfree(pool->base.hw_i2cs[i]);
1290 pool->base.hw_i2cs[i] = NULL;
1291 }
1292 if (pool->base.sw_i2cs[i] != NULL) {
1293 kfree(pool->base.sw_i2cs[i]);
1294 pool->base.sw_i2cs[i] = NULL;
1295 }
1296 }
1297
1298 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1299 if (pool->base.opps[i] != NULL)
1300 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1301 }
1302
1303 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1304 if (pool->base.timing_generators[i] != NULL) {
1305 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1306 pool->base.timing_generators[i] = NULL;
1307 }
1308 }
1309
1310 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1311 if (pool->base.dwbc[i] != NULL) {
1312 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1313 pool->base.dwbc[i] = NULL;
1314 }
1315 if (pool->base.mcif_wb[i] != NULL) {
1316 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1317 pool->base.mcif_wb[i] = NULL;
1318 }
1319 }
1320
1321 for (i = 0; i < pool->base.audio_count; i++) {
1322 if (pool->base.audios[i])
1323 dce_aud_destroy(&pool->base.audios[i]);
1324 }
1325
1326 for (i = 0; i < pool->base.clk_src_count; i++) {
1327 if (pool->base.clock_sources[i] != NULL) {
1328 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1329 pool->base.clock_sources[i] = NULL;
1330 }
1331 }
1332
1333 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1334 if (pool->base.mpc_lut[i] != NULL) {
1335 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1336 pool->base.mpc_lut[i] = NULL;
1337 }
1338 if (pool->base.mpc_shaper[i] != NULL) {
1339 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1340 pool->base.mpc_shaper[i] = NULL;
1341 }
1342 }
1343
1344 if (pool->base.dp_clock_source != NULL) {
1345 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1346 pool->base.dp_clock_source = NULL;
1347 }
1348
1349 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1350 if (pool->base.multiple_abms[i] != NULL)
1351 dce_abm_destroy(&pool->base.multiple_abms[i]);
1352 }
1353
1354 if (pool->base.dccg != NULL)
1355 dcn_dccg_destroy(&pool->base.dccg);
1356}
1357
1358struct hubp *dcn301_hubp_create(
1359 struct dc_context *ctx,
1360 uint32_t inst)
1361{
1362 struct dcn20_hubp *hubp2 =
1363 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
1364
1365 if (!hubp2)
1366 return NULL;
1367
1368 if (hubp3_construct(hubp2, ctx, inst,
1369 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1370 return &hubp2->base;
1371
1372 BREAK_TO_DEBUGGER();
1373 kfree(hubp2);
1374 return NULL;
1375}
1376
1377bool dcn301_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1378{
1379 int i;
1380 uint32_t pipe_count = pool->res_cap->num_dwb;
1381
1382 for (i = 0; i < pipe_count; i++) {
1383 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc),
1384 GFP_KERNEL);
1385
1386 if (!dwbc30) {
1387 dm_error("DC: failed to create dwbc30!\n");
1388 return false;
1389 }
1390
1391 dcn30_dwbc_construct(dwbc30, ctx,
1392 &dwbc30_regs[i],
1393 &dwbc30_shift,
1394 &dwbc30_mask,
1395 i);
1396
1397 pool->dwbc[i] = &dwbc30->base;
1398 }
1399 return true;
1400}
1401
1402bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1403{
1404 int i;
1405 uint32_t pipe_count = pool->res_cap->num_dwb;
1406
1407 for (i = 0; i < pipe_count; i++) {
1408 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1409 GFP_KERNEL);
1410
1411 if (!mcif_wb30) {
1412 dm_error("DC: failed to create mcif_wb30!\n");
1413 return false;
1414 }
1415
1416 dcn30_mmhubbub_construct(mcif_wb30, ctx,
1417 &mcif_wb30_regs[i],
1418 &mcif_wb30_shift,
1419 &mcif_wb30_mask,
1420 i);
1421
1422 pool->mcif_wb[i] = &mcif_wb30->base;
1423 }
1424 return true;
1425}
1426
1427static struct display_stream_compressor *dcn301_dsc_create(
1428 struct dc_context *ctx, uint32_t inst)
1429{
1430 struct dcn20_dsc *dsc =
1431 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1432
1433 if (!dsc) {
1434 BREAK_TO_DEBUGGER();
1435 return NULL;
1436 }
1437
1438 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1439 return &dsc->base;
1440}
1441
1442
1443static void dcn301_destroy_resource_pool(struct resource_pool **pool)
1444{
1445 struct dcn301_resource_pool *dcn301_pool = TO_DCN301_RES_POOL(*pool);
1446
1447 dcn301_destruct(dcn301_pool);
1448 kfree(dcn301_pool);
1449 *pool = NULL;
1450}
1451
1452static struct clock_source *dcn301_clock_source_create(
1453 struct dc_context *ctx,
1454 struct dc_bios *bios,
1455 enum clock_source_id id,
1456 const struct dce110_clk_src_regs *regs,
1457 bool dp_clk_src)
1458{
1459 struct dce110_clk_src *clk_src =
1460 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1461
1462 if (!clk_src)
1463 return NULL;
1464
1465 if (dcn301_clk_src_construct(clk_src, ctx, bios, id,
1466 regs, &cs_shift, &cs_mask)) {
1467 clk_src->base.dp_clk_src = dp_clk_src;
1468 return &clk_src->base;
1469 }
1470
1471 BREAK_TO_DEBUGGER();
1472 return NULL;
1473}
1474
1475static struct dc_cap_funcs cap_funcs = {
1476 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1477};
1478
1479#define fixed16_to_double(x) (((double) x) / ((double) (1 << 16)))
1480#define fixed16_to_double_to_cpu(x) fixed16_to_double(le32_to_cpu(x))
1481
1482static bool is_soc_bounding_box_valid(struct dc *dc)
1483{
1484 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1485
1486 if (ASICREV_IS_VANGOGH(hw_internal_rev))
1487 return true;
1488
1489 return false;
1490}
1491
1492static bool init_soc_bounding_box(struct dc *dc,
1493 struct dcn301_resource_pool *pool)
1494{
1495 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_01_soc;
1496 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_01_ip;
1497
1498 DC_LOGGER_INIT(dc->ctx->logger);
1499
1500 if (!is_soc_bounding_box_valid(dc)) {
1501 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1502 return false;
1503 }
1504
1505 loaded_ip->max_num_otg = pool->base.res_cap->num_timing_generator;
1506 loaded_ip->max_num_dpp = pool->base.pipe_count;
1507 dcn20_patch_bounding_box(dc, loaded_bb);
1508
1509 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1510 struct bp_soc_bb_info bb_info = {0};
1511
1512 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1513 if (bb_info.dram_clock_change_latency_100ns > 0)
1514 dcn3_01_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;
1515
1516 if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1517 dcn3_01_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;
1518
1519 if (bb_info.dram_sr_exit_latency_100ns > 0)
1520 dcn3_01_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;
1521 }
1522 }
1523
1524 return true;
1525}
1526
1527static void set_wm_ranges(
1528 struct pp_smu_funcs *pp_smu,
1529 struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
1530{
1531 struct pp_smu_wm_range_sets ranges = {0};
1532 int i;
1533
1534 ranges.num_reader_wm_sets = 0;
1535
1536 if (loaded_bb->num_states == 1) {
1537 ranges.reader_wm_sets[0].wm_inst = 0;
1538 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1539 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1540 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1541 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1542
1543 ranges.num_reader_wm_sets = 1;
1544 } else if (loaded_bb->num_states > 1) {
1545 for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
1546 ranges.reader_wm_sets[i].wm_inst = i;
1547 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1548 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1549 ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
1550 ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
1551
1552 ranges.num_reader_wm_sets = i + 1;
1553 }
1554
1555 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1556 ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1557 }
1558
1559 ranges.num_writer_wm_sets = 1;
1560
1561 ranges.writer_wm_sets[0].wm_inst = 0;
1562 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1563 ranges.writer_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1564 ranges.writer_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
1565 ranges.writer_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
1566
1567
1568 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges);
1569}
1570
1571static void dcn301_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1572{
1573 struct dcn301_resource_pool *pool = TO_DCN301_RES_POOL(dc->res_pool);
1574 struct clk_limit_table *clk_table = &bw_params->clk_table;
1575 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1576 unsigned int i, closest_clk_lvl;
1577 int j;
1578
1579
1580 if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
1581 dcn3_01_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1582 dcn3_01_ip.max_num_dpp = pool->base.pipe_count;
1583 dcn3_01_soc.num_chans = bw_params->num_channels;
1584
1585 ASSERT(clk_table->num_entries);
1586 for (i = 0; i < clk_table->num_entries; i++) {
1587
1588 for (closest_clk_lvl = 0, j = dcn3_01_soc.num_states - 1; j >= 0; j--) {
1589 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1590 closest_clk_lvl = j;
1591 break;
1592 }
1593 }
1594
1595 clock_limits[i].state = i;
1596 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1597 clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1598 clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz;
1599 clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1600
1601 clock_limits[i].dispclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1602 clock_limits[i].dppclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1603 clock_limits[i].dram_bw_per_chan_gbps = dcn3_01_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1604 clock_limits[i].dscclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1605 clock_limits[i].dtbclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1606 clock_limits[i].phyclk_d18_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1607 clock_limits[i].phyclk_mhz = dcn3_01_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1608 }
1609 for (i = 0; i < clk_table->num_entries; i++)
1610 dcn3_01_soc.clock_limits[i] = clock_limits[i];
1611 if (clk_table->num_entries) {
1612 dcn3_01_soc.num_states = clk_table->num_entries;
1613
1614 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states] = dcn3_01_soc.clock_limits[dcn3_01_soc.num_states - 1];
1615 dcn3_01_soc.clock_limits[dcn3_01_soc.num_states].state = dcn3_01_soc.num_states;
1616 }
1617 }
1618
1619 dcn3_01_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1620 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1621
1622 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1623}
1624
1625static struct resource_funcs dcn301_res_pool_funcs = {
1626 .destroy = dcn301_destroy_resource_pool,
1627 .link_enc_create = dcn301_link_encoder_create,
1628 .panel_cntl_create = dcn301_panel_cntl_create,
1629 .validate_bandwidth = dcn30_validate_bandwidth,
1630 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1631 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1632 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1633 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1634 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1635 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1636 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1637 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1638 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1639 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1640 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1641 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1642 .update_bw_bounding_box = dcn301_update_bw_bounding_box
1643};
1644
1645static bool dcn301_resource_construct(
1646 uint8_t num_virtual_links,
1647 struct dc *dc,
1648 struct dcn301_resource_pool *pool)
1649{
1650 int i, j;
1651 struct dc_context *ctx = dc->ctx;
1652 struct irq_service_init_data init_data;
1653 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1654 uint32_t num_pipes = 0;
1655
1656 DC_LOGGER_INIT(dc->ctx->logger);
1657
1658 ctx->dc_bios->regs = &bios_regs;
1659
1660 pool->base.res_cap = &res_cap_dcn301;
1661
1662 pool->base.funcs = &dcn301_res_pool_funcs;
1663
1664
1665
1666
1667 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1668 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1669 pool->base.mpcc_count = pool->base.res_cap->num_timing_generator;
1670 dc->caps.max_downscale_ratio = 600;
1671 dc->caps.i2c_speed_in_khz = 100;
1672 dc->caps.i2c_speed_in_khz_hdcp = 5;
1673 dc->caps.max_cursor_size = 256;
1674 dc->caps.min_horizontal_blanking_period = 80;
1675 dc->caps.dmdata_alloc_size = 2048;
1676 dc->caps.max_slave_planes = 1;
1677 dc->caps.max_slave_yuv_planes = 1;
1678 dc->caps.max_slave_rgb_planes = 1;
1679 dc->caps.is_apu = true;
1680 dc->caps.post_blend_color_processing = true;
1681 dc->caps.force_dp_tps4_for_cp2520 = true;
1682 dc->caps.extended_aux_timeout_support = true;
1683#ifdef CONFIG_DRM_AMD_DC_DMUB
1684 dc->caps.dmcub_support = true;
1685#endif
1686
1687
1688 dc->caps.color.dpp.dcn_arch = 1;
1689 dc->caps.color.dpp.input_lut_shared = 0;
1690 dc->caps.color.dpp.icsc = 1;
1691 dc->caps.color.dpp.dgam_ram = 0;
1692 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1693 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1694 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1695 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1696 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1697 dc->caps.color.dpp.post_csc = 1;
1698 dc->caps.color.dpp.gamma_corr = 1;
1699 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1700
1701 dc->caps.color.dpp.hw_3d_lut = 1;
1702 dc->caps.color.dpp.ogam_ram = 1;
1703
1704 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1705 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1706 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1707 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1708 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1709 dc->caps.color.dpp.ocsc = 0;
1710
1711 dc->caps.color.mpc.gamut_remap = 1;
1712 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut;
1713 dc->caps.color.mpc.ogam_ram = 1;
1714 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1715 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1716 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1717 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1718 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1719 dc->caps.color.mpc.ocsc = 1;
1720
1721 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1722 dc->debug = debug_defaults_drv;
1723 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
1724 dc->debug = debug_defaults_diags;
1725 } else
1726 dc->debug = debug_defaults_diags;
1727
1728 if (dc->vm_helper)
1729 vm_helper_init(dc->vm_helper, 16);
1730
1731
1732
1733
1734
1735
1736 pool->base.clock_sources[DCN301_CLK_SRC_PLL0] =
1737 dcn301_clock_source_create(ctx, ctx->dc_bios,
1738 CLOCK_SOURCE_COMBO_PHY_PLL0,
1739 &clk_src_regs[0], false);
1740 pool->base.clock_sources[DCN301_CLK_SRC_PLL1] =
1741 dcn301_clock_source_create(ctx, ctx->dc_bios,
1742 CLOCK_SOURCE_COMBO_PHY_PLL1,
1743 &clk_src_regs[1], false);
1744 pool->base.clock_sources[DCN301_CLK_SRC_PLL2] =
1745 dcn301_clock_source_create(ctx, ctx->dc_bios,
1746 CLOCK_SOURCE_COMBO_PHY_PLL2,
1747 &clk_src_regs[2], false);
1748 pool->base.clock_sources[DCN301_CLK_SRC_PLL3] =
1749 dcn301_clock_source_create(ctx, ctx->dc_bios,
1750 CLOCK_SOURCE_COMBO_PHY_PLL3,
1751 &clk_src_regs[3], false);
1752
1753 pool->base.clk_src_count = DCN301_CLK_SRC_TOTAL;
1754
1755
1756 pool->base.dp_clock_source =
1757 dcn301_clock_source_create(ctx, ctx->dc_bios,
1758 CLOCK_SOURCE_ID_DP_DTO,
1759 &clk_src_regs[0], true);
1760
1761 for (i = 0; i < pool->base.clk_src_count; i++) {
1762 if (pool->base.clock_sources[i] == NULL) {
1763 dm_error("DC: failed to create clock sources!\n");
1764 BREAK_TO_DEBUGGER();
1765 goto create_fail;
1766 }
1767 }
1768
1769
1770 pool->base.dccg = dccg301_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1771 if (pool->base.dccg == NULL) {
1772 dm_error("DC: failed to create dccg!\n");
1773 BREAK_TO_DEBUGGER();
1774 goto create_fail;
1775 }
1776
1777 init_soc_bounding_box(dc, pool);
1778
1779 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges)
1780 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc);
1781
1782 num_pipes = dcn3_01_ip.max_num_dpp;
1783
1784 for (i = 0; i < dcn3_01_ip.max_num_dpp; i++)
1785 if (pipe_fuses & 1 << i)
1786 num_pipes--;
1787 dcn3_01_ip.max_num_dpp = num_pipes;
1788 dcn3_01_ip.max_num_otg = num_pipes;
1789
1790
1791 dml_init_instance(&dc->dml, &dcn3_01_soc, &dcn3_01_ip, DML_PROJECT_DCN30);
1792
1793
1794 init_data.ctx = dc->ctx;
1795 pool->base.irqs = dal_irq_service_dcn30_create(&init_data);
1796 if (!pool->base.irqs)
1797 goto create_fail;
1798
1799
1800 pool->base.hubbub = dcn301_hubbub_create(ctx);
1801 if (pool->base.hubbub == NULL) {
1802 BREAK_TO_DEBUGGER();
1803 dm_error("DC: failed to create hubbub!\n");
1804 goto create_fail;
1805 }
1806
1807 j = 0;
1808
1809 for (i = 0; i < pool->base.pipe_count; i++) {
1810
1811
1812
1813
1814 if ((pipe_fuses & (1 << i)) != 0) {
1815 DC_LOG_DEBUG("%s: fusing pipe %d\n", __func__, i);
1816 continue;
1817 }
1818
1819 pool->base.hubps[j] = dcn301_hubp_create(ctx, i);
1820 if (pool->base.hubps[j] == NULL) {
1821 BREAK_TO_DEBUGGER();
1822 dm_error(
1823 "DC: failed to create hubps!\n");
1824 goto create_fail;
1825 }
1826
1827 pool->base.dpps[j] = dcn301_dpp_create(ctx, i);
1828 if (pool->base.dpps[j] == NULL) {
1829 BREAK_TO_DEBUGGER();
1830 dm_error(
1831 "DC: failed to create dpps!\n");
1832 goto create_fail;
1833 }
1834
1835 pool->base.opps[j] = dcn301_opp_create(ctx, i);
1836 if (pool->base.opps[j] == NULL) {
1837 BREAK_TO_DEBUGGER();
1838 dm_error(
1839 "DC: failed to create output pixel processor!\n");
1840 goto create_fail;
1841 }
1842
1843 pool->base.timing_generators[j] = dcn301_timing_generator_create(ctx, i);
1844 if (pool->base.timing_generators[j] == NULL) {
1845 BREAK_TO_DEBUGGER();
1846 dm_error("DC: failed to create tg!\n");
1847 goto create_fail;
1848 }
1849 j++;
1850 }
1851 pool->base.timing_generator_count = j;
1852 pool->base.pipe_count = j;
1853 pool->base.mpcc_count = j;
1854
1855
1856
1857 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1858 pool->base.multiple_abms[i] = dmub_abm_create(ctx,
1859 &abm_regs[i],
1860 &abm_shift,
1861 &abm_mask);
1862 if (pool->base.multiple_abms[i] == NULL) {
1863 dm_error("DC: failed to create abm for pipe %d!\n", i);
1864 BREAK_TO_DEBUGGER();
1865 goto create_fail;
1866 }
1867 }
1868
1869
1870 pool->base.mpc = dcn301_mpc_create(ctx, pool->base.mpcc_count, pool->base.res_cap->num_mpc_3dlut);
1871 if (pool->base.mpc == NULL) {
1872 BREAK_TO_DEBUGGER();
1873 dm_error("DC: failed to create mpc!\n");
1874 goto create_fail;
1875 }
1876
1877 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1878 pool->base.dscs[i] = dcn301_dsc_create(ctx, i);
1879 if (pool->base.dscs[i] == NULL) {
1880 BREAK_TO_DEBUGGER();
1881 dm_error("DC: failed to create display stream compressor %d!\n", i);
1882 goto create_fail;
1883 }
1884 }
1885
1886
1887 if (!dcn301_dwbc_create(ctx, &pool->base)) {
1888 BREAK_TO_DEBUGGER();
1889 dm_error("DC: failed to create dwbc!\n");
1890 goto create_fail;
1891 }
1892
1893 if (!dcn301_mmhubbub_create(ctx, &pool->base)) {
1894 BREAK_TO_DEBUGGER();
1895 dm_error("DC: failed to create mcif_wb!\n");
1896 goto create_fail;
1897 }
1898
1899
1900 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1901 pool->base.engines[i] = dcn301_aux_engine_create(ctx, i);
1902 if (pool->base.engines[i] == NULL) {
1903 BREAK_TO_DEBUGGER();
1904 dm_error(
1905 "DC:failed to create aux engine!!\n");
1906 goto create_fail;
1907 }
1908 pool->base.hw_i2cs[i] = dcn301_i2c_hw_create(ctx, i);
1909 if (pool->base.hw_i2cs[i] == NULL) {
1910 BREAK_TO_DEBUGGER();
1911 dm_error(
1912 "DC:failed to create hw i2c!!\n");
1913 goto create_fail;
1914 }
1915 pool->base.sw_i2cs[i] = NULL;
1916 }
1917
1918
1919 if (!resource_construct(num_virtual_links, dc, &pool->base,
1920 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1921 &res_create_funcs : &res_create_maximus_funcs)))
1922 goto create_fail;
1923
1924
1925 dcn301_hw_sequencer_construct(dc);
1926
1927 dc->caps.max_planes = pool->base.pipe_count;
1928
1929 for (i = 0; i < dc->caps.max_planes; ++i)
1930 dc->caps.planes[i] = plane_cap;
1931
1932 dc->cap_funcs = cap_funcs;
1933
1934 return true;
1935
1936create_fail:
1937
1938 dcn301_destruct(pool);
1939
1940 return false;
1941}
1942
1943struct resource_pool *dcn301_create_resource_pool(
1944 const struct dc_init_data *init_data,
1945 struct dc *dc)
1946{
1947 struct dcn301_resource_pool *pool =
1948 kzalloc(sizeof(struct dcn301_resource_pool), GFP_KERNEL);
1949
1950 if (!pool)
1951 return NULL;
1952
1953 if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
1954 return &pool->base;
1955
1956 BREAK_TO_DEBUGGER();
1957 kfree(pool);
1958 return NULL;
1959}
1960
