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26#include "dcn302_init.h"
27#include "dcn302_resource.h"
28#include "dcn302_dccg.h"
29#include "irq/dcn302/irq_service_dcn302.h"
30
31#include "dcn30/dcn30_dio_link_encoder.h"
32#include "dcn30/dcn30_dio_stream_encoder.h"
33#include "dcn30/dcn30_dwb.h"
34#include "dcn30/dcn30_dpp.h"
35#include "dcn30/dcn30_hubbub.h"
36#include "dcn30/dcn30_hubp.h"
37#include "dcn30/dcn30_mmhubbub.h"
38#include "dcn30/dcn30_mpc.h"
39#include "dcn30/dcn30_opp.h"
40#include "dcn30/dcn30_optc.h"
41#include "dcn30/dcn30_resource.h"
42
43#include "dcn20/dcn20_dsc.h"
44#include "dcn20/dcn20_resource.h"
45
46#include "dcn10/dcn10_resource.h"
47
48#include "dce/dce_abm.h"
49#include "dce/dce_audio.h"
50#include "dce/dce_aux.h"
51#include "dce/dce_clock_source.h"
52#include "dce/dce_hwseq.h"
53#include "dce/dce_i2c_hw.h"
54#include "dce/dce_panel_cntl.h"
55#include "dce/dmub_abm.h"
56#include "dce/dmub_psr.h"
57#include "clk_mgr.h"
58
59#include "hw_sequencer_private.h"
60#include "reg_helper.h"
61#include "resource.h"
62#include "vm_helper.h"
63
64#include "dimgrey_cavefish_ip_offset.h"
65#include "dcn/dcn_3_0_2_offset.h"
66#include "dcn/dcn_3_0_2_sh_mask.h"
67#include "dcn/dpcs_3_0_0_offset.h"
68#include "dcn/dpcs_3_0_0_sh_mask.h"
69#include "nbio/nbio_7_4_offset.h"
70#include "amdgpu_socbb.h"
71
72#define DC_LOGGER_INIT(logger)
73
74struct _vcs_dpi_ip_params_st dcn3_02_ip = {
75 .use_min_dcfclk = 0,
76 .clamp_min_dcfclk = 0,
77 .odm_capable = 1,
78 .gpuvm_enable = 1,
79 .hostvm_enable = 0,
80 .gpuvm_max_page_table_levels = 4,
81 .hostvm_max_page_table_levels = 4,
82 .hostvm_cached_page_table_levels = 0,
83 .pte_group_size_bytes = 2048,
84 .num_dsc = 5,
85 .rob_buffer_size_kbytes = 184,
86 .det_buffer_size_kbytes = 184,
87 .dpte_buffer_size_in_pte_reqs_luma = 64,
88 .dpte_buffer_size_in_pte_reqs_chroma = 34,
89 .pde_proc_buffer_size_64k_reqs = 48,
90 .dpp_output_buffer_pixels = 2560,
91 .opp_output_buffer_lines = 1,
92 .pixel_chunk_size_kbytes = 8,
93 .pte_enable = 1,
94 .max_page_table_levels = 2,
95 .pte_chunk_size_kbytes = 2,
96 .meta_chunk_size_kbytes = 2,
97 .writeback_chunk_size_kbytes = 8,
98 .line_buffer_size_bits = 789504,
99 .is_line_buffer_bpp_fixed = 0,
100 .line_buffer_fixed_bpp = 0,
101 .dcc_supported = true,
102 .writeback_interface_buffer_size_kbytes = 90,
103 .writeback_line_buffer_buffer_size = 0,
104 .max_line_buffer_lines = 12,
105 .writeback_luma_buffer_size_kbytes = 12,
106 .writeback_chroma_buffer_size_kbytes = 8,
107 .writeback_chroma_line_buffer_width_pixels = 4,
108 .writeback_max_hscl_ratio = 1,
109 .writeback_max_vscl_ratio = 1,
110 .writeback_min_hscl_ratio = 1,
111 .writeback_min_vscl_ratio = 1,
112 .writeback_max_hscl_taps = 1,
113 .writeback_max_vscl_taps = 1,
114 .writeback_line_buffer_luma_buffer_size = 0,
115 .writeback_line_buffer_chroma_buffer_size = 14643,
116 .cursor_buffer_size = 8,
117 .cursor_chunk_size = 2,
118 .max_num_otg = 5,
119 .max_num_dpp = 5,
120 .max_num_wb = 1,
121 .max_dchub_pscl_bw_pix_per_clk = 4,
122 .max_pscl_lb_bw_pix_per_clk = 2,
123 .max_lb_vscl_bw_pix_per_clk = 4,
124 .max_vscl_hscl_bw_pix_per_clk = 4,
125 .max_hscl_ratio = 6,
126 .max_vscl_ratio = 6,
127 .hscl_mults = 4,
128 .vscl_mults = 4,
129 .max_hscl_taps = 8,
130 .max_vscl_taps = 8,
131 .dispclk_ramp_margin_percent = 1,
132 .underscan_factor = 1.11,
133 .min_vblank_lines = 32,
134 .dppclk_delay_subtotal = 46,
135 .dynamic_metadata_vm_enabled = true,
136 .dppclk_delay_scl_lb_only = 16,
137 .dppclk_delay_scl = 50,
138 .dppclk_delay_cnvc_formatter = 27,
139 .dppclk_delay_cnvc_cursor = 6,
140 .dispclk_delay_subtotal = 119,
141 .dcfclk_cstate_latency = 5.2,
142 .max_inter_dcn_tile_repeaters = 8,
143 .max_num_hdmi_frl_outputs = 1,
144 .odm_combine_4to1_supported = true,
145
146 .xfc_supported = false,
147 .xfc_fill_bw_overhead_percent = 10.0,
148 .xfc_fill_constant_bytes = 0,
149 .gfx7_compat_tiling_supported = 0,
150 .number_of_cursors = 1,
151};
152
153struct _vcs_dpi_soc_bounding_box_st dcn3_02_soc = {
154 .clock_limits = {
155 {
156 .state = 0,
157 .dispclk_mhz = 562.0,
158 .dppclk_mhz = 300.0,
159 .phyclk_mhz = 300.0,
160 .phyclk_d18_mhz = 667.0,
161 .dscclk_mhz = 405.6,
162 },
163 },
164
165 .min_dcfclk = 500.0,
166 .num_states = 1,
167 .sr_exit_time_us = 26.5,
168 .sr_enter_plus_exit_time_us = 31,
169 .urgent_latency_us = 4.0,
170 .urgent_latency_pixel_data_only_us = 4.0,
171 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
172 .urgent_latency_vm_data_only_us = 4.0,
173 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
174 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
175 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
176 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
177 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
178 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
179 .max_avg_sdp_bw_use_normal_percent = 60.0,
180 .max_avg_dram_bw_use_normal_percent = 40.0,
181 .writeback_latency_us = 12.0,
182 .max_request_size_bytes = 256,
183 .fabric_datapath_to_dcn_data_return_bytes = 64,
184 .dcn_downspread_percent = 0.5,
185 .downspread_percent = 0.38,
186 .dram_page_open_time_ns = 50.0,
187 .dram_rw_turnaround_time_ns = 17.5,
188 .dram_return_buffer_per_channel_bytes = 8192,
189 .round_trip_ping_latency_dcfclk_cycles = 156,
190 .urgent_out_of_order_return_per_channel_bytes = 4096,
191 .channel_interleave_bytes = 256,
192 .num_banks = 8,
193 .gpuvm_min_page_size_bytes = 4096,
194 .hostvm_min_page_size_bytes = 4096,
195 .dram_clock_change_latency_us = 404,
196 .dummy_pstate_latency_us = 5,
197 .writeback_dram_clock_change_latency_us = 23.0,
198 .return_bus_width_bytes = 64,
199 .dispclk_dppclk_vco_speed_mhz = 3650,
200 .xfc_bus_transport_time_us = 20,
201 .xfc_xbuf_latency_tolerance_us = 4,
202 .use_urgent_burst_bw = 1,
203 .do_urgent_latency_adjustment = true,
204 .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
205 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
206};
207
208static const struct dc_debug_options debug_defaults_drv = {
209 .disable_dmcu = true,
210 .force_abm_enable = false,
211 .timing_trace = false,
212 .clock_trace = true,
213 .disable_pplib_clock_request = true,
214 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
215 .force_single_disp_pipe_split = false,
216 .disable_dcc = DCC_ENABLE,
217 .vsr_support = true,
218 .performance_trace = false,
219 .max_downscale_src_width = 7680,
220 .disable_pplib_wm_range = false,
221 .scl_reset_length10 = true,
222 .sanity_checks = false,
223 .underflow_assert_delay_us = 0xFFFFFFFF,
224 .dwb_fi_phase = -1,
225 .dmub_command_table = true,
226 .use_max_lb = true
227};
228
229static const struct dc_debug_options debug_defaults_diags = {
230 .disable_dmcu = true,
231 .force_abm_enable = false,
232 .timing_trace = true,
233 .clock_trace = true,
234 .disable_dpp_power_gate = true,
235 .disable_hubp_power_gate = true,
236 .disable_clock_gate = true,
237 .disable_pplib_clock_request = true,
238 .disable_pplib_wm_range = true,
239 .disable_stutter = false,
240 .scl_reset_length10 = true,
241 .dwb_fi_phase = -1,
242 .dmub_command_table = true,
243 .enable_tri_buf = true,
244 .disable_psr = true,
245 .use_max_lb = true
246};
247
248enum dcn302_clk_src_array_id {
249 DCN302_CLK_SRC_PLL0,
250 DCN302_CLK_SRC_PLL1,
251 DCN302_CLK_SRC_PLL2,
252 DCN302_CLK_SRC_PLL3,
253 DCN302_CLK_SRC_PLL4,
254 DCN302_CLK_SRC_TOTAL
255};
256
257static const struct resource_caps res_cap_dcn302 = {
258 .num_timing_generator = 5,
259 .num_opp = 5,
260 .num_video_plane = 5,
261 .num_audio = 5,
262 .num_stream_encoder = 5,
263 .num_dwb = 1,
264 .num_ddc = 5,
265 .num_vmid = 16,
266 .num_mpc_3dlut = 2,
267 .num_dsc = 5,
268};
269
270static const struct dc_plane_cap plane_cap = {
271 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
272 .blends_with_above = true,
273 .blends_with_below = true,
274 .per_pixel_alpha = true,
275 .pixel_format_support = {
276 .argb8888 = true,
277 .nv12 = true,
278 .fp16 = true,
279 .p010 = false,
280 .ayuv = false,
281 },
282 .max_upscale_factor = {
283 .argb8888 = 16000,
284 .nv12 = 16000,
285 .fp16 = 16000
286 },
287
288 .max_downscale_factor = {
289 .argb8888 = 167,
290 .nv12 = 167,
291 .fp16 = 167
292 },
293 16,
294 16
295};
296
297
298#define NBIO_BASE_INNER(seg) \
299 NBIO_BASE__INST0_SEG ## seg
300
301#define NBIO_BASE(seg) \
302 NBIO_BASE_INNER(seg)
303
304#define NBIO_SR(reg_name)\
305 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
306 mm ## reg_name
307
308
309#undef BASE_INNER
310#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
311
312#define BASE(seg) BASE_INNER(seg)
313
314#define SR(reg_name)\
315 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
316
317#define SF(reg_name, field_name, post_fix)\
318 .field_name = reg_name ## __ ## field_name ## post_fix
319
320#define SRI(reg_name, block, id)\
321 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
322
323#define SRI2(reg_name, block, id)\
324 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
325
326#define SRII(reg_name, block, id)\
327 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
328 mm ## block ## id ## _ ## reg_name
329
330#define DCCG_SRII(reg_name, block, id)\
331 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
332 mm ## block ## id ## _ ## reg_name
333
334#define VUPDATE_SRII(reg_name, block, id)\
335 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
336 mm ## reg_name ## _ ## block ## id
337
338#define SRII_DWB(reg_name, temp_name, block, id)\
339 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
340 mm ## block ## id ## _ ## temp_name
341
342#define SRII_MPC_RMU(reg_name, block, id)\
343 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
344 mm ## block ## id ## _ ## reg_name
345
346static const struct dcn_hubbub_registers hubbub_reg = {
347 HUBBUB_REG_LIST_DCN30(0)
348};
349
350static const struct dcn_hubbub_shift hubbub_shift = {
351 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
352};
353
354static const struct dcn_hubbub_mask hubbub_mask = {
355 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
356};
357
358#define vmid_regs(id)\
359 [id] = { DCN20_VMID_REG_LIST(id) }
360
361static const struct dcn_vmid_registers vmid_regs[] = {
362 vmid_regs(0),
363 vmid_regs(1),
364 vmid_regs(2),
365 vmid_regs(3),
366 vmid_regs(4),
367 vmid_regs(5),
368 vmid_regs(6),
369 vmid_regs(7),
370 vmid_regs(8),
371 vmid_regs(9),
372 vmid_regs(10),
373 vmid_regs(11),
374 vmid_regs(12),
375 vmid_regs(13),
376 vmid_regs(14),
377 vmid_regs(15)
378};
379
380static const struct dcn20_vmid_shift vmid_shifts = {
381 DCN20_VMID_MASK_SH_LIST(__SHIFT)
382};
383
384static const struct dcn20_vmid_mask vmid_masks = {
385 DCN20_VMID_MASK_SH_LIST(_MASK)
386};
387
388static struct hubbub *dcn302_hubbub_create(struct dc_context *ctx)
389{
390 int i;
391
392 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
393
394 if (!hubbub3)
395 return NULL;
396
397 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
398
399 for (i = 0; i < res_cap_dcn302.num_vmid; i++) {
400 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
401
402 vmid->ctx = ctx;
403
404 vmid->regs = &vmid_regs[i];
405 vmid->shifts = &vmid_shifts;
406 vmid->masks = &vmid_masks;
407 }
408
409 return &hubbub3->base;
410}
411
412#define vpg_regs(id)\
413 [id] = { VPG_DCN3_REG_LIST(id) }
414
415static const struct dcn30_vpg_registers vpg_regs[] = {
416 vpg_regs(0),
417 vpg_regs(1),
418 vpg_regs(2),
419 vpg_regs(3),
420 vpg_regs(4),
421 vpg_regs(5)
422};
423
424static const struct dcn30_vpg_shift vpg_shift = {
425 DCN3_VPG_MASK_SH_LIST(__SHIFT)
426};
427
428static const struct dcn30_vpg_mask vpg_mask = {
429 DCN3_VPG_MASK_SH_LIST(_MASK)
430};
431
432static struct vpg *dcn302_vpg_create(struct dc_context *ctx, uint32_t inst)
433{
434 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
435
436 if (!vpg3)
437 return NULL;
438
439 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
440
441 return &vpg3->base;
442}
443
444#define afmt_regs(id)\
445 [id] = { AFMT_DCN3_REG_LIST(id) }
446
447static const struct dcn30_afmt_registers afmt_regs[] = {
448 afmt_regs(0),
449 afmt_regs(1),
450 afmt_regs(2),
451 afmt_regs(3),
452 afmt_regs(4),
453 afmt_regs(5)
454};
455
456static const struct dcn30_afmt_shift afmt_shift = {
457 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
458};
459
460static const struct dcn30_afmt_mask afmt_mask = {
461 DCN3_AFMT_MASK_SH_LIST(_MASK)
462};
463
464static struct afmt *dcn302_afmt_create(struct dc_context *ctx, uint32_t inst)
465{
466 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
467
468 if (!afmt3)
469 return NULL;
470
471 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
472
473 return &afmt3->base;
474}
475
476#define audio_regs(id)\
477 [id] = { AUD_COMMON_REG_LIST(id) }
478
479static const struct dce_audio_registers audio_regs[] = {
480 audio_regs(0),
481 audio_regs(1),
482 audio_regs(2),
483 audio_regs(3),
484 audio_regs(4),
485 audio_regs(5),
486 audio_regs(6)
487};
488
489#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
490 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
491 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
492 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
493
494static const struct dce_audio_shift audio_shift = {
495 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
496};
497
498static const struct dce_audio_mask audio_mask = {
499 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
500};
501
502static struct audio *dcn302_create_audio(struct dc_context *ctx, unsigned int inst)
503{
504 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
505}
506
507#define stream_enc_regs(id)\
508 [id] = { SE_DCN3_REG_LIST(id) }
509
510static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
511 stream_enc_regs(0),
512 stream_enc_regs(1),
513 stream_enc_regs(2),
514 stream_enc_regs(3),
515 stream_enc_regs(4)
516};
517
518static const struct dcn10_stream_encoder_shift se_shift = {
519 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
520};
521
522static const struct dcn10_stream_encoder_mask se_mask = {
523 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
524};
525
526static struct stream_encoder *dcn302_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
527{
528 struct dcn10_stream_encoder *enc1;
529 struct vpg *vpg;
530 struct afmt *afmt;
531 int vpg_inst;
532 int afmt_inst;
533
534
535 if (eng_id <= ENGINE_ID_DIGE) {
536 vpg_inst = eng_id;
537 afmt_inst = eng_id;
538 } else
539 return NULL;
540
541 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
542 vpg = dcn302_vpg_create(ctx, vpg_inst);
543 afmt = dcn302_afmt_create(ctx, afmt_inst);
544
545 if (!enc1 || !vpg || !afmt)
546 return NULL;
547
548 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
549 &se_shift, &se_mask);
550
551 return &enc1->base;
552}
553
554#define clk_src_regs(index, pllid)\
555 [index] = { CS_COMMON_REG_LIST_DCN3_02(index, pllid) }
556
557static const struct dce110_clk_src_regs clk_src_regs[] = {
558 clk_src_regs(0, A),
559 clk_src_regs(1, B),
560 clk_src_regs(2, C),
561 clk_src_regs(3, D),
562 clk_src_regs(4, E)
563};
564
565static const struct dce110_clk_src_shift cs_shift = {
566 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
567};
568
569static const struct dce110_clk_src_mask cs_mask = {
570 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
571};
572
573static struct clock_source *dcn302_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
574 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
575{
576 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
577
578 if (!clk_src)
579 return NULL;
580
581 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
582 clk_src->base.dp_clk_src = dp_clk_src;
583 return &clk_src->base;
584 }
585
586 BREAK_TO_DEBUGGER();
587 return NULL;
588}
589
590static const struct dce_hwseq_registers hwseq_reg = {
591 HWSEQ_DCN302_REG_LIST()
592};
593
594static const struct dce_hwseq_shift hwseq_shift = {
595 HWSEQ_DCN302_MASK_SH_LIST(__SHIFT)
596};
597
598static const struct dce_hwseq_mask hwseq_mask = {
599 HWSEQ_DCN302_MASK_SH_LIST(_MASK)
600};
601
602static struct dce_hwseq *dcn302_hwseq_create(struct dc_context *ctx)
603{
604 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
605
606 if (hws) {
607 hws->ctx = ctx;
608 hws->regs = &hwseq_reg;
609 hws->shifts = &hwseq_shift;
610 hws->masks = &hwseq_mask;
611 }
612 return hws;
613}
614
615#define hubp_regs(id)\
616 [id] = { HUBP_REG_LIST_DCN30(id) }
617
618static const struct dcn_hubp2_registers hubp_regs[] = {
619 hubp_regs(0),
620 hubp_regs(1),
621 hubp_regs(2),
622 hubp_regs(3),
623 hubp_regs(4)
624};
625
626static const struct dcn_hubp2_shift hubp_shift = {
627 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
628};
629
630static const struct dcn_hubp2_mask hubp_mask = {
631 HUBP_MASK_SH_LIST_DCN30(_MASK)
632};
633
634static struct hubp *dcn302_hubp_create(struct dc_context *ctx, uint32_t inst)
635{
636 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
637
638 if (!hubp2)
639 return NULL;
640
641 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
642 return &hubp2->base;
643
644 BREAK_TO_DEBUGGER();
645 kfree(hubp2);
646 return NULL;
647}
648
649#define dpp_regs(id)\
650 [id] = { DPP_REG_LIST_DCN30(id) }
651
652static const struct dcn3_dpp_registers dpp_regs[] = {
653 dpp_regs(0),
654 dpp_regs(1),
655 dpp_regs(2),
656 dpp_regs(3),
657 dpp_regs(4)
658};
659
660static const struct dcn3_dpp_shift tf_shift = {
661 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
662};
663
664static const struct dcn3_dpp_mask tf_mask = {
665 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
666};
667
668static struct dpp *dcn302_dpp_create(struct dc_context *ctx, uint32_t inst)
669{
670 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
671
672 if (!dpp)
673 return NULL;
674
675 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
676 return &dpp->base;
677
678 BREAK_TO_DEBUGGER();
679 kfree(dpp);
680 return NULL;
681}
682
683#define opp_regs(id)\
684 [id] = { OPP_REG_LIST_DCN30(id) }
685
686static const struct dcn20_opp_registers opp_regs[] = {
687 opp_regs(0),
688 opp_regs(1),
689 opp_regs(2),
690 opp_regs(3),
691 opp_regs(4)
692};
693
694static const struct dcn20_opp_shift opp_shift = {
695 OPP_MASK_SH_LIST_DCN20(__SHIFT)
696};
697
698static const struct dcn20_opp_mask opp_mask = {
699 OPP_MASK_SH_LIST_DCN20(_MASK)
700};
701
702static struct output_pixel_processor *dcn302_opp_create(struct dc_context *ctx, uint32_t inst)
703{
704 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
705
706 if (!opp) {
707 BREAK_TO_DEBUGGER();
708 return NULL;
709 }
710
711 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
712 return &opp->base;
713}
714
715#define optc_regs(id)\
716 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
717
718static const struct dcn_optc_registers optc_regs[] = {
719 optc_regs(0),
720 optc_regs(1),
721 optc_regs(2),
722 optc_regs(3),
723 optc_regs(4)
724};
725
726static const struct dcn_optc_shift optc_shift = {
727 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
728};
729
730static const struct dcn_optc_mask optc_mask = {
731 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
732};
733
734static struct timing_generator *dcn302_timing_generator_create(struct dc_context *ctx, uint32_t instance)
735{
736 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
737
738 if (!tgn10)
739 return NULL;
740
741 tgn10->base.inst = instance;
742 tgn10->base.ctx = ctx;
743
744 tgn10->tg_regs = &optc_regs[instance];
745 tgn10->tg_shift = &optc_shift;
746 tgn10->tg_mask = &optc_mask;
747
748 dcn30_timing_generator_init(tgn10);
749
750 return &tgn10->base;
751}
752
753static const struct dcn30_mpc_registers mpc_regs = {
754 MPC_REG_LIST_DCN3_0(0),
755 MPC_REG_LIST_DCN3_0(1),
756 MPC_REG_LIST_DCN3_0(2),
757 MPC_REG_LIST_DCN3_0(3),
758 MPC_REG_LIST_DCN3_0(4),
759 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
760 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
761 MPC_OUT_MUX_REG_LIST_DCN3_0(2),
762 MPC_OUT_MUX_REG_LIST_DCN3_0(3),
763 MPC_OUT_MUX_REG_LIST_DCN3_0(4),
764 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
765 MPC_RMU_REG_LIST_DCN3AG(0),
766 MPC_RMU_REG_LIST_DCN3AG(1),
767 MPC_RMU_REG_LIST_DCN3AG(2),
768 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
769};
770
771static const struct dcn30_mpc_shift mpc_shift = {
772 MPC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
773};
774
775static const struct dcn30_mpc_mask mpc_mask = {
776 MPC_COMMON_MASK_SH_LIST_DCN30(_MASK)
777};
778
779static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
780{
781 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
782
783 if (!mpc30)
784 return NULL;
785
786 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
787
788 return &mpc30->base;
789}
790
791#define dsc_regsDCN20(id)\
792[id] = { DSC_REG_LIST_DCN20(id) }
793
794static const struct dcn20_dsc_registers dsc_regs[] = {
795 dsc_regsDCN20(0),
796 dsc_regsDCN20(1),
797 dsc_regsDCN20(2),
798 dsc_regsDCN20(3),
799 dsc_regsDCN20(4)
800};
801
802static const struct dcn20_dsc_shift dsc_shift = {
803 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
804};
805
806static const struct dcn20_dsc_mask dsc_mask = {
807 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
808};
809
810static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ctx, uint32_t inst)
811{
812 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
813
814 if (!dsc) {
815 BREAK_TO_DEBUGGER();
816 return NULL;
817 }
818
819 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
820 return &dsc->base;
821}
822
823#define dwbc_regs_dcn3(id)\
824[id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
825
826static const struct dcn30_dwbc_registers dwbc30_regs[] = {
827 dwbc_regs_dcn3(0)
828};
829
830static const struct dcn30_dwbc_shift dwbc30_shift = {
831 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
832};
833
834static const struct dcn30_dwbc_mask dwbc30_mask = {
835 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
836};
837
838static bool dcn302_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
839{
840 int i;
841 uint32_t pipe_count = pool->res_cap->num_dwb;
842
843 for (i = 0; i < pipe_count; i++) {
844 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
845
846 if (!dwbc30) {
847 dm_error("DC: failed to create dwbc30!\n");
848 return false;
849 }
850
851 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
852
853 pool->dwbc[i] = &dwbc30->base;
854 }
855 return true;
856}
857
858#define mcif_wb_regs_dcn3(id)\
859[id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
860
861static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
862 mcif_wb_regs_dcn3(0)
863};
864
865static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
866 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
867};
868
869static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
870 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
871};
872
873static bool dcn302_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
874{
875 int i;
876 uint32_t pipe_count = pool->res_cap->num_dwb;
877
878 for (i = 0; i < pipe_count; i++) {
879 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
880
881 if (!mcif_wb30) {
882 dm_error("DC: failed to create mcif_wb30!\n");
883 return false;
884 }
885
886 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
887
888 pool->mcif_wb[i] = &mcif_wb30->base;
889 }
890 return true;
891}
892
893#define aux_engine_regs(id)\
894[id] = {\
895 AUX_COMMON_REG_LIST0(id), \
896 .AUXN_IMPCAL = 0, \
897 .AUXP_IMPCAL = 0, \
898 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
899}
900
901static const struct dce110_aux_registers aux_engine_regs[] = {
902 aux_engine_regs(0),
903 aux_engine_regs(1),
904 aux_engine_regs(2),
905 aux_engine_regs(3),
906 aux_engine_regs(4)
907};
908
909static const struct dce110_aux_registers_shift aux_shift = {
910 DCN_AUX_MASK_SH_LIST(__SHIFT)
911};
912
913static const struct dce110_aux_registers_mask aux_mask = {
914 DCN_AUX_MASK_SH_LIST(_MASK)
915};
916
917static struct dce_aux *dcn302_aux_engine_create(struct dc_context *ctx, uint32_t inst)
918{
919 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
920
921 if (!aux_engine)
922 return NULL;
923
924 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
925 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
926
927 return &aux_engine->base;
928}
929
930#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
931
932static const struct dce_i2c_registers i2c_hw_regs[] = {
933 i2c_inst_regs(1),
934 i2c_inst_regs(2),
935 i2c_inst_regs(3),
936 i2c_inst_regs(4),
937 i2c_inst_regs(5)
938};
939
940static const struct dce_i2c_shift i2c_shifts = {
941 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
942};
943
944static const struct dce_i2c_mask i2c_masks = {
945 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
946};
947
948static struct dce_i2c_hw *dcn302_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
949{
950 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
951
952 if (!dce_i2c_hw)
953 return NULL;
954
955 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
956
957 return dce_i2c_hw;
958}
959
960static const struct encoder_feature_support link_enc_feature = {
961 .max_hdmi_deep_color = COLOR_DEPTH_121212,
962 .max_hdmi_pixel_clock = 600000,
963 .hdmi_ycbcr420_supported = true,
964 .dp_ycbcr420_supported = true,
965 .fec_supported = true,
966 .flags.bits.IS_HBR2_CAPABLE = true,
967 .flags.bits.IS_HBR3_CAPABLE = true,
968 .flags.bits.IS_TPS3_CAPABLE = true,
969 .flags.bits.IS_TPS4_CAPABLE = true
970};
971
972#define link_regs(id, phyid)\
973 [id] = {\
974 LE_DCN3_REG_LIST(id), \
975 UNIPHY_DCN2_REG_LIST(phyid), \
976 DPCS_DCN2_REG_LIST(id), \
977 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
978 }
979
980static const struct dcn10_link_enc_registers link_enc_regs[] = {
981 link_regs(0, A),
982 link_regs(1, B),
983 link_regs(2, C),
984 link_regs(3, D),
985 link_regs(4, E)
986};
987
988static const struct dcn10_link_enc_shift le_shift = {
989 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
990 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
991};
992
993static const struct dcn10_link_enc_mask le_mask = {
994 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
995 DPCS_DCN2_MASK_SH_LIST(_MASK)
996};
997
998#define aux_regs(id)\
999 [id] = { DCN2_AUX_REG_LIST(id) }
1000
1001static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1002 aux_regs(0),
1003 aux_regs(1),
1004 aux_regs(2),
1005 aux_regs(3),
1006 aux_regs(4)
1007};
1008
1009#define hpd_regs(id)\
1010 [id] = { HPD_REG_LIST(id) }
1011
1012static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1013 hpd_regs(0),
1014 hpd_regs(1),
1015 hpd_regs(2),
1016 hpd_regs(3),
1017 hpd_regs(4)
1018};
1019
1020static struct link_encoder *dcn302_link_encoder_create(const struct encoder_init_data *enc_init_data)
1021{
1022 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1023
1024 if (!enc20)
1025 return NULL;
1026
1027 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
1028 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
1029 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
1030
1031 return &enc20->enc10.base;
1032}
1033
1034static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1035 { DCN_PANEL_CNTL_REG_LIST() }
1036};
1037
1038static const struct dce_panel_cntl_shift panel_cntl_shift = {
1039 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1040};
1041
1042static const struct dce_panel_cntl_mask panel_cntl_mask = {
1043 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1044};
1045
1046static struct panel_cntl *dcn302_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1047{
1048 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1049
1050 if (!panel_cntl)
1051 return NULL;
1052
1053 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
1054 &panel_cntl_shift, &panel_cntl_mask);
1055
1056 return &panel_cntl->base;
1057}
1058
1059static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
1060{
1061 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1062 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1063}
1064
1065static const struct resource_create_funcs res_create_funcs = {
1066 .read_dce_straps = read_dce_straps,
1067 .create_audio = dcn302_create_audio,
1068 .create_stream_encoder = dcn302_stream_encoder_create,
1069 .create_hwseq = dcn302_hwseq_create,
1070};
1071
1072static const struct resource_create_funcs res_create_maximus_funcs = {
1073 .read_dce_straps = NULL,
1074 .create_audio = NULL,
1075 .create_stream_encoder = NULL,
1076 .create_hwseq = dcn302_hwseq_create,
1077};
1078
1079static bool is_soc_bounding_box_valid(struct dc *dc)
1080{
1081 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1082
1083 if (ASICREV_IS_DIMGREY_CAVEFISH_P(hw_internal_rev))
1084 return true;
1085
1086 return false;
1087}
1088
1089static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
1090{
1091 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_02_soc;
1092 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_02_ip;
1093
1094 DC_LOGGER_INIT(dc->ctx->logger);
1095
1096 if (!is_soc_bounding_box_valid(dc)) {
1097 DC_LOG_ERROR("%s: not valid soc bounding box\n", __func__);
1098 return false;
1099 }
1100
1101 loaded_ip->max_num_otg = pool->pipe_count;
1102 loaded_ip->max_num_dpp = pool->pipe_count;
1103 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1104 dcn20_patch_bounding_box(dc, loaded_bb);
1105
1106 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1107 struct bp_soc_bb_info bb_info = { 0 };
1108
1109 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
1110 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1111 if (bb_info.dram_clock_change_latency_100ns > 0)
1112 dcn3_02_soc.dram_clock_change_latency_us =
1113 bb_info.dram_clock_change_latency_100ns * 10;
1114
1115 if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1116 dcn3_02_soc.sr_enter_plus_exit_time_us =
1117 bb_info.dram_sr_enter_exit_latency_100ns * 10;
1118
1119 if (bb_info.dram_sr_exit_latency_100ns > 0)
1120 dcn3_02_soc.sr_exit_time_us =
1121 bb_info.dram_sr_exit_latency_100ns * 10;
1122 }
1123 }
1124
1125 return true;
1126}
1127
1128static void dcn302_resource_destruct(struct resource_pool *pool)
1129{
1130 unsigned int i;
1131
1132 for (i = 0; i < pool->stream_enc_count; i++) {
1133 if (pool->stream_enc[i] != NULL) {
1134 if (pool->stream_enc[i]->vpg != NULL) {
1135 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
1136 pool->stream_enc[i]->vpg = NULL;
1137 }
1138 if (pool->stream_enc[i]->afmt != NULL) {
1139 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1140 pool->stream_enc[i]->afmt = NULL;
1141 }
1142 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1143 pool->stream_enc[i] = NULL;
1144 }
1145 }
1146
1147 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1148 if (pool->dscs[i] != NULL)
1149 dcn20_dsc_destroy(&pool->dscs[i]);
1150 }
1151
1152 if (pool->mpc != NULL) {
1153 kfree(TO_DCN20_MPC(pool->mpc));
1154 pool->mpc = NULL;
1155 }
1156
1157 if (pool->hubbub != NULL) {
1158 kfree(pool->hubbub);
1159 pool->hubbub = NULL;
1160 }
1161
1162 for (i = 0; i < pool->pipe_count; i++) {
1163 if (pool->dpps[i] != NULL) {
1164 kfree(TO_DCN20_DPP(pool->dpps[i]));
1165 pool->dpps[i] = NULL;
1166 }
1167
1168 if (pool->hubps[i] != NULL) {
1169 kfree(TO_DCN20_HUBP(pool->hubps[i]));
1170 pool->hubps[i] = NULL;
1171 }
1172
1173 if (pool->irqs != NULL)
1174 dal_irq_service_destroy(&pool->irqs);
1175 }
1176
1177 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1178 if (pool->engines[i] != NULL)
1179 dce110_engine_destroy(&pool->engines[i]);
1180 if (pool->hw_i2cs[i] != NULL) {
1181 kfree(pool->hw_i2cs[i]);
1182 pool->hw_i2cs[i] = NULL;
1183 }
1184 if (pool->sw_i2cs[i] != NULL) {
1185 kfree(pool->sw_i2cs[i]);
1186 pool->sw_i2cs[i] = NULL;
1187 }
1188 }
1189
1190 for (i = 0; i < pool->res_cap->num_opp; i++) {
1191 if (pool->opps[i] != NULL)
1192 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1193 }
1194
1195 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1196 if (pool->timing_generators[i] != NULL) {
1197 kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1198 pool->timing_generators[i] = NULL;
1199 }
1200 }
1201
1202 for (i = 0; i < pool->res_cap->num_dwb; i++) {
1203 if (pool->dwbc[i] != NULL) {
1204 kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1205 pool->dwbc[i] = NULL;
1206 }
1207 if (pool->mcif_wb[i] != NULL) {
1208 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1209 pool->mcif_wb[i] = NULL;
1210 }
1211 }
1212
1213 for (i = 0; i < pool->audio_count; i++) {
1214 if (pool->audios[i])
1215 dce_aud_destroy(&pool->audios[i]);
1216 }
1217
1218 for (i = 0; i < pool->clk_src_count; i++) {
1219 if (pool->clock_sources[i] != NULL)
1220 dcn20_clock_source_destroy(&pool->clock_sources[i]);
1221 }
1222
1223 if (pool->dp_clock_source != NULL)
1224 dcn20_clock_source_destroy(&pool->dp_clock_source);
1225
1226 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1227 if (pool->mpc_lut[i] != NULL) {
1228 dc_3dlut_func_release(pool->mpc_lut[i]);
1229 pool->mpc_lut[i] = NULL;
1230 }
1231 if (pool->mpc_shaper[i] != NULL) {
1232 dc_transfer_func_release(pool->mpc_shaper[i]);
1233 pool->mpc_shaper[i] = NULL;
1234 }
1235 }
1236
1237 for (i = 0; i < pool->pipe_count; i++) {
1238 if (pool->multiple_abms[i] != NULL)
1239 dce_abm_destroy(&pool->multiple_abms[i]);
1240 }
1241
1242 if (pool->psr != NULL)
1243 dmub_psr_destroy(&pool->psr);
1244
1245 if (pool->dccg != NULL)
1246 dcn_dccg_destroy(&pool->dccg);
1247}
1248
1249static void dcn302_destroy_resource_pool(struct resource_pool **pool)
1250{
1251 dcn302_resource_destruct(*pool);
1252 kfree(*pool);
1253 *pool = NULL;
1254}
1255
1256static void dcn302_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
1257 unsigned int *optimal_dcfclk,
1258 unsigned int *optimal_fclk)
1259{
1260 double bw_from_dram, bw_from_dram1, bw_from_dram2;
1261
1262 bw_from_dram1 = uclk_mts * dcn3_02_soc.num_chans *
1263 dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_dram_bw_use_normal_percent / 100);
1264 bw_from_dram2 = uclk_mts * dcn3_02_soc.num_chans *
1265 dcn3_02_soc.dram_channel_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100);
1266
1267 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
1268
1269 if (optimal_fclk)
1270 *optimal_fclk = bw_from_dram /
1271 (dcn3_02_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100));
1272
1273 if (optimal_dcfclk)
1274 *optimal_dcfclk = bw_from_dram /
1275 (dcn3_02_soc.return_bus_width_bytes * (dcn3_02_soc.max_avg_sdp_bw_use_normal_percent / 100));
1276}
1277
1278void dcn302_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1279{
1280 unsigned int i, j;
1281 unsigned int num_states = 0;
1282
1283 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
1284 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
1285 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
1286 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
1287
1288 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
1289 unsigned int num_dcfclk_sta_targets = 4;
1290 unsigned int num_uclk_states;
1291
1292
1293 if (dc->ctx->dc_bios->vram_info.num_chans)
1294 dcn3_02_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
1295
1296 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
1297 dcn3_02_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
1298
1299 dcn3_02_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1300 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1301
1302 if (bw_params->clk_table.entries[0].memclk_mhz) {
1303 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
1304
1305 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
1306 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
1307 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
1308 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
1309 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
1310 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
1311 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
1312 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
1313 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
1314 }
1315 if (!max_dcfclk_mhz)
1316 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz;
1317 if (!max_dispclk_mhz)
1318 max_dispclk_mhz = dcn3_02_soc.clock_limits[0].dispclk_mhz;
1319 if (!max_dppclk_mhz)
1320 max_dppclk_mhz = dcn3_02_soc.clock_limits[0].dppclk_mhz;
1321 if (!max_phyclk_mhz)
1322 max_phyclk_mhz = dcn3_02_soc.clock_limits[0].phyclk_mhz;
1323
1324 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1325
1326 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
1327 num_dcfclk_sta_targets++;
1328 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1329
1330 for (i = 0; i < num_dcfclk_sta_targets; i++) {
1331 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
1332 dcfclk_sta_targets[i] = max_dcfclk_mhz;
1333 break;
1334 }
1335 }
1336
1337 num_dcfclk_sta_targets = i + 1;
1338 }
1339
1340 num_uclk_states = bw_params->clk_table.num_entries;
1341
1342
1343 for (i = 0; i < num_uclk_states; i++) {
1344 dcn302_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
1345 &optimal_dcfclk_for_uclk[i], NULL);
1346 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
1347 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
1348 }
1349 }
1350
1351
1352 for (i = 0; i < num_dcfclk_sta_targets; i++) {
1353 for (j = 0; j < num_uclk_states; j++) {
1354 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
1355 optimal_uclk_for_dcfclk_sta_targets[i] =
1356 bw_params->clk_table.entries[j].memclk_mhz * 16;
1357 break;
1358 }
1359 }
1360 }
1361
1362 i = 0;
1363 j = 0;
1364
1365 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
1366 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
1367 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1368 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1369 } else {
1370 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1371 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1372 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
1373 } else {
1374 j = num_uclk_states;
1375 }
1376 }
1377 }
1378
1379 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
1380 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1381 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1382 }
1383
1384 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
1385 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1386 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1387 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
1388 }
1389
1390 dcn3_02_soc.num_states = num_states;
1391 for (i = 0; i < dcn3_02_soc.num_states; i++) {
1392 dcn3_02_soc.clock_limits[i].state = i;
1393 dcn3_02_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
1394 dcn3_02_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
1395 dcn3_02_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
1396
1397
1398 dcn3_02_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
1399 dcn3_02_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
1400 dcn3_02_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
1401
1402 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
1403 dcn3_02_soc.clock_limits[i].dtbclk_mhz = dcn3_02_soc.clock_limits[i-1].dtbclk_mhz;
1404 else
1405 dcn3_02_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
1406 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
1407 dcn3_02_soc.clock_limits[i].socclk_mhz = dcn3_02_soc.clock_limits[i-1].socclk_mhz;
1408 else
1409 dcn3_02_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
1410
1411
1412 dcn3_02_soc.clock_limits[i].phyclk_d18_mhz = dcn3_02_soc.clock_limits[0].phyclk_d18_mhz;
1413 dcn3_02_soc.clock_limits[i].dscclk_mhz = dcn3_02_soc.clock_limits[0].dscclk_mhz;
1414 }
1415
1416 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1417 if (dc->current_state)
1418 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1419 }
1420}
1421
1422static struct resource_funcs dcn302_res_pool_funcs = {
1423 .destroy = dcn302_destroy_resource_pool,
1424 .link_enc_create = dcn302_link_encoder_create,
1425 .panel_cntl_create = dcn302_panel_cntl_create,
1426 .validate_bandwidth = dcn30_validate_bandwidth,
1427 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1428 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1429 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1430 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1431 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1432 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1433 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1434 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1435 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1436 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1437 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1438 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1439 .update_bw_bounding_box = dcn302_update_bw_bounding_box,
1440 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1441};
1442
1443static struct dc_cap_funcs cap_funcs = {
1444 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1445};
1446
1447static const struct bios_registers bios_regs = {
1448 NBIO_SR(BIOS_SCRATCH_3),
1449 NBIO_SR(BIOS_SCRATCH_6)
1450};
1451
1452static const struct dccg_registers dccg_regs = {
1453 DCCG_REG_LIST_DCN3_02()
1454};
1455
1456static const struct dccg_shift dccg_shift = {
1457 DCCG_MASK_SH_LIST_DCN3_02(__SHIFT)
1458};
1459
1460static const struct dccg_mask dccg_mask = {
1461 DCCG_MASK_SH_LIST_DCN3_02(_MASK)
1462};
1463
1464#define abm_regs(id)\
1465 [id] = { ABM_DCN301_REG_LIST(id) }
1466
1467static const struct dce_abm_registers abm_regs[] = {
1468 abm_regs(0),
1469 abm_regs(1),
1470 abm_regs(2),
1471 abm_regs(3),
1472 abm_regs(4)
1473};
1474
1475static const struct dce_abm_shift abm_shift = {
1476 ABM_MASK_SH_LIST_DCN30(__SHIFT)
1477};
1478
1479static const struct dce_abm_mask abm_mask = {
1480 ABM_MASK_SH_LIST_DCN30(_MASK)
1481};
1482
1483static bool dcn302_resource_construct(
1484 uint8_t num_virtual_links,
1485 struct dc *dc,
1486 struct resource_pool *pool)
1487{
1488 int i;
1489 struct dc_context *ctx = dc->ctx;
1490 struct irq_service_init_data init_data;
1491
1492 ctx->dc_bios->regs = &bios_regs;
1493
1494 pool->res_cap = &res_cap_dcn302;
1495
1496 pool->funcs = &dcn302_res_pool_funcs;
1497
1498
1499
1500
1501 pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1502 pool->pipe_count = pool->res_cap->num_timing_generator;
1503 pool->mpcc_count = pool->res_cap->num_timing_generator;
1504 dc->caps.max_downscale_ratio = 600;
1505 dc->caps.i2c_speed_in_khz = 100;
1506 dc->caps.i2c_speed_in_khz_hdcp = 5;
1507 dc->caps.max_cursor_size = 256;
1508 dc->caps.min_horizontal_blanking_period = 80;
1509 dc->caps.dmdata_alloc_size = 2048;
1510 dc->caps.mall_size_per_mem_channel = 4;
1511
1512 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1513 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1514 dc->caps.max_slave_planes = 1;
1515 dc->caps.max_slave_yuv_planes = 1;
1516 dc->caps.max_slave_rgb_planes = 1;
1517 dc->caps.post_blend_color_processing = true;
1518 dc->caps.force_dp_tps4_for_cp2520 = true;
1519 dc->caps.extended_aux_timeout_support = true;
1520 dc->caps.dmcub_support = true;
1521
1522
1523 dc->caps.color.dpp.dcn_arch = 1;
1524 dc->caps.color.dpp.input_lut_shared = 0;
1525 dc->caps.color.dpp.icsc = 1;
1526 dc->caps.color.dpp.dgam_ram = 0;
1527 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1528 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1529 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1530 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1531 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1532 dc->caps.color.dpp.post_csc = 1;
1533 dc->caps.color.dpp.gamma_corr = 1;
1534 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1535
1536 dc->caps.color.dpp.hw_3d_lut = 1;
1537 dc->caps.color.dpp.ogam_ram = 1;
1538
1539 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1540 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1541 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1542 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1543 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1544 dc->caps.color.dpp.ocsc = 0;
1545
1546 dc->caps.color.mpc.gamut_remap = 1;
1547 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut;
1548 dc->caps.color.mpc.ogam_ram = 1;
1549 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1550 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1551 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1552 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1553 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1554 dc->caps.color.mpc.ocsc = 1;
1555
1556 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1557 dc->debug = debug_defaults_drv;
1558 else
1559 dc->debug = debug_defaults_diags;
1560
1561
1562 if (dc->vm_helper)
1563 vm_helper_init(dc->vm_helper, 16);
1564
1565
1566
1567
1568
1569
1570 pool->clock_sources[DCN302_CLK_SRC_PLL0] =
1571 dcn302_clock_source_create(ctx, ctx->dc_bios,
1572 CLOCK_SOURCE_COMBO_PHY_PLL0,
1573 &clk_src_regs[0], false);
1574 pool->clock_sources[DCN302_CLK_SRC_PLL1] =
1575 dcn302_clock_source_create(ctx, ctx->dc_bios,
1576 CLOCK_SOURCE_COMBO_PHY_PLL1,
1577 &clk_src_regs[1], false);
1578 pool->clock_sources[DCN302_CLK_SRC_PLL2] =
1579 dcn302_clock_source_create(ctx, ctx->dc_bios,
1580 CLOCK_SOURCE_COMBO_PHY_PLL2,
1581 &clk_src_regs[2], false);
1582 pool->clock_sources[DCN302_CLK_SRC_PLL3] =
1583 dcn302_clock_source_create(ctx, ctx->dc_bios,
1584 CLOCK_SOURCE_COMBO_PHY_PLL3,
1585 &clk_src_regs[3], false);
1586 pool->clock_sources[DCN302_CLK_SRC_PLL4] =
1587 dcn302_clock_source_create(ctx, ctx->dc_bios,
1588 CLOCK_SOURCE_COMBO_PHY_PLL4,
1589 &clk_src_regs[4], false);
1590
1591 pool->clk_src_count = DCN302_CLK_SRC_TOTAL;
1592
1593
1594 pool->dp_clock_source =
1595 dcn302_clock_source_create(ctx, ctx->dc_bios,
1596 CLOCK_SOURCE_ID_DP_DTO,
1597 &clk_src_regs[0], true);
1598
1599 for (i = 0; i < pool->clk_src_count; i++) {
1600 if (pool->clock_sources[i] == NULL) {
1601 dm_error("DC: failed to create clock sources!\n");
1602 BREAK_TO_DEBUGGER();
1603 goto create_fail;
1604 }
1605 }
1606
1607
1608 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1609 if (pool->dccg == NULL) {
1610 dm_error("DC: failed to create dccg!\n");
1611 BREAK_TO_DEBUGGER();
1612 goto create_fail;
1613 }
1614
1615
1616 init_soc_bounding_box(dc, pool);
1617
1618
1619 dml_init_instance(&dc->dml, &dcn3_02_soc, &dcn3_02_ip, DML_PROJECT_DCN30);
1620
1621
1622 init_data.ctx = dc->ctx;
1623 pool->irqs = dal_irq_service_dcn302_create(&init_data);
1624 if (!pool->irqs)
1625 goto create_fail;
1626
1627
1628 pool->hubbub = dcn302_hubbub_create(ctx);
1629 if (pool->hubbub == NULL) {
1630 BREAK_TO_DEBUGGER();
1631 dm_error("DC: failed to create hubbub!\n");
1632 goto create_fail;
1633 }
1634
1635
1636 for (i = 0; i < pool->pipe_count; i++) {
1637 pool->hubps[i] = dcn302_hubp_create(ctx, i);
1638 if (pool->hubps[i] == NULL) {
1639 BREAK_TO_DEBUGGER();
1640 dm_error("DC: failed to create hubps!\n");
1641 goto create_fail;
1642 }
1643
1644 pool->dpps[i] = dcn302_dpp_create(ctx, i);
1645 if (pool->dpps[i] == NULL) {
1646 BREAK_TO_DEBUGGER();
1647 dm_error("DC: failed to create dpps!\n");
1648 goto create_fail;
1649 }
1650 }
1651
1652 for (i = 0; i < pool->res_cap->num_opp; i++) {
1653 pool->opps[i] = dcn302_opp_create(ctx, i);
1654 if (pool->opps[i] == NULL) {
1655 BREAK_TO_DEBUGGER();
1656 dm_error("DC: failed to create output pixel processor!\n");
1657 goto create_fail;
1658 }
1659 }
1660
1661 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1662 pool->timing_generators[i] = dcn302_timing_generator_create(ctx, i);
1663 if (pool->timing_generators[i] == NULL) {
1664 BREAK_TO_DEBUGGER();
1665 dm_error("DC: failed to create tg!\n");
1666 goto create_fail;
1667 }
1668 }
1669 pool->timing_generator_count = i;
1670
1671
1672 pool->psr = dmub_psr_create(ctx);
1673 if (pool->psr == NULL) {
1674 dm_error("DC: failed to create psr!\n");
1675 BREAK_TO_DEBUGGER();
1676 goto create_fail;
1677 }
1678
1679
1680 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1681 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1682 if (pool->multiple_abms[i] == NULL) {
1683 dm_error("DC: failed to create abm for pipe %d!\n", i);
1684 BREAK_TO_DEBUGGER();
1685 goto create_fail;
1686 }
1687 }
1688
1689
1690 pool->mpc = dcn302_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1691 if (pool->mpc == NULL) {
1692 BREAK_TO_DEBUGGER();
1693 dm_error("DC: failed to create mpc!\n");
1694 goto create_fail;
1695 }
1696
1697 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1698 pool->dscs[i] = dcn302_dsc_create(ctx, i);
1699 if (pool->dscs[i] == NULL) {
1700 BREAK_TO_DEBUGGER();
1701 dm_error("DC: failed to create display stream compressor %d!\n", i);
1702 goto create_fail;
1703 }
1704 }
1705
1706
1707 if (!dcn302_dwbc_create(ctx, pool)) {
1708 BREAK_TO_DEBUGGER();
1709 dm_error("DC: failed to create dwbc!\n");
1710 goto create_fail;
1711 }
1712
1713 if (!dcn302_mmhubbub_create(ctx, pool)) {
1714 BREAK_TO_DEBUGGER();
1715 dm_error("DC: failed to create mcif_wb!\n");
1716 goto create_fail;
1717 }
1718
1719
1720 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1721 pool->engines[i] = dcn302_aux_engine_create(ctx, i);
1722 if (pool->engines[i] == NULL) {
1723 BREAK_TO_DEBUGGER();
1724 dm_error("DC:failed to create aux engine!!\n");
1725 goto create_fail;
1726 }
1727 pool->hw_i2cs[i] = dcn302_i2c_hw_create(ctx, i);
1728 if (pool->hw_i2cs[i] == NULL) {
1729 BREAK_TO_DEBUGGER();
1730 dm_error("DC:failed to create hw i2c!!\n");
1731 goto create_fail;
1732 }
1733 pool->sw_i2cs[i] = NULL;
1734 }
1735
1736
1737 if (!resource_construct(num_virtual_links, dc, pool,
1738 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1739 &res_create_funcs : &res_create_maximus_funcs)))
1740 goto create_fail;
1741
1742
1743 dcn302_hw_sequencer_construct(dc);
1744
1745 dc->caps.max_planes = pool->pipe_count;
1746
1747 for (i = 0; i < dc->caps.max_planes; ++i)
1748 dc->caps.planes[i] = plane_cap;
1749
1750 dc->cap_funcs = cap_funcs;
1751
1752 return true;
1753
1754create_fail:
1755
1756 dcn302_resource_destruct(pool);
1757
1758 return false;
1759}
1760
1761struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1762{
1763 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1764
1765 if (!pool)
1766 return NULL;
1767
1768 if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
1769 return pool;
1770
1771 BREAK_TO_DEBUGGER();
1772 kfree(pool);
1773 return NULL;
1774}
1775
