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8#include "dcn303_init.h"
9#include "dcn303_resource.h"
10#include "dcn303_dccg.h"
11#include "irq/dcn303/irq_service_dcn303.h"
12
13#include "dcn30/dcn30_dio_link_encoder.h"
14#include "dcn30/dcn30_dio_stream_encoder.h"
15#include "dcn30/dcn30_dpp.h"
16#include "dcn30/dcn30_dwb.h"
17#include "dcn30/dcn30_hubbub.h"
18#include "dcn30/dcn30_hubp.h"
19#include "dcn30/dcn30_mmhubbub.h"
20#include "dcn30/dcn30_mpc.h"
21#include "dcn30/dcn30_opp.h"
22#include "dcn30/dcn30_optc.h"
23#include "dcn30/dcn30_resource.h"
24
25#include "dcn20/dcn20_dsc.h"
26#include "dcn20/dcn20_resource.h"
27
28#include "dcn10/dcn10_resource.h"
29
30#include "dc_link_ddc.h"
31
32#include "dce/dce_abm.h"
33#include "dce/dce_audio.h"
34#include "dce/dce_aux.h"
35#include "dce/dce_clock_source.h"
36#include "dce/dce_hwseq.h"
37#include "dce/dce_i2c_hw.h"
38#include "dce/dce_panel_cntl.h"
39#include "dce/dmub_abm.h"
40#include "dce/dmub_psr.h"
41#include "clk_mgr.h"
42
43#include "hw_sequencer_private.h"
44#include "reg_helper.h"
45#include "resource.h"
46#include "vm_helper.h"
47
48#include "sienna_cichlid_ip_offset.h"
49#include "dcn/dcn_3_0_3_offset.h"
50#include "dcn/dcn_3_0_3_sh_mask.h"
51#include "dcn/dpcs_3_0_3_offset.h"
52#include "dcn/dpcs_3_0_3_sh_mask.h"
53#include "nbio/nbio_2_3_offset.h"
54
55#define DC_LOGGER_INIT(logger)
56
57struct _vcs_dpi_ip_params_st dcn3_03_ip = {
58 .use_min_dcfclk = 0,
59 .clamp_min_dcfclk = 0,
60 .odm_capable = 1,
61 .gpuvm_enable = 1,
62 .hostvm_enable = 0,
63 .gpuvm_max_page_table_levels = 4,
64 .hostvm_max_page_table_levels = 4,
65 .hostvm_cached_page_table_levels = 0,
66 .pte_group_size_bytes = 2048,
67 .num_dsc = 2,
68 .rob_buffer_size_kbytes = 184,
69 .det_buffer_size_kbytes = 184,
70 .dpte_buffer_size_in_pte_reqs_luma = 64,
71 .dpte_buffer_size_in_pte_reqs_chroma = 34,
72 .pde_proc_buffer_size_64k_reqs = 48,
73 .dpp_output_buffer_pixels = 2560,
74 .opp_output_buffer_lines = 1,
75 .pixel_chunk_size_kbytes = 8,
76 .pte_enable = 1,
77 .max_page_table_levels = 2,
78 .pte_chunk_size_kbytes = 2,
79 .meta_chunk_size_kbytes = 2,
80 .writeback_chunk_size_kbytes = 8,
81 .line_buffer_size_bits = 789504,
82 .is_line_buffer_bpp_fixed = 0,
83 .line_buffer_fixed_bpp = 0,
84 .dcc_supported = true,
85 .writeback_interface_buffer_size_kbytes = 90,
86 .writeback_line_buffer_buffer_size = 0,
87 .max_line_buffer_lines = 12,
88 .writeback_luma_buffer_size_kbytes = 12,
89 .writeback_chroma_buffer_size_kbytes = 8,
90 .writeback_chroma_line_buffer_width_pixels = 4,
91 .writeback_max_hscl_ratio = 1,
92 .writeback_max_vscl_ratio = 1,
93 .writeback_min_hscl_ratio = 1,
94 .writeback_min_vscl_ratio = 1,
95 .writeback_max_hscl_taps = 1,
96 .writeback_max_vscl_taps = 1,
97 .writeback_line_buffer_luma_buffer_size = 0,
98 .writeback_line_buffer_chroma_buffer_size = 14643,
99 .cursor_buffer_size = 8,
100 .cursor_chunk_size = 2,
101 .max_num_otg = 2,
102 .max_num_dpp = 2,
103 .max_num_wb = 1,
104 .max_dchub_pscl_bw_pix_per_clk = 4,
105 .max_pscl_lb_bw_pix_per_clk = 2,
106 .max_lb_vscl_bw_pix_per_clk = 4,
107 .max_vscl_hscl_bw_pix_per_clk = 4,
108 .max_hscl_ratio = 6,
109 .max_vscl_ratio = 6,
110 .hscl_mults = 4,
111 .vscl_mults = 4,
112 .max_hscl_taps = 8,
113 .max_vscl_taps = 8,
114 .dispclk_ramp_margin_percent = 1,
115 .underscan_factor = 1.11,
116 .min_vblank_lines = 32,
117 .dppclk_delay_subtotal = 46,
118 .dynamic_metadata_vm_enabled = true,
119 .dppclk_delay_scl_lb_only = 16,
120 .dppclk_delay_scl = 50,
121 .dppclk_delay_cnvc_formatter = 27,
122 .dppclk_delay_cnvc_cursor = 6,
123 .dispclk_delay_subtotal = 119,
124 .dcfclk_cstate_latency = 5.2,
125 .max_inter_dcn_tile_repeaters = 8,
126 .max_num_hdmi_frl_outputs = 1,
127 .odm_combine_4to1_supported = false,
128 .xfc_supported = false,
129 .xfc_fill_bw_overhead_percent = 10.0,
130 .xfc_fill_constant_bytes = 0,
131 .gfx7_compat_tiling_supported = 0,
132 .number_of_cursors = 1,
133};
134
135struct _vcs_dpi_soc_bounding_box_st dcn3_03_soc = {
136 .clock_limits = {
137 {
138 .state = 0,
139 .dispclk_mhz = 1217.0,
140 .dppclk_mhz = 1217.0,
141 .phyclk_mhz = 810.0,
142 .phyclk_d18_mhz = 667.0,
143 .dscclk_mhz = 405.6,
144 },
145 },
146
147 .min_dcfclk = 500.0,
148 .num_states = 1,
149 .sr_exit_time_us = 35.5,
150 .sr_enter_plus_exit_time_us = 40,
151 .urgent_latency_us = 4.0,
152 .urgent_latency_pixel_data_only_us = 4.0,
153 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
154 .urgent_latency_vm_data_only_us = 4.0,
155 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
156 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
157 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
158 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
159 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 60.0,
160 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
161 .max_avg_sdp_bw_use_normal_percent = 60.0,
162 .max_avg_dram_bw_use_normal_percent = 40.0,
163 .writeback_latency_us = 12.0,
164 .max_request_size_bytes = 256,
165 .fabric_datapath_to_dcn_data_return_bytes = 64,
166 .dcn_downspread_percent = 0.5,
167 .downspread_percent = 0.38,
168 .dram_page_open_time_ns = 50.0,
169 .dram_rw_turnaround_time_ns = 17.5,
170 .dram_return_buffer_per_channel_bytes = 8192,
171 .round_trip_ping_latency_dcfclk_cycles = 156,
172 .urgent_out_of_order_return_per_channel_bytes = 4096,
173 .channel_interleave_bytes = 256,
174 .num_banks = 8,
175 .gpuvm_min_page_size_bytes = 4096,
176 .hostvm_min_page_size_bytes = 4096,
177 .dram_clock_change_latency_us = 404,
178 .dummy_pstate_latency_us = 5,
179 .writeback_dram_clock_change_latency_us = 23.0,
180 .return_bus_width_bytes = 64,
181 .dispclk_dppclk_vco_speed_mhz = 3650,
182 .xfc_bus_transport_time_us = 20,
183 .xfc_xbuf_latency_tolerance_us = 4,
184 .use_urgent_burst_bw = 1,
185 .do_urgent_latency_adjustment = true,
186 .urgent_latency_adjustment_fabric_clock_component_us = 1.0,
187 .urgent_latency_adjustment_fabric_clock_reference_mhz = 1000,
188};
189
190static const struct dc_debug_options debug_defaults_drv = {
191 .disable_dmcu = true,
192 .force_abm_enable = false,
193 .timing_trace = false,
194 .clock_trace = true,
195 .disable_pplib_clock_request = true,
196 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
197 .force_single_disp_pipe_split = false,
198 .disable_dcc = DCC_ENABLE,
199 .vsr_support = true,
200 .performance_trace = false,
201 .max_downscale_src_width = 7680,
202 .disable_pplib_wm_range = false,
203 .scl_reset_length10 = true,
204 .sanity_checks = false,
205 .underflow_assert_delay_us = 0xFFFFFFFF,
206 .dwb_fi_phase = -1,
207 .dmub_command_table = true,
208 .disable_idle_power_optimizations = false,
209};
210
211static const struct dc_debug_options debug_defaults_diags = {
212 .disable_dmcu = true,
213 .force_abm_enable = false,
214 .timing_trace = true,
215 .clock_trace = true,
216 .disable_dpp_power_gate = true,
217 .disable_hubp_power_gate = true,
218 .disable_clock_gate = true,
219 .disable_pplib_clock_request = true,
220 .disable_pplib_wm_range = true,
221 .disable_stutter = false,
222 .scl_reset_length10 = true,
223 .dwb_fi_phase = -1,
224 .dmub_command_table = true,
225 .enable_tri_buf = true,
226 .disable_psr = true,
227};
228
229enum dcn303_clk_src_array_id {
230 DCN303_CLK_SRC_PLL0,
231 DCN303_CLK_SRC_PLL1,
232 DCN303_CLK_SRC_TOTAL
233};
234
235static const struct resource_caps res_cap_dcn303 = {
236 .num_timing_generator = 2,
237 .num_opp = 2,
238 .num_video_plane = 2,
239 .num_audio = 2,
240 .num_stream_encoder = 2,
241 .num_dwb = 1,
242 .num_ddc = 2,
243 .num_vmid = 16,
244 .num_mpc_3dlut = 1,
245 .num_dsc = 2,
246};
247
248static const struct dc_plane_cap plane_cap = {
249 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
250 .blends_with_above = true,
251 .blends_with_below = true,
252 .per_pixel_alpha = true,
253 .pixel_format_support = {
254 .argb8888 = true,
255 .nv12 = true,
256 .fp16 = true,
257 .p010 = false,
258 .ayuv = false,
259 },
260 .max_upscale_factor = {
261 .argb8888 = 16000,
262 .nv12 = 16000,
263 .fp16 = 16000
264 },
265 .max_downscale_factor = {
266 .argb8888 = 600,
267 .nv12 = 600,
268 .fp16 = 600
269 },
270 16,
271 16
272};
273
274
275#define NBIO_BASE_INNER(seg) \
276 NBIO_BASE__INST0_SEG ## seg
277
278#define NBIO_BASE(seg) \
279 NBIO_BASE_INNER(seg)
280
281#define NBIO_SR(reg_name)\
282 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
283 mm ## reg_name
284
285
286#undef BASE_INNER
287#define BASE_INNER(seg) DCN_BASE__INST0_SEG ## seg
288
289#define BASE(seg) BASE_INNER(seg)
290
291#define SR(reg_name)\
292 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
293
294#define SF(reg_name, field_name, post_fix)\
295 .field_name = reg_name ## __ ## field_name ## post_fix
296
297#define SRI(reg_name, block, id)\
298 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + mm ## block ## id ## _ ## reg_name
299
300#define SRI2(reg_name, block, id)\
301 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + mm ## reg_name
302
303#define SRII(reg_name, block, id)\
304 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
305 mm ## block ## id ## _ ## reg_name
306
307#define DCCG_SRII(reg_name, block, id)\
308 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
309 mm ## block ## id ## _ ## reg_name
310
311#define VUPDATE_SRII(reg_name, block, id)\
312 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
313 mm ## reg_name ## _ ## block ## id
314
315#define SRII_DWB(reg_name, temp_name, block, id)\
316 .reg_name[id] = BASE(mm ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
317 mm ## block ## id ## _ ## temp_name
318
319#define SRII_MPC_RMU(reg_name, block, id)\
320 .RMU##_##reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
321 mm ## block ## id ## _ ## reg_name
322
323static const struct dcn_hubbub_registers hubbub_reg = {
324 HUBBUB_REG_LIST_DCN30(0)
325};
326
327static const struct dcn_hubbub_shift hubbub_shift = {
328 HUBBUB_MASK_SH_LIST_DCN30(__SHIFT)
329};
330
331static const struct dcn_hubbub_mask hubbub_mask = {
332 HUBBUB_MASK_SH_LIST_DCN30(_MASK)
333};
334
335#define vmid_regs(id)\
336 [id] = { DCN20_VMID_REG_LIST(id) }
337
338static const struct dcn_vmid_registers vmid_regs[] = {
339 vmid_regs(0),
340 vmid_regs(1),
341 vmid_regs(2),
342 vmid_regs(3),
343 vmid_regs(4),
344 vmid_regs(5),
345 vmid_regs(6),
346 vmid_regs(7),
347 vmid_regs(8),
348 vmid_regs(9),
349 vmid_regs(10),
350 vmid_regs(11),
351 vmid_regs(12),
352 vmid_regs(13),
353 vmid_regs(14),
354 vmid_regs(15)
355};
356
357static const struct dcn20_vmid_shift vmid_shifts = {
358 DCN20_VMID_MASK_SH_LIST(__SHIFT)
359};
360
361static const struct dcn20_vmid_mask vmid_masks = {
362 DCN20_VMID_MASK_SH_LIST(_MASK)
363};
364
365static struct hubbub *dcn303_hubbub_create(struct dc_context *ctx)
366{
367 int i;
368
369 struct dcn20_hubbub *hubbub3 = kzalloc(sizeof(struct dcn20_hubbub), GFP_KERNEL);
370
371 if (!hubbub3)
372 return NULL;
373
374 hubbub3_construct(hubbub3, ctx, &hubbub_reg, &hubbub_shift, &hubbub_mask);
375
376 for (i = 0; i < res_cap_dcn303.num_vmid; i++) {
377 struct dcn20_vmid *vmid = &hubbub3->vmid[i];
378
379 vmid->ctx = ctx;
380
381 vmid->regs = &vmid_regs[i];
382 vmid->shifts = &vmid_shifts;
383 vmid->masks = &vmid_masks;
384 }
385
386 return &hubbub3->base;
387}
388
389#define vpg_regs(id)\
390 [id] = { VPG_DCN3_REG_LIST(id) }
391
392static const struct dcn30_vpg_registers vpg_regs[] = {
393 vpg_regs(0),
394 vpg_regs(1),
395 vpg_regs(2)
396};
397
398static const struct dcn30_vpg_shift vpg_shift = {
399 DCN3_VPG_MASK_SH_LIST(__SHIFT)
400};
401
402static const struct dcn30_vpg_mask vpg_mask = {
403 DCN3_VPG_MASK_SH_LIST(_MASK)
404};
405
406static struct vpg *dcn303_vpg_create(struct dc_context *ctx, uint32_t inst)
407{
408 struct dcn30_vpg *vpg3 = kzalloc(sizeof(struct dcn30_vpg), GFP_KERNEL);
409
410 if (!vpg3)
411 return NULL;
412
413 vpg3_construct(vpg3, ctx, inst, &vpg_regs[inst], &vpg_shift, &vpg_mask);
414
415 return &vpg3->base;
416}
417
418#define afmt_regs(id)\
419 [id] = { AFMT_DCN3_REG_LIST(id) }
420
421static const struct dcn30_afmt_registers afmt_regs[] = {
422 afmt_regs(0),
423 afmt_regs(1),
424 afmt_regs(2)
425};
426
427static const struct dcn30_afmt_shift afmt_shift = {
428 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
429};
430
431static const struct dcn30_afmt_mask afmt_mask = {
432 DCN3_AFMT_MASK_SH_LIST(_MASK)
433};
434
435static struct afmt *dcn303_afmt_create(struct dc_context *ctx, uint32_t inst)
436{
437 struct dcn30_afmt *afmt3 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
438
439 if (!afmt3)
440 return NULL;
441
442 afmt3_construct(afmt3, ctx, inst, &afmt_regs[inst], &afmt_shift, &afmt_mask);
443
444 return &afmt3->base;
445}
446
447#define audio_regs(id)\
448 [id] = { AUD_COMMON_REG_LIST(id) }
449
450static const struct dce_audio_registers audio_regs[] = {
451 audio_regs(0),
452 audio_regs(1),
453 audio_regs(2),
454 audio_regs(3),
455 audio_regs(4),
456 audio_regs(5),
457 audio_regs(6)
458};
459
460#define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
461 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
462 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
463 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
464
465static const struct dce_audio_shift audio_shift = {
466 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
467};
468
469static const struct dce_audio_mask audio_mask = {
470 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
471};
472
473static struct audio *dcn303_create_audio(struct dc_context *ctx, unsigned int inst)
474{
475 return dce_audio_create(ctx, inst, &audio_regs[inst], &audio_shift, &audio_mask);
476}
477
478#define stream_enc_regs(id)\
479 [id] = { SE_DCN3_REG_LIST(id) }
480
481static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
482 stream_enc_regs(0),
483 stream_enc_regs(1)
484};
485
486static const struct dcn10_stream_encoder_shift se_shift = {
487 SE_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
488};
489
490static const struct dcn10_stream_encoder_mask se_mask = {
491 SE_COMMON_MASK_SH_LIST_DCN30(_MASK)
492};
493
494static struct stream_encoder *dcn303_stream_encoder_create(enum engine_id eng_id, struct dc_context *ctx)
495{
496 struct dcn10_stream_encoder *enc1;
497 struct vpg *vpg;
498 struct afmt *afmt;
499 int vpg_inst;
500 int afmt_inst;
501
502
503 if (eng_id <= ENGINE_ID_DIGE) {
504 vpg_inst = eng_id;
505 afmt_inst = eng_id;
506 } else
507 return NULL;
508
509 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
510 vpg = dcn303_vpg_create(ctx, vpg_inst);
511 afmt = dcn303_afmt_create(ctx, afmt_inst);
512
513 if (!enc1 || !vpg || !afmt) {
514 kfree(enc1);
515 kfree(vpg);
516 kfree(afmt);
517 return NULL;
518 }
519
520 dcn30_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id, vpg, afmt, &stream_enc_regs[eng_id],
521 &se_shift, &se_mask);
522
523 return &enc1->base;
524}
525
526#define clk_src_regs(index, pllid)\
527 [index] = { CS_COMMON_REG_LIST_DCN3_03(index, pllid) }
528
529static const struct dce110_clk_src_regs clk_src_regs[] = {
530 clk_src_regs(0, A),
531 clk_src_regs(1, B)
532};
533
534static const struct dce110_clk_src_shift cs_shift = {
535 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
536};
537
538static const struct dce110_clk_src_mask cs_mask = {
539 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
540};
541
542static struct clock_source *dcn303_clock_source_create(struct dc_context *ctx, struct dc_bios *bios,
543 enum clock_source_id id, const struct dce110_clk_src_regs *regs, bool dp_clk_src)
544{
545 struct dce110_clk_src *clk_src = kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
546
547 if (!clk_src)
548 return NULL;
549
550 if (dcn3_clk_src_construct(clk_src, ctx, bios, id, regs, &cs_shift, &cs_mask)) {
551 clk_src->base.dp_clk_src = dp_clk_src;
552 return &clk_src->base;
553 }
554
555 BREAK_TO_DEBUGGER();
556 return NULL;
557}
558
559static const struct dce_hwseq_registers hwseq_reg = {
560 HWSEQ_DCN303_REG_LIST()
561};
562
563static const struct dce_hwseq_shift hwseq_shift = {
564 HWSEQ_DCN303_MASK_SH_LIST(__SHIFT)
565};
566
567static const struct dce_hwseq_mask hwseq_mask = {
568 HWSEQ_DCN303_MASK_SH_LIST(_MASK)
569};
570
571static struct dce_hwseq *dcn303_hwseq_create(struct dc_context *ctx)
572{
573 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
574
575 if (hws) {
576 hws->ctx = ctx;
577 hws->regs = &hwseq_reg;
578 hws->shifts = &hwseq_shift;
579 hws->masks = &hwseq_mask;
580 }
581 return hws;
582}
583
584#define hubp_regs(id)\
585 [id] = { HUBP_REG_LIST_DCN30(id) }
586
587static const struct dcn_hubp2_registers hubp_regs[] = {
588 hubp_regs(0),
589 hubp_regs(1)
590};
591
592static const struct dcn_hubp2_shift hubp_shift = {
593 HUBP_MASK_SH_LIST_DCN30(__SHIFT)
594};
595
596static const struct dcn_hubp2_mask hubp_mask = {
597 HUBP_MASK_SH_LIST_DCN30(_MASK)
598};
599
600static struct hubp *dcn303_hubp_create(struct dc_context *ctx, uint32_t inst)
601{
602 struct dcn20_hubp *hubp2 = kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
603
604 if (!hubp2)
605 return NULL;
606
607 if (hubp3_construct(hubp2, ctx, inst, &hubp_regs[inst], &hubp_shift, &hubp_mask))
608 return &hubp2->base;
609
610 BREAK_TO_DEBUGGER();
611 kfree(hubp2);
612 return NULL;
613}
614
615#define dpp_regs(id)\
616 [id] = { DPP_REG_LIST_DCN30(id) }
617
618static const struct dcn3_dpp_registers dpp_regs[] = {
619 dpp_regs(0),
620 dpp_regs(1)
621};
622
623static const struct dcn3_dpp_shift tf_shift = {
624 DPP_REG_LIST_SH_MASK_DCN30(__SHIFT)
625};
626
627static const struct dcn3_dpp_mask tf_mask = {
628 DPP_REG_LIST_SH_MASK_DCN30(_MASK)
629};
630
631static struct dpp *dcn303_dpp_create(struct dc_context *ctx, uint32_t inst)
632{
633 struct dcn3_dpp *dpp = kzalloc(sizeof(struct dcn3_dpp), GFP_KERNEL);
634
635 if (!dpp)
636 return NULL;
637
638 if (dpp3_construct(dpp, ctx, inst, &dpp_regs[inst], &tf_shift, &tf_mask))
639 return &dpp->base;
640
641 BREAK_TO_DEBUGGER();
642 kfree(dpp);
643 return NULL;
644}
645
646#define opp_regs(id)\
647 [id] = { OPP_REG_LIST_DCN30(id) }
648
649static const struct dcn20_opp_registers opp_regs[] = {
650 opp_regs(0),
651 opp_regs(1)
652};
653
654static const struct dcn20_opp_shift opp_shift = {
655 OPP_MASK_SH_LIST_DCN20(__SHIFT)
656};
657
658static const struct dcn20_opp_mask opp_mask = {
659 OPP_MASK_SH_LIST_DCN20(_MASK)
660};
661
662static struct output_pixel_processor *dcn303_opp_create(struct dc_context *ctx, uint32_t inst)
663{
664 struct dcn20_opp *opp = kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
665
666 if (!opp) {
667 BREAK_TO_DEBUGGER();
668 return NULL;
669 }
670
671 dcn20_opp_construct(opp, ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
672 return &opp->base;
673}
674
675#define optc_regs(id)\
676 [id] = { OPTC_COMMON_REG_LIST_DCN3_0(id) }
677
678static const struct dcn_optc_registers optc_regs[] = {
679 optc_regs(0),
680 optc_regs(1)
681};
682
683static const struct dcn_optc_shift optc_shift = {
684 OPTC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
685};
686
687static const struct dcn_optc_mask optc_mask = {
688 OPTC_COMMON_MASK_SH_LIST_DCN30(_MASK)
689};
690
691static struct timing_generator *dcn303_timing_generator_create(struct dc_context *ctx, uint32_t instance)
692{
693 struct optc *tgn10 = kzalloc(sizeof(struct optc), GFP_KERNEL);
694
695 if (!tgn10)
696 return NULL;
697
698 tgn10->base.inst = instance;
699 tgn10->base.ctx = ctx;
700
701 tgn10->tg_regs = &optc_regs[instance];
702 tgn10->tg_shift = &optc_shift;
703 tgn10->tg_mask = &optc_mask;
704
705 dcn30_timing_generator_init(tgn10);
706
707 return &tgn10->base;
708}
709
710static const struct dcn30_mpc_registers mpc_regs = {
711 MPC_REG_LIST_DCN3_0(0),
712 MPC_REG_LIST_DCN3_0(1),
713 MPC_OUT_MUX_REG_LIST_DCN3_0(0),
714 MPC_OUT_MUX_REG_LIST_DCN3_0(1),
715 MPC_RMU_GLOBAL_REG_LIST_DCN3AG,
716 MPC_RMU_REG_LIST_DCN3AG(0),
717 MPC_DWB_MUX_REG_LIST_DCN3_0(0),
718};
719
720static const struct dcn30_mpc_shift mpc_shift = {
721 MPC_COMMON_MASK_SH_LIST_DCN303(__SHIFT)
722};
723
724static const struct dcn30_mpc_mask mpc_mask = {
725 MPC_COMMON_MASK_SH_LIST_DCN303(_MASK)
726};
727
728static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int num_rmu)
729{
730 struct dcn30_mpc *mpc30 = kzalloc(sizeof(struct dcn30_mpc), GFP_KERNEL);
731
732 if (!mpc30)
733 return NULL;
734
735 dcn30_mpc_construct(mpc30, ctx, &mpc_regs, &mpc_shift, &mpc_mask, num_mpcc, num_rmu);
736
737 return &mpc30->base;
738}
739
740#define dsc_regsDCN20(id)\
741[id] = { DSC_REG_LIST_DCN20(id) }
742
743static const struct dcn20_dsc_registers dsc_regs[] = {
744 dsc_regsDCN20(0),
745 dsc_regsDCN20(1)
746};
747
748static const struct dcn20_dsc_shift dsc_shift = {
749 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
750};
751
752static const struct dcn20_dsc_mask dsc_mask = {
753 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
754};
755
756static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ctx, uint32_t inst)
757{
758 struct dcn20_dsc *dsc = kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
759
760 if (!dsc) {
761 BREAK_TO_DEBUGGER();
762 return NULL;
763 }
764
765 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
766 return &dsc->base;
767}
768
769#define dwbc_regs_dcn3(id)\
770[id] = { DWBC_COMMON_REG_LIST_DCN30(id) }
771
772static const struct dcn30_dwbc_registers dwbc30_regs[] = {
773 dwbc_regs_dcn3(0)
774};
775
776static const struct dcn30_dwbc_shift dwbc30_shift = {
777 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
778};
779
780static const struct dcn30_dwbc_mask dwbc30_mask = {
781 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
782};
783
784static bool dcn303_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
785{
786 int i;
787 uint32_t pipe_count = pool->res_cap->num_dwb;
788
789 for (i = 0; i < pipe_count; i++) {
790 struct dcn30_dwbc *dwbc30 = kzalloc(sizeof(struct dcn30_dwbc), GFP_KERNEL);
791
792 if (!dwbc30) {
793 dm_error("DC: failed to create dwbc30!\n");
794 return false;
795 }
796
797 dcn30_dwbc_construct(dwbc30, ctx, &dwbc30_regs[i], &dwbc30_shift, &dwbc30_mask, i);
798
799 pool->dwbc[i] = &dwbc30->base;
800 }
801 return true;
802}
803
804#define mcif_wb_regs_dcn3(id)\
805[id] = { MCIF_WB_COMMON_REG_LIST_DCN30(id) }
806
807static const struct dcn30_mmhubbub_registers mcif_wb30_regs[] = {
808 mcif_wb_regs_dcn3(0)
809};
810
811static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
812 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
813};
814
815static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
816 MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK)
817};
818
819static bool dcn303_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
820{
821 int i;
822 uint32_t pipe_count = pool->res_cap->num_dwb;
823
824 for (i = 0; i < pipe_count; i++) {
825 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub), GFP_KERNEL);
826
827 if (!mcif_wb30) {
828 dm_error("DC: failed to create mcif_wb30!\n");
829 return false;
830 }
831
832 dcn30_mmhubbub_construct(mcif_wb30, ctx, &mcif_wb30_regs[i], &mcif_wb30_shift, &mcif_wb30_mask, i);
833
834 pool->mcif_wb[i] = &mcif_wb30->base;
835 }
836 return true;
837}
838
839#define aux_engine_regs(id)\
840[id] = {\
841 AUX_COMMON_REG_LIST0(id), \
842 .AUXN_IMPCAL = 0, \
843 .AUXP_IMPCAL = 0, \
844 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
845}
846
847static const struct dce110_aux_registers aux_engine_regs[] = {
848 aux_engine_regs(0),
849 aux_engine_regs(1)
850};
851
852static const struct dce110_aux_registers_shift aux_shift = {
853 DCN_AUX_MASK_SH_LIST(__SHIFT)
854};
855
856static const struct dce110_aux_registers_mask aux_mask = {
857 DCN_AUX_MASK_SH_LIST(_MASK)
858};
859
860static struct dce_aux *dcn303_aux_engine_create(struct dc_context *ctx, uint32_t inst)
861{
862 struct aux_engine_dce110 *aux_engine = kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
863
864 if (!aux_engine)
865 return NULL;
866
867 dce110_aux_engine_construct(aux_engine, ctx, inst, SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
868 &aux_engine_regs[inst], &aux_mask, &aux_shift, ctx->dc->caps.extended_aux_timeout_support);
869
870 return &aux_engine->base;
871}
872
873#define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
874
875static const struct dce_i2c_registers i2c_hw_regs[] = {
876 i2c_inst_regs(1),
877 i2c_inst_regs(2)
878};
879
880static const struct dce_i2c_shift i2c_shifts = {
881 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
882};
883
884static const struct dce_i2c_mask i2c_masks = {
885 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
886};
887
888static struct dce_i2c_hw *dcn303_i2c_hw_create(struct dc_context *ctx, uint32_t inst)
889{
890 struct dce_i2c_hw *dce_i2c_hw = kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
891
892 if (!dce_i2c_hw)
893 return NULL;
894
895 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst, &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
896
897 return dce_i2c_hw;
898}
899
900static const struct encoder_feature_support link_enc_feature = {
901 .max_hdmi_deep_color = COLOR_DEPTH_121212,
902 .max_hdmi_pixel_clock = 600000,
903 .hdmi_ycbcr420_supported = true,
904 .dp_ycbcr420_supported = true,
905 .fec_supported = true,
906 .flags.bits.IS_HBR2_CAPABLE = true,
907 .flags.bits.IS_HBR3_CAPABLE = true,
908 .flags.bits.IS_TPS3_CAPABLE = true,
909 .flags.bits.IS_TPS4_CAPABLE = true
910};
911
912#define link_regs(id, phyid)\
913 [id] = {\
914 LE_DCN3_REG_LIST(id), \
915 UNIPHY_DCN2_REG_LIST(phyid), \
916 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
917 }
918
919static const struct dcn10_link_enc_registers link_enc_regs[] = {
920 link_regs(0, A),
921 link_regs(1, B)
922};
923
924static const struct dcn10_link_enc_shift le_shift = {
925 LINK_ENCODER_MASK_SH_LIST_DCN30(__SHIFT),
926 DPCS_DCN2_MASK_SH_LIST(__SHIFT)
927};
928
929static const struct dcn10_link_enc_mask le_mask = {
930 LINK_ENCODER_MASK_SH_LIST_DCN30(_MASK),
931 DPCS_DCN2_MASK_SH_LIST(_MASK)
932};
933
934#define aux_regs(id)\
935 [id] = { DCN2_AUX_REG_LIST(id) }
936
937static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
938 aux_regs(0),
939 aux_regs(1)
940};
941
942#define hpd_regs(id)\
943 [id] = { HPD_REG_LIST(id) }
944
945static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
946 hpd_regs(0),
947 hpd_regs(1)
948};
949
950static struct link_encoder *dcn303_link_encoder_create(const struct encoder_init_data *enc_init_data)
951{
952 struct dcn20_link_encoder *enc20 = kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
953
954 if (!enc20)
955 return NULL;
956
957 dcn30_link_encoder_construct(enc20, enc_init_data, &link_enc_feature,
958 &link_enc_regs[enc_init_data->transmitter], &link_enc_aux_regs[enc_init_data->channel - 1],
959 &link_enc_hpd_regs[enc_init_data->hpd_source], &le_shift, &le_mask);
960
961 return &enc20->enc10.base;
962}
963
964static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
965 { DCN_PANEL_CNTL_REG_LIST() }
966};
967
968static const struct dce_panel_cntl_shift panel_cntl_shift = {
969 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
970};
971
972static const struct dce_panel_cntl_mask panel_cntl_mask = {
973 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
974};
975
976static struct panel_cntl *dcn303_panel_cntl_create(const struct panel_cntl_init_data *init_data)
977{
978 struct dce_panel_cntl *panel_cntl = kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
979
980 if (!panel_cntl)
981 return NULL;
982
983 dce_panel_cntl_construct(panel_cntl, init_data, &panel_cntl_regs[init_data->inst],
984 &panel_cntl_shift, &panel_cntl_mask);
985
986 return &panel_cntl->base;
987}
988
989static void read_dce_straps(struct dc_context *ctx, struct resource_straps *straps)
990{
991 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
992 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
993}
994
995static const struct resource_create_funcs res_create_funcs = {
996 .read_dce_straps = read_dce_straps,
997 .create_audio = dcn303_create_audio,
998 .create_stream_encoder = dcn303_stream_encoder_create,
999 .create_hwseq = dcn303_hwseq_create,
1000};
1001
1002static const struct resource_create_funcs res_create_maximus_funcs = {
1003 .read_dce_straps = NULL,
1004 .create_audio = NULL,
1005 .create_stream_encoder = NULL,
1006 .create_hwseq = dcn303_hwseq_create,
1007};
1008
1009static bool is_soc_bounding_box_valid(struct dc *dc)
1010{
1011 uint32_t hw_internal_rev = dc->ctx->asic_id.hw_internal_rev;
1012
1013 if (ASICREV_IS_BEIGE_GOBY_P(hw_internal_rev))
1014 return true;
1015
1016 return false;
1017}
1018
1019static bool init_soc_bounding_box(struct dc *dc, struct resource_pool *pool)
1020{
1021 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_03_soc;
1022 struct _vcs_dpi_ip_params_st *loaded_ip = &dcn3_03_ip;
1023
1024 DC_LOGGER_INIT(dc->ctx->logger);
1025
1026 if (!is_soc_bounding_box_valid(dc)) {
1027 DC_LOG_ERROR("%s: not valid soc bounding box/n", __func__);
1028 return false;
1029 }
1030
1031 loaded_ip->max_num_otg = pool->pipe_count;
1032 loaded_ip->max_num_dpp = pool->pipe_count;
1033 loaded_ip->clamp_min_dcfclk = dc->config.clamp_min_dcfclk;
1034 dcn20_patch_bounding_box(dc, loaded_bb);
1035
1036 if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {
1037 struct bp_soc_bb_info bb_info = { 0 };
1038
1039 if (dc->ctx->dc_bios->funcs->get_soc_bb_info(
1040 dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {
1041 if (bb_info.dram_clock_change_latency_100ns > 0)
1042 dcn3_03_soc.dram_clock_change_latency_us =
1043 bb_info.dram_clock_change_latency_100ns * 10;
1044
1045 if (bb_info.dram_sr_enter_exit_latency_100ns > 0)
1046 dcn3_03_soc.sr_enter_plus_exit_time_us =
1047 bb_info.dram_sr_enter_exit_latency_100ns * 10;
1048
1049 if (bb_info.dram_sr_exit_latency_100ns > 0)
1050 dcn3_03_soc.sr_exit_time_us =
1051 bb_info.dram_sr_exit_latency_100ns * 10;
1052 }
1053 }
1054
1055 return true;
1056}
1057
1058static void dcn303_resource_destruct(struct resource_pool *pool)
1059{
1060 unsigned int i;
1061
1062 for (i = 0; i < pool->stream_enc_count; i++) {
1063 if (pool->stream_enc[i] != NULL) {
1064 if (pool->stream_enc[i]->vpg != NULL) {
1065 kfree(DCN30_VPG_FROM_VPG(pool->stream_enc[i]->vpg));
1066 pool->stream_enc[i]->vpg = NULL;
1067 }
1068 if (pool->stream_enc[i]->afmt != NULL) {
1069 kfree(DCN30_AFMT_FROM_AFMT(pool->stream_enc[i]->afmt));
1070 pool->stream_enc[i]->afmt = NULL;
1071 }
1072 kfree(DCN10STRENC_FROM_STRENC(pool->stream_enc[i]));
1073 pool->stream_enc[i] = NULL;
1074 }
1075 }
1076
1077 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1078 if (pool->dscs[i] != NULL)
1079 dcn20_dsc_destroy(&pool->dscs[i]);
1080 }
1081
1082 if (pool->mpc != NULL) {
1083 kfree(TO_DCN20_MPC(pool->mpc));
1084 pool->mpc = NULL;
1085 }
1086
1087 if (pool->hubbub != NULL) {
1088 kfree(pool->hubbub);
1089 pool->hubbub = NULL;
1090 }
1091
1092 for (i = 0; i < pool->pipe_count; i++) {
1093 if (pool->dpps[i] != NULL) {
1094 kfree(TO_DCN20_DPP(pool->dpps[i]));
1095 pool->dpps[i] = NULL;
1096 }
1097
1098 if (pool->hubps[i] != NULL) {
1099 kfree(TO_DCN20_HUBP(pool->hubps[i]));
1100 pool->hubps[i] = NULL;
1101 }
1102
1103 if (pool->irqs != NULL)
1104 dal_irq_service_destroy(&pool->irqs);
1105 }
1106
1107 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1108 if (pool->engines[i] != NULL)
1109 dce110_engine_destroy(&pool->engines[i]);
1110 if (pool->hw_i2cs[i] != NULL) {
1111 kfree(pool->hw_i2cs[i]);
1112 pool->hw_i2cs[i] = NULL;
1113 }
1114 if (pool->sw_i2cs[i] != NULL) {
1115 kfree(pool->sw_i2cs[i]);
1116 pool->sw_i2cs[i] = NULL;
1117 }
1118 }
1119
1120 for (i = 0; i < pool->res_cap->num_opp; i++) {
1121 if (pool->opps[i] != NULL)
1122 pool->opps[i]->funcs->opp_destroy(&pool->opps[i]);
1123 }
1124
1125 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1126 if (pool->timing_generators[i] != NULL) {
1127 kfree(DCN10TG_FROM_TG(pool->timing_generators[i]));
1128 pool->timing_generators[i] = NULL;
1129 }
1130 }
1131
1132 for (i = 0; i < pool->res_cap->num_dwb; i++) {
1133 if (pool->dwbc[i] != NULL) {
1134 kfree(TO_DCN30_DWBC(pool->dwbc[i]));
1135 pool->dwbc[i] = NULL;
1136 }
1137 if (pool->mcif_wb[i] != NULL) {
1138 kfree(TO_DCN30_MMHUBBUB(pool->mcif_wb[i]));
1139 pool->mcif_wb[i] = NULL;
1140 }
1141 }
1142
1143 for (i = 0; i < pool->audio_count; i++) {
1144 if (pool->audios[i])
1145 dce_aud_destroy(&pool->audios[i]);
1146 }
1147
1148 for (i = 0; i < pool->clk_src_count; i++) {
1149 if (pool->clock_sources[i] != NULL)
1150 dcn20_clock_source_destroy(&pool->clock_sources[i]);
1151 }
1152
1153 if (pool->dp_clock_source != NULL)
1154 dcn20_clock_source_destroy(&pool->dp_clock_source);
1155
1156 for (i = 0; i < pool->res_cap->num_mpc_3dlut; i++) {
1157 if (pool->mpc_lut[i] != NULL) {
1158 dc_3dlut_func_release(pool->mpc_lut[i]);
1159 pool->mpc_lut[i] = NULL;
1160 }
1161 if (pool->mpc_shaper[i] != NULL) {
1162 dc_transfer_func_release(pool->mpc_shaper[i]);
1163 pool->mpc_shaper[i] = NULL;
1164 }
1165 }
1166
1167 for (i = 0; i < pool->pipe_count; i++) {
1168 if (pool->multiple_abms[i] != NULL)
1169 dce_abm_destroy(&pool->multiple_abms[i]);
1170 }
1171
1172 if (pool->psr != NULL)
1173 dmub_psr_destroy(&pool->psr);
1174
1175 if (pool->dccg != NULL)
1176 dcn_dccg_destroy(&pool->dccg);
1177
1178 if (pool->oem_device != NULL)
1179 dal_ddc_service_destroy(&pool->oem_device);
1180}
1181
1182static void dcn303_destroy_resource_pool(struct resource_pool **pool)
1183{
1184 dcn303_resource_destruct(*pool);
1185 kfree(*pool);
1186 *pool = NULL;
1187}
1188
1189static void dcn303_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,
1190 unsigned int *optimal_dcfclk,
1191 unsigned int *optimal_fclk)
1192{
1193 double bw_from_dram, bw_from_dram1, bw_from_dram2;
1194
1195 bw_from_dram1 = uclk_mts * dcn3_03_soc.num_chans *
1196 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_dram_bw_use_normal_percent / 100);
1197 bw_from_dram2 = uclk_mts * dcn3_03_soc.num_chans *
1198 dcn3_03_soc.dram_channel_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100);
1199
1200 bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;
1201
1202 if (optimal_fclk)
1203 *optimal_fclk = bw_from_dram /
1204 (dcn3_03_soc.fabric_datapath_to_dcn_data_return_bytes *
1205 (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100));
1206
1207 if (optimal_dcfclk)
1208 *optimal_dcfclk = bw_from_dram /
1209 (dcn3_03_soc.return_bus_width_bytes * (dcn3_03_soc.max_avg_sdp_bw_use_normal_percent / 100));
1210}
1211
1212void dcn303_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1213{
1214 unsigned int i, j;
1215 unsigned int num_states = 0;
1216
1217 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};
1218 unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};
1219 unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};
1220 unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};
1221
1222 unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {694, 875, 1000, 1200};
1223 unsigned int num_dcfclk_sta_targets = 4;
1224 unsigned int num_uclk_states;
1225
1226
1227 if (dc->ctx->dc_bios->vram_info.num_chans)
1228 dcn3_03_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;
1229
1230 if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)
1231 dcn3_03_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;
1232
1233 dcn3_03_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1234 dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;
1235
1236 if (bw_params->clk_table.entries[0].memclk_mhz) {
1237 int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;
1238
1239 for (i = 0; i < MAX_NUM_DPM_LVL; i++) {
1240 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
1241 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
1242 if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)
1243 max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;
1244 if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)
1245 max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;
1246 if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)
1247 max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;
1248 }
1249 if (!max_dcfclk_mhz)
1250 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz;
1251 if (!max_dispclk_mhz)
1252 max_dispclk_mhz = dcn3_03_soc.clock_limits[0].dispclk_mhz;
1253 if (!max_dppclk_mhz)
1254 max_dppclk_mhz = dcn3_03_soc.clock_limits[0].dppclk_mhz;
1255 if (!max_phyclk_mhz)
1256 max_phyclk_mhz = dcn3_03_soc.clock_limits[0].phyclk_mhz;
1257
1258 if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1259 dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;
1260 num_dcfclk_sta_targets++;
1261 } else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {
1262 for (i = 0; i < num_dcfclk_sta_targets; i++) {
1263 if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {
1264 dcfclk_sta_targets[i] = max_dcfclk_mhz;
1265 break;
1266 }
1267 }
1268
1269 num_dcfclk_sta_targets = i + 1;
1270 }
1271
1272 num_uclk_states = bw_params->clk_table.num_entries;
1273
1274
1275 for (i = 0; i < num_uclk_states; i++) {
1276 dcn303_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,
1277 &optimal_dcfclk_for_uclk[i], NULL);
1278 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz)
1279 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
1280 }
1281
1282
1283 for (i = 0; i < num_dcfclk_sta_targets; i++) {
1284 for (j = 0; j < num_uclk_states; j++) {
1285 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {
1286 optimal_uclk_for_dcfclk_sta_targets[i] =
1287 bw_params->clk_table.entries[j].memclk_mhz * 16;
1288 break;
1289 }
1290 }
1291 }
1292
1293 i = 0;
1294 j = 0;
1295
1296 while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {
1297 if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {
1298 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1299 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1300 } else {
1301 if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1302 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1303 dram_speed_mts[num_states++] =
1304 bw_params->clk_table.entries[j++].memclk_mhz * 16;
1305 } else {
1306 j = num_uclk_states;
1307 }
1308 }
1309 }
1310
1311 while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {
1312 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
1313 dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];
1314 }
1315
1316 while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&
1317 optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {
1318 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
1319 dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;
1320 }
1321
1322 dcn3_03_soc.num_states = num_states;
1323 for (i = 0; i < dcn3_03_soc.num_states; i++) {
1324 dcn3_03_soc.clock_limits[i].state = i;
1325 dcn3_03_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
1326 dcn3_03_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
1327 dcn3_03_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];
1328
1329
1330 dcn3_03_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;
1331 dcn3_03_soc.clock_limits[i].dppclk_mhz = max_dppclk_mhz;
1332 dcn3_03_soc.clock_limits[i].phyclk_mhz = max_phyclk_mhz;
1333
1334 if (!bw_params->clk_table.entries[i].dtbclk_mhz && i > 0)
1335 dcn3_03_soc.clock_limits[i].dtbclk_mhz = dcn3_03_soc.clock_limits[i-1].dtbclk_mhz;
1336 else
1337 dcn3_03_soc.clock_limits[i].dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;
1338 if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)
1339 dcn3_03_soc.clock_limits[i].socclk_mhz = dcn3_03_soc.clock_limits[i-1].socclk_mhz;
1340 else
1341 dcn3_03_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;
1342
1343
1344 dcn3_03_soc.clock_limits[i].phyclk_d18_mhz = dcn3_03_soc.clock_limits[0].phyclk_d18_mhz;
1345 dcn3_03_soc.clock_limits[i].dscclk_mhz = dcn3_03_soc.clock_limits[0].dscclk_mhz;
1346 }
1347
1348 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
1349 if (dc->current_state)
1350 dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
1351 }
1352}
1353
1354static struct resource_funcs dcn303_res_pool_funcs = {
1355 .destroy = dcn303_destroy_resource_pool,
1356 .link_enc_create = dcn303_link_encoder_create,
1357 .panel_cntl_create = dcn303_panel_cntl_create,
1358 .validate_bandwidth = dcn30_validate_bandwidth,
1359 .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg,
1360 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1361 .populate_dml_pipes = dcn30_populate_dml_pipes_from_context,
1362 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1363 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1364 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1365 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1366 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1367 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1368 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1369 .acquire_post_bldn_3dlut = dcn30_acquire_post_bldn_3dlut,
1370 .release_post_bldn_3dlut = dcn30_release_post_bldn_3dlut,
1371 .update_bw_bounding_box = dcn303_update_bw_bounding_box,
1372 .patch_unknown_plane_state = dcn20_patch_unknown_plane_state,
1373};
1374
1375static struct dc_cap_funcs cap_funcs = {
1376 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1377};
1378
1379static const struct bios_registers bios_regs = {
1380 NBIO_SR(BIOS_SCRATCH_3),
1381 NBIO_SR(BIOS_SCRATCH_6)
1382};
1383
1384static const struct dccg_registers dccg_regs = {
1385 DCCG_REG_LIST_DCN3_03()
1386};
1387
1388static const struct dccg_shift dccg_shift = {
1389 DCCG_MASK_SH_LIST_DCN3_03(__SHIFT)
1390};
1391
1392static const struct dccg_mask dccg_mask = {
1393 DCCG_MASK_SH_LIST_DCN3_03(_MASK)
1394};
1395
1396#define abm_regs(id)\
1397 [id] = { ABM_DCN301_REG_LIST(id) }
1398
1399static const struct dce_abm_registers abm_regs[] = {
1400 abm_regs(0),
1401 abm_regs(1)
1402};
1403
1404static const struct dce_abm_shift abm_shift = {
1405 ABM_MASK_SH_LIST_DCN30(__SHIFT)
1406};
1407
1408static const struct dce_abm_mask abm_mask = {
1409 ABM_MASK_SH_LIST_DCN30(_MASK)
1410};
1411
1412static bool dcn303_resource_construct(
1413 uint8_t num_virtual_links,
1414 struct dc *dc,
1415 struct resource_pool *pool)
1416{
1417 int i;
1418 struct dc_context *ctx = dc->ctx;
1419 struct irq_service_init_data init_data;
1420 struct ddc_service_init_data ddc_init_data;
1421
1422 ctx->dc_bios->regs = &bios_regs;
1423
1424 pool->res_cap = &res_cap_dcn303;
1425
1426 pool->funcs = &dcn303_res_pool_funcs;
1427
1428
1429
1430
1431 pool->underlay_pipe_index = NO_UNDERLAY_PIPE;
1432 pool->pipe_count = pool->res_cap->num_timing_generator;
1433 pool->mpcc_count = pool->res_cap->num_timing_generator;
1434 dc->caps.max_downscale_ratio = 600;
1435 dc->caps.i2c_speed_in_khz = 100;
1436 dc->caps.i2c_speed_in_khz_hdcp = 5;
1437 dc->caps.max_cursor_size = 256;
1438 dc->caps.min_horizontal_blanking_period = 80;
1439 dc->caps.dmdata_alloc_size = 2048;
1440#if defined(CONFIG_DRM_AMD_DC_DCN)
1441 dc->caps.mall_size_per_mem_channel = 4;
1442
1443 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel *
1444 dc->ctx->dc_bios->vram_info.num_chans *
1445 1024 * 1024;
1446 dc->caps.cursor_cache_size =
1447 dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1448#endif
1449 dc->caps.max_slave_planes = 1;
1450 dc->caps.post_blend_color_processing = true;
1451 dc->caps.force_dp_tps4_for_cp2520 = true;
1452 dc->caps.extended_aux_timeout_support = true;
1453 dc->caps.dmcub_support = true;
1454
1455
1456 dc->caps.color.dpp.dcn_arch = 1;
1457 dc->caps.color.dpp.input_lut_shared = 0;
1458 dc->caps.color.dpp.icsc = 1;
1459 dc->caps.color.dpp.dgam_ram = 0;
1460 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1461 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1462 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1463 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1464 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1465 dc->caps.color.dpp.post_csc = 1;
1466 dc->caps.color.dpp.gamma_corr = 1;
1467 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1468
1469 dc->caps.color.dpp.hw_3d_lut = 1;
1470 dc->caps.color.dpp.ogam_ram = 1;
1471
1472 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1473 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1474 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1475 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1476 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1477 dc->caps.color.dpp.ocsc = 0;
1478
1479 dc->caps.color.mpc.gamut_remap = 1;
1480 dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut;
1481 dc->caps.color.mpc.ogam_ram = 1;
1482 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1483 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1484 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1485 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1486 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1487 dc->caps.color.mpc.ocsc = 1;
1488
1489 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1490 dc->debug = debug_defaults_drv;
1491 else
1492 dc->debug = debug_defaults_diags;
1493
1494
1495 if (dc->vm_helper)
1496 vm_helper_init(dc->vm_helper, 16);
1497
1498
1499
1500
1501
1502
1503 pool->clock_sources[DCN303_CLK_SRC_PLL0] =
1504 dcn303_clock_source_create(ctx, ctx->dc_bios,
1505 CLOCK_SOURCE_COMBO_PHY_PLL0,
1506 &clk_src_regs[0], false);
1507 pool->clock_sources[DCN303_CLK_SRC_PLL1] =
1508 dcn303_clock_source_create(ctx, ctx->dc_bios,
1509 CLOCK_SOURCE_COMBO_PHY_PLL1,
1510 &clk_src_regs[1], false);
1511
1512 pool->clk_src_count = DCN303_CLK_SRC_TOTAL;
1513
1514
1515 pool->dp_clock_source =
1516 dcn303_clock_source_create(ctx, ctx->dc_bios,
1517 CLOCK_SOURCE_ID_DP_DTO,
1518 &clk_src_regs[0], true);
1519
1520 for (i = 0; i < pool->clk_src_count; i++) {
1521 if (pool->clock_sources[i] == NULL) {
1522 dm_error("DC: failed to create clock sources!\n");
1523 BREAK_TO_DEBUGGER();
1524 goto create_fail;
1525 }
1526 }
1527
1528
1529 pool->dccg = dccg30_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1530 if (pool->dccg == NULL) {
1531 dm_error("DC: failed to create dccg!\n");
1532 BREAK_TO_DEBUGGER();
1533 goto create_fail;
1534 }
1535
1536
1537 init_soc_bounding_box(dc, pool);
1538
1539
1540 dml_init_instance(&dc->dml, &dcn3_03_soc, &dcn3_03_ip, DML_PROJECT_DCN30);
1541
1542
1543 init_data.ctx = dc->ctx;
1544 pool->irqs = dal_irq_service_dcn303_create(&init_data);
1545 if (!pool->irqs)
1546 goto create_fail;
1547
1548
1549 pool->hubbub = dcn303_hubbub_create(ctx);
1550 if (pool->hubbub == NULL) {
1551 BREAK_TO_DEBUGGER();
1552 dm_error("DC: failed to create hubbub!\n");
1553 goto create_fail;
1554 }
1555
1556
1557 for (i = 0; i < pool->pipe_count; i++) {
1558 pool->hubps[i] = dcn303_hubp_create(ctx, i);
1559 if (pool->hubps[i] == NULL) {
1560 BREAK_TO_DEBUGGER();
1561 dm_error("DC: failed to create hubps!\n");
1562 goto create_fail;
1563 }
1564
1565 pool->dpps[i] = dcn303_dpp_create(ctx, i);
1566 if (pool->dpps[i] == NULL) {
1567 BREAK_TO_DEBUGGER();
1568 dm_error("DC: failed to create dpps!\n");
1569 goto create_fail;
1570 }
1571 }
1572
1573 for (i = 0; i < pool->res_cap->num_opp; i++) {
1574 pool->opps[i] = dcn303_opp_create(ctx, i);
1575 if (pool->opps[i] == NULL) {
1576 BREAK_TO_DEBUGGER();
1577 dm_error("DC: failed to create output pixel processor!\n");
1578 goto create_fail;
1579 }
1580 }
1581
1582 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1583 pool->timing_generators[i] = dcn303_timing_generator_create(ctx, i);
1584 if (pool->timing_generators[i] == NULL) {
1585 BREAK_TO_DEBUGGER();
1586 dm_error("DC: failed to create tg!\n");
1587 goto create_fail;
1588 }
1589 }
1590 pool->timing_generator_count = i;
1591
1592
1593 pool->psr = dmub_psr_create(ctx);
1594 if (pool->psr == NULL) {
1595 dm_error("DC: failed to create psr!\n");
1596 BREAK_TO_DEBUGGER();
1597 goto create_fail;
1598 }
1599
1600
1601 for (i = 0; i < pool->res_cap->num_timing_generator; i++) {
1602 pool->multiple_abms[i] = dmub_abm_create(ctx, &abm_regs[i], &abm_shift, &abm_mask);
1603 if (pool->multiple_abms[i] == NULL) {
1604 dm_error("DC: failed to create abm for pipe %d!\n", i);
1605 BREAK_TO_DEBUGGER();
1606 goto create_fail;
1607 }
1608 }
1609
1610
1611 pool->mpc = dcn303_mpc_create(ctx, pool->mpcc_count, pool->res_cap->num_mpc_3dlut);
1612 if (pool->mpc == NULL) {
1613 BREAK_TO_DEBUGGER();
1614 dm_error("DC: failed to create mpc!\n");
1615 goto create_fail;
1616 }
1617
1618 for (i = 0; i < pool->res_cap->num_dsc; i++) {
1619 pool->dscs[i] = dcn303_dsc_create(ctx, i);
1620 if (pool->dscs[i] == NULL) {
1621 BREAK_TO_DEBUGGER();
1622 dm_error("DC: failed to create display stream compressor %d!\n", i);
1623 goto create_fail;
1624 }
1625 }
1626
1627
1628 if (!dcn303_dwbc_create(ctx, pool)) {
1629 BREAK_TO_DEBUGGER();
1630 dm_error("DC: failed to create dwbc!\n");
1631 goto create_fail;
1632 }
1633
1634 if (!dcn303_mmhubbub_create(ctx, pool)) {
1635 BREAK_TO_DEBUGGER();
1636 dm_error("DC: failed to create mcif_wb!\n");
1637 goto create_fail;
1638 }
1639
1640
1641 for (i = 0; i < pool->res_cap->num_ddc; i++) {
1642 pool->engines[i] = dcn303_aux_engine_create(ctx, i);
1643 if (pool->engines[i] == NULL) {
1644 BREAK_TO_DEBUGGER();
1645 dm_error("DC:failed to create aux engine!!\n");
1646 goto create_fail;
1647 }
1648 pool->hw_i2cs[i] = dcn303_i2c_hw_create(ctx, i);
1649 if (pool->hw_i2cs[i] == NULL) {
1650 BREAK_TO_DEBUGGER();
1651 dm_error("DC:failed to create hw i2c!!\n");
1652 goto create_fail;
1653 }
1654 pool->sw_i2cs[i] = NULL;
1655 }
1656
1657
1658 if (!resource_construct(num_virtual_links, dc, pool,
1659 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
1660 &res_create_funcs : &res_create_maximus_funcs)))
1661 goto create_fail;
1662
1663
1664 dcn303_hw_sequencer_construct(dc);
1665
1666 dc->caps.max_planes = pool->pipe_count;
1667
1668 for (i = 0; i < dc->caps.max_planes; ++i)
1669 dc->caps.planes[i] = plane_cap;
1670
1671 dc->cap_funcs = cap_funcs;
1672
1673 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
1674 ddc_init_data.ctx = dc->ctx;
1675 ddc_init_data.link = NULL;
1676 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
1677 ddc_init_data.id.enum_id = 0;
1678 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
1679 pool->oem_device = dal_ddc_service_create(&ddc_init_data);
1680 } else {
1681 pool->oem_device = NULL;
1682 }
1683
1684 return true;
1685
1686create_fail:
1687
1688 dcn303_resource_destruct(pool);
1689
1690 return false;
1691}
1692
1693struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *init_data, struct dc *dc)
1694{
1695 struct resource_pool *pool = kzalloc(sizeof(struct resource_pool), GFP_KERNEL);
1696
1697 if (!pool)
1698 return NULL;
1699
1700 if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))
1701 return pool;
1702
1703 BREAK_TO_DEBUGGER();
1704 kfree(pool);
1705 return NULL;
1706}
1707
