LXR linux/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_dio_link

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26
  27#include "reg_helper.h"
  28
  29#include "core_types.h"
  30#include "link_encoder.h"
  31#include "dcn31_dio_link_encoder.h"
  32#include "stream_encoder.h"
  33#include "i2caux_interface.h"
  34#include "dc_bios_types.h"
  35
  36#include "gpio_service_interface.h"
  37
  38#include "link_enc_cfg.h"
  39#include "dc_dmub_srv.h"
  40#include "dal_asic_id.h"
  41
  42#define CTX \
  43        enc10->base.ctx
  44#define DC_LOGGER \
  45        enc10->base.ctx->logger
  46
  47#define REG(reg)\
  48        (enc10->link_regs->reg)
  49
  50#undef FN
  51#define FN(reg_name, field_name) \
  52        enc10->link_shift->field_name, enc10->link_mask->field_name
  53
  54#define IND_REG(index) \
  55        (enc10->link_regs->index)
  56
  57#define AUX_REG(reg)\
  58        (enc10->aux_regs->reg)
  59
  60#define AUX_REG_READ(reg_name) \
  61                dm_read_reg(CTX, AUX_REG(reg_name))
  62
  63#define AUX_REG_WRITE(reg_name, val) \
  64                        dm_write_reg(CTX, AUX_REG(reg_name), val)
  65
  66#ifndef MIN
  67#define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
  68#endif
  69
  70void dcn31_link_encoder_set_dio_phy_mux(
  71        struct link_encoder *enc,
  72        enum encoder_type_select sel,
  73        uint32_t hpo_inst)
  74{
  75        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
  76
  77        switch (enc->transmitter) {
  78        case TRANSMITTER_UNIPHY_A:
  79                if (sel == ENCODER_TYPE_HDMI_FRL)
  80                        REG_UPDATE(DIO_LINKA_CNTL,
  81                                        HPO_HDMI_ENC_SEL, hpo_inst);
  82                else if (sel == ENCODER_TYPE_DP_128B132B)
  83                        REG_UPDATE(DIO_LINKA_CNTL,
  84                                        HPO_DP_ENC_SEL, hpo_inst);
  85                REG_UPDATE(DIO_LINKA_CNTL,
  86                                ENC_TYPE_SEL, sel);
  87                break;
  88        case TRANSMITTER_UNIPHY_B:
  89                if (sel == ENCODER_TYPE_HDMI_FRL)
  90                        REG_UPDATE(DIO_LINKB_CNTL,
  91                                        HPO_HDMI_ENC_SEL, hpo_inst);
  92                else if (sel == ENCODER_TYPE_DP_128B132B)
  93                        REG_UPDATE(DIO_LINKB_CNTL,
  94                                        HPO_DP_ENC_SEL, hpo_inst);
  95                REG_UPDATE(DIO_LINKB_CNTL,
  96                                ENC_TYPE_SEL, sel);
  97                break;
  98        case TRANSMITTER_UNIPHY_C:
  99                if (sel == ENCODER_TYPE_HDMI_FRL)
 100                        REG_UPDATE(DIO_LINKC_CNTL,
 101                                        HPO_HDMI_ENC_SEL, hpo_inst);
 102                else if (sel == ENCODER_TYPE_DP_128B132B)
 103                        REG_UPDATE(DIO_LINKC_CNTL,
 104                                        HPO_DP_ENC_SEL, hpo_inst);
 105                REG_UPDATE(DIO_LINKC_CNTL,
 106                                ENC_TYPE_SEL, sel);
 107                break;
 108        case TRANSMITTER_UNIPHY_D:
 109                if (sel == ENCODER_TYPE_HDMI_FRL)
 110                        REG_UPDATE(DIO_LINKD_CNTL,
 111                                        HPO_HDMI_ENC_SEL, hpo_inst);
 112                else if (sel == ENCODER_TYPE_DP_128B132B)
 113                        REG_UPDATE(DIO_LINKD_CNTL,
 114                                        HPO_DP_ENC_SEL, hpo_inst);
 115                REG_UPDATE(DIO_LINKD_CNTL,
 116                                ENC_TYPE_SEL, sel);
 117                break;
 118        case TRANSMITTER_UNIPHY_E:
 119                if (sel == ENCODER_TYPE_HDMI_FRL)
 120                        REG_UPDATE(DIO_LINKE_CNTL,
 121                                        HPO_HDMI_ENC_SEL, hpo_inst);
 122                else if (sel == ENCODER_TYPE_DP_128B132B)
 123                        REG_UPDATE(DIO_LINKE_CNTL,
 124                                        HPO_DP_ENC_SEL, hpo_inst);
 125                REG_UPDATE(DIO_LINKE_CNTL,
 126                                ENC_TYPE_SEL, sel);
 127                break;
 128        case TRANSMITTER_UNIPHY_F:
 129                if (sel == ENCODER_TYPE_HDMI_FRL)
 130                        REG_UPDATE(DIO_LINKF_CNTL,
 131                                        HPO_HDMI_ENC_SEL, hpo_inst);
 132                else if (sel == ENCODER_TYPE_DP_128B132B)
 133                        REG_UPDATE(DIO_LINKF_CNTL,
 134                                        HPO_DP_ENC_SEL, hpo_inst);
 135                REG_UPDATE(DIO_LINKF_CNTL,
 136                                ENC_TYPE_SEL, sel);
 137                break;
 138        default:
 139                /* Do nothing */
 140                break;
 141        }
 142}
 143
 144void enc31_hw_init(struct link_encoder *enc)
 145{
 146        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 147
 148/*
 149        00 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__1to2 : 1/2
 150        01 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__3to4 : 3/4
 151        02 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__7to8 : 7/8
 152        03 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__15to16 : 15/16
 153        04 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__31to32 : 31/32
 154        05 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__63to64 : 63/64
 155        06 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__127to128 : 127/128
 156        07 - DP_AUX_DPHY_RX_DETECTION_THRESHOLD__255to256 : 255/256
 157*/
 158
 159/*
 160        AUX_REG_UPDATE_5(AUX_DPHY_RX_CONTROL0,
 161        AUX_RX_START_WINDOW = 1 [6:4]
 162        AUX_RX_RECEIVE_WINDOW = 1 default is 2 [10:8]
 163        AUX_RX_HALF_SYM_DETECT_LEN  = 1 [13:12] default is 1
 164        AUX_RX_TRANSITION_FILTER_EN = 1 [16] default is 1
 165        AUX_RX_ALLOW_BELOW_THRESHOLD_PHASE_DETECT [17] is 0  default is 0
 166        AUX_RX_ALLOW_BELOW_THRESHOLD_START [18] is 1  default is 1
 167        AUX_RX_ALLOW_BELOW_THRESHOLD_STOP [19] is 1  default is 1
 168        AUX_RX_PHASE_DETECT_LEN,  [21,20] = 0x3 default is 3
 169        AUX_RX_DETECTION_THRESHOLD [30:28] = 1
 170*/
 171        AUX_REG_WRITE(AUX_DPHY_RX_CONTROL0, 0x103d1110);
 172
 173        AUX_REG_WRITE(AUX_DPHY_TX_CONTROL, 0x21c7a);
 174
 175        //AUX_DPHY_TX_REF_CONTROL'AUX_TX_REF_DIV HW default is 0x32;
 176        // Set AUX_TX_REF_DIV Divider to generate 2 MHz reference from refclk
 177        // 27MHz -> 0xd
 178        // 100MHz -> 0x32
 179        // 48MHz -> 0x18
 180
 181#ifdef CLEANUP_FIXME
 182        /*from display_init*/
 183        REG_WRITE(RDPCSTX_DEBUG_CONFIG, 0);
 184#endif
 185
 186        // Set TMDS_CTL0 to 1.  This is a legacy setting.
 187        REG_UPDATE(TMDS_CTL_BITS, TMDS_CTL0, 1);
 188
 189        /*HW default is 5*/
 190        REG_UPDATE(RDPCSTX_CNTL,
 191                        RDPCS_TX_FIFO_RD_START_DELAY, 4);
 192
 193        dcn10_aux_initialize(enc10);
 194}
 195
 196static const struct link_encoder_funcs dcn31_link_enc_funcs = {
 197        .read_state = link_enc2_read_state,
 198        .validate_output_with_stream =
 199                        dcn30_link_encoder_validate_output_with_stream,
 200        .hw_init = enc31_hw_init,
 201        .setup = dcn10_link_encoder_setup,
 202        .enable_tmds_output = dcn10_link_encoder_enable_tmds_output,
 203        .enable_dp_output = dcn31_link_encoder_enable_dp_output,
 204        .enable_dp_mst_output = dcn31_link_encoder_enable_dp_mst_output,
 205        .disable_output = dcn31_link_encoder_disable_output,
 206        .dp_set_lane_settings = dcn10_link_encoder_dp_set_lane_settings,
 207        .dp_set_phy_pattern = dcn10_link_encoder_dp_set_phy_pattern,
 208        .update_mst_stream_allocation_table =
 209                dcn10_link_encoder_update_mst_stream_allocation_table,
 210        .psr_program_dp_dphy_fast_training =
 211                        dcn10_psr_program_dp_dphy_fast_training,
 212        .psr_program_secondary_packet = dcn10_psr_program_secondary_packet,
 213        .connect_dig_be_to_fe = dcn10_link_encoder_connect_dig_be_to_fe,
 214        .enable_hpd = dcn10_link_encoder_enable_hpd,
 215        .disable_hpd = dcn10_link_encoder_disable_hpd,
 216        .is_dig_enabled = dcn10_is_dig_enabled,
 217        .destroy = dcn10_link_encoder_destroy,
 218        .fec_set_enable = enc2_fec_set_enable,
 219        .fec_set_ready = enc2_fec_set_ready,
 220        .fec_is_active = enc2_fec_is_active,
 221        .get_dig_frontend = dcn10_get_dig_frontend,
 222        .get_dig_mode = dcn10_get_dig_mode,
 223        .is_in_alt_mode = dcn31_link_encoder_is_in_alt_mode,
 224        .get_max_link_cap = dcn31_link_encoder_get_max_link_cap,
 225        .set_dio_phy_mux = dcn31_link_encoder_set_dio_phy_mux,
 226};
 227
 228void dcn31_link_encoder_construct(
 229        struct dcn20_link_encoder *enc20,
 230        const struct encoder_init_data *init_data,
 231        const struct encoder_feature_support *enc_features,
 232        const struct dcn10_link_enc_registers *link_regs,
 233        const struct dcn10_link_enc_aux_registers *aux_regs,
 234        const struct dcn10_link_enc_hpd_registers *hpd_regs,
 235        const struct dcn10_link_enc_shift *link_shift,
 236        const struct dcn10_link_enc_mask *link_mask)
 237{
 238        struct bp_encoder_cap_info bp_cap_info = {0};
 239        const struct dc_vbios_funcs *bp_funcs = init_data->ctx->dc_bios->funcs;
 240        enum bp_result result = BP_RESULT_OK;
 241        struct dcn10_link_encoder *enc10 = &enc20->enc10;
 242
 243        enc10->base.funcs = &dcn31_link_enc_funcs;
 244        enc10->base.ctx = init_data->ctx;
 245        enc10->base.id = init_data->encoder;
 246
 247        enc10->base.hpd_source = init_data->hpd_source;
 248        enc10->base.connector = init_data->connector;
 249
 250        enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 251
 252        enc10->base.features = *enc_features;
 253
 254        enc10->base.transmitter = init_data->transmitter;
 255
 256        /* set the flag to indicate whether driver poll the I2C data pin
 257         * while doing the DP sink detect
 258         */
 259
 260/*      if (dal_adapter_service_is_feature_supported(as,
 261                FEATURE_DP_SINK_DETECT_POLL_DATA_PIN))
 262                enc10->base.features.flags.bits.
 263                        DP_SINK_DETECT_POLL_DATA_PIN = true;*/
 264
 265        enc10->base.output_signals =
 266                SIGNAL_TYPE_DVI_SINGLE_LINK |
 267                SIGNAL_TYPE_DVI_DUAL_LINK |
 268                SIGNAL_TYPE_LVDS |
 269                SIGNAL_TYPE_DISPLAY_PORT |
 270                SIGNAL_TYPE_DISPLAY_PORT_MST |
 271                SIGNAL_TYPE_EDP |
 272                SIGNAL_TYPE_HDMI_TYPE_A;
 273
 274        /* For DCE 8.0 and 8.1, by design, UNIPHY is hardwired to DIG_BE.
 275         * SW always assign DIG_FE 1:1 mapped to DIG_FE for non-MST UNIPHY.
 276         * SW assign DIG_FE to non-MST UNIPHY first and MST last. So prefer
 277         * DIG is per UNIPHY and used by SST DP, eDP, HDMI, DVI and LVDS.
 278         * Prefer DIG assignment is decided by board design.
 279         * For DCE 8.0, there are only max 6 UNIPHYs, we assume board design
 280         * and VBIOS will filter out 7 UNIPHY for DCE 8.0.
 281         * By this, adding DIGG should not hurt DCE 8.0.
 282         * This will let DCE 8.1 share DCE 8.0 as much as possible
 283         */
 284
 285        enc10->link_regs = link_regs;
 286        enc10->aux_regs = aux_regs;
 287        enc10->hpd_regs = hpd_regs;
 288        enc10->link_shift = link_shift;
 289        enc10->link_mask = link_mask;
 290
 291        switch (enc10->base.transmitter) {
 292        case TRANSMITTER_UNIPHY_A:
 293                enc10->base.preferred_engine = ENGINE_ID_DIGA;
 294        break;
 295        case TRANSMITTER_UNIPHY_B:
 296                enc10->base.preferred_engine = ENGINE_ID_DIGB;
 297        break;
 298        case TRANSMITTER_UNIPHY_C:
 299                enc10->base.preferred_engine = ENGINE_ID_DIGC;
 300        break;
 301        case TRANSMITTER_UNIPHY_D:
 302                enc10->base.preferred_engine = ENGINE_ID_DIGD;
 303        break;
 304        case TRANSMITTER_UNIPHY_E:
 305                enc10->base.preferred_engine = ENGINE_ID_DIGE;
 306        break;
 307        case TRANSMITTER_UNIPHY_F:
 308                enc10->base.preferred_engine = ENGINE_ID_DIGF;
 309        break;
 310        default:
 311                ASSERT_CRITICAL(false);
 312                enc10->base.preferred_engine = ENGINE_ID_UNKNOWN;
 313        }
 314
 315        /* default to one to mirror Windows behavior */
 316        enc10->base.features.flags.bits.HDMI_6GB_EN = 1;
 317
 318        result = bp_funcs->get_encoder_cap_info(enc10->base.ctx->dc_bios,
 319                                                enc10->base.id, &bp_cap_info);
 320
 321        /* Override features with DCE-specific values */
 322        if (result == BP_RESULT_OK) {
 323                enc10->base.features.flags.bits.IS_HBR2_CAPABLE =
 324                                bp_cap_info.DP_HBR2_EN;
 325                enc10->base.features.flags.bits.IS_HBR3_CAPABLE =
 326                                bp_cap_info.DP_HBR3_EN;
 327                enc10->base.features.flags.bits.HDMI_6GB_EN = bp_cap_info.HDMI_6GB_EN;
 328                enc10->base.features.flags.bits.DP_IS_USB_C =
 329                                bp_cap_info.DP_IS_USB_C;
 330        } else {
 331                DC_LOG_WARNING("%s: Failed to get encoder_cap_info from VBIOS with error code %d!\n",
 332                                __func__,
 333                                result);
 334        }
 335        if (enc10->base.ctx->dc->debug.hdmi20_disable) {
 336                enc10->base.features.flags.bits.HDMI_6GB_EN = 0;
 337        }
 338}
 339
 340void dcn31_link_encoder_construct_minimal(
 341        struct dcn20_link_encoder *enc20,
 342        struct dc_context *ctx,
 343        const struct encoder_feature_support *enc_features,
 344        const struct dcn10_link_enc_registers *link_regs,
 345        enum engine_id eng_id)
 346{
 347        struct dcn10_link_encoder *enc10 = &enc20->enc10;
 348
 349        enc10->base.funcs = &dcn31_link_enc_funcs;
 350        enc10->base.ctx = ctx;
 351        enc10->base.id.type = OBJECT_TYPE_ENCODER;
 352        enc10->base.hpd_source = HPD_SOURCEID_UNKNOWN;
 353        enc10->base.connector.type = OBJECT_TYPE_CONNECTOR;
 354        enc10->base.preferred_engine = eng_id;
 355        enc10->base.features = *enc_features;
 356        enc10->base.transmitter = TRANSMITTER_UNKNOWN;
 357        enc10->link_regs = link_regs;
 358
 359        enc10->base.output_signals =
 360                SIGNAL_TYPE_DISPLAY_PORT |
 361                SIGNAL_TYPE_DISPLAY_PORT_MST |
 362                SIGNAL_TYPE_EDP;
 363}
 364
 365void dcn31_link_encoder_enable_dp_output(
 366        struct link_encoder *enc,
 367        const struct dc_link_settings *link_settings,
 368        enum clock_source_id clock_source)
 369{
 370        /* Enable transmitter and encoder. */
 371        if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
 372
 373                dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source);
 374
 375        } else {
 376
 377                /** @todo Handle transmitter with programmable mapping to link encoder. */
 378        }
 379}
 380
 381void dcn31_link_encoder_enable_dp_mst_output(
 382        struct link_encoder *enc,
 383        const struct dc_link_settings *link_settings,
 384        enum clock_source_id clock_source)
 385{
 386        /* Enable transmitter and encoder. */
 387        if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
 388
 389                dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source);
 390
 391        } else {
 392
 393                /** @todo Handle transmitter with programmable mapping to link encoder. */
 394        }
 395}
 396
 397void dcn31_link_encoder_disable_output(
 398        struct link_encoder *enc,
 399        enum signal_type signal)
 400{
 401        /* Disable transmitter and encoder. */
 402        if (!link_enc_cfg_is_transmitter_mappable(enc->ctx->dc->current_state, enc)) {
 403
 404                dcn10_link_encoder_disable_output(enc, signal);
 405
 406        } else {
 407
 408                /** @todo Handle transmitter with programmable mapping to link encoder. */
 409        }
 410}
 411
 412bool dcn31_link_encoder_is_in_alt_mode(struct link_encoder *enc)
 413{
 414        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 415        uint32_t dp_alt_mode_disable;
 416        bool is_usb_c_alt_mode = false;
 417
 418        if (enc->features.flags.bits.DP_IS_USB_C) {
 419                if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
 420                        // [Note] no need to check hw_internal_rev once phy mux selection is ready
 421                        REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
 422                } else {
 423                /*
 424                 * B0 phys use a new set of registers to check whether alt mode is disabled.
 425                 * if value == 1 alt mode is disabled, otherwise it is enabled.
 426                 */
 427                        if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
 428                                        || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
 429                                        || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
 430                                REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
 431                        } else {
 432                        // [Note] need to change TRANSMITTER_UNIPHY_C/D to F/G once phy mux selection is ready
 433                                REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DISABLE, &dp_alt_mode_disable);
 434                        }
 435                }
 436
 437                is_usb_c_alt_mode = (dp_alt_mode_disable == 0);
 438        }
 439
 440        return is_usb_c_alt_mode;
 441}
 442
 443void dcn31_link_encoder_get_max_link_cap(struct link_encoder *enc,
 444                                                                                 struct dc_link_settings *link_settings)
 445{
 446        struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc);
 447        uint32_t is_in_usb_c_dp4_mode = 0;
 448
 449        dcn10_link_encoder_get_max_link_cap(enc, link_settings);
 450
 451        /* in usb c dp2 mode, max lane count is 2 */
 452        if (enc->funcs->is_in_alt_mode && enc->funcs->is_in_alt_mode(enc)) {
 453                if (enc->ctx->asic_id.hw_internal_rev != YELLOW_CARP_B0) {
 454                        // [Note] no need to check hw_internal_rev once phy mux selection is ready
 455                        REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
 456                } else {
 457                        if ((enc10->base.transmitter == TRANSMITTER_UNIPHY_A)
 458                                        || (enc10->base.transmitter == TRANSMITTER_UNIPHY_B)
 459                                        || (enc10->base.transmitter == TRANSMITTER_UNIPHY_E)) {
 460                                REG_GET(RDPCSTX_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
 461                        } else {
 462                                REG_GET(RDPCSPIPE_PHY_CNTL6, RDPCS_PHY_DPALT_DP4, &is_in_usb_c_dp4_mode);
 463                        }
 464                }
 465                if (!is_in_usb_c_dp4_mode)
 466                        link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count);
 467        }
 468}
 469