LXR linux/drivers/gpu/drm/amd/display/dc/inc/compressor.h

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DAL_COMPRESSOR_H__
  27#define __DAL_COMPRESSOR_H__
  28
  29#include "include/grph_object_id.h"
  30#include "bios_parser_interface.h"
  31
  32enum fbc_compress_ratio {
  33        FBC_COMPRESS_RATIO_INVALID = 0,
  34        FBC_COMPRESS_RATIO_1TO1 = 1,
  35        FBC_COMPRESS_RATIO_2TO1 = 2,
  36        FBC_COMPRESS_RATIO_4TO1 = 4,
  37        FBC_COMPRESS_RATIO_8TO1 = 8,
  38};
  39
  40union fbc_physical_address {
  41        struct {
  42                uint32_t low_part;
  43                int32_t high_part;
  44        } addr;
  45        uint64_t quad_part;
  46};
  47
  48struct compr_addr_and_pitch_params {
  49        /* enum controller_id controller_id; */
  50        uint32_t inst;
  51        uint32_t source_view_width;
  52        uint32_t source_view_height;
  53};
  54
  55enum fbc_hw_max_resolution_supported {
  56        FBC_MAX_X = 3840,
  57        FBC_MAX_Y = 2400,
  58        FBC_MAX_X_SG = 1920,
  59        FBC_MAX_Y_SG = 1080,
  60};
  61
  62struct compressor;
  63
  64struct compressor_funcs {
  65
  66        void (*power_up_fbc)(struct compressor *cp);
  67        void (*enable_fbc)(struct compressor *cp,
  68                struct compr_addr_and_pitch_params *params);
  69        void (*disable_fbc)(struct compressor *cp);
  70        void (*set_fbc_invalidation_triggers)(struct compressor *cp,
  71                uint32_t fbc_trigger);
  72        void (*surface_address_and_pitch)(
  73                struct compressor *cp,
  74                struct compr_addr_and_pitch_params *params);
  75        bool (*is_fbc_enabled_in_hw)(struct compressor *cp,
  76                uint32_t *fbc_mapped_crtc_id);
  77};
  78struct compressor {
  79        struct dc_context *ctx;
  80        /* CONTROLLER_ID_D0 + instance, CONTROLLER_ID_UNDEFINED = 0 */
  81        uint32_t attached_inst;
  82        bool is_enabled;
  83        const struct compressor_funcs *funcs;
  84        union {
  85                uint32_t raw;
  86                struct {
  87                        uint32_t FBC_SUPPORT:1;
  88                        uint32_t FB_POOL:1;
  89                        uint32_t DYNAMIC_ALLOC:1;
  90                        uint32_t LPT_SUPPORT:1;
  91                        uint32_t LPT_MC_CONFIG:1;
  92                        uint32_t DUMMY_BACKEND:1;
  93                        uint32_t CLK_GATING_DISABLED:1;
  94
  95                } bits;
  96        } options;
  97
  98        union fbc_physical_address compr_surface_address;
  99
 100        uint32_t embedded_panel_h_size;
 101        uint32_t embedded_panel_v_size;
 102        uint32_t memory_bus_width;
 103        uint32_t banks_num;
 104        uint32_t raw_size;
 105        uint32_t channel_interleave_size;
 106        uint32_t dram_channels_num;
 107
 108        uint32_t allocated_size;
 109        uint32_t preferred_requested_size;
 110        uint32_t lpt_channels_num;
 111        enum fbc_compress_ratio min_compress_ratio;
 112};
 113
 114struct fbc_input_info {
 115        bool           dynamic_fbc_buffer_alloc;
 116        unsigned int   source_view_width;
 117        unsigned int   source_view_height;
 118        unsigned int   num_of_active_targets;
 119};
 120
 121
 122struct fbc_requested_compressed_size {
 123        unsigned int   preferred_size;
 124        unsigned int   preferred_size_alignment;
 125        unsigned int   min_size;
 126        unsigned int   min_size_alignment;
 127        union {
 128                struct {
 129                        /* Above preferedSize must be allocated in FB pool */
 130                        unsigned int preferred_must_be_framebuffer_pool : 1;
 131                        /* Above minSize must be allocated in FB pool */
 132                        unsigned int min_must_be_framebuffer_pool : 1;
 133                } bits;
 134                unsigned int flags;
 135        };
 136};
 137#endif
 138