LXR linux/drivers/gpu/drm/amd/display/dc/inc/hw/link

   1/*
   2 * Copyright 2017 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23/*
  24 * link_encoder.h
  25 *
  26 *  Created on: Oct 6, 2015
  27 *      Author: yonsun
  28 */
  29
  30#ifndef LINK_ENCODER_H_
  31#define LINK_ENCODER_H_
  32
  33#include "grph_object_defs.h"
  34#include "signal_types.h"
  35#include "dc_types.h"
  36
  37struct dc_context;
  38struct encoder_set_dp_phy_pattern_param;
  39struct link_mst_stream_allocation_table;
  40struct dc_link_settings;
  41struct link_training_settings;
  42struct pipe_ctx;
  43
  44struct encoder_init_data {
  45        enum channel_id channel;
  46        struct graphics_object_id connector;
  47        enum hpd_source_id hpd_source;
  48        /* TODO: in DAL2, here was pointer to EventManagerInterface */
  49        struct graphics_object_id encoder;
  50        struct dc_context *ctx;
  51        enum transmitter transmitter;
  52};
  53
  54struct encoder_feature_support {
  55        union {
  56                struct {
  57                        uint32_t IS_HBR2_CAPABLE:1;
  58                        uint32_t IS_HBR3_CAPABLE:1;
  59                        uint32_t IS_TPS3_CAPABLE:1;
  60                        uint32_t IS_TPS4_CAPABLE:1;
  61                        uint32_t HDMI_6GB_EN:1;
  62                        uint32_t DP_IS_USB_C:1;
  63                } bits;
  64                uint32_t raw;
  65        } flags;
  66
  67        enum dc_color_depth max_hdmi_deep_color;
  68        unsigned int max_hdmi_pixel_clock;
  69        bool hdmi_ycbcr420_supported;
  70        bool dp_ycbcr420_supported;
  71        bool fec_supported;
  72};
  73
  74union dpcd_psr_configuration {
  75        struct {
  76                unsigned char ENABLE                    : 1;
  77                unsigned char TRANSMITTER_ACTIVE_IN_PSR : 1;
  78                unsigned char CRC_VERIFICATION          : 1;
  79                unsigned char FRAME_CAPTURE_INDICATION  : 1;
  80                /* For eDP 1.4, PSR v2*/
  81                unsigned char LINE_CAPTURE_INDICATION   : 1;
  82                /* For eDP 1.4, PSR v2*/
  83                unsigned char IRQ_HPD_WITH_CRC_ERROR    : 1;
  84                unsigned char RESERVED                  : 2;
  85        } bits;
  86        unsigned char raw;
  87};
  88
  89union psr_error_status {
  90        struct {
  91                unsigned char LINK_CRC_ERROR        :1;
  92                unsigned char RFB_STORAGE_ERROR     :1;
  93                unsigned char VSC_SDP_ERROR         :1;
  94                unsigned char RESERVED              :5;
  95        } bits;
  96        unsigned char raw;
  97};
  98
  99union psr_sink_psr_status {
 100        struct {
 101        unsigned char SINK_SELF_REFRESH_STATUS  :3;
 102        unsigned char RESERVED                  :5;
 103        } bits;
 104        unsigned char raw;
 105};
 106
 107struct link_encoder {
 108        const struct link_encoder_funcs *funcs;
 109        int32_t aux_channel_offset;
 110        struct dc_context *ctx;
 111        struct graphics_object_id id;
 112        struct graphics_object_id connector;
 113        uint32_t output_signals;
 114        enum engine_id preferred_engine;
 115        struct encoder_feature_support features;
 116        enum transmitter transmitter;
 117        enum hpd_source_id hpd_source;
 118        bool usbc_combo_phy;
 119};
 120
 121struct link_enc_state {
 122
 123                uint32_t dphy_fec_en;
 124                uint32_t dphy_fec_ready_shadow;
 125                uint32_t dphy_fec_active_status;
 126                uint32_t dp_link_training_complete;
 127
 128};
 129
 130enum encoder_type_select {
 131        ENCODER_TYPE_DIG = 0,
 132        ENCODER_TYPE_HDMI_FRL = 1,
 133        ENCODER_TYPE_DP_128B132B = 2
 134};
 135
 136struct link_encoder_funcs {
 137        void (*read_state)(
 138                        struct link_encoder *enc, struct link_enc_state *s);
 139        bool (*validate_output_with_stream)(
 140                struct link_encoder *enc, const struct dc_stream_state *stream);
 141        void (*hw_init)(struct link_encoder *enc);
 142        void (*setup)(struct link_encoder *enc,
 143                enum signal_type signal);
 144        void (*enable_tmds_output)(struct link_encoder *enc,
 145                enum clock_source_id clock_source,
 146                enum dc_color_depth color_depth,
 147                enum signal_type signal,
 148                uint32_t pixel_clock);
 149        void (*enable_dp_output)(struct link_encoder *enc,
 150                const struct dc_link_settings *link_settings,
 151                enum clock_source_id clock_source);
 152        void (*enable_dp_mst_output)(struct link_encoder *enc,
 153                const struct dc_link_settings *link_settings,
 154                enum clock_source_id clock_source);
 155        void (*enable_lvds_output)(struct link_encoder *enc,
 156                enum clock_source_id clock_source,
 157                uint32_t pixel_clock);
 158        void (*disable_output)(struct link_encoder *link_enc,
 159                enum signal_type signal);
 160        void (*dp_set_lane_settings)(struct link_encoder *enc,
 161                const struct link_training_settings *link_settings);
 162        void (*dp_set_phy_pattern)(struct link_encoder *enc,
 163                const struct encoder_set_dp_phy_pattern_param *para);
 164        void (*update_mst_stream_allocation_table)(
 165                struct link_encoder *enc,
 166                const struct link_mst_stream_allocation_table *table);
 167        void (*psr_program_dp_dphy_fast_training)(struct link_encoder *enc,
 168                        bool exit_link_training_required);
 169        void (*psr_program_secondary_packet)(struct link_encoder *enc,
 170                                unsigned int sdp_transmit_line_num_deadline);
 171        void (*connect_dig_be_to_fe)(struct link_encoder *enc,
 172                enum engine_id engine,
 173                bool connect);
 174        void (*enable_hpd)(struct link_encoder *enc);
 175        void (*disable_hpd)(struct link_encoder *enc);
 176        bool (*is_dig_enabled)(struct link_encoder *enc);
 177        unsigned int (*get_dig_frontend)(struct link_encoder *enc);
 178        void (*destroy)(struct link_encoder **enc);
 179
 180        void (*fec_set_enable)(struct link_encoder *enc,
 181                bool enable);
 182
 183        void (*fec_set_ready)(struct link_encoder *enc,
 184                bool ready);
 185
 186        bool (*fec_is_active)(struct link_encoder *enc);
 187        bool (*is_in_alt_mode) (struct link_encoder *enc);
 188
 189        void (*get_max_link_cap)(struct link_encoder *enc,
 190                struct dc_link_settings *link_settings);
 191
 192        enum signal_type (*get_dig_mode)(
 193                struct link_encoder *enc);
 194        void (*set_dio_phy_mux)(
 195                struct link_encoder *enc,
 196                enum encoder_type_select sel,
 197                uint32_t hpo_inst);
 198};
 199
 200/*
 201 * Used to track assignments of links (display endpoints) to link encoders.
 202 *
 203 * Entry in link_enc_assignments table in struct resource_context.
 204 * Entries only marked valid once encoder assigned to a link and invalidated once unassigned.
 205 * Uses engine ID as identifier since PHY ID not relevant for USB4 DPIA endpoint.
 206 */
 207struct link_enc_assignment {
 208        bool valid;
 209        struct display_endpoint_id ep_id;
 210        enum engine_id eng_id;
 211};
 212
 213#endif /* LINK_ENCODER_H_ */
 214