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26#include <linux/slab.h>
27
28#include "dm_services.h"
29
30#include "include/logger_interface.h"
31
32#include "../dce110/irq_service_dce110.h"
33
34#include "dcn/dcn_2_1_0_offset.h"
35#include "dcn/dcn_2_1_0_sh_mask.h"
36#include "renoir_ip_offset.h"
37
38
39#include "irq_service_dcn21.h"
40
41#include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
42
43enum dc_irq_source to_dal_irq_source_dcn21(
44 struct irq_service *irq_service,
45 uint32_t src_id,
46 uint32_t ext_id)
47{
48 switch (src_id) {
49 case DCN_1_0__SRCID__DC_D1_OTG_VSTARTUP:
50 return DC_IRQ_SOURCE_VBLANK1;
51 case DCN_1_0__SRCID__DC_D2_OTG_VSTARTUP:
52 return DC_IRQ_SOURCE_VBLANK2;
53 case DCN_1_0__SRCID__DC_D3_OTG_VSTARTUP:
54 return DC_IRQ_SOURCE_VBLANK3;
55 case DCN_1_0__SRCID__DC_D4_OTG_VSTARTUP:
56 return DC_IRQ_SOURCE_VBLANK4;
57 case DCN_1_0__SRCID__DC_D5_OTG_VSTARTUP:
58 return DC_IRQ_SOURCE_VBLANK5;
59 case DCN_1_0__SRCID__DC_D6_OTG_VSTARTUP:
60 return DC_IRQ_SOURCE_VBLANK6;
61 case DCN_1_0__SRCID__DMCUB_OUTBOX_LOW_PRIORITY_READY_INT:
62 return DC_IRQ_SOURCE_DMCUB_OUTBOX;
63 case DCN_1_0__SRCID__OTG1_VERTICAL_INTERRUPT0_CONTROL:
64 return DC_IRQ_SOURCE_DC1_VLINE0;
65 case DCN_1_0__SRCID__OTG2_VERTICAL_INTERRUPT0_CONTROL:
66 return DC_IRQ_SOURCE_DC2_VLINE0;
67 case DCN_1_0__SRCID__OTG3_VERTICAL_INTERRUPT0_CONTROL:
68 return DC_IRQ_SOURCE_DC3_VLINE0;
69 case DCN_1_0__SRCID__OTG4_VERTICAL_INTERRUPT0_CONTROL:
70 return DC_IRQ_SOURCE_DC4_VLINE0;
71 case DCN_1_0__SRCID__OTG5_VERTICAL_INTERRUPT0_CONTROL:
72 return DC_IRQ_SOURCE_DC5_VLINE0;
73 case DCN_1_0__SRCID__OTG6_VERTICAL_INTERRUPT0_CONTROL:
74 return DC_IRQ_SOURCE_DC6_VLINE0;
75 case DCN_1_0__SRCID__HUBP0_FLIP_INTERRUPT:
76 return DC_IRQ_SOURCE_PFLIP1;
77 case DCN_1_0__SRCID__HUBP1_FLIP_INTERRUPT:
78 return DC_IRQ_SOURCE_PFLIP2;
79 case DCN_1_0__SRCID__HUBP2_FLIP_INTERRUPT:
80 return DC_IRQ_SOURCE_PFLIP3;
81 case DCN_1_0__SRCID__HUBP3_FLIP_INTERRUPT:
82 return DC_IRQ_SOURCE_PFLIP4;
83 case DCN_1_0__SRCID__HUBP4_FLIP_INTERRUPT:
84 return DC_IRQ_SOURCE_PFLIP5;
85 case DCN_1_0__SRCID__HUBP5_FLIP_INTERRUPT:
86 return DC_IRQ_SOURCE_PFLIP6;
87 case DCN_1_0__SRCID__OTG0_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
88 return DC_IRQ_SOURCE_VUPDATE1;
89 case DCN_1_0__SRCID__OTG1_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
90 return DC_IRQ_SOURCE_VUPDATE2;
91 case DCN_1_0__SRCID__OTG2_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
92 return DC_IRQ_SOURCE_VUPDATE3;
93 case DCN_1_0__SRCID__OTG3_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
94 return DC_IRQ_SOURCE_VUPDATE4;
95 case DCN_1_0__SRCID__OTG4_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
96 return DC_IRQ_SOURCE_VUPDATE5;
97 case DCN_1_0__SRCID__OTG5_IHC_V_UPDATE_NO_LOCK_INTERRUPT:
98 return DC_IRQ_SOURCE_VUPDATE6;
99
100 case DCN_1_0__SRCID__DC_HPD1_INT:
101
102 switch (ext_id) {
103 case DCN_1_0__CTXID__DC_HPD1_INT:
104 return DC_IRQ_SOURCE_HPD1;
105 case DCN_1_0__CTXID__DC_HPD2_INT:
106 return DC_IRQ_SOURCE_HPD2;
107 case DCN_1_0__CTXID__DC_HPD3_INT:
108 return DC_IRQ_SOURCE_HPD3;
109 case DCN_1_0__CTXID__DC_HPD4_INT:
110 return DC_IRQ_SOURCE_HPD4;
111 case DCN_1_0__CTXID__DC_HPD5_INT:
112 return DC_IRQ_SOURCE_HPD5;
113 case DCN_1_0__CTXID__DC_HPD6_INT:
114 return DC_IRQ_SOURCE_HPD6;
115 case DCN_1_0__CTXID__DC_HPD1_RX_INT:
116 return DC_IRQ_SOURCE_HPD1RX;
117 case DCN_1_0__CTXID__DC_HPD2_RX_INT:
118 return DC_IRQ_SOURCE_HPD2RX;
119 case DCN_1_0__CTXID__DC_HPD3_RX_INT:
120 return DC_IRQ_SOURCE_HPD3RX;
121 case DCN_1_0__CTXID__DC_HPD4_RX_INT:
122 return DC_IRQ_SOURCE_HPD4RX;
123 case DCN_1_0__CTXID__DC_HPD5_RX_INT:
124 return DC_IRQ_SOURCE_HPD5RX;
125 case DCN_1_0__CTXID__DC_HPD6_RX_INT:
126 return DC_IRQ_SOURCE_HPD6RX;
127 default:
128 return DC_IRQ_SOURCE_INVALID;
129 }
130 break;
131
132 default:
133 break;
134 }
135 return DC_IRQ_SOURCE_INVALID;
136}
137
138static bool hpd_ack(
139 struct irq_service *irq_service,
140 const struct irq_source_info *info)
141{
142 uint32_t addr = info->status_reg;
143 uint32_t value = dm_read_reg(irq_service->ctx, addr);
144 uint32_t current_status =
145 get_reg_field_value(
146 value,
147 HPD0_DC_HPD_INT_STATUS,
148 DC_HPD_SENSE_DELAYED);
149
150 dal_irq_service_ack_generic(irq_service, info);
151
152 value = dm_read_reg(irq_service->ctx, info->enable_reg);
153
154 set_reg_field_value(
155 value,
156 current_status ? 0 : 1,
157 HPD0_DC_HPD_INT_CONTROL,
158 DC_HPD_INT_POLARITY);
159
160 dm_write_reg(irq_service->ctx, info->enable_reg, value);
161
162 return true;
163}
164
165static const struct irq_source_info_funcs hpd_irq_info_funcs = {
166 .set = NULL,
167 .ack = hpd_ack
168};
169
170static const struct irq_source_info_funcs hpd_rx_irq_info_funcs = {
171 .set = NULL,
172 .ack = NULL
173};
174
175static const struct irq_source_info_funcs pflip_irq_info_funcs = {
176 .set = NULL,
177 .ack = NULL
178};
179
180static const struct irq_source_info_funcs vblank_irq_info_funcs = {
181 .set = NULL,
182 .ack = NULL
183};
184
185static const struct irq_source_info_funcs vupdate_no_lock_irq_info_funcs = {
186 .set = NULL,
187 .ack = NULL
188};
189
190static const struct irq_source_info_funcs dmub_outbox_irq_info_funcs = {
191 .set = NULL,
192 .ack = NULL
193};
194
195static const struct irq_source_info_funcs vline0_irq_info_funcs = {
196 .set = NULL,
197 .ack = NULL
198};
199
200#undef BASE_INNER
201#define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
202
203
204#define BASE(seg) \
205 BASE_INNER(seg)
206
207
208#define SRI(reg_name, block, id)\
209 BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
210 mm ## block ## id ## _ ## reg_name
211
212#define SRI_DMUB(reg_name)\
213 BASE(mm ## reg_name ## _BASE_IDX) + \
214 mm ## reg_name
215
216#define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\
217 .enable_reg = SRI(reg1, block, reg_num),\
218 .enable_mask = \
219 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
220 .enable_value = {\
221 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
222 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
223 },\
224 .ack_reg = SRI(reg2, block, reg_num),\
225 .ack_mask = \
226 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
227 .ack_value = \
228 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
229
230#define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\
231 .enable_reg = SRI_DMUB(reg1),\
232 .enable_mask = \
233 reg1 ## __ ## mask1 ## _MASK,\
234 .enable_value = {\
235 reg1 ## __ ## mask1 ## _MASK,\
236 ~reg1 ## __ ## mask1 ## _MASK \
237 },\
238 .ack_reg = SRI_DMUB(reg2),\
239 .ack_mask = \
240 reg2 ## __ ## mask2 ## _MASK,\
241 .ack_value = \
242 reg2 ## __ ## mask2 ## _MASK \
243
244#define hpd_int_entry(reg_num)\
245 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
246 IRQ_REG_ENTRY(HPD, reg_num,\
247 DC_HPD_INT_CONTROL, DC_HPD_INT_EN,\
248 DC_HPD_INT_CONTROL, DC_HPD_INT_ACK),\
249 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
250 .funcs = &hpd_irq_info_funcs\
251 }
252
253#define hpd_rx_int_entry(reg_num)\
254 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
255 IRQ_REG_ENTRY(HPD, reg_num,\
256 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_EN,\
257 DC_HPD_INT_CONTROL, DC_HPD_RX_INT_ACK),\
258 .status_reg = SRI(DC_HPD_INT_STATUS, HPD, reg_num),\
259 .funcs = &hpd_rx_irq_info_funcs\
260 }
261#define pflip_int_entry(reg_num)\
262 [DC_IRQ_SOURCE_PFLIP1 + reg_num] = {\
263 IRQ_REG_ENTRY(HUBPREQ, reg_num,\
264 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_INT_MASK,\
265 DCSURF_SURFACE_FLIP_INTERRUPT, SURFACE_FLIP_CLEAR),\
266 .funcs = &pflip_irq_info_funcs\
267 }
268
269#define vupdate_int_entry(reg_num)\
270 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
271 IRQ_REG_ENTRY(OTG, reg_num,\
272 OTG_GLOBAL_SYNC_STATUS, VUPDATE_INT_EN,\
273 OTG_GLOBAL_SYNC_STATUS, VUPDATE_EVENT_CLEAR),\
274 .funcs = &vblank_irq_info_funcs\
275 }
276
277
278
279
280#define vupdate_no_lock_int_entry(reg_num)\
281 [DC_IRQ_SOURCE_VUPDATE1 + reg_num] = {\
282 IRQ_REG_ENTRY(OTG, reg_num,\
283 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_INT_EN,\
284 OTG_GLOBAL_SYNC_STATUS, VUPDATE_NO_LOCK_EVENT_CLEAR),\
285 .funcs = &vupdate_no_lock_irq_info_funcs\
286 }
287
288#define vblank_int_entry(reg_num)\
289 [DC_IRQ_SOURCE_VBLANK1 + reg_num] = {\
290 IRQ_REG_ENTRY(OTG, reg_num,\
291 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_INT_EN,\
292 OTG_GLOBAL_SYNC_STATUS, VSTARTUP_EVENT_CLEAR),\
293 .funcs = &vblank_irq_info_funcs\
294 }
295
296#define vline0_int_entry(reg_num)\
297 [DC_IRQ_SOURCE_DC1_VLINE0 + reg_num] = {\
298 IRQ_REG_ENTRY(OTG, reg_num,\
299 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE,\
300 OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_CLEAR),\
301 .funcs = &vline0_irq_info_funcs\
302 }
303
304#define dmub_outbox_int_entry()\
305 [DC_IRQ_SOURCE_DMCUB_OUTBOX] = {\
306 IRQ_REG_ENTRY_DMUB(DMCUB_INTERRUPT_ENABLE, DMCUB_OUTBOX1_READY_INT_EN,\
307 DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX1_READY_INT_ACK),\
308 .funcs = &dmub_outbox_irq_info_funcs\
309 }
310
311#define dummy_irq_entry() \
312 {\
313 .funcs = &dummy_irq_info_funcs\
314 }
315
316#define i2c_int_entry(reg_num) \
317 [DC_IRQ_SOURCE_I2C_DDC ## reg_num] = dummy_irq_entry()
318
319#define dp_sink_int_entry(reg_num) \
320 [DC_IRQ_SOURCE_DPSINK ## reg_num] = dummy_irq_entry()
321
322#define gpio_pad_int_entry(reg_num) \
323 [DC_IRQ_SOURCE_GPIOPAD ## reg_num] = dummy_irq_entry()
324
325#define dc_underflow_int_entry(reg_num) \
326 [DC_IRQ_SOURCE_DC ## reg_num ## UNDERFLOW] = dummy_irq_entry()
327
328static const struct irq_source_info_funcs dummy_irq_info_funcs = {
329 .set = dal_irq_service_dummy_set,
330 .ack = dal_irq_service_dummy_ack
331};
332
333static const struct irq_source_info
334irq_source_info_dcn21[DAL_IRQ_SOURCES_NUMBER] = {
335 [DC_IRQ_SOURCE_INVALID] = dummy_irq_entry(),
336 hpd_int_entry(0),
337 hpd_int_entry(1),
338 hpd_int_entry(2),
339 hpd_int_entry(3),
340 hpd_int_entry(4),
341 hpd_rx_int_entry(0),
342 hpd_rx_int_entry(1),
343 hpd_rx_int_entry(2),
344 hpd_rx_int_entry(3),
345 hpd_rx_int_entry(4),
346 i2c_int_entry(1),
347 i2c_int_entry(2),
348 i2c_int_entry(3),
349 i2c_int_entry(4),
350 i2c_int_entry(5),
351 i2c_int_entry(6),
352 dp_sink_int_entry(1),
353 dp_sink_int_entry(2),
354 dp_sink_int_entry(3),
355 dp_sink_int_entry(4),
356 dp_sink_int_entry(5),
357 dp_sink_int_entry(6),
358 [DC_IRQ_SOURCE_TIMER] = dummy_irq_entry(),
359 pflip_int_entry(0),
360 pflip_int_entry(1),
361 pflip_int_entry(2),
362 pflip_int_entry(3),
363 [DC_IRQ_SOURCE_PFLIP5] = dummy_irq_entry(),
364 [DC_IRQ_SOURCE_PFLIP6] = dummy_irq_entry(),
365 [DC_IRQ_SOURCE_PFLIP_UNDERLAY0] = dummy_irq_entry(),
366 gpio_pad_int_entry(0),
367 gpio_pad_int_entry(1),
368 gpio_pad_int_entry(2),
369 gpio_pad_int_entry(3),
370 gpio_pad_int_entry(4),
371 gpio_pad_int_entry(5),
372 gpio_pad_int_entry(6),
373 gpio_pad_int_entry(7),
374 gpio_pad_int_entry(8),
375 gpio_pad_int_entry(9),
376 gpio_pad_int_entry(10),
377 gpio_pad_int_entry(11),
378 gpio_pad_int_entry(12),
379 gpio_pad_int_entry(13),
380 gpio_pad_int_entry(14),
381 gpio_pad_int_entry(15),
382 gpio_pad_int_entry(16),
383 gpio_pad_int_entry(17),
384 gpio_pad_int_entry(18),
385 gpio_pad_int_entry(19),
386 gpio_pad_int_entry(20),
387 gpio_pad_int_entry(21),
388 gpio_pad_int_entry(22),
389 gpio_pad_int_entry(23),
390 gpio_pad_int_entry(24),
391 gpio_pad_int_entry(25),
392 gpio_pad_int_entry(26),
393 gpio_pad_int_entry(27),
394 gpio_pad_int_entry(28),
395 gpio_pad_int_entry(29),
396 gpio_pad_int_entry(30),
397 dc_underflow_int_entry(1),
398 dc_underflow_int_entry(2),
399 dc_underflow_int_entry(3),
400 dc_underflow_int_entry(4),
401 dc_underflow_int_entry(5),
402 dc_underflow_int_entry(6),
403 [DC_IRQ_SOURCE_DMCU_SCP] = dummy_irq_entry(),
404 [DC_IRQ_SOURCE_VBIOS_SW] = dummy_irq_entry(),
405 vupdate_int_entry(0),
406 vupdate_int_entry(1),
407 vupdate_int_entry(2),
408 vupdate_int_entry(3),
409 vupdate_int_entry(4),
410 vupdate_int_entry(5),
411 vupdate_no_lock_int_entry(0),
412 vupdate_no_lock_int_entry(1),
413 vupdate_no_lock_int_entry(2),
414 vupdate_no_lock_int_entry(3),
415 vupdate_no_lock_int_entry(4),
416 vupdate_no_lock_int_entry(5),
417 vblank_int_entry(0),
418 vblank_int_entry(1),
419 vblank_int_entry(2),
420 vblank_int_entry(3),
421 vblank_int_entry(4),
422 vblank_int_entry(5),
423 vline0_int_entry(0),
424 vline0_int_entry(1),
425 vline0_int_entry(2),
426 vline0_int_entry(3),
427 vline0_int_entry(4),
428 vline0_int_entry(5),
429 dmub_outbox_int_entry(),
430};
431
432static const struct irq_service_funcs irq_service_funcs_dcn21 = {
433 .to_dal_irq_source = to_dal_irq_source_dcn21
434};
435
436static void dcn21_irq_construct(
437 struct irq_service *irq_service,
438 struct irq_service_init_data *init_data)
439{
440 dal_irq_service_construct(irq_service, init_data);
441
442 irq_service->info = irq_source_info_dcn21;
443 irq_service->funcs = &irq_service_funcs_dcn21;
444}
445
446struct irq_service *dal_irq_service_dcn21_create(
447 struct irq_service_init_data *init_data)
448{
449 struct irq_service *irq_service = kzalloc(sizeof(*irq_service),
450 GFP_KERNEL);
451
452 if (!irq_service)
453 return NULL;
454
455 dcn21_irq_construct(irq_service, init_data);
456 return irq_service;
457}
458
