LXR linux/drivers/gpu/drm/amd/display/dc/irq

   1/*
   2 * Copyright 2012-15 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 * Authors: AMD
  23 *
  24 */
  25
  26#ifndef __DAL_IRQ_TYPES_H__
  27#define __DAL_IRQ_TYPES_H__
  28
  29#include "os_types.h"
  30
  31struct dc_context;
  32
  33typedef void (*interrupt_handler)(void *);
  34
  35typedef void *irq_handler_idx;
  36#define DAL_INVALID_IRQ_HANDLER_IDX NULL
  37
  38/* The order of the IRQ sources is important and MUST match the one's
  39of base driver */
  40enum dc_irq_source {
  41        /* Use as mask to specify invalid irq source */
  42        DC_IRQ_SOURCE_INVALID = 0,
  43
  44        DC_IRQ_SOURCE_HPD1,
  45        DC_IRQ_SOURCE_HPD2,
  46        DC_IRQ_SOURCE_HPD3,
  47        DC_IRQ_SOURCE_HPD4,
  48        DC_IRQ_SOURCE_HPD5,
  49        DC_IRQ_SOURCE_HPD6,
  50
  51        DC_IRQ_SOURCE_HPD1RX,
  52        DC_IRQ_SOURCE_HPD2RX,
  53        DC_IRQ_SOURCE_HPD3RX,
  54        DC_IRQ_SOURCE_HPD4RX,
  55        DC_IRQ_SOURCE_HPD5RX,
  56        DC_IRQ_SOURCE_HPD6RX,
  57
  58        DC_IRQ_SOURCE_I2C_DDC1,
  59        DC_IRQ_SOURCE_I2C_DDC2,
  60        DC_IRQ_SOURCE_I2C_DDC3,
  61        DC_IRQ_SOURCE_I2C_DDC4,
  62        DC_IRQ_SOURCE_I2C_DDC5,
  63        DC_IRQ_SOURCE_I2C_DDC6,
  64
  65        DC_IRQ_SOURCE_DPSINK1,
  66        DC_IRQ_SOURCE_DPSINK2,
  67        DC_IRQ_SOURCE_DPSINK3,
  68        DC_IRQ_SOURCE_DPSINK4,
  69        DC_IRQ_SOURCE_DPSINK5,
  70        DC_IRQ_SOURCE_DPSINK6,
  71
  72        DC_IRQ_SOURCE_TIMER,
  73
  74        DC_IRQ_SOURCE_PFLIP_FIRST,
  75        DC_IRQ_SOURCE_PFLIP1 = DC_IRQ_SOURCE_PFLIP_FIRST,
  76        DC_IRQ_SOURCE_PFLIP2,
  77        DC_IRQ_SOURCE_PFLIP3,
  78        DC_IRQ_SOURCE_PFLIP4,
  79        DC_IRQ_SOURCE_PFLIP5,
  80        DC_IRQ_SOURCE_PFLIP6,
  81        DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
  82        DC_IRQ_SOURCE_PFLIP_LAST = DC_IRQ_SOURCE_PFLIP_UNDERLAY0,
  83
  84        DC_IRQ_SOURCE_GPIOPAD0,
  85        DC_IRQ_SOURCE_GPIOPAD1,
  86        DC_IRQ_SOURCE_GPIOPAD2,
  87        DC_IRQ_SOURCE_GPIOPAD3,
  88        DC_IRQ_SOURCE_GPIOPAD4,
  89        DC_IRQ_SOURCE_GPIOPAD5,
  90        DC_IRQ_SOURCE_GPIOPAD6,
  91        DC_IRQ_SOURCE_GPIOPAD7,
  92        DC_IRQ_SOURCE_GPIOPAD8,
  93        DC_IRQ_SOURCE_GPIOPAD9,
  94        DC_IRQ_SOURCE_GPIOPAD10,
  95        DC_IRQ_SOURCE_GPIOPAD11,
  96        DC_IRQ_SOURCE_GPIOPAD12,
  97        DC_IRQ_SOURCE_GPIOPAD13,
  98        DC_IRQ_SOURCE_GPIOPAD14,
  99        DC_IRQ_SOURCE_GPIOPAD15,
 100        DC_IRQ_SOURCE_GPIOPAD16,
 101        DC_IRQ_SOURCE_GPIOPAD17,
 102        DC_IRQ_SOURCE_GPIOPAD18,
 103        DC_IRQ_SOURCE_GPIOPAD19,
 104        DC_IRQ_SOURCE_GPIOPAD20,
 105        DC_IRQ_SOURCE_GPIOPAD21,
 106        DC_IRQ_SOURCE_GPIOPAD22,
 107        DC_IRQ_SOURCE_GPIOPAD23,
 108        DC_IRQ_SOURCE_GPIOPAD24,
 109        DC_IRQ_SOURCE_GPIOPAD25,
 110        DC_IRQ_SOURCE_GPIOPAD26,
 111        DC_IRQ_SOURCE_GPIOPAD27,
 112        DC_IRQ_SOURCE_GPIOPAD28,
 113        DC_IRQ_SOURCE_GPIOPAD29,
 114        DC_IRQ_SOURCE_GPIOPAD30,
 115
 116        DC_IRQ_SOURCE_DC1UNDERFLOW,
 117        DC_IRQ_SOURCE_DC2UNDERFLOW,
 118        DC_IRQ_SOURCE_DC3UNDERFLOW,
 119        DC_IRQ_SOURCE_DC4UNDERFLOW,
 120        DC_IRQ_SOURCE_DC5UNDERFLOW,
 121        DC_IRQ_SOURCE_DC6UNDERFLOW,
 122
 123        DC_IRQ_SOURCE_DMCU_SCP,
 124        DC_IRQ_SOURCE_VBIOS_SW,
 125
 126        DC_IRQ_SOURCE_VUPDATE1,
 127        DC_IRQ_SOURCE_VUPDATE2,
 128        DC_IRQ_SOURCE_VUPDATE3,
 129        DC_IRQ_SOURCE_VUPDATE4,
 130        DC_IRQ_SOURCE_VUPDATE5,
 131        DC_IRQ_SOURCE_VUPDATE6,
 132
 133        DC_IRQ_SOURCE_VBLANK1,
 134        DC_IRQ_SOURCE_VBLANK2,
 135        DC_IRQ_SOURCE_VBLANK3,
 136        DC_IRQ_SOURCE_VBLANK4,
 137        DC_IRQ_SOURCE_VBLANK5,
 138        DC_IRQ_SOURCE_VBLANK6,
 139
 140        DC_IRQ_SOURCE_DC1_VLINE0,
 141        DC_IRQ_SOURCE_DC2_VLINE0,
 142        DC_IRQ_SOURCE_DC3_VLINE0,
 143        DC_IRQ_SOURCE_DC4_VLINE0,
 144        DC_IRQ_SOURCE_DC5_VLINE0,
 145        DC_IRQ_SOURCE_DC6_VLINE0,
 146
 147        DC_IRQ_SOURCE_DC1_VLINE1,
 148        DC_IRQ_SOURCE_DC2_VLINE1,
 149        DC_IRQ_SOURCE_DC3_VLINE1,
 150        DC_IRQ_SOURCE_DC4_VLINE1,
 151        DC_IRQ_SOURCE_DC5_VLINE1,
 152        DC_IRQ_SOURCE_DC6_VLINE1,
 153        DC_IRQ_SOURCE_DMCUB_OUTBOX,
 154        DC_IRQ_SOURCE_DMCUB_OUTBOX0,
 155        DC_IRQ_SOURCE_DMCUB_GENERAL_DATAOUT,
 156        DAL_IRQ_SOURCES_NUMBER
 157};
 158
 159enum irq_type
 160{
 161        IRQ_TYPE_PFLIP = DC_IRQ_SOURCE_PFLIP1,
 162        IRQ_TYPE_VUPDATE = DC_IRQ_SOURCE_VUPDATE1,
 163        IRQ_TYPE_VBLANK = DC_IRQ_SOURCE_VBLANK1,
 164        IRQ_TYPE_VLINE0 = DC_IRQ_SOURCE_DC1_VLINE0,
 165};
 166
 167#define DAL_VALID_IRQ_SRC_NUM(src) \
 168        ((src) < DAL_IRQ_SOURCES_NUMBER && (src) > DC_IRQ_SOURCE_INVALID)
 169
 170/* Number of Page Flip IRQ Sources. */
 171#define DAL_PFLIP_IRQ_SRC_NUM \
 172        (DC_IRQ_SOURCE_PFLIP_LAST - DC_IRQ_SOURCE_PFLIP_FIRST + 1)
 173
 174/* the number of contexts may be expanded in the future based on needs */
 175enum dc_interrupt_context {
 176        INTERRUPT_LOW_IRQ_CONTEXT = 0,
 177        INTERRUPT_HIGH_IRQ_CONTEXT,
 178        INTERRUPT_CONTEXT_NUMBER
 179};
 180
 181enum dc_interrupt_porlarity {
 182        INTERRUPT_POLARITY_DEFAULT = 0,
 183        INTERRUPT_POLARITY_LOW = INTERRUPT_POLARITY_DEFAULT,
 184        INTERRUPT_POLARITY_HIGH,
 185        INTERRUPT_POLARITY_BOTH
 186};
 187
 188#define DC_DECODE_INTERRUPT_POLARITY(int_polarity) \
 189        (int_polarity == INTERRUPT_POLARITY_LOW) ? "Low" : \
 190        (int_polarity == INTERRUPT_POLARITY_HIGH) ? "High" : \
 191        (int_polarity == INTERRUPT_POLARITY_BOTH) ? "Both" : "Invalid"
 192
 193struct dc_timer_interrupt_params {
 194        uint32_t micro_sec_interval;
 195        enum dc_interrupt_context int_context;
 196};
 197
 198struct dc_interrupt_params {
 199        /* The polarity *change* which will trigger an interrupt.
 200         * If 'requested_polarity == INTERRUPT_POLARITY_BOTH', then
 201         * 'current_polarity' must be initialised. */
 202        enum dc_interrupt_porlarity requested_polarity;
 203        /* If 'requested_polarity == INTERRUPT_POLARITY_BOTH',
 204         * 'current_polarity' should contain the current state, which means
 205         * the interrupt will be triggered when state changes from what is,
 206         * in 'current_polarity'. */
 207        enum dc_interrupt_porlarity current_polarity;
 208        enum dc_irq_source irq_source;
 209        enum dc_interrupt_context int_context;
 210};
 211
 212#endif
 213