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26#ifndef __DAL_BIOS_PARSER_TYPES_H__
27
28#define __DAL_BIOS_PARSER_TYPES_H__
29
30#include "dm_services.h"
31#include "include/signal_types.h"
32#include "include/grph_object_ctrl_defs.h"
33#include "include/gpio_types.h"
34#include "include/link_service_types.h"
35
36
37enum as_signal_type {
38 AS_SIGNAL_TYPE_NONE = 0L,
39 AS_SIGNAL_TYPE_DVI,
40 AS_SIGNAL_TYPE_HDMI,
41 AS_SIGNAL_TYPE_LVDS,
42 AS_SIGNAL_TYPE_DISPLAY_PORT,
43 AS_SIGNAL_TYPE_GPU_PLL,
44 AS_SIGNAL_TYPE_XGMI,
45 AS_SIGNAL_TYPE_UNKNOWN
46};
47
48enum bp_result {
49 BP_RESULT_OK = 0,
50 BP_RESULT_BADINPUT,
51 BP_RESULT_BADBIOSTABLE,
52 BP_RESULT_UNSUPPORTED,
53 BP_RESULT_NORECORD,
54 BP_RESULT_FAILURE
55};
56
57enum bp_encoder_control_action {
58
59 ENCODER_CONTROL_DISABLE = 0,
60 ENCODER_CONTROL_ENABLE,
61 ENCODER_CONTROL_SETUP,
62 ENCODER_CONTROL_INIT
63};
64
65enum bp_transmitter_control_action {
66
67 TRANSMITTER_CONTROL_DISABLE = 0,
68 TRANSMITTER_CONTROL_ENABLE,
69 TRANSMITTER_CONTROL_BACKLIGHT_OFF,
70 TRANSMITTER_CONTROL_BACKLIGHT_ON,
71 TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS,
72 TRANSMITTER_CONTROL_LCD_SETF_TEST_START,
73 TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP,
74 TRANSMITTER_CONTROL_INIT,
75 TRANSMITTER_CONTROL_DEACTIVATE,
76 TRANSMITTER_CONTROL_ACTIAVATE,
77 TRANSMITTER_CONTROL_SETUP,
78 TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS,
79
80
81
82 TRANSMITTER_CONTROL_POWER_ON,
83
84
85
86 TRANSMITTER_CONTROL_POWER_OFF
87};
88
89enum bp_external_encoder_control_action {
90 EXTERNAL_ENCODER_CONTROL_DISABLE = 0,
91 EXTERNAL_ENCODER_CONTROL_ENABLE = 1,
92 EXTERNAL_ENCODER_CONTROL_INIT = 0x7,
93 EXTERNAL_ENCODER_CONTROL_SETUP = 0xf,
94 EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10,
95 EXTERNAL_ENCODER_CONTROL_BLANK = 0x11,
96};
97
98enum bp_pipe_control_action {
99 ASIC_PIPE_DISABLE = 0,
100 ASIC_PIPE_ENABLE,
101 ASIC_PIPE_INIT
102};
103
104enum bp_lvtma_control_action {
105 LVTMA_CONTROL_LCD_BLOFF = 2,
106 LVTMA_CONTROL_LCD_BLON = 3,
107 LVTMA_CONTROL_POWER_ON = 12,
108 LVTMA_CONTROL_POWER_OFF = 13
109};
110
111struct bp_encoder_control {
112 enum bp_encoder_control_action action;
113 enum engine_id engine_id;
114 enum transmitter transmitter;
115 enum signal_type signal;
116 enum dc_lane_count lanes_number;
117 enum dc_color_depth color_depth;
118 bool enable_dp_audio;
119 uint32_t pixel_clock;
120};
121
122struct bp_external_encoder_control {
123 enum bp_external_encoder_control_action action;
124 enum engine_id engine_id;
125 enum dc_link_rate link_rate;
126 enum dc_lane_count lanes_number;
127 enum signal_type signal;
128 enum dc_color_depth color_depth;
129 bool coherent;
130 struct graphics_object_id encoder_id;
131 struct graphics_object_id connector_obj_id;
132 uint32_t pixel_clock;
133};
134
135struct bp_crtc_source_select {
136 enum engine_id engine_id;
137 enum controller_id controller_id;
138
139 enum signal_type signal;
140
141 enum signal_type sink_signal;
142 enum display_output_bit_depth display_output_bit_depth;
143 bool enable_dp_audio;
144};
145
146struct bp_transmitter_control {
147 enum bp_transmitter_control_action action;
148 enum engine_id engine_id;
149 enum transmitter transmitter;
150 enum dc_lane_count lanes_number;
151 enum clock_source_id pll_id;
152 enum signal_type signal;
153 enum dc_color_depth color_depth;
154 enum hpd_source_id hpd_sel;
155 struct graphics_object_id connector_obj_id;
156
157
158
159 uint32_t pixel_clock;
160 uint32_t lane_select;
161 uint32_t lane_settings;
162 bool coherent;
163 bool multi_path;
164 bool single_pll_mode;
165};
166
167struct bp_hw_crtc_timing_parameters {
168 enum controller_id controller_id;
169
170 uint32_t h_total;
171 uint32_t h_addressable;
172 uint32_t h_overscan_left;
173 uint32_t h_overscan_right;
174 uint32_t h_sync_start;
175 uint32_t h_sync_width;
176
177
178 uint32_t v_total;
179 uint32_t v_addressable;
180 uint32_t v_overscan_top;
181 uint32_t v_overscan_bottom;
182 uint32_t v_sync_start;
183 uint32_t v_sync_width;
184
185 struct timing_flags {
186 uint32_t INTERLACE:1;
187 uint32_t PIXEL_REPETITION:4;
188 uint32_t HSYNC_POSITIVE_POLARITY:1;
189 uint32_t VSYNC_POSITIVE_POLARITY:1;
190 uint32_t HORZ_COUNT_BY_TWO:1;
191 } flags;
192};
193
194struct bp_adjust_pixel_clock_parameters {
195
196 enum signal_type signal_type;
197
198 struct graphics_object_id encoder_object_id;
199
200
201
202 uint32_t pixel_clock;
203
204 uint32_t adjusted_pixel_clock;
205
206
207 uint32_t reference_divider;
208
209
210 uint32_t pixel_clock_post_divider;
211
212 bool ss_enable;
213};
214
215struct bp_pixel_clock_parameters {
216 enum controller_id controller_id;
217 enum clock_source_id pll_id;
218
219 enum signal_type signal_type;
220
221
222 uint32_t target_pixel_clock_100hz;
223
224 uint32_t reference_divider;
225
226 uint32_t feedback_divider;
227
228 uint32_t fractional_feedback_divider;
229
230 uint32_t pixel_clock_post_divider;
231 struct graphics_object_id encoder_object_id;
232
233
234 uint32_t dfs_bypass_display_clock;
235
236 enum transmitter_color_depth color_depth;
237
238 struct program_pixel_clock_flags {
239 uint32_t FORCE_PROGRAMMING_OF_PLL:1;
240
241
242 uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1;
243
244 uint32_t SET_EXTERNAL_REF_DIV_SRC:1;
245
246 uint32_t SET_DISPCLK_DFS_BYPASS:1;
247
248 uint32_t PROGRAM_PHY_PLL_ONLY:1;
249
250 uint32_t SUPPORT_YUV_420:1;
251
252 uint32_t SET_XTALIN_REF_SRC:1;
253
254 uint32_t SET_GENLOCK_REF_DIV_SRC:1;
255 } flags;
256};
257
258enum bp_dce_clock_type {
259 DCECLOCK_TYPE_DISPLAY_CLOCK = 0,
260 DCECLOCK_TYPE_DPREFCLK = 1
261};
262
263
264struct bp_set_dce_clock_parameters {
265 enum clock_source_id pll_id;
266
267 uint32_t target_clock_frequency;
268
269 enum bp_dce_clock_type clock_type;
270
271 struct set_dce_clock_flags {
272 uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1;
273
274 uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1;
275
276 uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1;
277
278 uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1;
279 } flags;
280};
281
282struct spread_spectrum_flags {
283
284 uint32_t CENTER_SPREAD:1;
285
286 uint32_t EXTERNAL_SS:1;
287
288 uint32_t DS_TYPE:1;
289};
290
291struct bp_spread_spectrum_parameters {
292 enum clock_source_id pll_id;
293 uint32_t percentage;
294 uint32_t ds_frac_amount;
295
296 union {
297 struct {
298 uint32_t step;
299 uint32_t delay;
300 uint32_t range;
301 } ver1;
302 struct {
303 uint32_t feedback_amount;
304 uint32_t nfrac_amount;
305 uint32_t ds_frac_size;
306 } ds;
307 };
308
309 struct spread_spectrum_flags flags;
310};
311
312struct bp_disp_connector_caps_info {
313 uint32_t INTERNAL_DISPLAY : 1;
314 uint32_t INTERNAL_DISPLAY_BL : 1;
315};
316
317struct bp_encoder_cap_info {
318 uint32_t DP_HBR2_CAP:1;
319 uint32_t DP_HBR2_EN:1;
320 uint32_t DP_HBR3_EN:1;
321 uint32_t HDMI_6GB_EN:1;
322 uint32_t DP_IS_USB_C:1;
323 uint32_t RESERVED:27;
324};
325
326struct bp_soc_bb_info {
327 uint32_t dram_clock_change_latency_100ns;
328 uint32_t dram_sr_exit_latency_100ns;
329 uint32_t dram_sr_enter_exit_latency_100ns;
330};
331
332#endif
333