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23#ifndef __AMD_SHARED_H__
24#define __AMD_SHARED_H__
25
26#include <drm/amd_asic_type.h>
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29#define AMD_MAX_USEC_TIMEOUT 1000000
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34enum amd_chip_flags {
35 AMD_ASIC_MASK = 0x0000ffffUL,
36 AMD_FLAGS_MASK = 0xffff0000UL,
37 AMD_IS_MOBILITY = 0x00010000UL,
38 AMD_IS_APU = 0x00020000UL,
39 AMD_IS_PX = 0x00040000UL,
40 AMD_EXP_HW_SUPPORT = 0x00080000UL,
41};
42
43enum amd_apu_flags {
44 AMD_APU_IS_RAVEN = 0x00000001UL,
45 AMD_APU_IS_RAVEN2 = 0x00000002UL,
46 AMD_APU_IS_PICASSO = 0x00000004UL,
47 AMD_APU_IS_RENOIR = 0x00000008UL,
48 AMD_APU_IS_GREEN_SARDINE = 0x00000010UL,
49 AMD_APU_IS_VANGOGH = 0x00000020UL,
50 AMD_APU_IS_CYAN_SKILLFISH2 = 0x00000040UL,
51};
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87enum amd_ip_block_type {
88 AMD_IP_BLOCK_TYPE_COMMON,
89 AMD_IP_BLOCK_TYPE_GMC,
90 AMD_IP_BLOCK_TYPE_IH,
91 AMD_IP_BLOCK_TYPE_SMC,
92 AMD_IP_BLOCK_TYPE_PSP,
93 AMD_IP_BLOCK_TYPE_DCE,
94 AMD_IP_BLOCK_TYPE_GFX,
95 AMD_IP_BLOCK_TYPE_SDMA,
96 AMD_IP_BLOCK_TYPE_UVD,
97 AMD_IP_BLOCK_TYPE_VCE,
98 AMD_IP_BLOCK_TYPE_ACP,
99 AMD_IP_BLOCK_TYPE_VCN,
100 AMD_IP_BLOCK_TYPE_MES,
101 AMD_IP_BLOCK_TYPE_JPEG
102};
103
104enum amd_clockgating_state {
105 AMD_CG_STATE_GATE = 0,
106 AMD_CG_STATE_UNGATE,
107};
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109
110enum amd_powergating_state {
111 AMD_PG_STATE_GATE = 0,
112 AMD_PG_STATE_UNGATE,
113};
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116
117#define AMD_CG_SUPPORT_GFX_MGCG (1 << 0)
118#define AMD_CG_SUPPORT_GFX_MGLS (1 << 1)
119#define AMD_CG_SUPPORT_GFX_CGCG (1 << 2)
120#define AMD_CG_SUPPORT_GFX_CGLS (1 << 3)
121#define AMD_CG_SUPPORT_GFX_CGTS (1 << 4)
122#define AMD_CG_SUPPORT_GFX_CGTS_LS (1 << 5)
123#define AMD_CG_SUPPORT_GFX_CP_LS (1 << 6)
124#define AMD_CG_SUPPORT_GFX_RLC_LS (1 << 7)
125#define AMD_CG_SUPPORT_MC_LS (1 << 8)
126#define AMD_CG_SUPPORT_MC_MGCG (1 << 9)
127#define AMD_CG_SUPPORT_SDMA_LS (1 << 10)
128#define AMD_CG_SUPPORT_SDMA_MGCG (1 << 11)
129#define AMD_CG_SUPPORT_BIF_LS (1 << 12)
130#define AMD_CG_SUPPORT_UVD_MGCG (1 << 13)
131#define AMD_CG_SUPPORT_VCE_MGCG (1 << 14)
132#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
133#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
134#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
135#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
136#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
137#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
138#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
139#define AMD_CG_SUPPORT_DRM_MGCG (1 << 22)
140#define AMD_CG_SUPPORT_DF_MGCG (1 << 23)
141#define AMD_CG_SUPPORT_VCN_MGCG (1 << 24)
142#define AMD_CG_SUPPORT_HDP_DS (1 << 25)
143#define AMD_CG_SUPPORT_HDP_SD (1 << 26)
144#define AMD_CG_SUPPORT_IH_CG (1 << 27)
145#define AMD_CG_SUPPORT_ATHUB_LS (1 << 28)
146#define AMD_CG_SUPPORT_ATHUB_MGCG (1 << 29)
147#define AMD_CG_SUPPORT_JPEG_MGCG (1 << 30)
148#define AMD_CG_SUPPORT_GFX_FGCG (1 << 31)
149
150#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
151#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
152#define AMD_PG_SUPPORT_GFX_DMG (1 << 2)
153#define AMD_PG_SUPPORT_UVD (1 << 3)
154#define AMD_PG_SUPPORT_VCE (1 << 4)
155#define AMD_PG_SUPPORT_CP (1 << 5)
156#define AMD_PG_SUPPORT_GDS (1 << 6)
157#define AMD_PG_SUPPORT_RLC_SMU_HS (1 << 7)
158#define AMD_PG_SUPPORT_SDMA (1 << 8)
159#define AMD_PG_SUPPORT_ACP (1 << 9)
160#define AMD_PG_SUPPORT_SAMU (1 << 10)
161#define AMD_PG_SUPPORT_GFX_QUICK_MG (1 << 11)
162#define AMD_PG_SUPPORT_GFX_PIPELINE (1 << 12)
163#define AMD_PG_SUPPORT_MMHUB (1 << 13)
164#define AMD_PG_SUPPORT_VCN (1 << 14)
165#define AMD_PG_SUPPORT_VCN_DPG (1 << 15)
166#define AMD_PG_SUPPORT_ATHUB (1 << 16)
167#define AMD_PG_SUPPORT_JPEG (1 << 17)
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197enum PP_FEATURE_MASK {
198 PP_SCLK_DPM_MASK = 0x1,
199 PP_MCLK_DPM_MASK = 0x2,
200 PP_PCIE_DPM_MASK = 0x4,
201 PP_SCLK_DEEP_SLEEP_MASK = 0x8,
202 PP_POWER_CONTAINMENT_MASK = 0x10,
203 PP_UVD_HANDSHAKE_MASK = 0x20,
204 PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
205 PP_VBI_TIME_SUPPORT_MASK = 0x80,
206 PP_ULV_MASK = 0x100,
207 PP_ENABLE_GFX_CG_THRU_SMU = 0x200,
208 PP_CLOCK_STRETCH_MASK = 0x400,
209 PP_OD_FUZZY_FAN_CONTROL_MASK = 0x800,
210 PP_SOCCLK_DPM_MASK = 0x1000,
211 PP_DCEFCLK_DPM_MASK = 0x2000,
212 PP_OVERDRIVE_MASK = 0x4000,
213 PP_GFXOFF_MASK = 0x8000,
214 PP_ACG_MASK = 0x10000,
215 PP_STUTTER_MODE = 0x20000,
216 PP_AVFS_MASK = 0x40000,
217 PP_GFX_DCS_MASK = 0x80000,
218};
219
220enum amd_harvest_ip_mask {
221 AMD_HARVEST_IP_VCN_MASK = 0x1,
222 AMD_HARVEST_IP_JPEG_MASK = 0x2,
223 AMD_HARVEST_IP_DMU_MASK = 0x4,
224};
225
226enum DC_FEATURE_MASK {
227
228 DC_FBC_MASK = (1 << 0),
229 DC_MULTI_MON_PP_MCLK_SWITCH_MASK = (1 << 1),
230 DC_DISABLE_FRACTIONAL_PWM_MASK = (1 << 2),
231 DC_PSR_MASK = (1 << 3),
232 DC_EDP_NO_POWER_SEQUENCING = (1 << 4),
233};
234
235enum DC_DEBUG_MASK {
236 DC_DISABLE_PIPE_SPLIT = 0x1,
237 DC_DISABLE_STUTTER = 0x2,
238 DC_DISABLE_DSC = 0x4,
239 DC_DISABLE_CLOCK_GATING = 0x8
240};
241
242enum amd_dpm_forced_level;
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275struct amd_ip_funcs {
276 char *name;
277 int (*early_init)(void *handle);
278 int (*late_init)(void *handle);
279 int (*sw_init)(void *handle);
280 int (*sw_fini)(void *handle);
281 int (*early_fini)(void *handle);
282 int (*hw_init)(void *handle);
283 int (*hw_fini)(void *handle);
284 void (*late_fini)(void *handle);
285 int (*suspend)(void *handle);
286 int (*resume)(void *handle);
287 bool (*is_idle)(void *handle);
288 int (*wait_for_idle)(void *handle);
289 bool (*check_soft_reset)(void *handle);
290 int (*pre_soft_reset)(void *handle);
291 int (*soft_reset)(void *handle);
292 int (*post_soft_reset)(void *handle);
293 int (*set_clockgating_state)(void *handle,
294 enum amd_clockgating_state state);
295 int (*set_powergating_state)(void *handle,
296 enum amd_powergating_state state);
297 void (*get_clockgating_state)(void *handle, u32 *flags);
298 int (*enable_umd_pstate)(void *handle, enum amd_dpm_forced_level *level);
299};
300
301
302#endif
303