1/* 2 * Copyright (C) 2017 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20 */ 21#ifndef _dcn_1_0_OFFSET_HEADER 22#define _dcn_1_0_OFFSET_HEADER 23 24 25 26// addressBlock: dce_dc_hda_azcontroller_azdec 27// base address: 0x1300000 28 29 30// addressBlock: dce_dc_hda_azendpoint_azdec 31// base address: 0x1300000 32 33 34// addressBlock: dce_dc_hda_azinputendpoint_azdec 35// base address: 0x1300000 36 37 38// addressBlock: dce_dc_hda_azroot_azdec 39// base address: 0x1300000 40 41 42// addressBlock: dce_dc_hda_azstream0_azdec 43// base address: 0x1300000 44 45 46// addressBlock: dce_dc_hda_azstream1_azdec 47// base address: 0x1300020 48 49 50// addressBlock: dce_dc_hda_azstream2_azdec 51// base address: 0x1300040 52 53 54// addressBlock: dce_dc_hda_azstream3_azdec 55// base address: 0x1300060 56 57 58// addressBlock: dce_dc_hda_azstream4_azdec 59// base address: 0x1300080 60 61 62// addressBlock: dce_dc_hda_azstream5_azdec 63// base address: 0x13000a0 64 65 66// addressBlock: dce_dc_hda_azstream6_azdec 67// base address: 0x13000c0 68 69 70// addressBlock: dce_dc_hda_azstream7_azdec 71// base address: 0x13000e0 72 73 74// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] 75// base address: 0x48 76#define mmVGA_MEM_WRITE_PAGE_ADDR 0x0000 77#define mmVGA_MEM_WRITE_PAGE_ADDR_BASE_IDX 0 78#define mmVGA_MEM_READ_PAGE_ADDR 0x0001 79#define mmVGA_MEM_READ_PAGE_ADDR_BASE_IDX 0 80 81 82// addressBlock: dce_dc_mmhubbub_vga_dispdec[948..986] 83// base address: 0x3b4 84#define mmCRTC8_IDX 0x002d 85#define mmCRTC8_IDX_BASE_IDX 1 86#define mmCRTC8_DATA 0x002d 87#define mmCRTC8_DATA_BASE_IDX 1 88#define mmGENFC_WT 0x002e 89#define mmGENFC_WT_BASE_IDX 1 90#define mmGENS1 0x002e 91#define mmGENS1_BASE_IDX 1 92#define mmATTRDW 0x0030 93#define mmATTRDW_BASE_IDX 1 94#define mmATTRX 0x0030 95#define mmATTRX_BASE_IDX 1 96#define mmATTRDR 0x0030 97#define mmATTRDR_BASE_IDX 1 98#define mmGENMO_WT 0x0030 99#define mmGENMO_WT_BASE_IDX 1 100#define mmGENS0 0x0030 101#define mmGENS0_BASE_IDX 1 102#define mmGENENB 0x0030 103#define mmGENENB_BASE_IDX 1 104#define mmSEQ8_IDX 0x0031 105#define mmSEQ8_IDX_BASE_IDX 1 106#define mmSEQ8_DATA 0x0031 107#define mmSEQ8_DATA_BASE_IDX 1 108#define mmDAC_MASK 0x0031 109#define mmDAC_MASK_BASE_IDX 1 110#define mmDAC_R_INDEX 0x0031 111#define mmDAC_R_INDEX_BASE_IDX 1 112#define mmDAC_W_INDEX 0x0032 113#define mmDAC_W_INDEX_BASE_IDX 1 114#define mmDAC_DATA 0x0032 115#define mmDAC_DATA_BASE_IDX 1 116#define mmGENFC_RD 0x0032 117#define mmGENFC_RD_BASE_IDX 1 118#define mmGENMO_RD 0x0033 119#define mmGENMO_RD_BASE_IDX 1 120#define mmGRPH8_IDX 0x0033 121#define mmGRPH8_IDX_BASE_IDX 1 122#define mmGRPH8_DATA 0x0033 123#define mmGRPH8_DATA_BASE_IDX 1 124#define mmCRTC8_IDX_1 0x0035 125#define mmCRTC8_IDX_1_BASE_IDX 1 126#define mmCRTC8_DATA_1 0x0035 127#define mmCRTC8_DATA_1_BASE_IDX 1 128#define mmGENFC_WT_1 0x0036 129#define mmGENFC_WT_1_BASE_IDX 1 130#define mmGENS1_1 0x0036 131#define mmGENS1_1_BASE_IDX 1 132 133 134// addressBlock: dce_dc_hda_azcontroller_azdec 135// base address: 0x0 136#define mmCORB_WRITE_POINTER 0x0000 137#define mmCORB_WRITE_POINTER_BASE_IDX 0 138#define mmCORB_READ_POINTER 0x0000 139#define mmCORB_READ_POINTER_BASE_IDX 0 140#define mmCORB_CONTROL 0x0001 141#define mmCORB_CONTROL_BASE_IDX 0 142#define mmCORB_STATUS 0x0001 143#define mmCORB_STATUS_BASE_IDX 0 144#define mmCORB_SIZE 0x0001 145#define mmCORB_SIZE_BASE_IDX 0 146#define mmRIRB_LOWER_BASE_ADDRESS 0x0002 147#define mmRIRB_LOWER_BASE_ADDRESS_BASE_IDX 0 148#define mmRIRB_UPPER_BASE_ADDRESS 0x0003 149#define mmRIRB_UPPER_BASE_ADDRESS_BASE_IDX 0 150#define mmRIRB_WRITE_POINTER 0x0004 151#define mmRIRB_WRITE_POINTER_BASE_IDX 0 152#define mmRESPONSE_INTERRUPT_COUNT 0x0004 153#define mmRESPONSE_INTERRUPT_COUNT_BASE_IDX 0 154#define mmRIRB_CONTROL 0x0005 155#define mmRIRB_CONTROL_BASE_IDX 0 156#define mmRIRB_STATUS 0x0005 157#define mmRIRB_STATUS_BASE_IDX 0 158#define mmRIRB_SIZE 0x0005 159#define mmRIRB_SIZE_BASE_IDX 0 160#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE 0x0006 161#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_BASE_IDX 0 162#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 163#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 164#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 165#define mmIMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 166#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE 0x0007 167#define mmIMMEDIATE_RESPONSE_INPUT_INTERFACE_BASE_IDX 0 168#define mmIMMEDIATE_COMMAND_STATUS 0x0008 169#define mmIMMEDIATE_COMMAND_STATUS_BASE_IDX 0 170#define mmDMA_POSITION_LOWER_BASE_ADDRESS 0x000a 171#define mmDMA_POSITION_LOWER_BASE_ADDRESS_BASE_IDX 0 172#define mmDMA_POSITION_UPPER_BASE_ADDRESS 0x000b 173#define mmDMA_POSITION_UPPER_BASE_ADDRESS_BASE_IDX 0 174#define mmWALL_CLOCK_COUNTER_ALIAS 0x074c 175#define mmWALL_CLOCK_COUNTER_ALIAS_BASE_IDX 1 176 177 178// addressBlock: dce_dc_hda_azendpoint_azdec 179// base address: 0x0 180#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 181#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 182#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 183#define mmAZENDPOINT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 184 185 186// addressBlock: dce_dc_hda_azinputendpoint_azdec 187// base address: 0x0 188#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA 0x0006 189#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_DATA_BASE_IDX 0 190#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX 0x0006 191#define mmAZENDPOINT_IMMEDIATE_COMMAND_INPUT_INTERFACE_INDEX_BASE_IDX 0 192 193 194// addressBlock: dce_dc_hda_azroot_azdec 195// base address: 0x0 196#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA 0x0006 197#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_DATA_BASE_IDX 0 198#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX 0x0006 199#define mmAZROOT_IMMEDIATE_COMMAND_OUTPUT_INTERFACE_INDEX_BASE_IDX 0 200 201 202// addressBlock: dce_dc_hda_azstream0_azdec 203// base address: 0x0 204#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x000e 205#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 206#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x000f 207#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 208#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0010 209#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 210#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0011 211#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 212#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0012 213#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 214#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0012 215#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 216#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0014 217#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 218#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0015 219#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 220#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0761 221#define mmAZSTREAM0_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 222 223 224// addressBlock: dce_dc_hda_azstream1_azdec 225// base address: 0x20 226#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0016 227#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 228#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0017 229#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 230#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0018 231#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 232#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0019 233#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 234#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x001a 235#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 236#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x001a 237#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 238#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x001c 239#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 240#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x001d 241#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 242#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0769 243#define mmAZSTREAM1_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 244 245 246// addressBlock: dce_dc_hda_azstream2_azdec 247// base address: 0x40 248#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x001e 249#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 250#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x001f 251#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 252#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0020 253#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 254#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0021 255#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 256#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0022 257#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 258#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0022 259#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 260#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0024 261#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 262#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0025 263#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 264#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0771 265#define mmAZSTREAM2_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 266 267 268// addressBlock: dce_dc_hda_azstream3_azdec 269// base address: 0x60 270#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0026 271#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 272#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0027 273#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 274#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0028 275#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 276#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0029 277#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 278#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x002a 279#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 280#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x002a 281#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 282#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x002c 283#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 284#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x002d 285#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 286#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0779 287#define mmAZSTREAM3_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 288 289 290// addressBlock: dce_dc_hda_azstream4_azdec 291// base address: 0x80 292#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x002e 293#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 294#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x002f 295#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 296#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0030 297#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 298#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0031 299#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 300#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0032 301#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 302#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0032 303#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 304#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0034 305#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 306#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0035 307#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 308#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0781 309#define mmAZSTREAM4_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 310 311 312// addressBlock: dce_dc_hda_azstream5_azdec 313// base address: 0xa0 314#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0036 315#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 316#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0037 317#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 318#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0038 319#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 320#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0039 321#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 322#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x003a 323#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 324#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x003a 325#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 326#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x003c 327#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 328#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x003d 329#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 330#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0789 331#define mmAZSTREAM5_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 332 333 334// addressBlock: dce_dc_hda_azstream6_azdec 335// base address: 0xc0 336#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x003e 337#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 338#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x003f 339#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 340#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0040 341#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 342#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0041 343#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 344#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x0042 345#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 346#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x0042 347#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 348#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x0044 349#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 350#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x0045 351#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 352#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0791 353#define mmAZSTREAM6_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 354 355 356// addressBlock: dce_dc_hda_azstream7_azdec 357// base address: 0xe0 358#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS 0x0046 359#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CONTROL_AND_STATUS_BASE_IDX 0 360#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER 0x0047 361#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_BASE_IDX 0 362#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH 0x0048 363#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_CYCLIC_BUFFER_LENGTH_BASE_IDX 0 364#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX 0x0049 365#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LAST_VALID_INDEX_BASE_IDX 0 366#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE 0x004a 367#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FIFO_SIZE_BASE_IDX 0 368#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT 0x004a 369#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_FORMAT_BASE_IDX 0 370#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS 0x004c 371#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_LOWER_BASE_ADDRESS_BASE_IDX 0 372#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS 0x004d 373#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_BDL_POINTER_UPPER_BASE_ADDRESS_BASE_IDX 0 374#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS 0x0799 375#define mmAZSTREAM7_1_OUTPUT_STREAM_DESCRIPTOR_LINK_POSITION_IN_CURRENT_BUFFER_ALIAS_BASE_IDX 1 376 377 378// addressBlock: dce_dc_mmhubbub_vga_dispdec[72..76] 379// base address: 0x48 380//#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 381//#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 382 383 384// addressBlock: dce_dc_mmhubbub_vga_dispdec 385// base address: 0x0 386//#define mmVGA_VGA_MEM_WRITE_PAGE_ADDR 0x0000 387//#define mmVGA_VGA_MEM_READ_PAGE_ADDR 0x0001 388#define mmVGA_RENDER_CONTROL 0x0000 389#define mmVGA_RENDER_CONTROL_BASE_IDX 1 390#define mmVGA_SEQUENCER_RESET_CONTROL 0x0001 391#define mmVGA_SEQUENCER_RESET_CONTROL_BASE_IDX 1 392#define mmVGA_MODE_CONTROL 0x0002 393#define mmVGA_MODE_CONTROL_BASE_IDX 1 394#define mmVGA_SURFACE_PITCH_SELECT 0x0003 395#define mmVGA_SURFACE_PITCH_SELECT_BASE_IDX 1 396#define mmVGA_MEMORY_BASE_ADDRESS 0x0004 397#define mmVGA_MEMORY_BASE_ADDRESS_BASE_IDX 1 398#define mmVGA_DISPBUF1_SURFACE_ADDR 0x0006 399#define mmVGA_DISPBUF1_SURFACE_ADDR_BASE_IDX 1 400#define mmVGA_DISPBUF2_SURFACE_ADDR 0x0008 401#define mmVGA_DISPBUF2_SURFACE_ADDR_BASE_IDX 1 402#define mmVGA_MEMORY_BASE_ADDRESS_HIGH 0x0009 403#define mmVGA_MEMORY_BASE_ADDRESS_HIGH_BASE_IDX 1 404#define mmVGA_HDP_CONTROL 0x000a 405#define mmVGA_HDP_CONTROL_BASE_IDX 1 406#define mmVGA_CACHE_CONTROL 0x000b 407#define mmVGA_CACHE_CONTROL_BASE_IDX 1 408#define mmD1VGA_CONTROL 0x000c 409#define mmD1VGA_CONTROL_BASE_IDX 1 410#define mmD2VGA_CONTROL 0x000e 411#define mmD2VGA_CONTROL_BASE_IDX 1 412#define mmVGA_STATUS 0x0010 413#define mmVGA_STATUS_BASE_IDX 1 414#define mmVGA_INTERRUPT_CONTROL 0x0011 415#define mmVGA_INTERRUPT_CONTROL_BASE_IDX 1 416#define mmVGA_STATUS_CLEAR 0x0012 417#define mmVGA_STATUS_CLEAR_BASE_IDX 1 418#define mmVGA_INTERRUPT_STATUS 0x0013 419#define mmVGA_INTERRUPT_STATUS_BASE_IDX 1 420#define mmVGA_MAIN_CONTROL 0x0014 421#define mmVGA_MAIN_CONTROL_BASE_IDX 1 422#define mmVGA_TEST_CONTROL 0x0015 423#define mmVGA_TEST_CONTROL_BASE_IDX 1 424#define mmVGA_QOS_CTRL 0x0018 425#define mmVGA_QOS_CTRL_BASE_IDX 1 426//#define mmVGA_CRTC8_IDX 0x002d 427//#define mmVGA_CRTC8_DATA 0x002d 428//#define mmVGA_GENFC_WT 0x002e 429//#define mmVGA_GENS1 0x002e 430//#define mmVGA_ATTRDW 0x0030 431//#define mmVGA_ATTRX 0x0030 432//#define mmVGA_ATTRDR 0x0030 433//#define mmVGA_GENMO_WT 0x0030 434//#define mmVGA_GENS0 0x0030 435//#define mmVGA_GENENB 0x0030 436//#define mmVGA_SEQ8_IDX 0x0031 437//#define mmVGA_SEQ8_DATA 0x0031 438//#define mmVGA_DAC_MASK 0x0031 439//#define mmVGA_DAC_R_INDEX 0x0031 440//#define mmVGA_DAC_W_INDEX 0x0032 441//#define mmVGA_DAC_DATA 0x0032 442//#define mmVGA_GENFC_RD 0x0032 443//#define mmVGA_GENMO_RD 0x0033 444//#define mmVGA_GRPH8_IDX 0x0033 445//#define mmVGA_GRPH8_DATA 0x0033 446//#define mmVGA_CRTC8_IDX_1 0x0035 447//#define mmVGA_CRTC8_DATA_1 0x0035 448//#define mmVGA_GENFC_WT_1 0x0036 449//#define mmVGA_GENS1_1 0x0036 450#define mmD3VGA_CONTROL 0x0038 451#define mmD3VGA_CONTROL_BASE_IDX 1 452#define mmD4VGA_CONTROL 0x0039 453#define mmD4VGA_CONTROL_BASE_IDX 1 454#define mmD5VGA_CONTROL 0x003a 455#define mmD5VGA_CONTROL_BASE_IDX 1 456#define mmD6VGA_CONTROL 0x003b 457#define mmD6VGA_CONTROL_BASE_IDX 1 458#define mmVGA_SOURCE_SELECT 0x003c 459#define mmVGA_SOURCE_SELECT_BASE_IDX 1 460 461 462// addressBlock: dce_dc_dccg_dccg_dispdec 463// base address: 0x0 464#define mmPHYPLLA_PIXCLK_RESYNC_CNTL 0x0040 465#define mmPHYPLLA_PIXCLK_RESYNC_CNTL_BASE_IDX 1 466#define mmPHYPLLB_PIXCLK_RESYNC_CNTL 0x0041 467#define mmPHYPLLB_PIXCLK_RESYNC_CNTL_BASE_IDX 1 468#define mmPHYPLLC_PIXCLK_RESYNC_CNTL 0x0042 469#define mmPHYPLLC_PIXCLK_RESYNC_CNTL_BASE_IDX 1 470#define mmPHYPLLD_PIXCLK_RESYNC_CNTL 0x0043 471#define mmPHYPLLD_PIXCLK_RESYNC_CNTL_BASE_IDX 1 472#define mmDP_DTO_DBUF_EN 0x0044 473#define mmDP_DTO_DBUF_EN_BASE_IDX 1 474#define mmDPREFCLK_CGTT_BLK_CTRL_REG 0x0048 475#define mmDPREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 476#define mmREFCLK_CNTL 0x0049 477#define mmREFCLK_CNTL_BASE_IDX 1 478#define mmMIPI_CLK_CNTL 0x004a 479#define mmMIPI_CLK_CNTL_BASE_IDX 1 480#define mmREFCLK_CGTT_BLK_CTRL_REG 0x004b 481#define mmREFCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 482#define mmPHYPLLE_PIXCLK_RESYNC_CNTL 0x004c 483#define mmPHYPLLE_PIXCLK_RESYNC_CNTL_BASE_IDX 1 484#define mmDCCG_PERFMON_CNTL2 0x004e 485#define mmDCCG_PERFMON_CNTL2_BASE_IDX 1 486#define mmDSICLK_CGTT_BLK_CTRL_REG 0x004f 487#define mmDSICLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 488#define mmDCCG_CBUS_WRCMD_DELAY 0x0050 489#define mmDCCG_CBUS_WRCMD_DELAY_BASE_IDX 1 490#define mmDCCG_DS_DTO_INCR 0x0053 491#define mmDCCG_DS_DTO_INCR_BASE_IDX 1 492#define mmDCCG_DS_DTO_MODULO 0x0054 493#define mmDCCG_DS_DTO_MODULO_BASE_IDX 1 494#define mmDCCG_DS_CNTL 0x0055 495#define mmDCCG_DS_CNTL_BASE_IDX 1 496#define mmDCCG_DS_HW_CAL_INTERVAL 0x0056 497#define mmDCCG_DS_HW_CAL_INTERVAL_BASE_IDX 1 498#define mmSYMCLKG_CLOCK_ENABLE 0x0057 499#define mmSYMCLKG_CLOCK_ENABLE_BASE_IDX 1 500#define mmDPREFCLK_CNTL 0x0058 501#define mmDPREFCLK_CNTL_BASE_IDX 1 502#define mmAOMCLK0_CNTL 0x0059 503#define mmAOMCLK0_CNTL_BASE_IDX 1 504#define mmAOMCLK1_CNTL 0x005a 505#define mmAOMCLK1_CNTL_BASE_IDX 1 506#define mmAOMCLK2_CNTL 0x005b 507#define mmAOMCLK2_CNTL_BASE_IDX 1 508#define mmDCCG_AUDIO_DTO2_PHASE 0x005c 509#define mmDCCG_AUDIO_DTO2_PHASE_BASE_IDX 1 510#define mmDCCG_AUDIO_DTO2_MODULO 0x005d 511#define mmDCCG_AUDIO_DTO2_MODULO_BASE_IDX 1 512#define mmDCE_VERSION 0x005e 513#define mmDCE_VERSION_BASE_IDX 1 514#define mmPHYPLLG_PIXCLK_RESYNC_CNTL 0x005f 515#define mmPHYPLLG_PIXCLK_RESYNC_CNTL_BASE_IDX 1 516#define mmDCCG_GTC_CNTL 0x0060 517#define mmDCCG_GTC_CNTL_BASE_IDX 1 518#define mmDCCG_GTC_DTO_INCR 0x0061 519#define mmDCCG_GTC_DTO_INCR_BASE_IDX 1 520#define mmDCCG_GTC_DTO_MODULO 0x0062 521#define mmDCCG_GTC_DTO_MODULO_BASE_IDX 1 522#define mmDCCG_GTC_CURRENT 0x0063 523#define mmDCCG_GTC_CURRENT_BASE_IDX 1 524#define mmMIPI_DTO_CNTL 0x0065 525#define mmMIPI_DTO_CNTL_BASE_IDX 1 526#define mmMIPI_DTO_PHASE 0x0066 527#define mmMIPI_DTO_PHASE_BASE_IDX 1 528#define mmMIPI_DTO_MODULO 0x0067 529#define mmMIPI_DTO_MODULO_BASE_IDX 1 530#define mmDAC_CLK_ENABLE 0x0068 531#define mmDAC_CLK_ENABLE_BASE_IDX 1 532#define mmDVO_CLK_ENABLE 0x0069 533#define mmDVO_CLK_ENABLE_BASE_IDX 1 534#define mmAVSYNC_COUNTER_WRITE 0x006a 535#define mmAVSYNC_COUNTER_WRITE_BASE_IDX 1 536#define mmAVSYNC_COUNTER_CONTROL 0x006b 537#define mmAVSYNC_COUNTER_CONTROL_BASE_IDX 1 538#define mmAVSYNC_COUNTER_READ 0x006f 539#define mmAVSYNC_COUNTER_READ_BASE_IDX 1 540#define mmMILLISECOND_TIME_BASE_DIV 0x0070 541#define mmMILLISECOND_TIME_BASE_DIV_BASE_IDX 1 542#define mmDISPCLK_FREQ_CHANGE_CNTL 0x0071 543#define mmDISPCLK_FREQ_CHANGE_CNTL_BASE_IDX 1 544#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL 0x0072 545#define mmDC_MEM_GLOBAL_PWR_REQ_CNTL_BASE_IDX 1 546#define mmDCCG_PERFMON_CNTL 0x0073 547#define mmDCCG_PERFMON_CNTL_BASE_IDX 1 548#define mmDCCG_GATE_DISABLE_CNTL 0x0074 549#define mmDCCG_GATE_DISABLE_CNTL_BASE_IDX 1 550#define mmDISPCLK_CGTT_BLK_CTRL_REG 0x0075 551#define mmDISPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 552#define mmSOCCLK_CGTT_BLK_CTRL_REG 0x0076 553#define mmSOCCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 554#define mmDCCG_CAC_STATUS 0x0077 555#define mmDCCG_CAC_STATUS_BASE_IDX 1 556#define mmPIXCLK1_RESYNC_CNTL 0x0078 557#define mmPIXCLK1_RESYNC_CNTL_BASE_IDX 1 558#define mmPIXCLK2_RESYNC_CNTL 0x0079 559#define mmPIXCLK2_RESYNC_CNTL_BASE_IDX 1 560#define mmPIXCLK0_RESYNC_CNTL 0x007a 561#define mmPIXCLK0_RESYNC_CNTL_BASE_IDX 1 562#define mmMICROSECOND_TIME_BASE_DIV 0x007b 563#define mmMICROSECOND_TIME_BASE_DIV_BASE_IDX 1 564#define mmDCCG_GATE_DISABLE_CNTL2 0x007c 565#define mmDCCG_GATE_DISABLE_CNTL2_BASE_IDX 1 566#define mmSYMCLK_CGTT_BLK_CTRL_REG 0x007d 567#define mmSYMCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 568#define mmPHYPLLF_PIXCLK_RESYNC_CNTL 0x007e 569#define mmPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 570#define mmDCCG_DISP_CNTL_REG 0x007f 571#define mmDCCG_DISP_CNTL_REG_BASE_IDX 1 572#define mmOTG0_PIXEL_RATE_CNTL 0x0080 573#define mmOTG0_PIXEL_RATE_CNTL_BASE_IDX 1 574#define mmDP_DTO0_PHASE 0x0081 575#define mmDP_DTO0_PHASE_BASE_IDX 1 576#define mmDP_DTO0_MODULO 0x0082 577#define mmDP_DTO0_MODULO_BASE_IDX 1 578#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL 0x0083 579#define mmOTG0_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 580#define mmOTG1_PIXEL_RATE_CNTL 0x0084 581#define mmOTG1_PIXEL_RATE_CNTL_BASE_IDX 1 582#define mmDP_DTO1_PHASE 0x0085 583#define mmDP_DTO1_PHASE_BASE_IDX 1 584#define mmDP_DTO1_MODULO 0x0086 585#define mmDP_DTO1_MODULO_BASE_IDX 1 586#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL 0x0087 587#define mmOTG1_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 588#define mmOTG2_PIXEL_RATE_CNTL 0x0088 589#define mmOTG2_PIXEL_RATE_CNTL_BASE_IDX 1 590#define mmDP_DTO2_PHASE 0x0089 591#define mmDP_DTO2_PHASE_BASE_IDX 1 592#define mmDP_DTO2_MODULO 0x008a 593#define mmDP_DTO2_MODULO_BASE_IDX 1 594#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL 0x008b 595#define mmOTG2_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 596#define mmOTG3_PIXEL_RATE_CNTL 0x008c 597#define mmOTG3_PIXEL_RATE_CNTL_BASE_IDX 1 598#define mmDP_DTO3_PHASE 0x008d 599#define mmDP_DTO3_PHASE_BASE_IDX 1 600#define mmDP_DTO3_MODULO 0x008e 601#define mmDP_DTO3_MODULO_BASE_IDX 1 602#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL 0x008f 603#define mmOTG3_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 604#define mmOTG4_PIXEL_RATE_CNTL 0x0090 605#define mmOTG4_PIXEL_RATE_CNTL_BASE_IDX 1 606#define mmDP_DTO4_PHASE 0x0091 607#define mmDP_DTO4_PHASE_BASE_IDX 1 608#define mmDP_DTO4_MODULO 0x0092 609#define mmDP_DTO4_MODULO_BASE_IDX 1 610#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL 0x0093 611#define mmOTG4_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 612#define mmOTG5_PIXEL_RATE_CNTL 0x0094 613#define mmOTG5_PIXEL_RATE_CNTL_BASE_IDX 1 614#define mmDP_DTO5_PHASE 0x0095 615#define mmDP_DTO5_PHASE_BASE_IDX 1 616#define mmDP_DTO5_MODULO 0x0096 617#define mmDP_DTO5_MODULO_BASE_IDX 1 618#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL 0x0097 619#define mmOTG5_PHYPLL_PIXEL_RATE_CNTL_BASE_IDX 1 620#define mmDPPCLK_CGTT_BLK_CTRL_REG 0x0098 621#define mmDPPCLK_CGTT_BLK_CTRL_REG_BASE_IDX 1 622#define mmSYMCLKA_CLOCK_ENABLE 0x00a0 623#define mmSYMCLKA_CLOCK_ENABLE_BASE_IDX 1 624#define mmSYMCLKB_CLOCK_ENABLE 0x00a1 625#define mmSYMCLKB_CLOCK_ENABLE_BASE_IDX 1 626#define mmSYMCLKC_CLOCK_ENABLE 0x00a2 627#define mmSYMCLKC_CLOCK_ENABLE_BASE_IDX 1 628#define mmSYMCLKD_CLOCK_ENABLE 0x00a3 629#define mmSYMCLKD_CLOCK_ENABLE_BASE_IDX 1 630#define mmSYMCLKE_CLOCK_ENABLE 0x00a4 631#define mmSYMCLKE_CLOCK_ENABLE_BASE_IDX 1 632#define mmSYMCLKF_CLOCK_ENABLE 0x00a5 633#define mmSYMCLKF_CLOCK_ENABLE_BASE_IDX 1 634#define mmDCCG_SOFT_RESET 0x00a6 635#define mmDCCG_SOFT_RESET_BASE_IDX 1 636#define mmDVOACLKD_CNTL 0x00a8 637#define mmDVOACLKD_CNTL_BASE_IDX 1 638#define mmDVOACLKC_MVP_CNTL 0x00a9 639#define mmDVOACLKC_MVP_CNTL_BASE_IDX 1 640#define mmDVOACLKC_CNTL 0x00aa 641#define mmDVOACLKC_CNTL_BASE_IDX 1 642#define mmDCCG_AUDIO_DTO_SOURCE 0x00ab 643#define mmDCCG_AUDIO_DTO_SOURCE_BASE_IDX 1 644#define mmDCCG_AUDIO_DTO0_PHASE 0x00ac 645#define mmDCCG_AUDIO_DTO0_PHASE_BASE_IDX 1 646#define mmDCCG_AUDIO_DTO0_MODULE 0x00ad 647#define mmDCCG_AUDIO_DTO0_MODULE_BASE_IDX 1 648#define mmDCCG_AUDIO_DTO1_PHASE 0x00ae 649#define mmDCCG_AUDIO_DTO1_PHASE_BASE_IDX 1 650#define mmDCCG_AUDIO_DTO1_MODULE 0x00af 651#define mmDCCG_AUDIO_DTO1_MODULE_BASE_IDX 1 652#define mmDCCG_VSYNC_OTG0_LATCH_VALUE 0x00b0 653#define mmDCCG_VSYNC_OTG0_LATCH_VALUE_BASE_IDX 1 654#define mmDCCG_VSYNC_OTG1_LATCH_VALUE 0x00b1 655#define mmDCCG_VSYNC_OTG1_LATCH_VALUE_BASE_IDX 1 656#define mmDCCG_VSYNC_OTG2_LATCH_VALUE 0x00b2 657#define mmDCCG_VSYNC_OTG2_LATCH_VALUE_BASE_IDX 1 658#define mmDCCG_VSYNC_OTG3_LATCH_VALUE 0x00b3 659#define mmDCCG_VSYNC_OTG3_LATCH_VALUE_BASE_IDX 1 660#define mmDCCG_VSYNC_OTG4_LATCH_VALUE 0x00b4 661#define mmDCCG_VSYNC_OTG4_LATCH_VALUE_BASE_IDX 1 662#define mmDCCG_VSYNC_OTG5_LATCH_VALUE 0x00b5 663#define mmDCCG_VSYNC_OTG5_LATCH_VALUE_BASE_IDX 1 664#define mmDCCG_VSYNC_CNT_CTRL 0x00b8 665#define mmDCCG_VSYNC_CNT_CTRL_BASE_IDX 1 666#define mmDCCG_VSYNC_CNT_INT_CTRL 0x00b9 667#define mmDCCG_VSYNC_CNT_INT_CTRL_BASE_IDX 1 668#define mmDCCG_TEST_CLK_SEL 0x00be 669#define mmDCCG_TEST_CLK_SEL_BASE_IDX 1 670 671 672// addressBlock: dce_dc_dccg_dccg_dfs_dispdec 673// base address: 0x0 674#define mmDENTIST_DISPCLK_CNTL 0x0064 675#define mmDENTIST_DISPCLK_CNTL_BASE_IDX 1 676 677 678// addressBlock: dce_dc_dccg_dccg_dcperfmon0_dc_perfmon_dispdec 679// base address: 0x0 680#define mmDC_PERFMON0_PERFCOUNTER_CNTL 0x0000 681#define mmDC_PERFMON0_PERFCOUNTER_CNTL_BASE_IDX 2 682#define mmDC_PERFMON0_PERFCOUNTER_CNTL2 0x0001 683#define mmDC_PERFMON0_PERFCOUNTER_CNTL2_BASE_IDX 2 684#define mmDC_PERFMON0_PERFCOUNTER_STATE 0x0002 685#define mmDC_PERFMON0_PERFCOUNTER_STATE_BASE_IDX 2 686#define mmDC_PERFMON0_PERFMON_CNTL 0x0003 687#define mmDC_PERFMON0_PERFMON_CNTL_BASE_IDX 2 688#define mmDC_PERFMON0_PERFMON_CNTL2 0x0004 689#define mmDC_PERFMON0_PERFMON_CNTL2_BASE_IDX 2 690#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC 0x0005 691#define mmDC_PERFMON0_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 692#define mmDC_PERFMON0_PERFMON_CVALUE_LOW 0x0006 693#define mmDC_PERFMON0_PERFMON_CVALUE_LOW_BASE_IDX 2 694#define mmDC_PERFMON0_PERFMON_HI 0x0007 695#define mmDC_PERFMON0_PERFMON_HI_BASE_IDX 2 696#define mmDC_PERFMON0_PERFMON_LOW 0x0008 697#define mmDC_PERFMON0_PERFMON_LOW_BASE_IDX 2 698 699 700// addressBlock: dce_dc_dccg_dccg_dcperfmon1_dc_perfmon_dispdec 701// base address: 0x30 702#define mmDC_PERFMON1_PERFCOUNTER_CNTL 0x000c 703#define mmDC_PERFMON1_PERFCOUNTER_CNTL_BASE_IDX 2 704#define mmDC_PERFMON1_PERFCOUNTER_CNTL2 0x000d 705#define mmDC_PERFMON1_PERFCOUNTER_CNTL2_BASE_IDX 2 706#define mmDC_PERFMON1_PERFCOUNTER_STATE 0x000e 707#define mmDC_PERFMON1_PERFCOUNTER_STATE_BASE_IDX 2 708#define mmDC_PERFMON1_PERFMON_CNTL 0x000f 709#define mmDC_PERFMON1_PERFMON_CNTL_BASE_IDX 2 710#define mmDC_PERFMON1_PERFMON_CNTL2 0x0010 711#define mmDC_PERFMON1_PERFMON_CNTL2_BASE_IDX 2 712#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC 0x0011 713#define mmDC_PERFMON1_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 714#define mmDC_PERFMON1_PERFMON_CVALUE_LOW 0x0012 715#define mmDC_PERFMON1_PERFMON_CVALUE_LOW_BASE_IDX 2 716#define mmDC_PERFMON1_PERFMON_HI 0x0013 717#define mmDC_PERFMON1_PERFMON_HI_BASE_IDX 2 718#define mmDC_PERFMON1_PERFMON_LOW 0x0014 719#define mmDC_PERFMON1_PERFMON_LOW_BASE_IDX 2 720 721 722// addressBlock: dce_dc_dccg_dccg_pll_dispdec 723// base address: 0x0 724#define mmPLL_MACRO_CNTL_RESERVED0 0x0018 725#define mmPLL_MACRO_CNTL_RESERVED0_BASE_IDX 2 726#define mmPLL_MACRO_CNTL_RESERVED1 0x0019 727#define mmPLL_MACRO_CNTL_RESERVED1_BASE_IDX 2 728#define mmPLL_MACRO_CNTL_RESERVED2 0x001a 729#define mmPLL_MACRO_CNTL_RESERVED2_BASE_IDX 2 730#define mmPLL_MACRO_CNTL_RESERVED3 0x001b 731#define mmPLL_MACRO_CNTL_RESERVED3_BASE_IDX 2 732#define mmPLL_MACRO_CNTL_RESERVED4 0x001c 733#define mmPLL_MACRO_CNTL_RESERVED4_BASE_IDX 2 734#define mmPLL_MACRO_CNTL_RESERVED5 0x001d 735#define mmPLL_MACRO_CNTL_RESERVED5_BASE_IDX 2 736#define mmPLL_MACRO_CNTL_RESERVED6 0x001e 737#define mmPLL_MACRO_CNTL_RESERVED6_BASE_IDX 2 738#define mmPLL_MACRO_CNTL_RESERVED7 0x001f 739#define mmPLL_MACRO_CNTL_RESERVED7_BASE_IDX 2 740#define mmPLL_MACRO_CNTL_RESERVED8 0x0020 741#define mmPLL_MACRO_CNTL_RESERVED8_BASE_IDX 2 742#define mmPLL_MACRO_CNTL_RESERVED9 0x0021 743#define mmPLL_MACRO_CNTL_RESERVED9_BASE_IDX 2 744#define mmPLL_MACRO_CNTL_RESERVED10 0x0022 745#define mmPLL_MACRO_CNTL_RESERVED10_BASE_IDX 2 746#define mmPLL_MACRO_CNTL_RESERVED11 0x0023 747#define mmPLL_MACRO_CNTL_RESERVED11_BASE_IDX 2 748#define mmPLL_MACRO_CNTL_RESERVED12 0x0024 749#define mmPLL_MACRO_CNTL_RESERVED12_BASE_IDX 2 750#define mmPLL_MACRO_CNTL_RESERVED13 0x0025 751#define mmPLL_MACRO_CNTL_RESERVED13_BASE_IDX 2 752#define mmPLL_MACRO_CNTL_RESERVED14 0x0026 753#define mmPLL_MACRO_CNTL_RESERVED14_BASE_IDX 2 754#define mmPLL_MACRO_CNTL_RESERVED15 0x0027 755#define mmPLL_MACRO_CNTL_RESERVED15_BASE_IDX 2 756#define mmPLL_MACRO_CNTL_RESERVED16 0x0028 757#define mmPLL_MACRO_CNTL_RESERVED16_BASE_IDX 2 758#define mmPLL_MACRO_CNTL_RESERVED17 0x0029 759#define mmPLL_MACRO_CNTL_RESERVED17_BASE_IDX 2 760#define mmPLL_MACRO_CNTL_RESERVED18 0x002a 761#define mmPLL_MACRO_CNTL_RESERVED18_BASE_IDX 2 762#define mmPLL_MACRO_CNTL_RESERVED19 0x002b 763#define mmPLL_MACRO_CNTL_RESERVED19_BASE_IDX 2 764#define mmPLL_MACRO_CNTL_RESERVED20 0x002c 765#define mmPLL_MACRO_CNTL_RESERVED20_BASE_IDX 2 766#define mmPLL_MACRO_CNTL_RESERVED21 0x002d 767#define mmPLL_MACRO_CNTL_RESERVED21_BASE_IDX 2 768#define mmPLL_MACRO_CNTL_RESERVED22 0x002e 769#define mmPLL_MACRO_CNTL_RESERVED22_BASE_IDX 2 770#define mmPLL_MACRO_CNTL_RESERVED23 0x002f 771#define mmPLL_MACRO_CNTL_RESERVED23_BASE_IDX 2 772#define mmPLL_MACRO_CNTL_RESERVED24 0x0030 773#define mmPLL_MACRO_CNTL_RESERVED24_BASE_IDX 2 774#define mmPLL_MACRO_CNTL_RESERVED25 0x0031 775#define mmPLL_MACRO_CNTL_RESERVED25_BASE_IDX 2 776#define mmPLL_MACRO_CNTL_RESERVED26 0x0032 777#define mmPLL_MACRO_CNTL_RESERVED26_BASE_IDX 2 778#define mmPLL_MACRO_CNTL_RESERVED27 0x0033 779#define mmPLL_MACRO_CNTL_RESERVED27_BASE_IDX 2 780#define mmPLL_MACRO_CNTL_RESERVED28 0x0034 781#define mmPLL_MACRO_CNTL_RESERVED28_BASE_IDX 2 782#define mmPLL_MACRO_CNTL_RESERVED29 0x0035 783#define mmPLL_MACRO_CNTL_RESERVED29_BASE_IDX 2 784#define mmPLL_MACRO_CNTL_RESERVED30 0x0036 785#define mmPLL_MACRO_CNTL_RESERVED30_BASE_IDX 2 786#define mmPLL_MACRO_CNTL_RESERVED31 0x0037 787#define mmPLL_MACRO_CNTL_RESERVED31_BASE_IDX 2 788#define mmPLL_MACRO_CNTL_RESERVED32 0x0038 789#define mmPLL_MACRO_CNTL_RESERVED32_BASE_IDX 2 790#define mmPLL_MACRO_CNTL_RESERVED33 0x0039 791#define mmPLL_MACRO_CNTL_RESERVED33_BASE_IDX 2 792#define mmPLL_MACRO_CNTL_RESERVED34 0x003a 793#define mmPLL_MACRO_CNTL_RESERVED34_BASE_IDX 2 794#define mmPLL_MACRO_CNTL_RESERVED35 0x003b 795#define mmPLL_MACRO_CNTL_RESERVED35_BASE_IDX 2 796#define mmPLL_MACRO_CNTL_RESERVED36 0x003c 797#define mmPLL_MACRO_CNTL_RESERVED36_BASE_IDX 2 798#define mmPLL_MACRO_CNTL_RESERVED37 0x003d 799#define mmPLL_MACRO_CNTL_RESERVED37_BASE_IDX 2 800#define mmPLL_MACRO_CNTL_RESERVED38 0x003e 801#define mmPLL_MACRO_CNTL_RESERVED38_BASE_IDX 2 802#define mmPLL_MACRO_CNTL_RESERVED39 0x003f 803#define mmPLL_MACRO_CNTL_RESERVED39_BASE_IDX 2 804#define mmPLL_MACRO_CNTL_RESERVED40 0x0040 805#define mmPLL_MACRO_CNTL_RESERVED40_BASE_IDX 2 806#define mmPLL_MACRO_CNTL_RESERVED41 0x0041 807#define mmPLL_MACRO_CNTL_RESERVED41_BASE_IDX 2 808 809 810// addressBlock: dce_dc_dmu_rbbmif_dispdec 811// base address: 0x0 812#define mmRBBMIF_TIMEOUT 0x0055 813#define mmRBBMIF_TIMEOUT_BASE_IDX 2 814#define mmRBBMIF_STATUS 0x0056 815#define mmRBBMIF_STATUS_BASE_IDX 2 816#define mmRBBMIF_INT_STATUS 0x0057 817#define mmRBBMIF_INT_STATUS_BASE_IDX 2 818#define mmRBBMIF_TIMEOUT_DIS 0x0058 819#define mmRBBMIF_TIMEOUT_DIS_BASE_IDX 2 820#define mmRBBMIF_STATUS_FLAG 0x0059 821#define mmRBBMIF_STATUS_FLAG_BASE_IDX 2 822 823 824// addressBlock: dce_dc_dmu_dc_pg_dispdec 825// base address: 0x0 826#define mmDOMAIN0_PG_CONFIG 0x008a 827#define mmDOMAIN0_PG_CONFIG_BASE_IDX 2 828#define mmDOMAIN0_PG_STATUS 0x008b 829#define mmDOMAIN0_PG_STATUS_BASE_IDX 2 830#define mmDOMAIN1_PG_CONFIG 0x008c 831#define mmDOMAIN1_PG_CONFIG_BASE_IDX 2 832#define mmDOMAIN1_PG_STATUS 0x008d 833#define mmDOMAIN1_PG_STATUS_BASE_IDX 2 834#define mmDOMAIN2_PG_CONFIG 0x008e 835#define mmDOMAIN2_PG_CONFIG_BASE_IDX 2 836#define mmDOMAIN2_PG_STATUS 0x008f 837#define mmDOMAIN2_PG_STATUS_BASE_IDX 2 838#define mmDOMAIN3_PG_CONFIG 0x0090 839#define mmDOMAIN3_PG_CONFIG_BASE_IDX 2 840#define mmDOMAIN3_PG_STATUS 0x0091 841#define mmDOMAIN3_PG_STATUS_BASE_IDX 2 842#define mmDOMAIN4_PG_CONFIG 0x0092 843#define mmDOMAIN4_PG_CONFIG_BASE_IDX 2 844#define mmDOMAIN4_PG_STATUS 0x0093 845#define mmDOMAIN4_PG_STATUS_BASE_IDX 2 846#define mmDOMAIN5_PG_CONFIG 0x0094 847#define mmDOMAIN5_PG_CONFIG_BASE_IDX 2 848#define mmDOMAIN5_PG_STATUS 0x0095 849#define mmDOMAIN5_PG_STATUS_BASE_IDX 2 850#define mmDOMAIN6_PG_CONFIG 0x0096 851#define mmDOMAIN6_PG_CONFIG_BASE_IDX 2 852#define mmDOMAIN6_PG_STATUS 0x0097 853#define mmDOMAIN6_PG_STATUS_BASE_IDX 2 854#define mmDOMAIN7_PG_CONFIG 0x0098 855#define mmDOMAIN7_PG_CONFIG_BASE_IDX 2 856#define mmDOMAIN7_PG_STATUS 0x0099 857#define mmDOMAIN7_PG_STATUS_BASE_IDX 2 858#define mmDOMAIN8_PG_CONFIG 0x009a 859#define mmDOMAIN8_PG_CONFIG_BASE_IDX 2 860#define mmDOMAIN8_PG_STATUS 0x009b 861#define mmDOMAIN8_PG_STATUS_BASE_IDX 2 862#define mmDOMAIN9_PG_CONFIG 0x009c 863#define mmDOMAIN9_PG_CONFIG_BASE_IDX 2 864#define mmDOMAIN9_PG_STATUS 0x009d 865#define mmDOMAIN9_PG_STATUS_BASE_IDX 2 866#define mmDOMAIN10_PG_CONFIG 0x009e 867#define mmDOMAIN10_PG_CONFIG_BASE_IDX 2 868#define mmDOMAIN10_PG_STATUS 0x009f 869#define mmDOMAIN10_PG_STATUS_BASE_IDX 2 870#define mmDOMAIN11_PG_CONFIG 0x00a0 871#define mmDOMAIN11_PG_CONFIG_BASE_IDX 2 872#define mmDOMAIN11_PG_STATUS 0x00a1 873#define mmDOMAIN11_PG_STATUS_BASE_IDX 2 874#define mmDOMAIN12_PG_CONFIG 0x00a2 875#define mmDOMAIN12_PG_CONFIG_BASE_IDX 2 876#define mmDOMAIN12_PG_STATUS 0x00a3 877#define mmDOMAIN12_PG_STATUS_BASE_IDX 2 878#define mmDOMAIN13_PG_CONFIG 0x00a4 879#define mmDOMAIN13_PG_CONFIG_BASE_IDX 2 880#define mmDOMAIN13_PG_STATUS 0x00a5 881#define mmDOMAIN13_PG_STATUS_BASE_IDX 2 882#define mmDOMAIN14_PG_CONFIG 0x00a6 883#define mmDOMAIN14_PG_CONFIG_BASE_IDX 2 884#define mmDOMAIN14_PG_STATUS 0x00a7 885#define mmDOMAIN14_PG_STATUS_BASE_IDX 2 886#define mmDOMAIN15_PG_CONFIG 0x00a8 887#define mmDOMAIN15_PG_CONFIG_BASE_IDX 2 888#define mmDOMAIN15_PG_STATUS 0x00a9 889#define mmDOMAIN15_PG_STATUS_BASE_IDX 2 890#define mmDCPG_INTERRUPT_STATUS 0x00aa 891#define mmDCPG_INTERRUPT_STATUS_BASE_IDX 2 892#define mmDCPG_INTERRUPT_CONTROL_1 0x00ab 893#define mmDCPG_INTERRUPT_CONTROL_1_BASE_IDX 2 894#define mmDCPG_INTERRUPT_CONTROL_2 0x00ac 895#define mmDCPG_INTERRUPT_CONTROL_2_BASE_IDX 2 896#define mmDC_IP_REQUEST_CNTL 0x00ad 897#define mmDC_IP_REQUEST_CNTL_BASE_IDX 2 898#define mmDC_PGCNTL_STATUS_REG 0x00ae 899#define mmDC_PGCNTL_STATUS_REG_BASE_IDX 2 900 901 902// addressBlock: dce_dc_dmu_dmu_dcperfmon_dc_perfmon_dispdec 903// base address: 0x2f8 904#define mmDC_PERFMON2_PERFCOUNTER_CNTL 0x00be 905#define mmDC_PERFMON2_PERFCOUNTER_CNTL_BASE_IDX 2 906#define mmDC_PERFMON2_PERFCOUNTER_CNTL2 0x00bf 907#define mmDC_PERFMON2_PERFCOUNTER_CNTL2_BASE_IDX 2 908#define mmDC_PERFMON2_PERFCOUNTER_STATE 0x00c0 909#define mmDC_PERFMON2_PERFCOUNTER_STATE_BASE_IDX 2 910#define mmDC_PERFMON2_PERFMON_CNTL 0x00c1 911#define mmDC_PERFMON2_PERFMON_CNTL_BASE_IDX 2 912#define mmDC_PERFMON2_PERFMON_CNTL2 0x00c2 913#define mmDC_PERFMON2_PERFMON_CNTL2_BASE_IDX 2 914#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC 0x00c3 915#define mmDC_PERFMON2_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 916#define mmDC_PERFMON2_PERFMON_CVALUE_LOW 0x00c4 917#define mmDC_PERFMON2_PERFMON_CVALUE_LOW_BASE_IDX 2 918#define mmDC_PERFMON2_PERFMON_HI 0x00c5 919#define mmDC_PERFMON2_PERFMON_HI_BASE_IDX 2 920#define mmDC_PERFMON2_PERFMON_LOW 0x00c6 921#define mmDC_PERFMON2_PERFMON_LOW_BASE_IDX 2 922 923 924// addressBlock: dce_dc_dmu_dmu_misc_dispdec 925// base address: 0x0 926#define mmCC_DC_PIPE_DIS 0x00ca 927#define mmCC_DC_PIPE_DIS_BASE_IDX 2 928#define mmDMU_CLK_CNTL 0x00cb 929#define mmDMU_CLK_CNTL_BASE_IDX 2 930#define mmDMU_MEM_PWR_CNTL 0x00cc 931#define mmDMU_MEM_PWR_CNTL_BASE_IDX 2 932#define mmDMCU_SMU_INTERRUPT_CNTL 0x00cd 933#define mmDMCU_SMU_INTERRUPT_CNTL_BASE_IDX 2 934#define mmSMU_INTERRUPT_CONTROL 0x00ce 935#define mmSMU_INTERRUPT_CONTROL_BASE_IDX 2 936 937 938// addressBlock: dce_dc_dmu_dmcu_dispdec 939// base address: 0x0 940#define mmDMCU_CTRL 0x00da 941#define mmDMCU_CTRL_BASE_IDX 2 942#define mmDMCU_STATUS 0x00db 943#define mmDMCU_STATUS_BASE_IDX 2 944#define mmDMCU_PC_START_ADDR 0x00dc 945#define mmDMCU_PC_START_ADDR_BASE_IDX 2 946#define mmDMCU_FW_START_ADDR 0x00dd 947#define mmDMCU_FW_START_ADDR_BASE_IDX 2 948#define mmDMCU_FW_END_ADDR 0x00de 949#define mmDMCU_FW_END_ADDR_BASE_IDX 2 950#define mmDMCU_FW_ISR_START_ADDR 0x00df 951#define mmDMCU_FW_ISR_START_ADDR_BASE_IDX 2 952#define mmDMCU_FW_CS_HI 0x00e0 953#define mmDMCU_FW_CS_HI_BASE_IDX 2 954#define mmDMCU_FW_CS_LO 0x00e1 955#define mmDMCU_FW_CS_LO_BASE_IDX 2 956#define mmDMCU_RAM_ACCESS_CTRL 0x00e2 957#define mmDMCU_RAM_ACCESS_CTRL_BASE_IDX 2 958#define mmDMCU_ERAM_WR_CTRL 0x00e3 959#define mmDMCU_ERAM_WR_CTRL_BASE_IDX 2 960#define mmDMCU_ERAM_WR_DATA 0x00e4 961#define mmDMCU_ERAM_WR_DATA_BASE_IDX 2 962#define mmDMCU_ERAM_RD_CTRL 0x00e5 963#define mmDMCU_ERAM_RD_CTRL_BASE_IDX 2 964#define mmDMCU_ERAM_RD_DATA 0x00e6 965#define mmDMCU_ERAM_RD_DATA_BASE_IDX 2 966#define mmDMCU_IRAM_WR_CTRL 0x00e7 967#define mmDMCU_IRAM_WR_CTRL_BASE_IDX 2 968#define mmDMCU_IRAM_WR_DATA 0x00e8 969#define mmDMCU_IRAM_WR_DATA_BASE_IDX 2 970#define mmDMCU_IRAM_RD_CTRL 0x00e9 971#define mmDMCU_IRAM_RD_CTRL_BASE_IDX 2 972#define mmDMCU_IRAM_RD_DATA 0x00ea 973#define mmDMCU_IRAM_RD_DATA_BASE_IDX 2 974#define mmDMCU_EVENT_TRIGGER 0x00eb 975#define mmDMCU_EVENT_TRIGGER_BASE_IDX 2 976#define mmDMCU_UC_INTERNAL_INT_STATUS 0x00ec 977#define mmDMCU_UC_INTERNAL_INT_STATUS_BASE_IDX 2 978#define mmDMCU_SS_INTERRUPT_CNTL_STATUS 0x00ed 979#define mmDMCU_SS_INTERRUPT_CNTL_STATUS_BASE_IDX 2 980#define mmDMCU_INTERRUPT_STATUS 0x00ee 981#define mmDMCU_INTERRUPT_STATUS_BASE_IDX 2 982#define mmDMCU_INTERRUPT_STATUS_1 0x00ef 983#define mmDMCU_INTERRUPT_STATUS_1_BASE_IDX 2 984#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK 0x00f0 985#define mmDMCU_INTERRUPT_TO_HOST_EN_MASK_BASE_IDX 2 986#define mmDMCU_INTERRUPT_TO_UC_EN_MASK 0x00f1 987#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_BASE_IDX 2 988#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1 0x00f2 989#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_1_BASE_IDX 2 990#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL 0x00f3 991#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_BASE_IDX 2 992#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1 0x00f4 993#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_1_BASE_IDX 2 994#define mmDC_DMCU_SCRATCH 0x00f5 995#define mmDC_DMCU_SCRATCH_BASE_IDX 2 996#define mmDMCU_INT_CNT 0x00f6 997#define mmDMCU_INT_CNT_BASE_IDX 2 998#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS 0x00f7 999#define mmDMCU_FW_CHECKSUM_SMPL_BYTE_POS_BASE_IDX 2 1000#define mmDMCU_UC_CLK_GATING_CNTL 0x00f8
1001#define mmDMCU_UC_CLK_GATING_CNTL_BASE_IDX 2 1002#define mmMASTER_COMM_DATA_REG1 0x00f9 1003#define mmMASTER_COMM_DATA_REG1_BASE_IDX 2 1004#define mmMASTER_COMM_DATA_REG2 0x00fa 1005#define mmMASTER_COMM_DATA_REG2_BASE_IDX 2 1006#define mmMASTER_COMM_DATA_REG3 0x00fb 1007#define mmMASTER_COMM_DATA_REG3_BASE_IDX 2 1008#define mmMASTER_COMM_CMD_REG 0x00fc 1009#define mmMASTER_COMM_CMD_REG_BASE_IDX 2 1010#define mmMASTER_COMM_CNTL_REG 0x00fd 1011#define mmMASTER_COMM_CNTL_REG_BASE_IDX 2 1012#define mmSLAVE_COMM_DATA_REG1 0x00fe 1013#define mmSLAVE_COMM_DATA_REG1_BASE_IDX 2 1014#define mmSLAVE_COMM_DATA_REG2 0x00ff 1015#define mmSLAVE_COMM_DATA_REG2_BASE_IDX 2 1016#define mmSLAVE_COMM_DATA_REG3 0x0100 1017#define mmSLAVE_COMM_DATA_REG3_BASE_IDX 2 1018#define mmSLAVE_COMM_CMD_REG 0x0101 1019#define mmSLAVE_COMM_CMD_REG_BASE_IDX 2 1020#define mmSLAVE_COMM_CNTL_REG 0x0102 1021#define mmSLAVE_COMM_CNTL_REG_BASE_IDX 2 1022#define mmDMCU_PERFMON_INTERRUPT_STATUS1 0x0105 1023#define mmDMCU_PERFMON_INTERRUPT_STATUS1_BASE_IDX 2 1024#define mmDMCU_PERFMON_INTERRUPT_STATUS2 0x0106 1025#define mmDMCU_PERFMON_INTERRUPT_STATUS2_BASE_IDX 2 1026#define mmDMCU_PERFMON_INTERRUPT_STATUS3 0x0107 1027#define mmDMCU_PERFMON_INTERRUPT_STATUS3_BASE_IDX 2 1028#define mmDMCU_PERFMON_INTERRUPT_STATUS4 0x0108 1029#define mmDMCU_PERFMON_INTERRUPT_STATUS4_BASE_IDX 2 1030#define mmDMCU_PERFMON_INTERRUPT_STATUS5 0x0109 1031#define mmDMCU_PERFMON_INTERRUPT_STATUS5_BASE_IDX 2 1032#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1 0x010a 1033#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 1034#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2 0x010b 1035#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK2_BASE_IDX 2 1036#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3 0x010c 1037#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK3_BASE_IDX 2 1038#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4 0x010d 1039#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK4_BASE_IDX 2 1040#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5 0x010e 1041#define mmDMCU_PERFMON_INTERRUPT_TO_UC_EN_MASK5_BASE_IDX 2 1042#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x010f 1043#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 1044#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2 0x0110 1045#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL2_BASE_IDX 2 1046#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3 0x0111 1047#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL3_BASE_IDX 2 1048#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4 0x0112 1049#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL4_BASE_IDX 2 1050#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5 0x0113 1051#define mmDMCU_PERFMON_INTERRUPT_TO_UC_XIRQ_IRQ_SEL5_BASE_IDX 2 1052#define mmDMCU_DPRX_INTERRUPT_STATUS1 0x0114 1053#define mmDMCU_DPRX_INTERRUPT_STATUS1_BASE_IDX 2 1054#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1 0x0115 1055#define mmDMCU_DPRX_INTERRUPT_TO_UC_EN_MASK1_BASE_IDX 2 1056#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1 0x0116 1057#define mmDMCU_DPRX_INTERRUPT_TO_UC_XIRQ_IRQ_SEL1_BASE_IDX 2 1058#define mmDMCU_INTERRUPT_STATUS_CONTINUE 0x0119 1059#define mmDMCU_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 1060#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE 0x011a 1061#define mmDMCU_INTERRUPT_TO_UC_EN_MASK_CONTINUE_BASE_IDX 2 1062#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE 0x011b 1063#define mmDMCU_INTERRUPT_TO_UC_XIRQ_IRQ_SEL_CONTINUE_BASE_IDX 2 1064#define mmDMCU_INT_CNT_CONTINUE 0x011c 1065#define mmDMCU_INT_CNT_CONTINUE_BASE_IDX 2 1066 1067 1068// addressBlock: dce_dc_dmu_ihc_dispdec 1069// base address: 0x0 1070#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE 0x0126 1071#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_BASE_IDX 2 1072#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP 0x0127 1073#define mmDC_GPU_TIMER_START_POSITION_VSTARTUP_BASE_IDX 2 1074#define mmDC_GPU_TIMER_READ 0x0128 1075#define mmDC_GPU_TIMER_READ_BASE_IDX 2 1076#define mmDC_GPU_TIMER_READ_CNTL 0x0129 1077#define mmDC_GPU_TIMER_READ_CNTL_BASE_IDX 2 1078#define mmDISP_INTERRUPT_STATUS 0x012a 1079#define mmDISP_INTERRUPT_STATUS_BASE_IDX 2 1080#define mmDISP_INTERRUPT_STATUS_CONTINUE 0x012b 1081#define mmDISP_INTERRUPT_STATUS_CONTINUE_BASE_IDX 2 1082#define mmDISP_INTERRUPT_STATUS_CONTINUE2 0x012c 1083#define mmDISP_INTERRUPT_STATUS_CONTINUE2_BASE_IDX 2 1084#define mmDISP_INTERRUPT_STATUS_CONTINUE3 0x012d 1085#define mmDISP_INTERRUPT_STATUS_CONTINUE3_BASE_IDX 2 1086#define mmDISP_INTERRUPT_STATUS_CONTINUE4 0x012e 1087#define mmDISP_INTERRUPT_STATUS_CONTINUE4_BASE_IDX 2 1088#define mmDISP_INTERRUPT_STATUS_CONTINUE5 0x012f 1089#define mmDISP_INTERRUPT_STATUS_CONTINUE5_BASE_IDX 2 1090#define mmDISP_INTERRUPT_STATUS_CONTINUE6 0x0130 1091#define mmDISP_INTERRUPT_STATUS_CONTINUE6_BASE_IDX 2 1092#define mmDISP_INTERRUPT_STATUS_CONTINUE7 0x0131 1093#define mmDISP_INTERRUPT_STATUS_CONTINUE7_BASE_IDX 2 1094#define mmDISP_INTERRUPT_STATUS_CONTINUE8 0x0132 1095#define mmDISP_INTERRUPT_STATUS_CONTINUE8_BASE_IDX 2 1096#define mmDISP_INTERRUPT_STATUS_CONTINUE9 0x0133 1097#define mmDISP_INTERRUPT_STATUS_CONTINUE9_BASE_IDX 2 1098#define mmDISP_INTERRUPT_STATUS_CONTINUE10 0x0134 1099#define mmDISP_INTERRUPT_STATUS_CONTINUE10_BASE_IDX 2 1100#define mmDISP_INTERRUPT_STATUS_CONTINUE11 0x0135 1101#define mmDISP_INTERRUPT_STATUS_CONTINUE11_BASE_IDX 2 1102#define mmDISP_INTERRUPT_STATUS_CONTINUE12 0x0136 1103#define mmDISP_INTERRUPT_STATUS_CONTINUE12_BASE_IDX 2 1104#define mmDISP_INTERRUPT_STATUS_CONTINUE13 0x0137 1105#define mmDISP_INTERRUPT_STATUS_CONTINUE13_BASE_IDX 2 1106#define mmDISP_INTERRUPT_STATUS_CONTINUE14 0x0138 1107#define mmDISP_INTERRUPT_STATUS_CONTINUE14_BASE_IDX 2 1108#define mmDISP_INTERRUPT_STATUS_CONTINUE15 0x0139 1109#define mmDISP_INTERRUPT_STATUS_CONTINUE15_BASE_IDX 2 1110#define mmDISP_INTERRUPT_STATUS_CONTINUE16 0x013a 1111#define mmDISP_INTERRUPT_STATUS_CONTINUE16_BASE_IDX 2 1112#define mmDISP_INTERRUPT_STATUS_CONTINUE17 0x013b 1113#define mmDISP_INTERRUPT_STATUS_CONTINUE17_BASE_IDX 2 1114#define mmDISP_INTERRUPT_STATUS_CONTINUE18 0x013c 1115#define mmDISP_INTERRUPT_STATUS_CONTINUE18_BASE_IDX 2 1116#define mmDISP_INTERRUPT_STATUS_CONTINUE19 0x013d 1117#define mmDISP_INTERRUPT_STATUS_CONTINUE19_BASE_IDX 2 1118#define mmDISP_INTERRUPT_STATUS_CONTINUE20 0x013e 1119#define mmDISP_INTERRUPT_STATUS_CONTINUE20_BASE_IDX 2 1120#define mmDISP_INTERRUPT_STATUS_CONTINUE21 0x013f 1121#define mmDISP_INTERRUPT_STATUS_CONTINUE21_BASE_IDX 2 1122#define mmDISP_INTERRUPT_STATUS_CONTINUE22 0x0140 1123#define mmDISP_INTERRUPT_STATUS_CONTINUE22_BASE_IDX 2 1124#define mmDC_GPU_TIMER_START_POSITION_VREADY 0x0141 1125#define mmDC_GPU_TIMER_START_POSITION_VREADY_BASE_IDX 2 1126#define mmDC_GPU_TIMER_START_POSITION_FLIP 0x0142 1127#define mmDC_GPU_TIMER_START_POSITION_FLIP_BASE_IDX 2 1128#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK 0x0143 1129#define mmDC_GPU_TIMER_START_POSITION_V_UPDATE_NO_LOCK_BASE_IDX 2 1130#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY 0x0144 1131#define mmDC_GPU_TIMER_START_POSITION_FLIP_AWAY_BASE_IDX 2 1132 1133 1134// addressBlock: dce_dc_wb0_dispdec_cnv_dispdec 1135// base address: 0x0 1136#define mmCNV0_WB_ENABLE 0x01da 1137#define mmCNV0_WB_ENABLE_BASE_IDX 2 1138#define mmCNV0_WB_EC_CONFIG 0x01db 1139#define mmCNV0_WB_EC_CONFIG_BASE_IDX 2 1140#define mmCNV0_CNV_MODE 0x01dc 1141#define mmCNV0_CNV_MODE_BASE_IDX 2 1142#define mmCNV0_CNV_WINDOW_START 0x01dd 1143#define mmCNV0_CNV_WINDOW_START_BASE_IDX 2 1144#define mmCNV0_CNV_WINDOW_SIZE 0x01de 1145#define mmCNV0_CNV_WINDOW_SIZE_BASE_IDX 2 1146#define mmCNV0_CNV_UPDATE 0x01df 1147#define mmCNV0_CNV_UPDATE_BASE_IDX 2 1148#define mmCNV0_CNV_SOURCE_SIZE 0x01e0 1149#define mmCNV0_CNV_SOURCE_SIZE_BASE_IDX 2 1150#define mmCNV0_CNV_CSC_CONTROL 0x01e1 1151#define mmCNV0_CNV_CSC_CONTROL_BASE_IDX 2 1152#define mmCNV0_CNV_CSC_C11_C12 0x01e2 1153#define mmCNV0_CNV_CSC_C11_C12_BASE_IDX 2 1154#define mmCNV0_CNV_CSC_C13_C14 0x01e3 1155#define mmCNV0_CNV_CSC_C13_C14_BASE_IDX 2 1156#define mmCNV0_CNV_CSC_C21_C22 0x01e4 1157#define mmCNV0_CNV_CSC_C21_C22_BASE_IDX 2 1158#define mmCNV0_CNV_CSC_C23_C24 0x01e5 1159#define mmCNV0_CNV_CSC_C23_C24_BASE_IDX 2 1160#define mmCNV0_CNV_CSC_C31_C32 0x01e6 1161#define mmCNV0_CNV_CSC_C31_C32_BASE_IDX 2 1162#define mmCNV0_CNV_CSC_C33_C34 0x01e7 1163#define mmCNV0_CNV_CSC_C33_C34_BASE_IDX 2 1164#define mmCNV0_CNV_CSC_ROUND_OFFSET_R 0x01e8 1165#define mmCNV0_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2 1166#define mmCNV0_CNV_CSC_ROUND_OFFSET_G 0x01e9 1167#define mmCNV0_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2 1168#define mmCNV0_CNV_CSC_ROUND_OFFSET_B 0x01ea 1169#define mmCNV0_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2 1170#define mmCNV0_CNV_CSC_CLAMP_R 0x01eb 1171#define mmCNV0_CNV_CSC_CLAMP_R_BASE_IDX 2 1172#define mmCNV0_CNV_CSC_CLAMP_G 0x01ec 1173#define mmCNV0_CNV_CSC_CLAMP_G_BASE_IDX 2 1174#define mmCNV0_CNV_CSC_CLAMP_B 0x01ed 1175#define mmCNV0_CNV_CSC_CLAMP_B_BASE_IDX 2 1176#define mmCNV0_CNV_TEST_CNTL 0x01ee 1177#define mmCNV0_CNV_TEST_CNTL_BASE_IDX 2 1178#define mmCNV0_CNV_TEST_CRC_RED 0x01ef 1179#define mmCNV0_CNV_TEST_CRC_RED_BASE_IDX 2 1180#define mmCNV0_CNV_TEST_CRC_GREEN 0x01f0 1181#define mmCNV0_CNV_TEST_CRC_GREEN_BASE_IDX 2 1182#define mmCNV0_CNV_TEST_CRC_BLUE 0x01f1 1183#define mmCNV0_CNV_TEST_CRC_BLUE_BASE_IDX 2 1184#define mmCNV0_CNV_INPUT_SELECT 0x01f5 1185#define mmCNV0_CNV_INPUT_SELECT_BASE_IDX 2 1186#define mmCNV0_WB_SOFT_RESET 0x01f8 1187#define mmCNV0_WB_SOFT_RESET_BASE_IDX 2 1188#define mmCNV0_WB_WARM_UP_MODE_CTL1 0x01f9 1189#define mmCNV0_WB_WARM_UP_MODE_CTL1_BASE_IDX 2 1190#define mmCNV0_WB_WARM_UP_MODE_CTL2 0x01fa 1191#define mmCNV0_WB_WARM_UP_MODE_CTL2_BASE_IDX 2 1192 1193 1194// addressBlock: dce_dc_wb0_dispdec_wbscl_dispdec 1195// base address: 0x0 1196#define mmWBSCL0_WBSCL_COEF_RAM_SELECT 0x020a 1197#define mmWBSCL0_WBSCL_COEF_RAM_SELECT_BASE_IDX 2 1198#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA 0x020b 1199#define mmWBSCL0_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 1200#define mmWBSCL0_WBSCL_MODE 0x020c 1201#define mmWBSCL0_WBSCL_MODE_BASE_IDX 2 1202#define mmWBSCL0_WBSCL_TAP_CONTROL 0x020d 1203#define mmWBSCL0_WBSCL_TAP_CONTROL_BASE_IDX 2 1204#define mmWBSCL0_WBSCL_DEST_SIZE 0x020e 1205#define mmWBSCL0_WBSCL_DEST_SIZE_BASE_IDX 2 1206#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO 0x020f 1207#define mmWBSCL0_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 1208#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x0210 1209#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 1210#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR 0x0211 1211#define mmWBSCL0_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 1212#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO 0x0212 1213#define mmWBSCL0_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 1214#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB 0x0213 1215#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 1216#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR 0x0214 1217#define mmWBSCL0_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 1218#define mmWBSCL0_WBSCL_ROUND_OFFSET 0x0215 1219#define mmWBSCL0_WBSCL_ROUND_OFFSET_BASE_IDX 2 1220#define mmWBSCL0_WBSCL_CLAMP 0x0216 1221#define mmWBSCL0_WBSCL_CLAMP_BASE_IDX 2 1222#define mmWBSCL0_WBSCL_OVERFLOW_STATUS 0x0217 1223#define mmWBSCL0_WBSCL_OVERFLOW_STATUS_BASE_IDX 2 1224#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0218 1225#define mmWBSCL0_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 1226#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY 0x0219 1227#define mmWBSCL0_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 1228#define mmWBSCL0_WBSCL_TEST_CNTL 0x021a 1229#define mmWBSCL0_WBSCL_TEST_CNTL_BASE_IDX 2 1230#define mmWBSCL0_WBSCL_TEST_CRC_RED 0x021b 1231#define mmWBSCL0_WBSCL_TEST_CRC_RED_BASE_IDX 2 1232#define mmWBSCL0_WBSCL_TEST_CRC_GREEN 0x021c 1233#define mmWBSCL0_WBSCL_TEST_CRC_GREEN_BASE_IDX 2 1234#define mmWBSCL0_WBSCL_TEST_CRC_BLUE 0x021d 1235#define mmWBSCL0_WBSCL_TEST_CRC_BLUE_BASE_IDX 2 1236#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN 0x021e 1237#define mmWBSCL0_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 1238#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT 0x021f 1239#define mmWBSCL0_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 1240#define mmWBSCL0_WBSCL_RAM_SHUTDOWN 0x0222 1241#define mmWBSCL0_WBSCL_RAM_SHUTDOWN_BASE_IDX 2 1242 1243 1244// addressBlock: dce_dc_wb0_dispdec_wb_dcperfmon_dc_perfmon_dispdec 1245// base address: 0x8e8 1246#define mmDC_PERFMON3_PERFCOUNTER_CNTL 0x023a 1247#define mmDC_PERFMON3_PERFCOUNTER_CNTL_BASE_IDX 2 1248#define mmDC_PERFMON3_PERFCOUNTER_CNTL2 0x023b 1249#define mmDC_PERFMON3_PERFCOUNTER_CNTL2_BASE_IDX 2 1250#define mmDC_PERFMON3_PERFCOUNTER_STATE 0x023c 1251#define mmDC_PERFMON3_PERFCOUNTER_STATE_BASE_IDX 2 1252#define mmDC_PERFMON3_PERFMON_CNTL 0x023d 1253#define mmDC_PERFMON3_PERFMON_CNTL_BASE_IDX 2 1254#define mmDC_PERFMON3_PERFMON_CNTL2 0x023e 1255#define mmDC_PERFMON3_PERFMON_CNTL2_BASE_IDX 2 1256#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC 0x023f 1257#define mmDC_PERFMON3_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1258#define mmDC_PERFMON3_PERFMON_CVALUE_LOW 0x0240 1259#define mmDC_PERFMON3_PERFMON_CVALUE_LOW_BASE_IDX 2 1260#define mmDC_PERFMON3_PERFMON_HI 0x0241 1261#define mmDC_PERFMON3_PERFMON_HI_BASE_IDX 2 1262#define mmDC_PERFMON3_PERFMON_LOW 0x0242 1263#define mmDC_PERFMON3_PERFMON_LOW_BASE_IDX 2 1264 1265 1266// addressBlock: dce_dc_wb1_dispdec_cnv_dispdec 1267// base address: 0x1b0 1268#define mmCNV1_WB_ENABLE 0x0246 1269#define mmCNV1_WB_ENABLE_BASE_IDX 2 1270#define mmCNV1_WB_EC_CONFIG 0x0247 1271#define mmCNV1_WB_EC_CONFIG_BASE_IDX 2 1272#define mmCNV1_CNV_MODE 0x0248 1273#define mmCNV1_CNV_MODE_BASE_IDX 2 1274#define mmCNV1_CNV_WINDOW_START 0x0249 1275#define mmCNV1_CNV_WINDOW_START_BASE_IDX 2 1276#define mmCNV1_CNV_WINDOW_SIZE 0x024a 1277#define mmCNV1_CNV_WINDOW_SIZE_BASE_IDX 2 1278#define mmCNV1_CNV_UPDATE 0x024b 1279#define mmCNV1_CNV_UPDATE_BASE_IDX 2 1280#define mmCNV1_CNV_SOURCE_SIZE 0x024c 1281#define mmCNV1_CNV_SOURCE_SIZE_BASE_IDX 2 1282#define mmCNV1_CNV_CSC_CONTROL 0x024d 1283#define mmCNV1_CNV_CSC_CONTROL_BASE_IDX 2 1284#define mmCNV1_CNV_CSC_C11_C12 0x024e 1285#define mmCNV1_CNV_CSC_C11_C12_BASE_IDX 2 1286#define mmCNV1_CNV_CSC_C13_C14 0x024f 1287#define mmCNV1_CNV_CSC_C13_C14_BASE_IDX 2 1288#define mmCNV1_CNV_CSC_C21_C22 0x0250 1289#define mmCNV1_CNV_CSC_C21_C22_BASE_IDX 2 1290#define mmCNV1_CNV_CSC_C23_C24 0x0251 1291#define mmCNV1_CNV_CSC_C23_C24_BASE_IDX 2 1292#define mmCNV1_CNV_CSC_C31_C32 0x0252 1293#define mmCNV1_CNV_CSC_C31_C32_BASE_IDX 2 1294#define mmCNV1_CNV_CSC_C33_C34 0x0253 1295#define mmCNV1_CNV_CSC_C33_C34_BASE_IDX 2 1296#define mmCNV1_CNV_CSC_ROUND_OFFSET_R 0x0254 1297#define mmCNV1_CNV_CSC_ROUND_OFFSET_R_BASE_IDX 2 1298#define mmCNV1_CNV_CSC_ROUND_OFFSET_G 0x0255 1299#define mmCNV1_CNV_CSC_ROUND_OFFSET_G_BASE_IDX 2 1300#define mmCNV1_CNV_CSC_ROUND_OFFSET_B 0x0256 1301#define mmCNV1_CNV_CSC_ROUND_OFFSET_B_BASE_IDX 2 1302#define mmCNV1_CNV_CSC_CLAMP_R 0x0257 1303#define mmCNV1_CNV_CSC_CLAMP_R_BASE_IDX 2 1304#define mmCNV1_CNV_CSC_CLAMP_G 0x0258 1305#define mmCNV1_CNV_CSC_CLAMP_G_BASE_IDX 2 1306#define mmCNV1_CNV_CSC_CLAMP_B 0x0259 1307#define mmCNV1_CNV_CSC_CLAMP_B_BASE_IDX 2 1308#define mmCNV1_CNV_TEST_CNTL 0x025a 1309#define mmCNV1_CNV_TEST_CNTL_BASE_IDX 2 1310#define mmCNV1_CNV_TEST_CRC_RED 0x025b 1311#define mmCNV1_CNV_TEST_CRC_RED_BASE_IDX 2 1312#define mmCNV1_CNV_TEST_CRC_GREEN 0x025c 1313#define mmCNV1_CNV_TEST_CRC_GREEN_BASE_IDX 2 1314#define mmCNV1_CNV_TEST_CRC_BLUE 0x025d 1315#define mmCNV1_CNV_TEST_CRC_BLUE_BASE_IDX 2 1316#define mmCNV1_CNV_INPUT_SELECT 0x0261 1317#define mmCNV1_CNV_INPUT_SELECT_BASE_IDX 2 1318#define mmCNV1_WB_SOFT_RESET 0x0264 1319#define mmCNV1_WB_SOFT_RESET_BASE_IDX 2 1320#define mmCNV1_WB_WARM_UP_MODE_CTL1 0x0265 1321#define mmCNV1_WB_WARM_UP_MODE_CTL1_BASE_IDX 2 1322#define mmCNV1_WB_WARM_UP_MODE_CTL2 0x0266 1323#define mmCNV1_WB_WARM_UP_MODE_CTL2_BASE_IDX 2 1324 1325 1326// addressBlock: dce_dc_wb1_dispdec_wbscl_dispdec 1327// base address: 0x1b0 1328#define mmWBSCL1_WBSCL_COEF_RAM_SELECT 0x0276 1329#define mmWBSCL1_WBSCL_COEF_RAM_SELECT_BASE_IDX 2 1330#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA 0x0277 1331#define mmWBSCL1_WBSCL_COEF_RAM_TAP_DATA_BASE_IDX 2 1332#define mmWBSCL1_WBSCL_MODE 0x0278 1333#define mmWBSCL1_WBSCL_MODE_BASE_IDX 2 1334#define mmWBSCL1_WBSCL_TAP_CONTROL 0x0279 1335#define mmWBSCL1_WBSCL_TAP_CONTROL_BASE_IDX 2 1336#define mmWBSCL1_WBSCL_DEST_SIZE 0x027a 1337#define mmWBSCL1_WBSCL_DEST_SIZE_BASE_IDX 2 1338#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO 0x027b 1339#define mmWBSCL1_WBSCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 1340#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB 0x027c 1341#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_Y_RGB_BASE_IDX 2 1342#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR 0x027d 1343#define mmWBSCL1_WBSCL_HORZ_FILTER_INIT_CBCR_BASE_IDX 2 1344#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO 0x027e 1345#define mmWBSCL1_WBSCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 1346#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB 0x027f 1347#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_Y_RGB_BASE_IDX 2 1348#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR 0x0280 1349#define mmWBSCL1_WBSCL_VERT_FILTER_INIT_CBCR_BASE_IDX 2 1350#define mmWBSCL1_WBSCL_ROUND_OFFSET 0x0281 1351#define mmWBSCL1_WBSCL_ROUND_OFFSET_BASE_IDX 2 1352#define mmWBSCL1_WBSCL_CLAMP 0x0282 1353#define mmWBSCL1_WBSCL_CLAMP_BASE_IDX 2 1354#define mmWBSCL1_WBSCL_OVERFLOW_STATUS 0x0283 1355#define mmWBSCL1_WBSCL_OVERFLOW_STATUS_BASE_IDX 2 1356#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS 0x0284 1357#define mmWBSCL1_WBSCL_COEF_RAM_CONFLICT_STATUS_BASE_IDX 2 1358#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY 0x0285 1359#define mmWBSCL1_WBSCL_OUTSIDE_PIX_STRATEGY_BASE_IDX 2 1360#define mmWBSCL1_WBSCL_TEST_CNTL 0x0286 1361#define mmWBSCL1_WBSCL_TEST_CNTL_BASE_IDX 2 1362#define mmWBSCL1_WBSCL_TEST_CRC_RED 0x0287 1363#define mmWBSCL1_WBSCL_TEST_CRC_RED_BASE_IDX 2 1364#define mmWBSCL1_WBSCL_TEST_CRC_GREEN 0x0288 1365#define mmWBSCL1_WBSCL_TEST_CRC_GREEN_BASE_IDX 2 1366#define mmWBSCL1_WBSCL_TEST_CRC_BLUE 0x0289 1367#define mmWBSCL1_WBSCL_TEST_CRC_BLUE_BASE_IDX 2 1368#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN 0x028a 1369#define mmWBSCL1_WBSCL_BACKPRESSURE_CNT_EN_BASE_IDX 2 1370#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT 0x028b 1371#define mmWBSCL1_WB_MCIF_BACKPRESSURE_CNT_BASE_IDX 2 1372#define mmWBSCL1_WBSCL_RAM_SHUTDOWN 0x028e 1373#define mmWBSCL1_WBSCL_RAM_SHUTDOWN_BASE_IDX 2 1374 1375 1376// addressBlock: dce_dc_wb1_dispdec_wb_dcperfmon_dc_perfmon_dispdec 1377// base address: 0xa98 1378#define mmDC_PERFMON4_PERFCOUNTER_CNTL 0x02a6 1379#define mmDC_PERFMON4_PERFCOUNTER_CNTL_BASE_IDX 2 1380#define mmDC_PERFMON4_PERFCOUNTER_CNTL2 0x02a7 1381#define mmDC_PERFMON4_PERFCOUNTER_CNTL2_BASE_IDX 2 1382#define mmDC_PERFMON4_PERFCOUNTER_STATE 0x02a8 1383#define mmDC_PERFMON4_PERFCOUNTER_STATE_BASE_IDX 2 1384#define mmDC_PERFMON4_PERFMON_CNTL 0x02a9 1385#define mmDC_PERFMON4_PERFMON_CNTL_BASE_IDX 2 1386#define mmDC_PERFMON4_PERFMON_CNTL2 0x02aa 1387#define mmDC_PERFMON4_PERFMON_CNTL2_BASE_IDX 2 1388#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC 0x02ab 1389#define mmDC_PERFMON4_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1390#define mmDC_PERFMON4_PERFMON_CVALUE_LOW 0x02ac 1391#define mmDC_PERFMON4_PERFMON_CVALUE_LOW_BASE_IDX 2 1392#define mmDC_PERFMON4_PERFMON_HI 0x02ad 1393#define mmDC_PERFMON4_PERFMON_HI_BASE_IDX 2 1394#define mmDC_PERFMON4_PERFMON_LOW 0x02ae 1395#define mmDC_PERFMON4_PERFMON_LOW_BASE_IDX 2 1396 1397 1398// addressBlock: dce_dc_mmhubbub_mcif_wb0_dispdec 1399// base address: 0x0 1400#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL 0x02b2 1401#define mmMCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1402#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R 0x02b3 1403#define mmMCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 1404#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS 0x02b4 1405#define mmMCIF_WB0_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1406#define mmMCIF_WB0_MCIF_WB_BUF_PITCH 0x02b5 1407#define mmMCIF_WB0_MCIF_WB_BUF_PITCH_BASE_IDX 2 1408#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS 0x02b6 1409#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 1410#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2 0x02b7 1411#define mmMCIF_WB0_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1412#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS 0x02b8 1413#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 1414#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2 0x02b9 1415#define mmMCIF_WB0_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1416#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS 0x02ba 1417#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 1418#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2 0x02bb 1419#define mmMCIF_WB0_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1420#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS 0x02bc 1421#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 1422#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2 0x02bd 1423#define mmMCIF_WB0_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1424#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL 0x02be 1425#define mmMCIF_WB0_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1426#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE 0x02bf 1427#define mmMCIF_WB0_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 1428#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y 0x02c2 1429#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1430#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x02c3 1431#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 1432#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C 0x02c4 1433#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1434#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x02c5 1435#define mmMCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 1436#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y 0x02c6 1437#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1438#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x02c7 1439#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 1440#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C 0x02c8 1441#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1442#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x02c9 1443#define mmMCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 1444#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y 0x02ca 1445#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1446#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x02cb 1447#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 1448#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C 0x02cc 1449#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1450#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x02cd 1451#define mmMCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 1452#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y 0x02ce 1453#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1454#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x02cf 1455#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 1456#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C 0x02d0 1457#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1458#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x02d1 1459#define mmMCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 1460#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL 0x02d2 1461#define mmMCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1462#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x02d3 1463#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1464#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL 0x02d4 1465#define mmMCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1466#define mmMCIF_WB0_MCIF_WB_WATERMARK 0x02d5 1467#define mmMCIF_WB0_MCIF_WB_WATERMARK_BASE_IDX 2 1468#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL 0x02d6 1469#define mmMCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1470#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL 0x02d7 1471#define mmMCIF_WB0_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 1472#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL 0x02d8 1473#define mmMCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1474#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL 0x02d9 1475#define mmMCIF_WB0_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1476#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE 0x02db 1477#define mmMCIF_WB0_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1478#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE 0x02dc 1479#define mmMCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1480 1481 1482// addressBlock: dce_dc_mmhubbub_mcif_wb1_dispdec 1483// base address: 0x100 1484#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL 0x02f2 1485#define mmMCIF_WB1_MCIF_WB_BUFMGR_SW_CONTROL_BASE_IDX 2 1486#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R 0x02f3 1487#define mmMCIF_WB1_MCIF_WB_BUFMGR_CUR_LINE_R_BASE_IDX 2 1488#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS 0x02f4 1489#define mmMCIF_WB1_MCIF_WB_BUFMGR_STATUS_BASE_IDX 2 1490#define mmMCIF_WB1_MCIF_WB_BUF_PITCH 0x02f5 1491#define mmMCIF_WB1_MCIF_WB_BUF_PITCH_BASE_IDX 2 1492#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS 0x02f6 1493#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS_BASE_IDX 2 1494#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2 0x02f7 1495#define mmMCIF_WB1_MCIF_WB_BUF_1_STATUS2_BASE_IDX 2 1496#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS 0x02f8 1497#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS_BASE_IDX 2 1498#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2 0x02f9 1499#define mmMCIF_WB1_MCIF_WB_BUF_2_STATUS2_BASE_IDX 2 1500#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS 0x02fa 1501#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS_BASE_IDX 2 1502#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2 0x02fb 1503#define mmMCIF_WB1_MCIF_WB_BUF_3_STATUS2_BASE_IDX 2 1504#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS 0x02fc 1505#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS_BASE_IDX 2 1506#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2 0x02fd 1507#define mmMCIF_WB1_MCIF_WB_BUF_4_STATUS2_BASE_IDX 2 1508#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL 0x02fe 1509#define mmMCIF_WB1_MCIF_WB_ARBITRATION_CONTROL_BASE_IDX 2 1510#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE 0x02ff 1511#define mmMCIF_WB1_MCIF_WB_SCLK_CHANGE_BASE_IDX 2 1512#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y 0x0302 1513#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_BASE_IDX 2 1514#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET 0x0303 1515#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_Y_OFFSET_BASE_IDX 2 1516#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C 0x0304 1517#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_BASE_IDX 2 1518#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET 0x0305 1519#define mmMCIF_WB1_MCIF_WB_BUF_1_ADDR_C_OFFSET_BASE_IDX 2 1520#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y 0x0306 1521#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_BASE_IDX 2 1522#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET 0x0307 1523#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_Y_OFFSET_BASE_IDX 2 1524#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C 0x0308 1525#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_BASE_IDX 2 1526#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET 0x0309 1527#define mmMCIF_WB1_MCIF_WB_BUF_2_ADDR_C_OFFSET_BASE_IDX 2 1528#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y 0x030a 1529#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_BASE_IDX 2 1530#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET 0x030b 1531#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_Y_OFFSET_BASE_IDX 2 1532#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C 0x030c 1533#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_BASE_IDX 2 1534#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET 0x030d 1535#define mmMCIF_WB1_MCIF_WB_BUF_3_ADDR_C_OFFSET_BASE_IDX 2 1536#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y 0x030e 1537#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_BASE_IDX 2 1538#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET 0x030f 1539#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_Y_OFFSET_BASE_IDX 2 1540#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C 0x0310 1541#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_BASE_IDX 2 1542#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET 0x0311 1543#define mmMCIF_WB1_MCIF_WB_BUF_4_ADDR_C_OFFSET_BASE_IDX 2 1544#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL 0x0312 1545#define mmMCIF_WB1_MCIF_WB_BUFMGR_VCE_CONTROL_BASE_IDX 2 1546#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK 0x0313 1547#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK_BASE_IDX 2 1548#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL 0x0314 1549#define mmMCIF_WB1_MCIF_WB_NB_PSTATE_CONTROL_BASE_IDX 2 1550#define mmMCIF_WB1_MCIF_WB_WATERMARK 0x0315 1551#define mmMCIF_WB1_MCIF_WB_WATERMARK_BASE_IDX 2 1552#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL 0x0316 1553#define mmMCIF_WB1_MCIF_WB_CLOCK_GATER_CONTROL_BASE_IDX 2 1554#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL 0x0317 1555#define mmMCIF_WB1_MCIF_WB_WARM_UP_CNTL_BASE_IDX 2 1556#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL 0x0318 1557#define mmMCIF_WB1_MCIF_WB_SELF_REFRESH_CONTROL_BASE_IDX 2 1558#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL 0x0319 1559#define mmMCIF_WB1_MULTI_LEVEL_QOS_CTRL_BASE_IDX 2 1560#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE 0x031b 1561#define mmMCIF_WB1_MCIF_WB_BUF_LUMA_SIZE_BASE_IDX 2 1562#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE 0x031c 1563#define mmMCIF_WB1_MCIF_WB_BUF_CHROMA_SIZE_BASE_IDX 2 1564 1565 1566// addressBlock: dce_dc_mmhubbub_mmhubbub_dispdec 1567// base address: 0x0 1568#define mmWBIF0_MISC_CTRL 0x0333 1569#define mmWBIF0_MISC_CTRL_BASE_IDX 2 1570#define mmWBIF0_SMU_WM_CONTROL 0x0334 1571#define mmWBIF0_SMU_WM_CONTROL_BASE_IDX 2 1572#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER 0x0335 1573#define mmWBIF0_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1574#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER 0x0336 1575#define mmWBIF0_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1576#define mmWBIF1_MISC_CTRL 0x0337 1577#define mmWBIF1_MISC_CTRL_BASE_IDX 2 1578#define mmWBIF1_SMU_WM_CONTROL 0x0338 1579#define mmWBIF1_SMU_WM_CONTROL_BASE_IDX 2 1580#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER 0x0339 1581#define mmWBIF1_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1582#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER 0x033a 1583#define mmWBIF1_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1584#define mmVGA_SRC_SPLIT_CNTL 0x033b 1585#define mmVGA_SRC_SPLIT_CNTL_BASE_IDX 2 1586#define mmMMHUBBUB_MEM_PWR_STATUS 0x033c 1587#define mmMMHUBBUB_MEM_PWR_STATUS_BASE_IDX 2 1588#define mmMMHUBBUB_MEM_PWR_CNTL 0x033d 1589#define mmMMHUBBUB_MEM_PWR_CNTL_BASE_IDX 2 1590#define mmMMHUBBUB_CLOCK_CNTL 0x033e 1591#define mmMMHUBBUB_CLOCK_CNTL_BASE_IDX 2 1592#define mmMMHUBBUB_SOFT_RESET 0x033f 1593#define mmMMHUBBUB_SOFT_RESET_BASE_IDX 2 1594 1595 1596// addressBlock: dce_dc_mmhubbub_vgaif_dispdec 1597// base address: 0x0 1598#define mmMCIF_CONTROL 0x034a 1599#define mmMCIF_CONTROL_BASE_IDX 2 1600#define mmMCIF_WRITE_COMBINE_CONTROL 0x034b 1601#define mmMCIF_WRITE_COMBINE_CONTROL_BASE_IDX 2 1602#define mmMCIF_PHASE0_OUTSTANDING_COUNTER 0x034e 1603#define mmMCIF_PHASE0_OUTSTANDING_COUNTER_BASE_IDX 2 1604#define mmMCIF_PHASE1_OUTSTANDING_COUNTER 0x034f 1605#define mmMCIF_PHASE1_OUTSTANDING_COUNTER_BASE_IDX 2 1606#define mmMCIF_PHASE2_OUTSTANDING_COUNTER 0x0350 1607#define mmMCIF_PHASE2_OUTSTANDING_COUNTER_BASE_IDX 2 1608 1609 1610// addressBlock: dce_dc_mmhubbub_mmhubbub_dcperfmon_dc_perfmon_dispdec 1611// base address: 0xd48 1612#define mmDC_PERFMON5_PERFCOUNTER_CNTL 0x0352 1613#define mmDC_PERFMON5_PERFCOUNTER_CNTL_BASE_IDX 2 1614#define mmDC_PERFMON5_PERFCOUNTER_CNTL2 0x0353 1615#define mmDC_PERFMON5_PERFCOUNTER_CNTL2_BASE_IDX 2 1616#define mmDC_PERFMON5_PERFCOUNTER_STATE 0x0354 1617#define mmDC_PERFMON5_PERFCOUNTER_STATE_BASE_IDX 2 1618#define mmDC_PERFMON5_PERFMON_CNTL 0x0355 1619#define mmDC_PERFMON5_PERFMON_CNTL_BASE_IDX 2 1620#define mmDC_PERFMON5_PERFMON_CNTL2 0x0356 1621#define mmDC_PERFMON5_PERFMON_CNTL2_BASE_IDX 2 1622#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC 0x0357 1623#define mmDC_PERFMON5_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1624#define mmDC_PERFMON5_PERFMON_CVALUE_LOW 0x0358 1625#define mmDC_PERFMON5_PERFMON_CVALUE_LOW_BASE_IDX 2 1626#define mmDC_PERFMON5_PERFMON_HI 0x0359 1627#define mmDC_PERFMON5_PERFMON_HI_BASE_IDX 2 1628#define mmDC_PERFMON5_PERFMON_LOW 0x035a 1629#define mmDC_PERFMON5_PERFMON_LOW_BASE_IDX 2 1630 1631 1632// addressBlock: dce_dc_hda_azf0stream0_dispdec 1633// base address: 0x0 1634#define mmAZF0STREAM0_AZALIA_STREAM_INDEX 0x035e 1635#define mmAZF0STREAM0_AZALIA_STREAM_INDEX_BASE_IDX 2 1636#define mmAZF0STREAM0_AZALIA_STREAM_DATA 0x035f 1637#define mmAZF0STREAM0_AZALIA_STREAM_DATA_BASE_IDX 2 1638 1639 1640// addressBlock: dce_dc_hda_azf0stream1_dispdec 1641// base address: 0x8 1642#define mmAZF0STREAM1_AZALIA_STREAM_INDEX 0x0360 1643#define mmAZF0STREAM1_AZALIA_STREAM_INDEX_BASE_IDX 2 1644#define mmAZF0STREAM1_AZALIA_STREAM_DATA 0x0361 1645#define mmAZF0STREAM1_AZALIA_STREAM_DATA_BASE_IDX 2 1646 1647 1648// addressBlock: dce_dc_hda_azf0stream2_dispdec 1649// base address: 0x10 1650#define mmAZF0STREAM2_AZALIA_STREAM_INDEX 0x0362 1651#define mmAZF0STREAM2_AZALIA_STREAM_INDEX_BASE_IDX 2 1652#define mmAZF0STREAM2_AZALIA_STREAM_DATA 0x0363 1653#define mmAZF0STREAM2_AZALIA_STREAM_DATA_BASE_IDX 2 1654 1655 1656// addressBlock: dce_dc_hda_azf0stream3_dispdec 1657// base address: 0x18 1658#define mmAZF0STREAM3_AZALIA_STREAM_INDEX 0x0364 1659#define mmAZF0STREAM3_AZALIA_STREAM_INDEX_BASE_IDX 2 1660#define mmAZF0STREAM3_AZALIA_STREAM_DATA 0x0365 1661#define mmAZF0STREAM3_AZALIA_STREAM_DATA_BASE_IDX 2 1662 1663 1664// addressBlock: dce_dc_hda_azf0stream4_dispdec 1665// base address: 0x20 1666#define mmAZF0STREAM4_AZALIA_STREAM_INDEX 0x0366 1667#define mmAZF0STREAM4_AZALIA_STREAM_INDEX_BASE_IDX 2 1668#define mmAZF0STREAM4_AZALIA_STREAM_DATA 0x0367 1669#define mmAZF0STREAM4_AZALIA_STREAM_DATA_BASE_IDX 2 1670 1671 1672// addressBlock: dce_dc_hda_azf0stream5_dispdec 1673// base address: 0x28 1674#define mmAZF0STREAM5_AZALIA_STREAM_INDEX 0x0368 1675#define mmAZF0STREAM5_AZALIA_STREAM_INDEX_BASE_IDX 2 1676#define mmAZF0STREAM5_AZALIA_STREAM_DATA 0x0369 1677#define mmAZF0STREAM5_AZALIA_STREAM_DATA_BASE_IDX 2 1678 1679 1680// addressBlock: dce_dc_hda_azf0stream6_dispdec 1681// base address: 0x30 1682#define mmAZF0STREAM6_AZALIA_STREAM_INDEX 0x036a 1683#define mmAZF0STREAM6_AZALIA_STREAM_INDEX_BASE_IDX 2 1684#define mmAZF0STREAM6_AZALIA_STREAM_DATA 0x036b 1685#define mmAZF0STREAM6_AZALIA_STREAM_DATA_BASE_IDX 2 1686 1687 1688// addressBlock: dce_dc_hda_azf0stream7_dispdec 1689// base address: 0x38 1690#define mmAZF0STREAM7_AZALIA_STREAM_INDEX 0x036c 1691#define mmAZF0STREAM7_AZALIA_STREAM_INDEX_BASE_IDX 2 1692#define mmAZF0STREAM7_AZALIA_STREAM_DATA 0x036d 1693#define mmAZF0STREAM7_AZALIA_STREAM_DATA_BASE_IDX 2 1694 1695 1696// addressBlock: dce_dc_hda_az_misc_dispdec 1697// base address: 0x0 1698#define mmAZ_CLOCK_CNTL 0x0372 1699#define mmAZ_CLOCK_CNTL_BASE_IDX 2 1700 1701 1702// addressBlock: dce_dc_hda_az_dcperfmon_dc_perfmon_dispdec 1703// base address: 0xde8 1704#define mmDC_PERFMON6_PERFCOUNTER_CNTL 0x037a 1705#define mmDC_PERFMON6_PERFCOUNTER_CNTL_BASE_IDX 2 1706#define mmDC_PERFMON6_PERFCOUNTER_CNTL2 0x037b 1707#define mmDC_PERFMON6_PERFCOUNTER_CNTL2_BASE_IDX 2 1708#define mmDC_PERFMON6_PERFCOUNTER_STATE 0x037c 1709#define mmDC_PERFMON6_PERFCOUNTER_STATE_BASE_IDX 2 1710#define mmDC_PERFMON6_PERFMON_CNTL 0x037d 1711#define mmDC_PERFMON6_PERFMON_CNTL_BASE_IDX 2 1712#define mmDC_PERFMON6_PERFMON_CNTL2 0x037e 1713#define mmDC_PERFMON6_PERFMON_CNTL2_BASE_IDX 2 1714#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC 0x037f 1715#define mmDC_PERFMON6_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 1716#define mmDC_PERFMON6_PERFMON_CVALUE_LOW 0x0380 1717#define mmDC_PERFMON6_PERFMON_CVALUE_LOW_BASE_IDX 2 1718#define mmDC_PERFMON6_PERFMON_HI 0x0381 1719#define mmDC_PERFMON6_PERFMON_HI_BASE_IDX 2 1720#define mmDC_PERFMON6_PERFMON_LOW 0x0382 1721#define mmDC_PERFMON6_PERFMON_LOW_BASE_IDX 2 1722 1723 1724// addressBlock: dce_dc_hda_azf0endpoint0_dispdec 1725// base address: 0x0 1726#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0386 1727#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1728#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0387 1729#define mmAZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1730 1731 1732// addressBlock: dce_dc_hda_azf0endpoint1_dispdec 1733// base address: 0x18 1734#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x038c 1735#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1736#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA 0x038d 1737#define mmAZF0ENDPOINT1_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1738 1739 1740// addressBlock: dce_dc_hda_azf0endpoint2_dispdec 1741// base address: 0x30 1742#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0392 1743#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1744#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0393 1745#define mmAZF0ENDPOINT2_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1746 1747 1748// addressBlock: dce_dc_hda_azf0endpoint3_dispdec 1749// base address: 0x48 1750#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x0398 1751#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1752#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA 0x0399 1753#define mmAZF0ENDPOINT3_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1754 1755 1756// addressBlock: dce_dc_hda_azf0endpoint4_dispdec 1757// base address: 0x60 1758#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x039e 1759#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1760#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA 0x039f 1761#define mmAZF0ENDPOINT4_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1762 1763 1764// addressBlock: dce_dc_hda_azf0endpoint5_dispdec 1765// base address: 0x78 1766#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03a4 1767#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1768#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03a5 1769#define mmAZF0ENDPOINT5_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1770 1771 1772// addressBlock: dce_dc_hda_azf0endpoint6_dispdec 1773// base address: 0x90 1774#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03aa 1775#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1776#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03ab 1777#define mmAZF0ENDPOINT6_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1778 1779 1780// addressBlock: dce_dc_hda_azf0endpoint7_dispdec 1781// base address: 0xa8 1782#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX 0x03b0 1783#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_INDEX_BASE_IDX 2 1784#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA 0x03b1 1785#define mmAZF0ENDPOINT7_AZALIA_F0_CODEC_ENDPOINT_DATA_BASE_IDX 2 1786 1787 1788// addressBlock: dce_dc_hda_azf0controller_dispdec 1789// base address: 0x0 1790#define mmAZALIA_CONTROLLER_CLOCK_GATING 0x03c2 1791#define mmAZALIA_CONTROLLER_CLOCK_GATING_BASE_IDX 2 1792#define mmAZALIA_AUDIO_DTO 0x03c3 1793#define mmAZALIA_AUDIO_DTO_BASE_IDX 2 1794#define mmAZALIA_AUDIO_DTO_CONTROL 0x03c4 1795#define mmAZALIA_AUDIO_DTO_CONTROL_BASE_IDX 2 1796#define mmAZALIA_SOCCLK_CONTROL 0x03c5 1797#define mmAZALIA_SOCCLK_CONTROL_BASE_IDX 2 1798#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE 0x03c6 1799#define mmAZALIA_UNDERFLOW_FILLER_SAMPLE_BASE_IDX 2 1800#define mmAZALIA_DATA_DMA_CONTROL 0x03c7 1801#define mmAZALIA_DATA_DMA_CONTROL_BASE_IDX 2 1802#define mmAZALIA_BDL_DMA_CONTROL 0x03c8 1803#define mmAZALIA_BDL_DMA_CONTROL_BASE_IDX 2 1804#define mmAZALIA_RIRB_AND_DP_CONTROL 0x03c9 1805#define mmAZALIA_RIRB_AND_DP_CONTROL_BASE_IDX 2 1806#define mmAZALIA_CORB_DMA_CONTROL 0x03ca 1807#define mmAZALIA_CORB_DMA_CONTROL_BASE_IDX 2 1808#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER 0x03d1 1809#define mmAZALIA_APPLICATION_POSITION_IN_CYCLIC_BUFFER_BASE_IDX 2 1810#define mmAZALIA_CYCLIC_BUFFER_SYNC 0x03d2 1811#define mmAZALIA_CYCLIC_BUFFER_SYNC_BASE_IDX 2 1812#define mmAZALIA_GLOBAL_CAPABILITIES 0x03d3 1813#define mmAZALIA_GLOBAL_CAPABILITIES_BASE_IDX 2 1814#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY 0x03d4 1815#define mmAZALIA_OUTPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1816#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL 0x03d5 1817#define mmAZALIA_OUTPUT_STREAM_ARBITER_CONTROL_BASE_IDX 2 1818#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY 0x03d6 1819#define mmAZALIA_INPUT_PAYLOAD_CAPABILITY_BASE_IDX 2 1820#define mmAZALIA_INPUT_CRC0_CONTROL0 0x03d9 1821#define mmAZALIA_INPUT_CRC0_CONTROL0_BASE_IDX 2 1822#define mmAZALIA_INPUT_CRC0_CONTROL1 0x03da 1823#define mmAZALIA_INPUT_CRC0_CONTROL1_BASE_IDX 2 1824#define mmAZALIA_INPUT_CRC0_CONTROL2 0x03db 1825#define mmAZALIA_INPUT_CRC0_CONTROL2_BASE_IDX 2 1826#define mmAZALIA_INPUT_CRC0_CONTROL3 0x03dc 1827#define mmAZALIA_INPUT_CRC0_CONTROL3_BASE_IDX 2 1828#define mmAZALIA_INPUT_CRC0_RESULT 0x03dd 1829#define mmAZALIA_INPUT_CRC0_RESULT_BASE_IDX 2 1830#define mmAZALIA_INPUT_CRC1_CONTROL0 0x03de 1831#define mmAZALIA_INPUT_CRC1_CONTROL0_BASE_IDX 2 1832#define mmAZALIA_INPUT_CRC1_CONTROL1 0x03df 1833#define mmAZALIA_INPUT_CRC1_CONTROL1_BASE_IDX 2 1834#define mmAZALIA_INPUT_CRC1_CONTROL2 0x03e0 1835#define mmAZALIA_INPUT_CRC1_CONTROL2_BASE_IDX 2 1836#define mmAZALIA_INPUT_CRC1_CONTROL3 0x03e1 1837#define mmAZALIA_INPUT_CRC1_CONTROL3_BASE_IDX 2 1838#define mmAZALIA_INPUT_CRC1_RESULT 0x03e2 1839#define mmAZALIA_INPUT_CRC1_RESULT_BASE_IDX 2 1840#define mmAZALIA_CRC0_CONTROL0 0x03e3 1841#define mmAZALIA_CRC0_CONTROL0_BASE_IDX 2 1842#define mmAZALIA_CRC0_CONTROL1 0x03e4 1843#define mmAZALIA_CRC0_CONTROL1_BASE_IDX 2 1844#define mmAZALIA_CRC0_CONTROL2 0x03e5 1845#define mmAZALIA_CRC0_CONTROL2_BASE_IDX 2 1846#define mmAZALIA_CRC0_CONTROL3 0x03e6 1847#define mmAZALIA_CRC0_CONTROL3_BASE_IDX 2 1848#define mmAZALIA_CRC0_RESULT 0x03e7 1849#define mmAZALIA_CRC0_RESULT_BASE_IDX 2 1850#define mmAZALIA_CRC1_CONTROL0 0x03e8 1851#define mmAZALIA_CRC1_CONTROL0_BASE_IDX 2 1852#define mmAZALIA_CRC1_CONTROL1 0x03e9 1853#define mmAZALIA_CRC1_CONTROL1_BASE_IDX 2 1854#define mmAZALIA_CRC1_CONTROL2 0x03ea 1855#define mmAZALIA_CRC1_CONTROL2_BASE_IDX 2 1856#define mmAZALIA_CRC1_CONTROL3 0x03eb 1857#define mmAZALIA_CRC1_CONTROL3_BASE_IDX 2 1858#define mmAZALIA_CRC1_RESULT 0x03ec 1859#define mmAZALIA_CRC1_RESULT_BASE_IDX 2 1860#define mmAZALIA_MEM_PWR_CTRL 0x03ee 1861#define mmAZALIA_MEM_PWR_CTRL_BASE_IDX 2 1862#define mmAZALIA_MEM_PWR_STATUS 0x03ef 1863#define mmAZALIA_MEM_PWR_STATUS_BASE_IDX 2 1864 1865 1866// addressBlock: dce_dc_hda_azf0root_dispdec 1867// base address: 0x0 1868#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0406 1869#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID_BASE_IDX 2 1870#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID 0x0407 1871#define mmAZALIA_F0_CODEC_ROOT_PARAMETER_REVISION_ID_BASE_IDX 2 1872#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL 0x0408 1873#define mmAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX 2 1874#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL 0x0409 1875#define mmAZALIA_F0_CODEC_RESYNC_FIFO_CONTROL_BASE_IDX 2 1876#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x040a 1877#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_GROUP_TYPE_BASE_IDX 2 1878#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x040b 1879#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES_BASE_IDX 2 1880#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x040c 1881#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS_BASE_IDX 2 1882#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x040d 1883#define mmAZALIA_F0_CODEC_FUNCTION_PARAMETER_POWER_STATES_BASE_IDX 2 1884#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE 0x040e 1885#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_POWER_STATE_BASE_IDX 2 1886#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET 0x040f 1887#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESET_BASE_IDX 2 1888#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x0410 1889#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_BASE_IDX 2 1890#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x0411 1891#define mmAZALIA_F0_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION_BASE_IDX 2 1892#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY 0x0412 1893#define mmCC_RCU_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1894#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x0413 1895#define mmCC_RCU_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1896#define mmAZALIA_F0_GTC_GROUP_OFFSET0 0x0415 1897#define mmAZALIA_F0_GTC_GROUP_OFFSET0_BASE_IDX 2 1898#define mmAZALIA_F0_GTC_GROUP_OFFSET1 0x0416 1899#define mmAZALIA_F0_GTC_GROUP_OFFSET1_BASE_IDX 2 1900#define mmAZALIA_F0_GTC_GROUP_OFFSET2 0x0417 1901#define mmAZALIA_F0_GTC_GROUP_OFFSET2_BASE_IDX 2 1902#define mmAZALIA_F0_GTC_GROUP_OFFSET3 0x0418 1903#define mmAZALIA_F0_GTC_GROUP_OFFSET3_BASE_IDX 2 1904#define mmAZALIA_F0_GTC_GROUP_OFFSET4 0x0419 1905#define mmAZALIA_F0_GTC_GROUP_OFFSET4_BASE_IDX 2 1906#define mmAZALIA_F0_GTC_GROUP_OFFSET5 0x041a 1907#define mmAZALIA_F0_GTC_GROUP_OFFSET5_BASE_IDX 2 1908#define mmAZALIA_F0_GTC_GROUP_OFFSET6 0x041b 1909#define mmAZALIA_F0_GTC_GROUP_OFFSET6_BASE_IDX 2 1910#define mmREG_DC_AUDIO_PORT_CONNECTIVITY 0x041c 1911#define mmREG_DC_AUDIO_PORT_CONNECTIVITY_BASE_IDX 2 1912#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY 0x041d 1913#define mmREG_DC_AUDIO_INPUT_PORT_CONNECTIVITY_BASE_IDX 2 1914 1915 1916// addressBlock: dce_dc_hda_azf0stream8_dispdec 1917// base address: 0x320 1918#define mmAZF0STREAM8_AZALIA_STREAM_INDEX 0x0426 1919#define mmAZF0STREAM8_AZALIA_STREAM_INDEX_BASE_IDX 2 1920#define mmAZF0STREAM8_AZALIA_STREAM_DATA 0x0427 1921#define mmAZF0STREAM8_AZALIA_STREAM_DATA_BASE_IDX 2 1922 1923 1924// addressBlock: dce_dc_hda_azf0stream9_dispdec 1925// base address: 0x328 1926#define mmAZF0STREAM9_AZALIA_STREAM_INDEX 0x0428 1927#define mmAZF0STREAM9_AZALIA_STREAM_INDEX_BASE_IDX 2 1928#define mmAZF0STREAM9_AZALIA_STREAM_DATA 0x0429 1929#define mmAZF0STREAM9_AZALIA_STREAM_DATA_BASE_IDX 2 1930 1931 1932// addressBlock: dce_dc_hda_azf0stream10_dispdec 1933// base address: 0x330 1934#define mmAZF0STREAM10_AZALIA_STREAM_INDEX 0x042a 1935#define mmAZF0STREAM10_AZALIA_STREAM_INDEX_BASE_IDX 2 1936#define mmAZF0STREAM10_AZALIA_STREAM_DATA 0x042b 1937#define mmAZF0STREAM10_AZALIA_STREAM_DATA_BASE_IDX 2 1938 1939 1940// addressBlock: dce_dc_hda_azf0stream11_dispdec 1941// base address: 0x338 1942#define mmAZF0STREAM11_AZALIA_STREAM_INDEX 0x042c 1943#define mmAZF0STREAM11_AZALIA_STREAM_INDEX_BASE_IDX 2 1944#define mmAZF0STREAM11_AZALIA_STREAM_DATA 0x042d 1945#define mmAZF0STREAM11_AZALIA_STREAM_DATA_BASE_IDX 2 1946 1947 1948// addressBlock: dce_dc_hda_azf0stream12_dispdec 1949// base address: 0x340 1950#define mmAZF0STREAM12_AZALIA_STREAM_INDEX 0x042e 1951#define mmAZF0STREAM12_AZALIA_STREAM_INDEX_BASE_IDX 2 1952#define mmAZF0STREAM12_AZALIA_STREAM_DATA 0x042f 1953#define mmAZF0STREAM12_AZALIA_STREAM_DATA_BASE_IDX 2 1954 1955 1956// addressBlock: dce_dc_hda_azf0stream13_dispdec 1957// base address: 0x348 1958#define mmAZF0STREAM13_AZALIA_STREAM_INDEX 0x0430 1959#define mmAZF0STREAM13_AZALIA_STREAM_INDEX_BASE_IDX 2 1960#define mmAZF0STREAM13_AZALIA_STREAM_DATA 0x0431 1961#define mmAZF0STREAM13_AZALIA_STREAM_DATA_BASE_IDX 2 1962 1963 1964// addressBlock: dce_dc_hda_azf0stream14_dispdec 1965// base address: 0x350 1966#define mmAZF0STREAM14_AZALIA_STREAM_INDEX 0x0432 1967#define mmAZF0STREAM14_AZALIA_STREAM_INDEX_BASE_IDX 2 1968#define mmAZF0STREAM14_AZALIA_STREAM_DATA 0x0433 1969#define mmAZF0STREAM14_AZALIA_STREAM_DATA_BASE_IDX 2 1970 1971 1972// addressBlock: dce_dc_hda_azf0stream15_dispdec 1973// base address: 0x358 1974#define mmAZF0STREAM15_AZALIA_STREAM_INDEX 0x0434 1975#define mmAZF0STREAM15_AZALIA_STREAM_INDEX_BASE_IDX 2 1976#define mmAZF0STREAM15_AZALIA_STREAM_DATA 0x0435 1977#define mmAZF0STREAM15_AZALIA_STREAM_DATA_BASE_IDX 2 1978 1979 1980// addressBlock: dce_dc_hda_azf0inputendpoint0_dispdec 1981// base address: 0x0 1982#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043a 1983#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1984#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043b 1985#define mmAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1986 1987 1988// addressBlock: dce_dc_hda_azf0inputendpoint1_dispdec 1989// base address: 0x10 1990#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x043e 1991#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 1992#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x043f 1993#define mmAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 1994 1995 1996// addressBlock: dce_dc_hda_azf0inputendpoint2_dispdec 1997// base address: 0x20 1998#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0442 1999#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2000#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0443
2001#define mmAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2002 2003 2004// addressBlock: dce_dc_hda_azf0inputendpoint3_dispdec 2005// base address: 0x30 2006#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0446 2007#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2008#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0447 2009#define mmAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2010 2011 2012// addressBlock: dce_dc_hda_azf0inputendpoint4_dispdec 2013// base address: 0x40 2014#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044a 2015#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2016#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044b 2017#define mmAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2018 2019 2020// addressBlock: dce_dc_hda_azf0inputendpoint5_dispdec 2021// base address: 0x50 2022#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x044e 2023#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2024#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x044f 2025#define mmAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2026 2027 2028// addressBlock: dce_dc_hda_azf0inputendpoint6_dispdec 2029// base address: 0x60 2030#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0452 2031#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2032#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0453 2033#define mmAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2034 2035 2036// addressBlock: dce_dc_hda_azf0inputendpoint7_dispdec 2037// base address: 0x70 2038#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX 0x0456 2039#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_INDEX_BASE_IDX 2 2040#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA 0x0457 2041#define mmAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_ENDPOINT_DATA_BASE_IDX 2 2042 2043 2044// addressBlock: dce_dc_dchubbub_hubbub_sdpif_dispdec 2045// base address: 0x0 2046#define mmDCHUBBUB_SDPIF_CFG0 0x048f 2047#define mmDCHUBBUB_SDPIF_CFG0_BASE_IDX 2 2048#define mmDCHUBBUB_SDPIF_CFG1 0x0490 2049#define mmDCHUBBUB_SDPIF_CFG1_BASE_IDX 2 2050#define mmDCHUBBUB_FORCE_IO_STATUS_0 0x0491 2051#define mmDCHUBBUB_FORCE_IO_STATUS_0_BASE_IDX 2 2052#define mmDCHUBBUB_FORCE_IO_STATUS_1 0x0492 2053#define mmDCHUBBUB_FORCE_IO_STATUS_1_BASE_IDX 2 2054#define mmDCHUBBUB_SDPIF_FB_BASE 0x0493 2055#define mmDCHUBBUB_SDPIF_FB_BASE_BASE_IDX 2 2056#define mmDCHUBBUB_SDPIF_FB_TOP 0x0494 2057#define mmDCHUBBUB_SDPIF_FB_TOP_BASE_IDX 2 2058#define mmDCHUBBUB_SDPIF_FB_OFFSET 0x0495 2059#define mmDCHUBBUB_SDPIF_FB_OFFSET_BASE_IDX 2 2060#define mmDCHUBBUB_SDPIF_AGP_BOT 0x0496 2061#define mmDCHUBBUB_SDPIF_AGP_BOT_BASE_IDX 2 2062#define mmDCHUBBUB_SDPIF_AGP_TOP 0x0497 2063#define mmDCHUBBUB_SDPIF_AGP_TOP_BASE_IDX 2 2064#define mmDCHUBBUB_SDPIF_AGP_BASE 0x0498 2065#define mmDCHUBBUB_SDPIF_AGP_BASE_BASE_IDX 2 2066#define mmDCHUBBUB_SDPIF_APER_BASE 0x0499 2067#define mmDCHUBBUB_SDPIF_APER_BASE_BASE_IDX 2 2068#define mmDCHUBBUB_SDPIF_APER_TOP 0x049a 2069#define mmDCHUBBUB_SDPIF_APER_TOP_BASE_IDX 2 2070#define mmDCHUBBUB_SDPIF_APER_DEF_0 0x049b 2071#define mmDCHUBBUB_SDPIF_APER_DEF_0_BASE_IDX 2 2072#define mmDCHUBBUB_SDPIF_APER_DEF_1 0x049c 2073#define mmDCHUBBUB_SDPIF_APER_DEF_1_BASE_IDX 2 2074#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d 2075#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2 2076#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1 0x049e 2077#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_1_BASE_IDX 2 2078#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W 0x049f 2079#define mmDCHUBBUB_SDPIF_MMIO_CNTRL_W_BASE_IDX 2 2080#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0 0x04a0 2081#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_0_BASE_IDX 2 2082#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0 0x04a1 2083#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_0_BASE_IDX 2 2084#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0 0x04a2 2085#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_0_BASE_IDX 2 2086#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0 0x04a3 2087#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_0_BASE_IDX 2 2088#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0 0x04a4 2089#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_0_BASE_IDX 2 2090#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0 0x04a5 2091#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_0_BASE_IDX 2 2092#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1 0x04a6 2093#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_1_BASE_IDX 2 2094#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1 0x04a7 2095#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_1_BASE_IDX 2 2096#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1 0x04a8 2097#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_1_BASE_IDX 2 2098#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1 0x04a9 2099#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_1_BASE_IDX 2 2100#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1 0x04aa 2101#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_1_BASE_IDX 2 2102#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1 0x04ab 2103#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_1_BASE_IDX 2 2104#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2 0x04ac 2105#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_2_BASE_IDX 2 2106#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2 0x04ad 2107#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_2_BASE_IDX 2 2108#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2 0x04ae 2109#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_2_BASE_IDX 2 2110#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2 0x04af 2111#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_2_BASE_IDX 2 2112#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2 0x04b0 2113#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_2_BASE_IDX 2 2114#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2 0x04b1 2115#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_2_BASE_IDX 2 2116#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3 0x04b2 2117#define mmDCHUBBUB_SDPIF_MARC_BASE_LO_3_BASE_IDX 2 2118#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3 0x04b3 2119#define mmDCHUBBUB_SDPIF_MARC_BASE_HI_3_BASE_IDX 2 2120#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3 0x04b4 2121#define mmDCHUBBUB_SDPIF_MARC_RELOC_LO_3_BASE_IDX 2 2122#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3 0x04b5 2123#define mmDCHUBBUB_SDPIF_MARC_RELOC_HI_3_BASE_IDX 2 2124#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3 0x04b6 2125#define mmDCHUBBUB_SDPIF_MARC_LENGTH_LO_3_BASE_IDX 2 2126#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3 0x04b7 2127#define mmDCHUBBUB_SDPIF_MARC_LENGTH_HI_3_BASE_IDX 2 2128#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL 0x04b8 2129#define mmDCHUBBUB_SDPIF_PIPE_SEC_LVL_BASE_IDX 2 2130#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL 0x04b9 2131#define mmDCHUBBUB_SDPIF_MEM_PWR_CTRL_BASE_IDX 2 2132#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS 0x04ba 2133#define mmDCHUBBUB_SDPIF_MEM_PWR_STATUS_BASE_IDX 2 2134 2135 2136// addressBlock: dce_dc_dchubbub_hubbub_ret_path_dispdec 2137// base address: 0x0 2138#define mmDCHUBBUB_RET_PATH_DCC_CFG 0x04cf 2139#define mmDCHUBBUB_RET_PATH_DCC_CFG_BASE_IDX 2 2140#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0 0x04d0 2141#define mmDCHUBBUB_RET_PATH_DCC_CFG0_0_BASE_IDX 2 2142#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1 0x04d1 2143#define mmDCHUBBUB_RET_PATH_DCC_CFG0_1_BASE_IDX 2 2144#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0 0x04d2 2145#define mmDCHUBBUB_RET_PATH_DCC_CFG1_0_BASE_IDX 2 2146#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1 0x04d3 2147#define mmDCHUBBUB_RET_PATH_DCC_CFG1_1_BASE_IDX 2 2148#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0 0x04d4 2149#define mmDCHUBBUB_RET_PATH_DCC_CFG2_0_BASE_IDX 2 2150#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1 0x04d5 2151#define mmDCHUBBUB_RET_PATH_DCC_CFG2_1_BASE_IDX 2 2152#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0 0x04d6 2153#define mmDCHUBBUB_RET_PATH_DCC_CFG3_0_BASE_IDX 2 2154#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1 0x04d7 2155#define mmDCHUBBUB_RET_PATH_DCC_CFG3_1_BASE_IDX 2 2156#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0 0x04d8 2157#define mmDCHUBBUB_RET_PATH_DCC_CFG4_0_BASE_IDX 2 2158#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1 0x04d9 2159#define mmDCHUBBUB_RET_PATH_DCC_CFG4_1_BASE_IDX 2 2160#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0 0x04da 2161#define mmDCHUBBUB_RET_PATH_DCC_CFG5_0_BASE_IDX 2 2162#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1 0x04db 2163#define mmDCHUBBUB_RET_PATH_DCC_CFG5_1_BASE_IDX 2 2164#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0 0x04dc 2165#define mmDCHUBBUB_RET_PATH_DCC_CFG6_0_BASE_IDX 2 2166#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1 0x04dd 2167#define mmDCHUBBUB_RET_PATH_DCC_CFG6_1_BASE_IDX 2 2168#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0 0x04de 2169#define mmDCHUBBUB_RET_PATH_DCC_CFG7_0_BASE_IDX 2 2170#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1 0x04df 2171#define mmDCHUBBUB_RET_PATH_DCC_CFG7_1_BASE_IDX 2 2172#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL 0x04e0 2173#define mmDCHUBBUB_RET_PATH_MEM_PWR_CTRL_BASE_IDX 2 2174#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS 0x04e1 2175#define mmDCHUBBUB_RET_PATH_MEM_PWR_STATUS_BASE_IDX 2 2176#define mmDCHUBBUB_CRC_CTRL 0x04e2 2177#define mmDCHUBBUB_CRC_CTRL_BASE_IDX 2 2178#define mmDCHUBBUB_CRC0_VAL_R_G 0x04e3 2179#define mmDCHUBBUB_CRC0_VAL_R_G_BASE_IDX 2 2180#define mmDCHUBBUB_CRC0_VAL_B_A 0x04e4 2181#define mmDCHUBBUB_CRC0_VAL_B_A_BASE_IDX 2 2182#define mmDCHUBBUB_CRC1_VAL_R_G 0x04e5 2183#define mmDCHUBBUB_CRC1_VAL_R_G_BASE_IDX 2 2184#define mmDCHUBBUB_CRC1_VAL_B_A 0x04e6 2185#define mmDCHUBBUB_CRC1_VAL_B_A_BASE_IDX 2 2186 2187 2188// addressBlock: dce_dc_dchubbub_hubbub_dispdec 2189// base address: 0x0 2190#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND 0x0505 2191#define mmDCHUBBUB_ARB_DF_REQ_OUTSTAND_BASE_IDX 2 2192#define mmDCHUBBUB_ARB_SAT_LEVEL 0x0506 2193#define mmDCHUBBUB_ARB_SAT_LEVEL_BASE_IDX 2 2194#define mmDCHUBBUB_ARB_QOS_FORCE 0x0507 2195#define mmDCHUBBUB_ARB_QOS_FORCE_BASE_IDX 2 2196#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL 0x0508 2197#define mmDCHUBBUB_ARB_DRAM_STATE_CNTL_BASE_IDX 2 2198#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A 0x0509 2199#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_A_BASE_IDX 2 2200#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A 0x050a 2201#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_A_BASE_IDX 2 2202#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A 0x050b 2203#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A_BASE_IDX 2 2204#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A 0x050c 2205#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_A_BASE_IDX 2 2206#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A 0x050d 2207#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_A_BASE_IDX 2 2208#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B 0x050e 2209#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_B_BASE_IDX 2 2210#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B 0x050f 2211#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_B_BASE_IDX 2 2212#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B 0x0510 2213#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_B_BASE_IDX 2 2214#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B 0x0511 2215#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_B_BASE_IDX 2 2216#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B 0x0512 2217#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_B_BASE_IDX 2 2218#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C 0x0513 2219#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_C_BASE_IDX 2 2220#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C 0x0514 2221#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_C_BASE_IDX 2 2222#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C 0x0515 2223#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_C_BASE_IDX 2 2224#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C 0x0516 2225#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_C_BASE_IDX 2 2226#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C 0x0517 2227#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_C_BASE_IDX 2 2228#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D 0x0518 2229#define mmDCHUBBUB_ARB_DATA_URGENCY_WATERMARK_D_BASE_IDX 2 2230#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D 0x0519 2231#define mmDCHUBBUB_ARB_PTE_META_URGENCY_WATERMARK_D_BASE_IDX 2 2232#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D 0x051a 2233#define mmDCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_D_BASE_IDX 2 2234#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D 0x051b 2235#define mmDCHUBBUB_ARB_ALLOW_SR_EXIT_WATERMARK_D_BASE_IDX 2 2236#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D 0x051c 2237#define mmDCHUBBUB_ARB_ALLOW_DRAM_CLK_CHANGE_WATERMARK_D_BASE_IDX 2 2238#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL 0x051d 2239#define mmDCHUBBUB_ARB_WATERMARK_CHANGE_CNTL_BASE_IDX 2 2240#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE 0x051e 2241#define mmDCHUBBUB_ARB_TIMEOUT_ENABLE_BASE_IDX 2 2242#define mmDCHUBBUB_GLOBAL_TIMER_CNTL 0x051f 2243#define mmDCHUBBUB_GLOBAL_TIMER_CNTL_BASE_IDX 2 2244#define mmSURFACE_CHECK0_ADDRESS_LSB 0x0520 2245#define mmSURFACE_CHECK0_ADDRESS_LSB_BASE_IDX 2 2246#define mmSURFACE_CHECK0_ADDRESS_MSB 0x0521 2247#define mmSURFACE_CHECK0_ADDRESS_MSB_BASE_IDX 2 2248#define mmSURFACE_CHECK1_ADDRESS_LSB 0x0522 2249#define mmSURFACE_CHECK1_ADDRESS_LSB_BASE_IDX 2 2250#define mmSURFACE_CHECK1_ADDRESS_MSB 0x0523 2251#define mmSURFACE_CHECK1_ADDRESS_MSB_BASE_IDX 2 2252#define mmSURFACE_CHECK2_ADDRESS_LSB 0x0524 2253#define mmSURFACE_CHECK2_ADDRESS_LSB_BASE_IDX 2 2254#define mmSURFACE_CHECK2_ADDRESS_MSB 0x0525 2255#define mmSURFACE_CHECK2_ADDRESS_MSB_BASE_IDX 2 2256#define mmSURFACE_CHECK3_ADDRESS_LSB 0x0526 2257#define mmSURFACE_CHECK3_ADDRESS_LSB_BASE_IDX 2 2258#define mmSURFACE_CHECK3_ADDRESS_MSB 0x0527 2259#define mmSURFACE_CHECK3_ADDRESS_MSB_BASE_IDX 2 2260#define mmVTG0_CONTROL 0x0528 2261#define mmVTG0_CONTROL_BASE_IDX 2 2262#define mmVTG1_CONTROL 0x0529 2263#define mmVTG1_CONTROL_BASE_IDX 2 2264#define mmVTG2_CONTROL 0x052a 2265#define mmVTG2_CONTROL_BASE_IDX 2 2266#define mmVTG3_CONTROL 0x052b 2267#define mmVTG3_CONTROL_BASE_IDX 2 2268#define mmVTG4_CONTROL 0x052c 2269#define mmVTG4_CONTROL_BASE_IDX 2 2270#define mmVTG5_CONTROL 0x052d 2271#define mmVTG5_CONTROL_BASE_IDX 2 2272#define mmDCHUBBUB_SOFT_RESET 0x052e 2273#define mmDCHUBBUB_SOFT_RESET_BASE_IDX 2 2274#define mmDCHUBBUB_CLOCK_CNTL 0x052f 2275#define mmDCHUBBUB_CLOCK_CNTL_BASE_IDX 2 2276#define mmDCFCLK_CNTL 0x0530 2277#define mmDCFCLK_CNTL_BASE_IDX 2 2278#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL 0x0531 2279#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL_BASE_IDX 2 2280#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2 0x0532 2281#define mmDCHUBBUB_PERFORMANCE_MEASUREMENT_CNTL2_BASE_IDX 2 2282#define mmDCHUBBUB_VLINE_SNAPSHOT 0x0533 2283#define mmDCHUBBUB_VLINE_SNAPSHOT_BASE_IDX 2 2284#define mmDCHUBBUB_SPARE 0x0534 2285#define mmDCHUBBUB_SPARE_BASE_IDX 2 2286#define mmDCHUBBUB_TEST_DEBUG_INDEX 0x053a 2287#define mmDCHUBBUB_TEST_DEBUG_INDEX_BASE_IDX 2 2288#define mmDCHUBBUB_TEST_DEBUG_DATA 0x053b 2289#define mmDCHUBBUB_TEST_DEBUG_DATA_BASE_IDX 2 2290 2291 2292// addressBlock: dce_dc_dchubbub_dchubbub_dcperfmon_dc_perfmon_dispdec 2293// base address: 0x1534 2294#define mmDC_PERFMON7_PERFCOUNTER_CNTL 0x054d 2295#define mmDC_PERFMON7_PERFCOUNTER_CNTL_BASE_IDX 2 2296#define mmDC_PERFMON7_PERFCOUNTER_CNTL2 0x054e 2297#define mmDC_PERFMON7_PERFCOUNTER_CNTL2_BASE_IDX 2 2298#define mmDC_PERFMON7_PERFCOUNTER_STATE 0x054f 2299#define mmDC_PERFMON7_PERFCOUNTER_STATE_BASE_IDX 2 2300#define mmDC_PERFMON7_PERFMON_CNTL 0x0550 2301#define mmDC_PERFMON7_PERFMON_CNTL_BASE_IDX 2 2302#define mmDC_PERFMON7_PERFMON_CNTL2 0x0551 2303#define mmDC_PERFMON7_PERFMON_CNTL2_BASE_IDX 2 2304#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC 0x0552 2305#define mmDC_PERFMON7_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2306#define mmDC_PERFMON7_PERFMON_CVALUE_LOW 0x0553 2307#define mmDC_PERFMON7_PERFMON_CVALUE_LOW_BASE_IDX 2 2308#define mmDC_PERFMON7_PERFMON_HI 0x0554 2309#define mmDC_PERFMON7_PERFMON_HI_BASE_IDX 2 2310#define mmDC_PERFMON7_PERFMON_LOW 0x0555 2311#define mmDC_PERFMON7_PERFMON_LOW_BASE_IDX 2 2312 2313 2314// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dispdec 2315// base address: 0x0 2316#define mmHUBP0_DCSURF_SURFACE_CONFIG 0x0559 2317#define mmHUBP0_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2318#define mmHUBP0_DCSURF_ADDR_CONFIG 0x055a 2319#define mmHUBP0_DCSURF_ADDR_CONFIG_BASE_IDX 2 2320#define mmHUBP0_DCSURF_TILING_CONFIG 0x055b 2321#define mmHUBP0_DCSURF_TILING_CONFIG_BASE_IDX 2 2322#define mmHUBP0_DCSURF_PRI_VIEWPORT_START 0x055c 2323#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2324#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d 2325#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2326#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C 0x055e 2327#define mmHUBP0_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2328#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x055f 2329#define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2330#define mmHUBP0_DCSURF_SEC_VIEWPORT_START 0x0560 2331#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2332#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION 0x0561 2333#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2334#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C 0x0562 2335#define mmHUBP0_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2336#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0563 2337#define mmHUBP0_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2338#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG 0x0564 2339#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2340#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C 0x0565 2341#define mmHUBP0_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2342#define mmHUBP0_DCHUBP_CNTL 0x0566 2343#define mmHUBP0_DCHUBP_CNTL_BASE_IDX 2 2344#define mmHUBP0_HUBP_CLK_CNTL 0x0567 2345#define mmHUBP0_HUBP_CLK_CNTL_BASE_IDX 2 2346#define mmHUBP0_DCHUBP_VMPG_CONFIG 0x0568 2347#define mmHUBP0_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2348#define mmHUBP0_HUBPREQ_DEBUG_DB 0x0569 2349#define mmHUBP0_HUBPREQ_DEBUG_DB_BASE_IDX 2 2350#define mmHUBP0_HUBPREQ_DEBUG 0x056a 2351#define mmHUBP0_HUBPREQ_DEBUG_BASE_IDX 2 2352#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x056e 2353#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2354#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x056f 2355#define mmHUBP0_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2356 2357 2358// addressBlock: dce_dc_dcbubp0_dispdec_hubpreq_dispdec 2359// base address: 0x0 2360#define mmHUBPREQ0_DCSURF_SURFACE_PITCH 0x057b 2361#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_BASE_IDX 2 2362#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C 0x057c 2363#define mmHUBPREQ0_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2364#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS 0x057d 2365#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2366#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x057e 2367#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2368#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x057f 2369#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2370#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0580 2371#define mmHUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2372#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0581 2373#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2374#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0582 2375#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2376#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0583 2377#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2378#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0584 2379#define mmHUBPREQ0_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2380#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0585 2381#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2382#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x0586 2383#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2384#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x0587 2385#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2386#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0588 2387#define mmHUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2388#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0589 2389#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2390#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x058a 2391#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2392#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x058b 2393#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2394#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x058c 2395#define mmHUBPREQ0_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2396#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL 0x058d 2397#define mmHUBPREQ0_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2398#define mmHUBPREQ0_DCSURF_FLIP_CONTROL 0x058e 2399#define mmHUBPREQ0_DCSURF_FLIP_CONTROL_BASE_IDX 2 2400#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2 0x058f 2401#define mmHUBPREQ0_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2402#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL 0x0590 2403#define mmHUBPREQ0_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 2404#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME 0x0591 2405#define mmHUBPREQ0_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 2406#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT 0x0592 2407#define mmHUBPREQ0_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2408#define mmHUBPREQ0_DCSURF_SURFACE_INUSE 0x0593 2409#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_BASE_IDX 2 2410#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH 0x0594 2411#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2412#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C 0x0595 2413#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2414#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C 0x0596 2415#define mmHUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2416#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE 0x0597 2417#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2418#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0598 2419#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2420#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0599 2421#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2422#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x059a 2423#define mmHUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2424#define mmHUBPREQ0_DCN_EXPANSION_MODE 0x059b 2425#define mmHUBPREQ0_DCN_EXPANSION_MODE_BASE_IDX 2 2426#define mmHUBPREQ0_DCN_TTU_QOS_WM 0x059c 2427#define mmHUBPREQ0_DCN_TTU_QOS_WM_BASE_IDX 2 2428#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL 0x059d 2429#define mmHUBPREQ0_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2430#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0 0x059e 2431#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2432#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1 0x059f 2433#define mmHUBPREQ0_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2434#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0 0x05a0 2435#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2436#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1 0x05a1 2437#define mmHUBPREQ0_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2438#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0 0x05a2 2439#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2440#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1 0x05a3 2441#define mmHUBPREQ0_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2442#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x05a4 2443#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 2444#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x05a5 2445#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 2446#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x05a6 2447#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 2448#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x05a7 2449#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 2450#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x05a8 2451#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 2452#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x05a9 2453#define mmHUBPREQ0_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 2454#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x05aa 2455#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 2456#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x05ab 2457#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 2458#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x05ac 2459#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 2460#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x05ad 2461#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 2462#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x05ae 2463#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 2464#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x05af 2465#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 2466#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x05b0 2467#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 2468#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x05b1 2469#define mmHUBPREQ0_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 2470#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS 0x05b2 2471#define mmHUBPREQ0_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 2472#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x05b3 2473#define mmHUBPREQ0_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 2474#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL 0x05b4 2475#define mmHUBPREQ0_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 2476#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL 0x05b5 2477#define mmHUBPREQ0_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2478#define mmHUBPREQ0_BLANK_OFFSET_0 0x05b6 2479#define mmHUBPREQ0_BLANK_OFFSET_0_BASE_IDX 2 2480#define mmHUBPREQ0_BLANK_OFFSET_1 0x05b7 2481#define mmHUBPREQ0_BLANK_OFFSET_1_BASE_IDX 2 2482#define mmHUBPREQ0_DST_DIMENSIONS 0x05b8 2483#define mmHUBPREQ0_DST_DIMENSIONS_BASE_IDX 2 2484#define mmHUBPREQ0_DST_AFTER_SCALER 0x05b9 2485#define mmHUBPREQ0_DST_AFTER_SCALER_BASE_IDX 2 2486#define mmHUBPREQ0_PREFETCH_SETTINS 0x05ba 2487#define mmHUBPREQ0_PREFETCH_SETTINS_BASE_IDX 2 2488#define mmHUBPREQ0_PREFETCH_SETTINS_C 0x05bb 2489#define mmHUBPREQ0_PREFETCH_SETTINS_C_BASE_IDX 2 2490#define mmHUBPREQ0_VBLANK_PARAMETERS_0 0x05bc 2491#define mmHUBPREQ0_VBLANK_PARAMETERS_0_BASE_IDX 2 2492#define mmHUBPREQ0_VBLANK_PARAMETERS_1 0x05bd 2493#define mmHUBPREQ0_VBLANK_PARAMETERS_1_BASE_IDX 2 2494#define mmHUBPREQ0_VBLANK_PARAMETERS_2 0x05be 2495#define mmHUBPREQ0_VBLANK_PARAMETERS_2_BASE_IDX 2 2496#define mmHUBPREQ0_VBLANK_PARAMETERS_3 0x05bf 2497#define mmHUBPREQ0_VBLANK_PARAMETERS_3_BASE_IDX 2 2498#define mmHUBPREQ0_VBLANK_PARAMETERS_4 0x05c0 2499#define mmHUBPREQ0_VBLANK_PARAMETERS_4_BASE_IDX 2 2500#define mmHUBPREQ0_NOM_PARAMETERS_0 0x05c1 2501#define mmHUBPREQ0_NOM_PARAMETERS_0_BASE_IDX 2 2502#define mmHUBPREQ0_NOM_PARAMETERS_1 0x05c2 2503#define mmHUBPREQ0_NOM_PARAMETERS_1_BASE_IDX 2 2504#define mmHUBPREQ0_NOM_PARAMETERS_2 0x05c3 2505#define mmHUBPREQ0_NOM_PARAMETERS_2_BASE_IDX 2 2506#define mmHUBPREQ0_NOM_PARAMETERS_3 0x05c4 2507#define mmHUBPREQ0_NOM_PARAMETERS_3_BASE_IDX 2 2508#define mmHUBPREQ0_NOM_PARAMETERS_4 0x05c5 2509#define mmHUBPREQ0_NOM_PARAMETERS_4_BASE_IDX 2 2510#define mmHUBPREQ0_NOM_PARAMETERS_5 0x05c6 2511#define mmHUBPREQ0_NOM_PARAMETERS_5_BASE_IDX 2 2512#define mmHUBPREQ0_NOM_PARAMETERS_6 0x05c7 2513#define mmHUBPREQ0_NOM_PARAMETERS_6_BASE_IDX 2 2514#define mmHUBPREQ0_NOM_PARAMETERS_7 0x05c8 2515#define mmHUBPREQ0_NOM_PARAMETERS_7_BASE_IDX 2 2516#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE 0x05c9 2517#define mmHUBPREQ0_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2518#define mmHUBPREQ0_PER_LINE_DELIVERY 0x05ca 2519#define mmHUBPREQ0_PER_LINE_DELIVERY_BASE_IDX 2 2520#define mmHUBPREQ0_CURSOR_SETTINS 0x05cb 2521#define mmHUBPREQ0_CURSOR_SETTINS_BASE_IDX 2 2522#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ 0x05cc 2523#define mmHUBPREQ0_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2524#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL 0x05cd 2525#define mmHUBPREQ0_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2526#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS 0x05ce 2527#define mmHUBPREQ0_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2528 2529 2530// addressBlock: dce_dc_dcbubp0_dispdec_hubpret_dispdec 2531// base address: 0x0 2532#define mmHUBPRET0_HUBPRET_CONTROL 0x05e0 2533#define mmHUBPRET0_HUBPRET_CONTROL_BASE_IDX 2 2534#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL 0x05e1 2535#define mmHUBPRET0_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2536#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS 0x05e2 2537#define mmHUBPRET0_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2538#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0 0x05e3 2539#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2540#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1 0x05e4 2541#define mmHUBPRET0_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2542#define mmHUBPRET0_HUBPRET_READ_LINE0 0x05e5 2543#define mmHUBPRET0_HUBPRET_READ_LINE0_BASE_IDX 2 2544#define mmHUBPRET0_HUBPRET_READ_LINE1 0x05e6 2545#define mmHUBPRET0_HUBPRET_READ_LINE1_BASE_IDX 2 2546#define mmHUBPRET0_HUBPRET_INTERRUPT 0x05e7 2547#define mmHUBPRET0_HUBPRET_INTERRUPT_BASE_IDX 2 2548#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE 0x05e8 2549#define mmHUBPRET0_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2550#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS 0x05e9 2551#define mmHUBPRET0_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2552 2553 2554// addressBlock: dce_dc_dcbubp0_dispdec_cursor_dispdec 2555// base address: 0x0 2556#define mmCURSOR0_CURSOR_CONTROL 0x05ec 2557#define mmCURSOR0_CURSOR_CONTROL_BASE_IDX 2 2558#define mmCURSOR0_CURSOR_SURFACE_ADDRESS 0x05ed 2559#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2560#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH 0x05ee 2561#define mmCURSOR0_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2562#define mmCURSOR0_CURSOR_SIZE 0x05ef 2563#define mmCURSOR0_CURSOR_SIZE_BASE_IDX 2 2564#define mmCURSOR0_CURSOR_POSITION 0x05f0 2565#define mmCURSOR0_CURSOR_POSITION_BASE_IDX 2 2566#define mmCURSOR0_CURSOR_HOT_SPOT 0x05f1 2567#define mmCURSOR0_CURSOR_HOT_SPOT_BASE_IDX 2 2568#define mmCURSOR0_CURSOR_STEREO_CONTROL 0x05f2 2569#define mmCURSOR0_CURSOR_STEREO_CONTROL_BASE_IDX 2 2570#define mmCURSOR0_CURSOR_DST_OFFSET 0x05f3 2571#define mmCURSOR0_CURSOR_DST_OFFSET_BASE_IDX 2 2572#define mmCURSOR0_CURSOR_MEM_PWR_CTRL 0x05f4 2573#define mmCURSOR0_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2574#define mmCURSOR0_CURSOR_MEM_PWR_STATUS 0x05f5 2575#define mmCURSOR0_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2576 2577 2578// addressBlock: dce_dc_dcbubp0_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2579// base address: 0x1844 2580#define mmDC_PERFMON8_PERFCOUNTER_CNTL 0x0611 2581#define mmDC_PERFMON8_PERFCOUNTER_CNTL_BASE_IDX 2 2582#define mmDC_PERFMON8_PERFCOUNTER_CNTL2 0x0612 2583#define mmDC_PERFMON8_PERFCOUNTER_CNTL2_BASE_IDX 2 2584#define mmDC_PERFMON8_PERFCOUNTER_STATE 0x0613 2585#define mmDC_PERFMON8_PERFCOUNTER_STATE_BASE_IDX 2 2586#define mmDC_PERFMON8_PERFMON_CNTL 0x0614 2587#define mmDC_PERFMON8_PERFMON_CNTL_BASE_IDX 2 2588#define mmDC_PERFMON8_PERFMON_CNTL2 0x0615 2589#define mmDC_PERFMON8_PERFMON_CNTL2_BASE_IDX 2 2590#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC 0x0616 2591#define mmDC_PERFMON8_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2592#define mmDC_PERFMON8_PERFMON_CVALUE_LOW 0x0617 2593#define mmDC_PERFMON8_PERFMON_CVALUE_LOW_BASE_IDX 2 2594#define mmDC_PERFMON8_PERFMON_HI 0x0618 2595#define mmDC_PERFMON8_PERFMON_HI_BASE_IDX 2 2596#define mmDC_PERFMON8_PERFMON_LOW 0x0619 2597#define mmDC_PERFMON8_PERFMON_LOW_BASE_IDX 2 2598 2599 2600// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dispdec 2601// base address: 0x310 2602#define mmHUBP1_DCSURF_SURFACE_CONFIG 0x061d 2603#define mmHUBP1_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2604#define mmHUBP1_DCSURF_ADDR_CONFIG 0x061e 2605#define mmHUBP1_DCSURF_ADDR_CONFIG_BASE_IDX 2 2606#define mmHUBP1_DCSURF_TILING_CONFIG 0x061f 2607#define mmHUBP1_DCSURF_TILING_CONFIG_BASE_IDX 2 2608#define mmHUBP1_DCSURF_PRI_VIEWPORT_START 0x0620 2609#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2610#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION 0x0621 2611#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2612#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C 0x0622 2613#define mmHUBP1_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2614#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x0623 2615#define mmHUBP1_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2616#define mmHUBP1_DCSURF_SEC_VIEWPORT_START 0x0624 2617#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2618#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION 0x0625 2619#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2620#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C 0x0626 2621#define mmHUBP1_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2622#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x0627 2623#define mmHUBP1_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2624#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG 0x0628 2625#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2626#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C 0x0629 2627#define mmHUBP1_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2628#define mmHUBP1_DCHUBP_CNTL 0x062a 2629#define mmHUBP1_DCHUBP_CNTL_BASE_IDX 2 2630#define mmHUBP1_HUBP_CLK_CNTL 0x062b 2631#define mmHUBP1_HUBP_CLK_CNTL_BASE_IDX 2 2632#define mmHUBP1_DCHUBP_VMPG_CONFIG 0x062c 2633#define mmHUBP1_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2634#define mmHUBP1_HUBPREQ_DEBUG_DB 0x062d 2635#define mmHUBP1_HUBPREQ_DEBUG_DB_BASE_IDX 2 2636#define mmHUBP1_HUBPREQ_DEBUG 0x062e 2637#define mmHUBP1_HUBPREQ_DEBUG_BASE_IDX 2 2638#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x0632 2639#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2640#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x0633 2641#define mmHUBP1_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2642 2643 2644// addressBlock: dce_dc_dcbubp1_dispdec_hubpreq_dispdec 2645// base address: 0x310 2646#define mmHUBPREQ1_DCSURF_SURFACE_PITCH 0x063f 2647#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_BASE_IDX 2 2648#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C 0x0640 2649#define mmHUBPREQ1_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2650#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0641 2651#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2652#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0642 2653#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2654#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0643 2655#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2656#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0644 2657#define mmHUBPREQ1_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2658#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0645 2659#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2660#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x0646 2661#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2662#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x0647 2663#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2664#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x0648 2665#define mmHUBPREQ1_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2666#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x0649 2667#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2668#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x064a 2669#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2670#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x064b 2671#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2672#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x064c 2673#define mmHUBPREQ1_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2674#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x064d 2675#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2676#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x064e 2677#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2678#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x064f 2679#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2680#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0650 2681#define mmHUBPREQ1_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2682#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL 0x0651 2683#define mmHUBPREQ1_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2684#define mmHUBPREQ1_DCSURF_FLIP_CONTROL 0x0652 2685#define mmHUBPREQ1_DCSURF_FLIP_CONTROL_BASE_IDX 2 2686#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2 0x0653 2687#define mmHUBPREQ1_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2688#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL 0x0654 2689#define mmHUBPREQ1_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 2690#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME 0x0655 2691#define mmHUBPREQ1_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 2692#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT 0x0656 2693#define mmHUBPREQ1_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2694#define mmHUBPREQ1_DCSURF_SURFACE_INUSE 0x0657 2695#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_BASE_IDX 2 2696#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH 0x0658 2697#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2698#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C 0x0659 2699#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2700#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C 0x065a 2701#define mmHUBPREQ1_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2702#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE 0x065b 2703#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2704#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x065c 2705#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2706#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C 0x065d 2707#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2708#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x065e 2709#define mmHUBPREQ1_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2710#define mmHUBPREQ1_DCN_EXPANSION_MODE 0x065f 2711#define mmHUBPREQ1_DCN_EXPANSION_MODE_BASE_IDX 2 2712#define mmHUBPREQ1_DCN_TTU_QOS_WM 0x0660 2713#define mmHUBPREQ1_DCN_TTU_QOS_WM_BASE_IDX 2 2714#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL 0x0661 2715#define mmHUBPREQ1_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 2716#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0 0x0662 2717#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 2718#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1 0x0663 2719#define mmHUBPREQ1_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 2720#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0 0x0664 2721#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 2722#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1 0x0665 2723#define mmHUBPREQ1_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 2724#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0 0x0666 2725#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 2726#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1 0x0667 2727#define mmHUBPREQ1_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 2728#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x0668 2729#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 2730#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x0669 2731#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 2732#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x066a 2733#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 2734#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x066b 2735#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 2736#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x066c 2737#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 2738#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x066d 2739#define mmHUBPREQ1_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 2740#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x066e 2741#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 2742#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x066f 2743#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 2744#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0670 2745#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 2746#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0671 2747#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 2748#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0672 2749#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 2750#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0673 2751#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 2752#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0674 2753#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 2754#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0675 2755#define mmHUBPREQ1_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 2756#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS 0x0676 2757#define mmHUBPREQ1_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 2758#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x0677 2759#define mmHUBPREQ1_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 2760#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL 0x0678 2761#define mmHUBPREQ1_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 2762#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL 0x0679 2763#define mmHUBPREQ1_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 2764#define mmHUBPREQ1_BLANK_OFFSET_0 0x067a 2765#define mmHUBPREQ1_BLANK_OFFSET_0_BASE_IDX 2 2766#define mmHUBPREQ1_BLANK_OFFSET_1 0x067b 2767#define mmHUBPREQ1_BLANK_OFFSET_1_BASE_IDX 2 2768#define mmHUBPREQ1_DST_DIMENSIONS 0x067c 2769#define mmHUBPREQ1_DST_DIMENSIONS_BASE_IDX 2 2770#define mmHUBPREQ1_DST_AFTER_SCALER 0x067d 2771#define mmHUBPREQ1_DST_AFTER_SCALER_BASE_IDX 2 2772#define mmHUBPREQ1_PREFETCH_SETTINS 0x067e 2773#define mmHUBPREQ1_PREFETCH_SETTINS_BASE_IDX 2 2774#define mmHUBPREQ1_PREFETCH_SETTINS_C 0x067f 2775#define mmHUBPREQ1_PREFETCH_SETTINS_C_BASE_IDX 2 2776#define mmHUBPREQ1_VBLANK_PARAMETERS_0 0x0680 2777#define mmHUBPREQ1_VBLANK_PARAMETERS_0_BASE_IDX 2 2778#define mmHUBPREQ1_VBLANK_PARAMETERS_1 0x0681 2779#define mmHUBPREQ1_VBLANK_PARAMETERS_1_BASE_IDX 2 2780#define mmHUBPREQ1_VBLANK_PARAMETERS_2 0x0682 2781#define mmHUBPREQ1_VBLANK_PARAMETERS_2_BASE_IDX 2 2782#define mmHUBPREQ1_VBLANK_PARAMETERS_3 0x0683 2783#define mmHUBPREQ1_VBLANK_PARAMETERS_3_BASE_IDX 2 2784#define mmHUBPREQ1_VBLANK_PARAMETERS_4 0x0684 2785#define mmHUBPREQ1_VBLANK_PARAMETERS_4_BASE_IDX 2 2786#define mmHUBPREQ1_NOM_PARAMETERS_0 0x0685 2787#define mmHUBPREQ1_NOM_PARAMETERS_0_BASE_IDX 2 2788#define mmHUBPREQ1_NOM_PARAMETERS_1 0x0686 2789#define mmHUBPREQ1_NOM_PARAMETERS_1_BASE_IDX 2 2790#define mmHUBPREQ1_NOM_PARAMETERS_2 0x0687 2791#define mmHUBPREQ1_NOM_PARAMETERS_2_BASE_IDX 2 2792#define mmHUBPREQ1_NOM_PARAMETERS_3 0x0688 2793#define mmHUBPREQ1_NOM_PARAMETERS_3_BASE_IDX 2 2794#define mmHUBPREQ1_NOM_PARAMETERS_4 0x0689 2795#define mmHUBPREQ1_NOM_PARAMETERS_4_BASE_IDX 2 2796#define mmHUBPREQ1_NOM_PARAMETERS_5 0x068a 2797#define mmHUBPREQ1_NOM_PARAMETERS_5_BASE_IDX 2 2798#define mmHUBPREQ1_NOM_PARAMETERS_6 0x068b 2799#define mmHUBPREQ1_NOM_PARAMETERS_6_BASE_IDX 2 2800#define mmHUBPREQ1_NOM_PARAMETERS_7 0x068c 2801#define mmHUBPREQ1_NOM_PARAMETERS_7_BASE_IDX 2 2802#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE 0x068d 2803#define mmHUBPREQ1_PER_LINE_DELIVERY_PRE_BASE_IDX 2 2804#define mmHUBPREQ1_PER_LINE_DELIVERY 0x068e 2805#define mmHUBPREQ1_PER_LINE_DELIVERY_BASE_IDX 2 2806#define mmHUBPREQ1_CURSOR_SETTINS 0x068f 2807#define mmHUBPREQ1_CURSOR_SETTINS_BASE_IDX 2 2808#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ 0x0690 2809#define mmHUBPREQ1_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 2810#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL 0x0691 2811#define mmHUBPREQ1_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 2812#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS 0x0692 2813#define mmHUBPREQ1_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 2814 2815 2816// addressBlock: dce_dc_dcbubp1_dispdec_hubpret_dispdec 2817// base address: 0x310 2818#define mmHUBPRET1_HUBPRET_CONTROL 0x06a4 2819#define mmHUBPRET1_HUBPRET_CONTROL_BASE_IDX 2 2820#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL 0x06a5 2821#define mmHUBPRET1_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 2822#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS 0x06a6 2823#define mmHUBPRET1_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 2824#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0 0x06a7 2825#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 2826#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1 0x06a8 2827#define mmHUBPRET1_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 2828#define mmHUBPRET1_HUBPRET_READ_LINE0 0x06a9 2829#define mmHUBPRET1_HUBPRET_READ_LINE0_BASE_IDX 2 2830#define mmHUBPRET1_HUBPRET_READ_LINE1 0x06aa 2831#define mmHUBPRET1_HUBPRET_READ_LINE1_BASE_IDX 2 2832#define mmHUBPRET1_HUBPRET_INTERRUPT 0x06ab 2833#define mmHUBPRET1_HUBPRET_INTERRUPT_BASE_IDX 2 2834#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE 0x06ac 2835#define mmHUBPRET1_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 2836#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS 0x06ad 2837#define mmHUBPRET1_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 2838 2839 2840// addressBlock: dce_dc_dcbubp1_dispdec_cursor_dispdec 2841// base address: 0x310 2842#define mmCURSOR1_CURSOR_CONTROL 0x06b0 2843#define mmCURSOR1_CURSOR_CONTROL_BASE_IDX 2 2844#define mmCURSOR1_CURSOR_SURFACE_ADDRESS 0x06b1 2845#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 2846#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH 0x06b2 2847#define mmCURSOR1_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2848#define mmCURSOR1_CURSOR_SIZE 0x06b3 2849#define mmCURSOR1_CURSOR_SIZE_BASE_IDX 2 2850#define mmCURSOR1_CURSOR_POSITION 0x06b4 2851#define mmCURSOR1_CURSOR_POSITION_BASE_IDX 2 2852#define mmCURSOR1_CURSOR_HOT_SPOT 0x06b5 2853#define mmCURSOR1_CURSOR_HOT_SPOT_BASE_IDX 2 2854#define mmCURSOR1_CURSOR_STEREO_CONTROL 0x06b6 2855#define mmCURSOR1_CURSOR_STEREO_CONTROL_BASE_IDX 2 2856#define mmCURSOR1_CURSOR_DST_OFFSET 0x06b7 2857#define mmCURSOR1_CURSOR_DST_OFFSET_BASE_IDX 2 2858#define mmCURSOR1_CURSOR_MEM_PWR_CTRL 0x06b8 2859#define mmCURSOR1_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 2860#define mmCURSOR1_CURSOR_MEM_PWR_STATUS 0x06b9 2861#define mmCURSOR1_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 2862 2863 2864// addressBlock: dce_dc_dcbubp1_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 2865// base address: 0x1b54 2866#define mmDC_PERFMON9_PERFCOUNTER_CNTL 0x06d5 2867#define mmDC_PERFMON9_PERFCOUNTER_CNTL_BASE_IDX 2 2868#define mmDC_PERFMON9_PERFCOUNTER_CNTL2 0x06d6 2869#define mmDC_PERFMON9_PERFCOUNTER_CNTL2_BASE_IDX 2 2870#define mmDC_PERFMON9_PERFCOUNTER_STATE 0x06d7 2871#define mmDC_PERFMON9_PERFCOUNTER_STATE_BASE_IDX 2 2872#define mmDC_PERFMON9_PERFMON_CNTL 0x06d8 2873#define mmDC_PERFMON9_PERFMON_CNTL_BASE_IDX 2 2874#define mmDC_PERFMON9_PERFMON_CNTL2 0x06d9 2875#define mmDC_PERFMON9_PERFMON_CNTL2_BASE_IDX 2 2876#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC 0x06da 2877#define mmDC_PERFMON9_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 2878#define mmDC_PERFMON9_PERFMON_CVALUE_LOW 0x06db 2879#define mmDC_PERFMON9_PERFMON_CVALUE_LOW_BASE_IDX 2 2880#define mmDC_PERFMON9_PERFMON_HI 0x06dc 2881#define mmDC_PERFMON9_PERFMON_HI_BASE_IDX 2 2882#define mmDC_PERFMON9_PERFMON_LOW 0x06dd 2883#define mmDC_PERFMON9_PERFMON_LOW_BASE_IDX 2 2884 2885 2886// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dispdec 2887// base address: 0x620 2888#define mmHUBP2_DCSURF_SURFACE_CONFIG 0x06e1 2889#define mmHUBP2_DCSURF_SURFACE_CONFIG_BASE_IDX 2 2890#define mmHUBP2_DCSURF_ADDR_CONFIG 0x06e2 2891#define mmHUBP2_DCSURF_ADDR_CONFIG_BASE_IDX 2 2892#define mmHUBP2_DCSURF_TILING_CONFIG 0x06e3 2893#define mmHUBP2_DCSURF_TILING_CONFIG_BASE_IDX 2 2894#define mmHUBP2_DCSURF_PRI_VIEWPORT_START 0x06e4 2895#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 2896#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION 0x06e5 2897#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 2898#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C 0x06e6 2899#define mmHUBP2_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 2900#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x06e7 2901#define mmHUBP2_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 2902#define mmHUBP2_DCSURF_SEC_VIEWPORT_START 0x06e8 2903#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 2904#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION 0x06e9 2905#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 2906#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C 0x06ea 2907#define mmHUBP2_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 2908#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x06eb 2909#define mmHUBP2_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 2910#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG 0x06ec 2911#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 2912#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C 0x06ed 2913#define mmHUBP2_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 2914#define mmHUBP2_DCHUBP_CNTL 0x06ee 2915#define mmHUBP2_DCHUBP_CNTL_BASE_IDX 2 2916#define mmHUBP2_HUBP_CLK_CNTL 0x06ef 2917#define mmHUBP2_HUBP_CLK_CNTL_BASE_IDX 2 2918#define mmHUBP2_DCHUBP_VMPG_CONFIG 0x06f0 2919#define mmHUBP2_DCHUBP_VMPG_CONFIG_BASE_IDX 2 2920#define mmHUBP2_HUBPREQ_DEBUG_DB 0x06f1 2921#define mmHUBP2_HUBPREQ_DEBUG_DB_BASE_IDX 2 2922#define mmHUBP2_HUBPREQ_DEBUG 0x06f2 2923#define mmHUBP2_HUBPREQ_DEBUG_BASE_IDX 2 2924#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x06f6 2925#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 2926#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x06f7 2927#define mmHUBP2_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 2928 2929 2930// addressBlock: dce_dc_dcbubp2_dispdec_hubpreq_dispdec 2931// base address: 0x620 2932#define mmHUBPREQ2_DCSURF_SURFACE_PITCH 0x0703 2933#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_BASE_IDX 2 2934#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C 0x0704 2935#define mmHUBPREQ2_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 2936#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS 0x0705 2937#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 2938#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x0706 2939#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2940#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x0707 2941#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 2942#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x0708 2943#define mmHUBPREQ2_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2944#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS 0x0709 2945#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 2946#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x070a 2947#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2948#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x070b 2949#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 2950#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x070c 2951#define mmHUBPREQ2_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2952#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x070d 2953#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 2954#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x070e 2955#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2956#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x070f 2957#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2958#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x0710 2959#define mmHUBPREQ2_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2960#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x0711 2961#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 2962#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x0712 2963#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 2964#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x0713 2965#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 2966#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x0714 2967#define mmHUBPREQ2_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 2968#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL 0x0715 2969#define mmHUBPREQ2_DCSURF_SURFACE_CONTROL_BASE_IDX 2 2970#define mmHUBPREQ2_DCSURF_FLIP_CONTROL 0x0716 2971#define mmHUBPREQ2_DCSURF_FLIP_CONTROL_BASE_IDX 2 2972#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2 0x0717 2973#define mmHUBPREQ2_DCSURF_FLIP_CONTROL2_BASE_IDX 2 2974#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL 0x0718 2975#define mmHUBPREQ2_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 2976#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME 0x0719 2977#define mmHUBPREQ2_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 2978#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT 0x071a 2979#define mmHUBPREQ2_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 2980#define mmHUBPREQ2_DCSURF_SURFACE_INUSE 0x071b 2981#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_BASE_IDX 2 2982#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH 0x071c 2983#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 2984#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C 0x071d 2985#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 2986#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C 0x071e 2987#define mmHUBPREQ2_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 2988#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE 0x071f 2989#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 2990#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x0720 2991#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 2992#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C 0x0721 2993#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 2994#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x0722 2995#define mmHUBPREQ2_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 2996#define mmHUBPREQ2_DCN_EXPANSION_MODE 0x0723 2997#define mmHUBPREQ2_DCN_EXPANSION_MODE_BASE_IDX 2 2998#define mmHUBPREQ2_DCN_TTU_QOS_WM 0x0724 2999#define mmHUBPREQ2_DCN_TTU_QOS_WM_BASE_IDX 2 3000#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL 0x0725
3001#define mmHUBPREQ2_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3002#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0 0x0726 3003#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3004#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1 0x0727 3005#define mmHUBPREQ2_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3006#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0 0x0728 3007#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3008#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1 0x0729 3009#define mmHUBPREQ2_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3010#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0 0x072a 3011#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3012#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1 0x072b 3013#define mmHUBPREQ2_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3014#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x072c 3015#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 3016#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x072d 3017#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 3018#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x072e 3019#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 3020#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x072f 3021#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 3022#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x0730 3023#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 3024#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x0731 3025#define mmHUBPREQ2_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 3026#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x0732 3027#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 3028#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x0733 3029#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 3030#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x0734 3031#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 3032#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x0735 3033#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 3034#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x0736 3035#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 3036#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x0737 3037#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 3038#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x0738 3039#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 3040#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x0739 3041#define mmHUBPREQ2_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 3042#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS 0x073a 3043#define mmHUBPREQ2_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 3044#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x073b 3045#define mmHUBPREQ2_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 3046#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL 0x073c 3047#define mmHUBPREQ2_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 3048#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL 0x073d 3049#define mmHUBPREQ2_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3050#define mmHUBPREQ2_BLANK_OFFSET_0 0x073e 3051#define mmHUBPREQ2_BLANK_OFFSET_0_BASE_IDX 2 3052#define mmHUBPREQ2_BLANK_OFFSET_1 0x073f 3053#define mmHUBPREQ2_BLANK_OFFSET_1_BASE_IDX 2 3054#define mmHUBPREQ2_DST_DIMENSIONS 0x0740 3055#define mmHUBPREQ2_DST_DIMENSIONS_BASE_IDX 2 3056#define mmHUBPREQ2_DST_AFTER_SCALER 0x0741 3057#define mmHUBPREQ2_DST_AFTER_SCALER_BASE_IDX 2 3058#define mmHUBPREQ2_PREFETCH_SETTINS 0x0742 3059#define mmHUBPREQ2_PREFETCH_SETTINS_BASE_IDX 2 3060#define mmHUBPREQ2_PREFETCH_SETTINS_C 0x0743 3061#define mmHUBPREQ2_PREFETCH_SETTINS_C_BASE_IDX 2 3062#define mmHUBPREQ2_VBLANK_PARAMETERS_0 0x0744 3063#define mmHUBPREQ2_VBLANK_PARAMETERS_0_BASE_IDX 2 3064#define mmHUBPREQ2_VBLANK_PARAMETERS_1 0x0745 3065#define mmHUBPREQ2_VBLANK_PARAMETERS_1_BASE_IDX 2 3066#define mmHUBPREQ2_VBLANK_PARAMETERS_2 0x0746 3067#define mmHUBPREQ2_VBLANK_PARAMETERS_2_BASE_IDX 2 3068#define mmHUBPREQ2_VBLANK_PARAMETERS_3 0x0747 3069#define mmHUBPREQ2_VBLANK_PARAMETERS_3_BASE_IDX 2 3070#define mmHUBPREQ2_VBLANK_PARAMETERS_4 0x0748 3071#define mmHUBPREQ2_VBLANK_PARAMETERS_4_BASE_IDX 2 3072#define mmHUBPREQ2_NOM_PARAMETERS_0 0x0749 3073#define mmHUBPREQ2_NOM_PARAMETERS_0_BASE_IDX 2 3074#define mmHUBPREQ2_NOM_PARAMETERS_1 0x074a 3075#define mmHUBPREQ2_NOM_PARAMETERS_1_BASE_IDX 2 3076#define mmHUBPREQ2_NOM_PARAMETERS_2 0x074b 3077#define mmHUBPREQ2_NOM_PARAMETERS_2_BASE_IDX 2 3078#define mmHUBPREQ2_NOM_PARAMETERS_3 0x074c 3079#define mmHUBPREQ2_NOM_PARAMETERS_3_BASE_IDX 2 3080#define mmHUBPREQ2_NOM_PARAMETERS_4 0x074d 3081#define mmHUBPREQ2_NOM_PARAMETERS_4_BASE_IDX 2 3082#define mmHUBPREQ2_NOM_PARAMETERS_5 0x074e 3083#define mmHUBPREQ2_NOM_PARAMETERS_5_BASE_IDX 2 3084#define mmHUBPREQ2_NOM_PARAMETERS_6 0x074f 3085#define mmHUBPREQ2_NOM_PARAMETERS_6_BASE_IDX 2 3086#define mmHUBPREQ2_NOM_PARAMETERS_7 0x0750 3087#define mmHUBPREQ2_NOM_PARAMETERS_7_BASE_IDX 2 3088#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE 0x0751 3089#define mmHUBPREQ2_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3090#define mmHUBPREQ2_PER_LINE_DELIVERY 0x0752 3091#define mmHUBPREQ2_PER_LINE_DELIVERY_BASE_IDX 2 3092#define mmHUBPREQ2_CURSOR_SETTINS 0x0753 3093#define mmHUBPREQ2_CURSOR_SETTINS_BASE_IDX 2 3094#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ 0x0754 3095#define mmHUBPREQ2_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3096#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL 0x0755 3097#define mmHUBPREQ2_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3098#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS 0x0756 3099#define mmHUBPREQ2_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3100 3101 3102// addressBlock: dce_dc_dcbubp2_dispdec_hubpret_dispdec 3103// base address: 0x620 3104#define mmHUBPRET2_HUBPRET_CONTROL 0x0768 3105#define mmHUBPRET2_HUBPRET_CONTROL_BASE_IDX 2 3106#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL 0x0769 3107#define mmHUBPRET2_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3108#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS 0x076a 3109#define mmHUBPRET2_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3110#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0 0x076b 3111#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3112#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1 0x076c 3113#define mmHUBPRET2_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3114#define mmHUBPRET2_HUBPRET_READ_LINE0 0x076d 3115#define mmHUBPRET2_HUBPRET_READ_LINE0_BASE_IDX 2 3116#define mmHUBPRET2_HUBPRET_READ_LINE1 0x076e 3117#define mmHUBPRET2_HUBPRET_READ_LINE1_BASE_IDX 2 3118#define mmHUBPRET2_HUBPRET_INTERRUPT 0x076f 3119#define mmHUBPRET2_HUBPRET_INTERRUPT_BASE_IDX 2 3120#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE 0x0770 3121#define mmHUBPRET2_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3122#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS 0x0771 3123#define mmHUBPRET2_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3124 3125 3126// addressBlock: dce_dc_dcbubp2_dispdec_cursor_dispdec 3127// base address: 0x620 3128#define mmCURSOR2_CURSOR_CONTROL 0x0774 3129#define mmCURSOR2_CURSOR_CONTROL_BASE_IDX 2 3130#define mmCURSOR2_CURSOR_SURFACE_ADDRESS 0x0775 3131#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3132#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH 0x0776 3133#define mmCURSOR2_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3134#define mmCURSOR2_CURSOR_SIZE 0x0777 3135#define mmCURSOR2_CURSOR_SIZE_BASE_IDX 2 3136#define mmCURSOR2_CURSOR_POSITION 0x0778 3137#define mmCURSOR2_CURSOR_POSITION_BASE_IDX 2 3138#define mmCURSOR2_CURSOR_HOT_SPOT 0x0779 3139#define mmCURSOR2_CURSOR_HOT_SPOT_BASE_IDX 2 3140#define mmCURSOR2_CURSOR_STEREO_CONTROL 0x077a 3141#define mmCURSOR2_CURSOR_STEREO_CONTROL_BASE_IDX 2 3142#define mmCURSOR2_CURSOR_DST_OFFSET 0x077b 3143#define mmCURSOR2_CURSOR_DST_OFFSET_BASE_IDX 2 3144#define mmCURSOR2_CURSOR_MEM_PWR_CTRL 0x077c 3145#define mmCURSOR2_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3146#define mmCURSOR2_CURSOR_MEM_PWR_STATUS 0x077d 3147#define mmCURSOR2_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3148 3149 3150// addressBlock: dce_dc_dcbubp2_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3151// base address: 0x1e64 3152#define mmDC_PERFMON10_PERFCOUNTER_CNTL 0x0799 3153#define mmDC_PERFMON10_PERFCOUNTER_CNTL_BASE_IDX 2 3154#define mmDC_PERFMON10_PERFCOUNTER_CNTL2 0x079a 3155#define mmDC_PERFMON10_PERFCOUNTER_CNTL2_BASE_IDX 2 3156#define mmDC_PERFMON10_PERFCOUNTER_STATE 0x079b 3157#define mmDC_PERFMON10_PERFCOUNTER_STATE_BASE_IDX 2 3158#define mmDC_PERFMON10_PERFMON_CNTL 0x079c 3159#define mmDC_PERFMON10_PERFMON_CNTL_BASE_IDX 2 3160#define mmDC_PERFMON10_PERFMON_CNTL2 0x079d 3161#define mmDC_PERFMON10_PERFMON_CNTL2_BASE_IDX 2 3162#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC 0x079e 3163#define mmDC_PERFMON10_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3164#define mmDC_PERFMON10_PERFMON_CVALUE_LOW 0x079f 3165#define mmDC_PERFMON10_PERFMON_CVALUE_LOW_BASE_IDX 2 3166#define mmDC_PERFMON10_PERFMON_HI 0x07a0 3167#define mmDC_PERFMON10_PERFMON_HI_BASE_IDX 2 3168#define mmDC_PERFMON10_PERFMON_LOW 0x07a1 3169#define mmDC_PERFMON10_PERFMON_LOW_BASE_IDX 2 3170 3171 3172// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dispdec 3173// base address: 0x930 3174#define mmHUBP3_DCSURF_SURFACE_CONFIG 0x07a5 3175#define mmHUBP3_DCSURF_SURFACE_CONFIG_BASE_IDX 2 3176#define mmHUBP3_DCSURF_ADDR_CONFIG 0x07a6 3177#define mmHUBP3_DCSURF_ADDR_CONFIG_BASE_IDX 2 3178#define mmHUBP3_DCSURF_TILING_CONFIG 0x07a7 3179#define mmHUBP3_DCSURF_TILING_CONFIG_BASE_IDX 2 3180#define mmHUBP3_DCSURF_PRI_VIEWPORT_START 0x07a8 3181#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_BASE_IDX 2 3182#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION 0x07a9 3183#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2 3184#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C 0x07aa 3185#define mmHUBP3_DCSURF_PRI_VIEWPORT_START_C_BASE_IDX 2 3186#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C 0x07ab 3187#define mmHUBP3_DCSURF_PRI_VIEWPORT_DIMENSION_C_BASE_IDX 2 3188#define mmHUBP3_DCSURF_SEC_VIEWPORT_START 0x07ac 3189#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_BASE_IDX 2 3190#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION 0x07ad 3191#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_BASE_IDX 2 3192#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C 0x07ae 3193#define mmHUBP3_DCSURF_SEC_VIEWPORT_START_C_BASE_IDX 2 3194#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C 0x07af 3195#define mmHUBP3_DCSURF_SEC_VIEWPORT_DIMENSION_C_BASE_IDX 2 3196#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG 0x07b0 3197#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_BASE_IDX 2 3198#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C 0x07b1 3199#define mmHUBP3_DCHUBP_REQ_SIZE_CONFIG_C_BASE_IDX 2 3200#define mmHUBP3_DCHUBP_CNTL 0x07b2 3201#define mmHUBP3_DCHUBP_CNTL_BASE_IDX 2 3202#define mmHUBP3_HUBP_CLK_CNTL 0x07b3 3203#define mmHUBP3_HUBP_CLK_CNTL_BASE_IDX 2 3204#define mmHUBP3_DCHUBP_VMPG_CONFIG 0x07b4 3205#define mmHUBP3_DCHUBP_VMPG_CONFIG_BASE_IDX 2 3206#define mmHUBP3_HUBPREQ_DEBUG_DB 0x07b5 3207#define mmHUBP3_HUBPREQ_DEBUG_DB_BASE_IDX 2 3208#define mmHUBP3_HUBPREQ_DEBUG 0x07b6 3209#define mmHUBP3_HUBPREQ_DEBUG_BASE_IDX 2 3210#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK 0x07ba 3211#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DCFCLK_BASE_IDX 2 3212#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK 0x07bb 3213#define mmHUBP3_HUBP_MEASURE_WIN_CTRL_DPPCLK_BASE_IDX 2 3214 3215 3216// addressBlock: dce_dc_dcbubp3_dispdec_hubpreq_dispdec 3217// base address: 0x930 3218#define mmHUBPREQ3_DCSURF_SURFACE_PITCH 0x07c7 3219#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_BASE_IDX 2 3220#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C 0x07c8 3221#define mmHUBPREQ3_DCSURF_SURFACE_PITCH_C_BASE_IDX 2 3222#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS 0x07c9 3223#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_BASE_IDX 2 3224#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH 0x07ca 3225#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3226#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C 0x07cb 3227#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_C_BASE_IDX 2 3228#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C 0x07cc 3229#define mmHUBPREQ3_DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3230#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS 0x07cd 3231#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_BASE_IDX 2 3232#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH 0x07ce 3233#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3234#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C 0x07cf 3235#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_C_BASE_IDX 2 3236#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C 0x07d0 3237#define mmHUBPREQ3_DCSURF_SECONDARY_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3238#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS 0x07d1 3239#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_BASE_IDX 2 3240#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH 0x07d2 3241#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3242#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C 0x07d3 3243#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3244#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C 0x07d4 3245#define mmHUBPREQ3_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3246#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS 0x07d5 3247#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_BASE_IDX 2 3248#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH 0x07d6 3249#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3250#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C 0x07d7 3251#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_C_BASE_IDX 2 3252#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C 0x07d8 3253#define mmHUBPREQ3_DCSURF_SECONDARY_META_SURFACE_ADDRESS_HIGH_C_BASE_IDX 2 3254#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL 0x07d9 3255#define mmHUBPREQ3_DCSURF_SURFACE_CONTROL_BASE_IDX 2 3256#define mmHUBPREQ3_DCSURF_FLIP_CONTROL 0x07da 3257#define mmHUBPREQ3_DCSURF_FLIP_CONTROL_BASE_IDX 2 3258#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2 0x07db 3259#define mmHUBPREQ3_DCSURF_FLIP_CONTROL2_BASE_IDX 2 3260#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL 0x07dc 3261#define mmHUBPREQ3_DCSURF_FRAME_PACING_CONTROL_BASE_IDX 2 3262#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME 0x07dd 3263#define mmHUBPREQ3_DCSURF_FRAME_PACING_TIME_BASE_IDX 2 3264#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT 0x07de 3265#define mmHUBPREQ3_DCSURF_SURFACE_FLIP_INTERRUPT_BASE_IDX 2 3266#define mmHUBPREQ3_DCSURF_SURFACE_INUSE 0x07df 3267#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_BASE_IDX 2 3268#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH 0x07e0 3269#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_BASE_IDX 2 3270#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C 0x07e1 3271#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_C_BASE_IDX 2 3272#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C 0x07e2 3273#define mmHUBPREQ3_DCSURF_SURFACE_INUSE_HIGH_C_BASE_IDX 2 3274#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE 0x07e3 3275#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_BASE_IDX 2 3276#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH 0x07e4 3277#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_BASE_IDX 2 3278#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C 0x07e5 3279#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_C_BASE_IDX 2 3280#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C 0x07e6 3281#define mmHUBPREQ3_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C_BASE_IDX 2 3282#define mmHUBPREQ3_DCN_EXPANSION_MODE 0x07e7 3283#define mmHUBPREQ3_DCN_EXPANSION_MODE_BASE_IDX 2 3284#define mmHUBPREQ3_DCN_TTU_QOS_WM 0x07e8 3285#define mmHUBPREQ3_DCN_TTU_QOS_WM_BASE_IDX 2 3286#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL 0x07e9 3287#define mmHUBPREQ3_DCN_GLOBAL_TTU_CNTL_BASE_IDX 2 3288#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0 0x07ea 3289#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL0_BASE_IDX 2 3290#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1 0x07eb 3291#define mmHUBPREQ3_DCN_SURF0_TTU_CNTL1_BASE_IDX 2 3292#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0 0x07ec 3293#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL0_BASE_IDX 2 3294#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1 0x07ed 3295#define mmHUBPREQ3_DCN_SURF1_TTU_CNTL1_BASE_IDX 2 3296#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0 0x07ee 3297#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL0_BASE_IDX 2 3298#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1 0x07ef 3299#define mmHUBPREQ3_DCN_CUR0_TTU_CNTL1_BASE_IDX 2 3300#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB 0x07f0 3301#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_LSB_BASE_IDX 2 3302#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB 0x07f1 3303#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_LOW_ADDR_MSB_BASE_IDX 2 3304#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB 0x07f2 3305#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_LSB_BASE_IDX 2 3306#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB 0x07f3 3307#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_HIGH_ADDR_MSB_BASE_IDX 2 3308#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 0x07f4 3309#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB_BASE_IDX 2 3310#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 0x07f5 3311#define mmHUBPREQ3_DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB_BASE_IDX 2 3312#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB 0x07f6 3313#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_LSB_BASE_IDX 2 3314#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB 0x07f7 3315#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR_MSB_BASE_IDX 2 3316#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB 0x07f8 3317#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LSB_BASE_IDX 2 3318#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB 0x07f9 3319#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_MSB_BASE_IDX 2 3320#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB 0x07fa 3321#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LSB_BASE_IDX 2 3322#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB 0x07fb 3323#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_START_ADDR_MSB_BASE_IDX 2 3324#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB 0x07fc 3325#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LSB_BASE_IDX 2 3326#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB 0x07fd 3327#define mmHUBPREQ3_DCN_VM_CONTEXT0_PAGE_TABLE_END_ADDR_MSB_BASE_IDX 2 3328#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS 0x07fe 3329#define mmHUBPREQ3_DCN_VM_CONTEXT0_STATUS_BASE_IDX 2 3330#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB 0x07ff 3331#define mmHUBPREQ3_DCN_VM_CONTEXT0_PROTECTION_FAULT_ADDR_LSB_BASE_IDX 2 3332#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL 0x0800 3333#define mmHUBPREQ3_DCN_VM_CONTEXT0_CNTL_BASE_IDX 2 3334#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL 0x0801 3335#define mmHUBPREQ3_DCN_VM_MX_L1_TLB_CNTL_BASE_IDX 2 3336#define mmHUBPREQ3_BLANK_OFFSET_0 0x0802 3337#define mmHUBPREQ3_BLANK_OFFSET_0_BASE_IDX 2 3338#define mmHUBPREQ3_BLANK_OFFSET_1 0x0803 3339#define mmHUBPREQ3_BLANK_OFFSET_1_BASE_IDX 2 3340#define mmHUBPREQ3_DST_DIMENSIONS 0x0804 3341#define mmHUBPREQ3_DST_DIMENSIONS_BASE_IDX 2 3342#define mmHUBPREQ3_DST_AFTER_SCALER 0x0805 3343#define mmHUBPREQ3_DST_AFTER_SCALER_BASE_IDX 2 3344#define mmHUBPREQ3_PREFETCH_SETTINS 0x0806 3345#define mmHUBPREQ3_PREFETCH_SETTINS_BASE_IDX 2 3346#define mmHUBPREQ3_PREFETCH_SETTINS_C 0x0807 3347#define mmHUBPREQ3_PREFETCH_SETTINS_C_BASE_IDX 2 3348#define mmHUBPREQ3_VBLANK_PARAMETERS_0 0x0808 3349#define mmHUBPREQ3_VBLANK_PARAMETERS_0_BASE_IDX 2 3350#define mmHUBPREQ3_VBLANK_PARAMETERS_1 0x0809 3351#define mmHUBPREQ3_VBLANK_PARAMETERS_1_BASE_IDX 2 3352#define mmHUBPREQ3_VBLANK_PARAMETERS_2 0x080a 3353#define mmHUBPREQ3_VBLANK_PARAMETERS_2_BASE_IDX 2 3354#define mmHUBPREQ3_VBLANK_PARAMETERS_3 0x080b 3355#define mmHUBPREQ3_VBLANK_PARAMETERS_3_BASE_IDX 2 3356#define mmHUBPREQ3_VBLANK_PARAMETERS_4 0x080c 3357#define mmHUBPREQ3_VBLANK_PARAMETERS_4_BASE_IDX 2 3358#define mmHUBPREQ3_NOM_PARAMETERS_0 0x080d 3359#define mmHUBPREQ3_NOM_PARAMETERS_0_BASE_IDX 2 3360#define mmHUBPREQ3_NOM_PARAMETERS_1 0x080e 3361#define mmHUBPREQ3_NOM_PARAMETERS_1_BASE_IDX 2 3362#define mmHUBPREQ3_NOM_PARAMETERS_2 0x080f 3363#define mmHUBPREQ3_NOM_PARAMETERS_2_BASE_IDX 2 3364#define mmHUBPREQ3_NOM_PARAMETERS_3 0x0810 3365#define mmHUBPREQ3_NOM_PARAMETERS_3_BASE_IDX 2 3366#define mmHUBPREQ3_NOM_PARAMETERS_4 0x0811 3367#define mmHUBPREQ3_NOM_PARAMETERS_4_BASE_IDX 2 3368#define mmHUBPREQ3_NOM_PARAMETERS_5 0x0812 3369#define mmHUBPREQ3_NOM_PARAMETERS_5_BASE_IDX 2 3370#define mmHUBPREQ3_NOM_PARAMETERS_6 0x0813 3371#define mmHUBPREQ3_NOM_PARAMETERS_6_BASE_IDX 2 3372#define mmHUBPREQ3_NOM_PARAMETERS_7 0x0814 3373#define mmHUBPREQ3_NOM_PARAMETERS_7_BASE_IDX 2 3374#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE 0x0815 3375#define mmHUBPREQ3_PER_LINE_DELIVERY_PRE_BASE_IDX 2 3376#define mmHUBPREQ3_PER_LINE_DELIVERY 0x0816 3377#define mmHUBPREQ3_PER_LINE_DELIVERY_BASE_IDX 2 3378#define mmHUBPREQ3_CURSOR_SETTINS 0x0817 3379#define mmHUBPREQ3_CURSOR_SETTINS_BASE_IDX 2 3380#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ 0x0818 3381#define mmHUBPREQ3_REF_FREQ_TO_PIX_FREQ_BASE_IDX 2 3382#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL 0x0819 3383#define mmHUBPREQ3_HUBPREQ_MEM_PWR_CTRL_BASE_IDX 2 3384#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS 0x081a 3385#define mmHUBPREQ3_HUBPREQ_MEM_PWR_STATUS_BASE_IDX 2 3386 3387 3388// addressBlock: dce_dc_dcbubp3_dispdec_hubpret_dispdec 3389// base address: 0x930 3390#define mmHUBPRET3_HUBPRET_CONTROL 0x082c 3391#define mmHUBPRET3_HUBPRET_CONTROL_BASE_IDX 2 3392#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL 0x082d 3393#define mmHUBPRET3_HUBPRET_MEM_PWR_CTRL_BASE_IDX 2 3394#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS 0x082e 3395#define mmHUBPRET3_HUBPRET_MEM_PWR_STATUS_BASE_IDX 2 3396#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0 0x082f 3397#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL0_BASE_IDX 2 3398#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1 0x0830 3399#define mmHUBPRET3_HUBPRET_READ_LINE_CTRL1_BASE_IDX 2 3400#define mmHUBPRET3_HUBPRET_READ_LINE0 0x0831 3401#define mmHUBPRET3_HUBPRET_READ_LINE0_BASE_IDX 2 3402#define mmHUBPRET3_HUBPRET_READ_LINE1 0x0832 3403#define mmHUBPRET3_HUBPRET_READ_LINE1_BASE_IDX 2 3404#define mmHUBPRET3_HUBPRET_INTERRUPT 0x0833 3405#define mmHUBPRET3_HUBPRET_INTERRUPT_BASE_IDX 2 3406#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE 0x0834 3407#define mmHUBPRET3_HUBPRET_READ_LINE_VALUE_BASE_IDX 2 3408#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS 0x0835 3409#define mmHUBPRET3_HUBPRET_READ_LINE_STATUS_BASE_IDX 2 3410 3411 3412// addressBlock: dce_dc_dcbubp3_dispdec_cursor_dispdec 3413// base address: 0x930 3414#define mmCURSOR3_CURSOR_CONTROL 0x0838 3415#define mmCURSOR3_CURSOR_CONTROL_BASE_IDX 2 3416#define mmCURSOR3_CURSOR_SURFACE_ADDRESS 0x0839 3417#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_BASE_IDX 2 3418#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH 0x083a 3419#define mmCURSOR3_CURSOR_SURFACE_ADDRESS_HIGH_BASE_IDX 2 3420#define mmCURSOR3_CURSOR_SIZE 0x083b 3421#define mmCURSOR3_CURSOR_SIZE_BASE_IDX 2 3422#define mmCURSOR3_CURSOR_POSITION 0x083c 3423#define mmCURSOR3_CURSOR_POSITION_BASE_IDX 2 3424#define mmCURSOR3_CURSOR_HOT_SPOT 0x083d 3425#define mmCURSOR3_CURSOR_HOT_SPOT_BASE_IDX 2 3426#define mmCURSOR3_CURSOR_STEREO_CONTROL 0x083e 3427#define mmCURSOR3_CURSOR_STEREO_CONTROL_BASE_IDX 2 3428#define mmCURSOR3_CURSOR_DST_OFFSET 0x083f 3429#define mmCURSOR3_CURSOR_DST_OFFSET_BASE_IDX 2 3430#define mmCURSOR3_CURSOR_MEM_PWR_CTRL 0x0840 3431#define mmCURSOR3_CURSOR_MEM_PWR_CTRL_BASE_IDX 2 3432#define mmCURSOR3_CURSOR_MEM_PWR_STATUS 0x0841 3433#define mmCURSOR3_CURSOR_MEM_PWR_STATUS_BASE_IDX 2 3434 3435 3436// addressBlock: dce_dc_dcbubp3_dispdec_hubp_dcperfmon_dc_perfmon_dispdec 3437// base address: 0x2174 3438#define mmDC_PERFMON11_PERFCOUNTER_CNTL 0x085d 3439#define mmDC_PERFMON11_PERFCOUNTER_CNTL_BASE_IDX 2 3440#define mmDC_PERFMON11_PERFCOUNTER_CNTL2 0x085e 3441#define mmDC_PERFMON11_PERFCOUNTER_CNTL2_BASE_IDX 2 3442#define mmDC_PERFMON11_PERFCOUNTER_STATE 0x085f 3443#define mmDC_PERFMON11_PERFCOUNTER_STATE_BASE_IDX 2 3444#define mmDC_PERFMON11_PERFMON_CNTL 0x0860 3445#define mmDC_PERFMON11_PERFMON_CNTL_BASE_IDX 2 3446#define mmDC_PERFMON11_PERFMON_CNTL2 0x0861 3447#define mmDC_PERFMON11_PERFMON_CNTL2_BASE_IDX 2 3448#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC 0x0862 3449#define mmDC_PERFMON11_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3450#define mmDC_PERFMON11_PERFMON_CVALUE_LOW 0x0863 3451#define mmDC_PERFMON11_PERFMON_CVALUE_LOW_BASE_IDX 2 3452#define mmDC_PERFMON11_PERFMON_HI 0x0864 3453#define mmDC_PERFMON11_PERFMON_HI_BASE_IDX 2 3454#define mmDC_PERFMON11_PERFMON_LOW 0x0865 3455#define mmDC_PERFMON11_PERFMON_LOW_BASE_IDX 2 3456 3457 3458// addressBlock: dce_dc_dpp0_dispdec_dpp_top_dispdec 3459// base address: 0x0 3460#define mmDPP_TOP0_DPP_CONTROL 0x0c3d 3461#define mmDPP_TOP0_DPP_CONTROL_BASE_IDX 2 3462#define mmDPP_TOP0_DPP_SOFT_RESET 0x0c3e 3463#define mmDPP_TOP0_DPP_SOFT_RESET_BASE_IDX 2 3464#define mmDPP_TOP0_DPP_CRC_VAL_R_G 0x0c3f 3465#define mmDPP_TOP0_DPP_CRC_VAL_R_G_BASE_IDX 2 3466#define mmDPP_TOP0_DPP_CRC_VAL_B_A 0x0c40 3467#define mmDPP_TOP0_DPP_CRC_VAL_B_A_BASE_IDX 2 3468#define mmDPP_TOP0_DPP_CRC_CTRL 0x0c41 3469#define mmDPP_TOP0_DPP_CRC_CTRL_BASE_IDX 2 3470#define mmDPP_TOP0_HOST_READ_CONTROL 0x0c42 3471#define mmDPP_TOP0_HOST_READ_CONTROL_BASE_IDX 2 3472 3473 3474// addressBlock: dce_dc_dpp0_dispdec_cnvc_cfg_dispdec 3475// base address: 0x0 3476#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT 0x0c47 3477#define mmCNVC_CFG0_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3478#define mmCNVC_CFG0_FORMAT_CONTROL 0x0c48 3479#define mmCNVC_CFG0_FORMAT_CONTROL_BASE_IDX 2 3480#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS 0x0c49 3481#define mmCNVC_CFG0_FCNV_FP_SCALE_BIAS_BASE_IDX 2 3482#define mmCNVC_CFG0_DENORM_CONTROL 0x0c4a 3483#define mmCNVC_CFG0_DENORM_CONTROL_BASE_IDX 2 3484#define mmCNVC_CFG0_COLOR_KEYER_CONTROL 0x0c4c 3485#define mmCNVC_CFG0_COLOR_KEYER_CONTROL_BASE_IDX 2 3486#define mmCNVC_CFG0_COLOR_KEYER_ALPHA 0x0c4d 3487#define mmCNVC_CFG0_COLOR_KEYER_ALPHA_BASE_IDX 2 3488#define mmCNVC_CFG0_COLOR_KEYER_RED 0x0c4e 3489#define mmCNVC_CFG0_COLOR_KEYER_RED_BASE_IDX 2 3490#define mmCNVC_CFG0_COLOR_KEYER_GREEN 0x0c4f 3491#define mmCNVC_CFG0_COLOR_KEYER_GREEN_BASE_IDX 2 3492#define mmCNVC_CFG0_COLOR_KEYER_BLUE 0x0c50 3493#define mmCNVC_CFG0_COLOR_KEYER_BLUE_BASE_IDX 2 3494 3495 3496// addressBlock: dce_dc_dpp0_dispdec_cnvc_cur_dispdec 3497// base address: 0x0 3498#define mmCNVC_CUR0_CURSOR0_CONTROL 0x0c58 3499#define mmCNVC_CUR0_CURSOR0_CONTROL_BASE_IDX 2 3500#define mmCNVC_CUR0_CURSOR0_COLOR0 0x0c59 3501#define mmCNVC_CUR0_CURSOR0_COLOR0_BASE_IDX 2 3502#define mmCNVC_CUR0_CURSOR0_COLOR1 0x0c5a 3503#define mmCNVC_CUR0_CURSOR0_COLOR1_BASE_IDX 2 3504#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS 0x0c5b 3505#define mmCNVC_CUR0_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3506 3507 3508// addressBlock: dce_dc_dpp0_dispdec_dscl_dispdec 3509// base address: 0x0 3510#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT 0x0c62 3511#define mmDSCL0_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3512#define mmDSCL0_SCL_COEF_RAM_TAP_DATA 0x0c63 3513#define mmDSCL0_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3514#define mmDSCL0_SCL_MODE 0x0c64 3515#define mmDSCL0_SCL_MODE_BASE_IDX 2 3516#define mmDSCL0_SCL_TAP_CONTROL 0x0c65 3517#define mmDSCL0_SCL_TAP_CONTROL_BASE_IDX 2 3518#define mmDSCL0_DSCL_CONTROL 0x0c66 3519#define mmDSCL0_DSCL_CONTROL_BASE_IDX 2 3520#define mmDSCL0_DSCL_2TAP_CONTROL 0x0c67 3521#define mmDSCL0_DSCL_2TAP_CONTROL_BASE_IDX 2 3522#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL 0x0c68 3523#define mmDSCL0_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 3524#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO 0x0c69 3525#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 3526#define mmDSCL0_SCL_HORZ_FILTER_INIT 0x0c6a 3527#define mmDSCL0_SCL_HORZ_FILTER_INIT_BASE_IDX 2 3528#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0c6b 3529#define mmDSCL0_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 3530#define mmDSCL0_SCL_HORZ_FILTER_INIT_C 0x0c6c 3531#define mmDSCL0_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 3532#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO 0x0c6d 3533#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 3534#define mmDSCL0_SCL_VERT_FILTER_INIT 0x0c6e 3535#define mmDSCL0_SCL_VERT_FILTER_INIT_BASE_IDX 2 3536#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT 0x0c6f 3537#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 3538#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C 0x0c70 3539#define mmDSCL0_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 3540#define mmDSCL0_SCL_VERT_FILTER_INIT_C 0x0c71 3541#define mmDSCL0_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 3542#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C 0x0c72 3543#define mmDSCL0_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 3544#define mmDSCL0_SCL_BLACK_OFFSET 0x0c73 3545#define mmDSCL0_SCL_BLACK_OFFSET_BASE_IDX 2 3546#define mmDSCL0_DSCL_UPDATE 0x0c74 3547#define mmDSCL0_DSCL_UPDATE_BASE_IDX 2 3548#define mmDSCL0_DSCL_AUTOCAL 0x0c75 3549#define mmDSCL0_DSCL_AUTOCAL_BASE_IDX 2 3550#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0c76 3551#define mmDSCL0_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 3552#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0c77 3553#define mmDSCL0_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 3554#define mmDSCL0_OTG_H_BLANK 0x0c78 3555#define mmDSCL0_OTG_H_BLANK_BASE_IDX 2 3556#define mmDSCL0_OTG_V_BLANK 0x0c79 3557#define mmDSCL0_OTG_V_BLANK_BASE_IDX 2 3558#define mmDSCL0_RECOUT_START 0x0c7a 3559#define mmDSCL0_RECOUT_START_BASE_IDX 2 3560#define mmDSCL0_RECOUT_SIZE 0x0c7b 3561#define mmDSCL0_RECOUT_SIZE_BASE_IDX 2 3562#define mmDSCL0_MPC_SIZE 0x0c7c 3563#define mmDSCL0_MPC_SIZE_BASE_IDX 2 3564#define mmDSCL0_LB_DATA_FORMAT 0x0c7d 3565#define mmDSCL0_LB_DATA_FORMAT_BASE_IDX 2 3566#define mmDSCL0_LB_MEMORY_CTRL 0x0c7e 3567#define mmDSCL0_LB_MEMORY_CTRL_BASE_IDX 2 3568#define mmDSCL0_LB_V_COUNTER 0x0c7f 3569#define mmDSCL0_LB_V_COUNTER_BASE_IDX 2 3570#define mmDSCL0_DSCL_MEM_PWR_CTRL 0x0c80 3571#define mmDSCL0_DSCL_MEM_PWR_CTRL_BASE_IDX 2 3572#define mmDSCL0_DSCL_MEM_PWR_STATUS 0x0c81 3573#define mmDSCL0_DSCL_MEM_PWR_STATUS_BASE_IDX 2 3574#define mmDSCL0_OBUF_CONTROL 0x0c82 3575#define mmDSCL0_OBUF_CONTROL_BASE_IDX 2 3576#define mmDSCL0_OBUF_MEM_PWR_CTRL 0x0c83 3577#define mmDSCL0_OBUF_MEM_PWR_CTRL_BASE_IDX 2 3578 3579 3580// addressBlock: dce_dc_dpp0_dispdec_cm_dispdec 3581// base address: 0x0 3582#define mmCM0_CM_CONTROL 0x0c92 3583#define mmCM0_CM_CONTROL_BASE_IDX 2 3584#define mmCM0_CM_COMA_C11_C12 0x0c93 3585#define mmCM0_CM_COMA_C11_C12_BASE_IDX 2 3586#define mmCM0_CM_COMA_C13_C14 0x0c94 3587#define mmCM0_CM_COMA_C13_C14_BASE_IDX 2 3588#define mmCM0_CM_COMA_C21_C22 0x0c95 3589#define mmCM0_CM_COMA_C21_C22_BASE_IDX 2 3590#define mmCM0_CM_COMA_C23_C24 0x0c96 3591#define mmCM0_CM_COMA_C23_C24_BASE_IDX 2 3592#define mmCM0_CM_COMA_C31_C32 0x0c97 3593#define mmCM0_CM_COMA_C31_C32_BASE_IDX 2 3594#define mmCM0_CM_COMA_C33_C34 0x0c98 3595#define mmCM0_CM_COMA_C33_C34_BASE_IDX 2 3596#define mmCM0_CM_COMB_C11_C12 0x0c99 3597#define mmCM0_CM_COMB_C11_C12_BASE_IDX 2 3598#define mmCM0_CM_COMB_C13_C14 0x0c9a 3599#define mmCM0_CM_COMB_C13_C14_BASE_IDX 2 3600#define mmCM0_CM_COMB_C21_C22 0x0c9b 3601#define mmCM0_CM_COMB_C21_C22_BASE_IDX 2 3602#define mmCM0_CM_COMB_C23_C24 0x0c9c 3603#define mmCM0_CM_COMB_C23_C24_BASE_IDX 2 3604#define mmCM0_CM_COMB_C31_C32 0x0c9d 3605#define mmCM0_CM_COMB_C31_C32_BASE_IDX 2 3606#define mmCM0_CM_COMB_C33_C34 0x0c9e 3607#define mmCM0_CM_COMB_C33_C34_BASE_IDX 2 3608#define mmCM0_CM_IGAM_CONTROL 0x0c9f 3609#define mmCM0_CM_IGAM_CONTROL_BASE_IDX 2 3610#define mmCM0_CM_IGAM_LUT_RW_CONTROL 0x0ca0 3611#define mmCM0_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 3612#define mmCM0_CM_IGAM_LUT_RW_INDEX 0x0ca1 3613#define mmCM0_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 3614#define mmCM0_CM_IGAM_LUT_SEQ_COLOR 0x0ca2 3615#define mmCM0_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 3616#define mmCM0_CM_IGAM_LUT_30_COLOR 0x0ca3 3617#define mmCM0_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 3618#define mmCM0_CM_IGAM_LUT_PWL_DATA 0x0ca4 3619#define mmCM0_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 3620#define mmCM0_CM_IGAM_LUT_AUTOFILL 0x0ca5 3621#define mmCM0_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 3622#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ca6 3623#define mmCM0_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 3624#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ca7 3625#define mmCM0_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 3626#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED 0x0ca8 3627#define mmCM0_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 3628#define mmCM0_CM_ICSC_CONTROL 0x0ca9 3629#define mmCM0_CM_ICSC_CONTROL_BASE_IDX 2 3630#define mmCM0_CM_ICSC_C11_C12 0x0caa 3631#define mmCM0_CM_ICSC_C11_C12_BASE_IDX 2 3632#define mmCM0_CM_ICSC_C13_C14 0x0cab 3633#define mmCM0_CM_ICSC_C13_C14_BASE_IDX 2 3634#define mmCM0_CM_ICSC_C21_C22 0x0cac 3635#define mmCM0_CM_ICSC_C21_C22_BASE_IDX 2 3636#define mmCM0_CM_ICSC_C23_C24 0x0cad 3637#define mmCM0_CM_ICSC_C23_C24_BASE_IDX 2 3638#define mmCM0_CM_ICSC_C31_C32 0x0cae 3639#define mmCM0_CM_ICSC_C31_C32_BASE_IDX 2 3640#define mmCM0_CM_ICSC_C33_C34 0x0caf 3641#define mmCM0_CM_ICSC_C33_C34_BASE_IDX 2 3642#define mmCM0_CM_GAMUT_REMAP_CONTROL 0x0cb0 3643#define mmCM0_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 3644#define mmCM0_CM_GAMUT_REMAP_C11_C12 0x0cb1 3645#define mmCM0_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 3646#define mmCM0_CM_GAMUT_REMAP_C13_C14 0x0cb2 3647#define mmCM0_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 3648#define mmCM0_CM_GAMUT_REMAP_C21_C22 0x0cb3 3649#define mmCM0_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 3650#define mmCM0_CM_GAMUT_REMAP_C23_C24 0x0cb4 3651#define mmCM0_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 3652#define mmCM0_CM_GAMUT_REMAP_C31_C32 0x0cb5 3653#define mmCM0_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 3654#define mmCM0_CM_GAMUT_REMAP_C33_C34 0x0cb6 3655#define mmCM0_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 3656#define mmCM0_CM_OCSC_CONTROL 0x0cb7 3657#define mmCM0_CM_OCSC_CONTROL_BASE_IDX 2 3658#define mmCM0_CM_OCSC_C11_C12 0x0cb8 3659#define mmCM0_CM_OCSC_C11_C12_BASE_IDX 2 3660#define mmCM0_CM_OCSC_C13_C14 0x0cb9 3661#define mmCM0_CM_OCSC_C13_C14_BASE_IDX 2 3662#define mmCM0_CM_OCSC_C21_C22 0x0cba 3663#define mmCM0_CM_OCSC_C21_C22_BASE_IDX 2 3664#define mmCM0_CM_OCSC_C23_C24 0x0cbb 3665#define mmCM0_CM_OCSC_C23_C24_BASE_IDX 2 3666#define mmCM0_CM_OCSC_C31_C32 0x0cbc 3667#define mmCM0_CM_OCSC_C31_C32_BASE_IDX 2 3668#define mmCM0_CM_OCSC_C33_C34 0x0cbd 3669#define mmCM0_CM_OCSC_C33_C34_BASE_IDX 2 3670#define mmCM0_CM_BNS_VALUES_R 0x0cbe 3671#define mmCM0_CM_BNS_VALUES_R_BASE_IDX 2 3672#define mmCM0_CM_BNS_VALUES_G 0x0cbf 3673#define mmCM0_CM_BNS_VALUES_G_BASE_IDX 2 3674#define mmCM0_CM_BNS_VALUES_B 0x0cc0 3675#define mmCM0_CM_BNS_VALUES_B_BASE_IDX 2 3676#define mmCM0_CM_DGAM_CONTROL 0x0cc1 3677#define mmCM0_CM_DGAM_CONTROL_BASE_IDX 2 3678#define mmCM0_CM_DGAM_LUT_INDEX 0x0cc2 3679#define mmCM0_CM_DGAM_LUT_INDEX_BASE_IDX 2 3680#define mmCM0_CM_DGAM_LUT_DATA 0x0cc3 3681#define mmCM0_CM_DGAM_LUT_DATA_BASE_IDX 2 3682#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK 0x0cc4 3683#define mmCM0_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 3684#define mmCM0_CM_DGAM_RAMA_START_CNTL_B 0x0cc5 3685#define mmCM0_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 3686#define mmCM0_CM_DGAM_RAMA_START_CNTL_G 0x0cc6 3687#define mmCM0_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 3688#define mmCM0_CM_DGAM_RAMA_START_CNTL_R 0x0cc7 3689#define mmCM0_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 3690#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0cc8 3691#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 3692#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0cc9 3693#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 3694#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0cca 3695#define mmCM0_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 3696#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B 0x0ccb 3697#define mmCM0_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 3698#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B 0x0ccc 3699#define mmCM0_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 3700#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G 0x0ccd 3701#define mmCM0_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 3702#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G 0x0cce 3703#define mmCM0_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 3704#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R 0x0ccf 3705#define mmCM0_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 3706#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R 0x0cd0 3707#define mmCM0_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 3708#define mmCM0_CM_DGAM_RAMA_REGION_0_1 0x0cd1 3709#define mmCM0_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 3710#define mmCM0_CM_DGAM_RAMA_REGION_2_3 0x0cd2 3711#define mmCM0_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 3712#define mmCM0_CM_DGAM_RAMA_REGION_4_5 0x0cd3 3713#define mmCM0_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 3714#define mmCM0_CM_DGAM_RAMA_REGION_6_7 0x0cd4 3715#define mmCM0_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 3716#define mmCM0_CM_DGAM_RAMA_REGION_8_9 0x0cd5 3717#define mmCM0_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 3718#define mmCM0_CM_DGAM_RAMA_REGION_10_11 0x0cd6 3719#define mmCM0_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 3720#define mmCM0_CM_DGAM_RAMA_REGION_12_13 0x0cd7 3721#define mmCM0_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 3722#define mmCM0_CM_DGAM_RAMA_REGION_14_15 0x0cd8 3723#define mmCM0_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 3724#define mmCM0_CM_DGAM_RAMB_START_CNTL_B 0x0cd9 3725#define mmCM0_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 3726#define mmCM0_CM_DGAM_RAMB_START_CNTL_G 0x0cda 3727#define mmCM0_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 3728#define mmCM0_CM_DGAM_RAMB_START_CNTL_R 0x0cdb 3729#define mmCM0_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 3730#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0cdc 3731#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 3732#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0cdd 3733#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 3734#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0cde 3735#define mmCM0_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 3736#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B 0x0cdf 3737#define mmCM0_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 3738#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B 0x0ce0 3739#define mmCM0_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 3740#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G 0x0ce1 3741#define mmCM0_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 3742#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G 0x0ce2 3743#define mmCM0_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 3744#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R 0x0ce3 3745#define mmCM0_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 3746#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R 0x0ce4 3747#define mmCM0_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 3748#define mmCM0_CM_DGAM_RAMB_REGION_0_1 0x0ce5 3749#define mmCM0_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 3750#define mmCM0_CM_DGAM_RAMB_REGION_2_3 0x0ce6 3751#define mmCM0_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 3752#define mmCM0_CM_DGAM_RAMB_REGION_4_5 0x0ce7 3753#define mmCM0_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 3754#define mmCM0_CM_DGAM_RAMB_REGION_6_7 0x0ce8 3755#define mmCM0_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 3756#define mmCM0_CM_DGAM_RAMB_REGION_8_9 0x0ce9 3757#define mmCM0_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 3758#define mmCM0_CM_DGAM_RAMB_REGION_10_11 0x0cea 3759#define mmCM0_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 3760#define mmCM0_CM_DGAM_RAMB_REGION_12_13 0x0ceb 3761#define mmCM0_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 3762#define mmCM0_CM_DGAM_RAMB_REGION_14_15 0x0cec 3763#define mmCM0_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 3764#define mmCM0_CM_RGAM_CONTROL 0x0ced 3765#define mmCM0_CM_RGAM_CONTROL_BASE_IDX 2 3766#define mmCM0_CM_RGAM_LUT_INDEX 0x0cee 3767#define mmCM0_CM_RGAM_LUT_INDEX_BASE_IDX 2 3768#define mmCM0_CM_RGAM_LUT_DATA 0x0cef 3769#define mmCM0_CM_RGAM_LUT_DATA_BASE_IDX 2 3770#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK 0x0cf0 3771#define mmCM0_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 3772#define mmCM0_CM_RGAM_RAMA_START_CNTL_B 0x0cf1 3773#define mmCM0_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 3774#define mmCM0_CM_RGAM_RAMA_START_CNTL_G 0x0cf2 3775#define mmCM0_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 3776#define mmCM0_CM_RGAM_RAMA_START_CNTL_R 0x0cf3 3777#define mmCM0_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 3778#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0cf4 3779#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 3780#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0cf5 3781#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 3782#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0cf6 3783#define mmCM0_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 3784#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B 0x0cf7 3785#define mmCM0_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 3786#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B 0x0cf8 3787#define mmCM0_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 3788#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G 0x0cf9 3789#define mmCM0_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 3790#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G 0x0cfa 3791#define mmCM0_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 3792#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R 0x0cfb 3793#define mmCM0_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 3794#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R 0x0cfc 3795#define mmCM0_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 3796#define mmCM0_CM_RGAM_RAMA_REGION_0_1 0x0cfd 3797#define mmCM0_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 3798#define mmCM0_CM_RGAM_RAMA_REGION_2_3 0x0cfe 3799#define mmCM0_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 3800#define mmCM0_CM_RGAM_RAMA_REGION_4_5 0x0cff 3801#define mmCM0_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 3802#define mmCM0_CM_RGAM_RAMA_REGION_6_7 0x0d00 3803#define mmCM0_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 3804#define mmCM0_CM_RGAM_RAMA_REGION_8_9 0x0d01 3805#define mmCM0_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 3806#define mmCM0_CM_RGAM_RAMA_REGION_10_11 0x0d02 3807#define mmCM0_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 3808#define mmCM0_CM_RGAM_RAMA_REGION_12_13 0x0d03 3809#define mmCM0_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 3810#define mmCM0_CM_RGAM_RAMA_REGION_14_15 0x0d04 3811#define mmCM0_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 3812#define mmCM0_CM_RGAM_RAMA_REGION_16_17 0x0d05 3813#define mmCM0_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 3814#define mmCM0_CM_RGAM_RAMA_REGION_18_19 0x0d06 3815#define mmCM0_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 3816#define mmCM0_CM_RGAM_RAMA_REGION_20_21 0x0d07 3817#define mmCM0_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 3818#define mmCM0_CM_RGAM_RAMA_REGION_22_23 0x0d08 3819#define mmCM0_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 3820#define mmCM0_CM_RGAM_RAMA_REGION_24_25 0x0d09 3821#define mmCM0_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 3822#define mmCM0_CM_RGAM_RAMA_REGION_26_27 0x0d0a 3823#define mmCM0_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 3824#define mmCM0_CM_RGAM_RAMA_REGION_28_29 0x0d0b 3825#define mmCM0_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 3826#define mmCM0_CM_RGAM_RAMA_REGION_30_31 0x0d0c 3827#define mmCM0_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 3828#define mmCM0_CM_RGAM_RAMA_REGION_32_33 0x0d0d 3829#define mmCM0_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 3830#define mmCM0_CM_RGAM_RAMB_START_CNTL_B 0x0d0e 3831#define mmCM0_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 3832#define mmCM0_CM_RGAM_RAMB_START_CNTL_G 0x0d0f 3833#define mmCM0_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 3834#define mmCM0_CM_RGAM_RAMB_START_CNTL_R 0x0d10 3835#define mmCM0_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 3836#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0d11 3837#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 3838#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0d12 3839#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 3840#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0d13 3841#define mmCM0_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 3842#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B 0x0d14 3843#define mmCM0_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 3844#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B 0x0d15 3845#define mmCM0_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 3846#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G 0x0d16 3847#define mmCM0_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 3848#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G 0x0d17 3849#define mmCM0_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 3850#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R 0x0d18 3851#define mmCM0_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 3852#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R 0x0d19 3853#define mmCM0_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 3854#define mmCM0_CM_RGAM_RAMB_REGION_0_1 0x0d1a 3855#define mmCM0_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 3856#define mmCM0_CM_RGAM_RAMB_REGION_2_3 0x0d1b 3857#define mmCM0_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 3858#define mmCM0_CM_RGAM_RAMB_REGION_4_5 0x0d1c 3859#define mmCM0_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 3860#define mmCM0_CM_RGAM_RAMB_REGION_6_7 0x0d1d 3861#define mmCM0_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 3862#define mmCM0_CM_RGAM_RAMB_REGION_8_9 0x0d1e 3863#define mmCM0_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 3864#define mmCM0_CM_RGAM_RAMB_REGION_10_11 0x0d1f 3865#define mmCM0_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 3866#define mmCM0_CM_RGAM_RAMB_REGION_12_13 0x0d20 3867#define mmCM0_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 3868#define mmCM0_CM_RGAM_RAMB_REGION_14_15 0x0d21 3869#define mmCM0_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 3870#define mmCM0_CM_RGAM_RAMB_REGION_16_17 0x0d22 3871#define mmCM0_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 3872#define mmCM0_CM_RGAM_RAMB_REGION_18_19 0x0d23 3873#define mmCM0_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 3874#define mmCM0_CM_RGAM_RAMB_REGION_20_21 0x0d24 3875#define mmCM0_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 3876#define mmCM0_CM_RGAM_RAMB_REGION_22_23 0x0d25 3877#define mmCM0_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 3878#define mmCM0_CM_RGAM_RAMB_REGION_24_25 0x0d26 3879#define mmCM0_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 3880#define mmCM0_CM_RGAM_RAMB_REGION_26_27 0x0d27 3881#define mmCM0_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 3882#define mmCM0_CM_RGAM_RAMB_REGION_28_29 0x0d28 3883#define mmCM0_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 3884#define mmCM0_CM_RGAM_RAMB_REGION_30_31 0x0d29 3885#define mmCM0_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 3886#define mmCM0_CM_RGAM_RAMB_REGION_32_33 0x0d2a 3887#define mmCM0_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 3888#define mmCM0_CM_HDR_MULT_COEF 0x0d2b 3889#define mmCM0_CM_HDR_MULT_COEF_BASE_IDX 2 3890#define mmCM0_CM_RANGE_CLAMP_CONTROL_R 0x0d2c 3891#define mmCM0_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 3892#define mmCM0_CM_RANGE_CLAMP_CONTROL_G 0x0d2d 3893#define mmCM0_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 3894#define mmCM0_CM_RANGE_CLAMP_CONTROL_B 0x0d2e 3895#define mmCM0_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 3896#define mmCM0_CM_DENORM_CONTROL 0x0d2f 3897#define mmCM0_CM_DENORM_CONTROL_BASE_IDX 2 3898#define mmCM0_CM_CMOUT_CONTROL 0x0d30 3899#define mmCM0_CM_CMOUT_CONTROL_BASE_IDX 2 3900#define mmCM0_CM_CMOUT_RANDOM_SEEDS 0x0d31 3901#define mmCM0_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 3902#define mmCM0_CM_MEM_PWR_CTRL 0x0d32 3903#define mmCM0_CM_MEM_PWR_CTRL_BASE_IDX 2 3904#define mmCM0_CM_MEM_PWR_STATUS 0x0d33 3905#define mmCM0_CM_MEM_PWR_STATUS_BASE_IDX 2 3906#define mmCM0_CM_TEST_DEBUG_INDEX 0x0d35 3907#define mmCM0_CM_TEST_DEBUG_INDEX_BASE_IDX 2 3908#define mmCM0_CM_TEST_DEBUG_DATA 0x0d36 3909#define mmCM0_CM_TEST_DEBUG_DATA_BASE_IDX 2 3910 3911 3912// addressBlock: dce_dc_dpp0_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 3913// base address: 0x3530 3914#define mmDC_PERFMON12_PERFCOUNTER_CNTL 0x0d4c 3915#define mmDC_PERFMON12_PERFCOUNTER_CNTL_BASE_IDX 2 3916#define mmDC_PERFMON12_PERFCOUNTER_CNTL2 0x0d4d 3917#define mmDC_PERFMON12_PERFCOUNTER_CNTL2_BASE_IDX 2 3918#define mmDC_PERFMON12_PERFCOUNTER_STATE 0x0d4e 3919#define mmDC_PERFMON12_PERFCOUNTER_STATE_BASE_IDX 2 3920#define mmDC_PERFMON12_PERFMON_CNTL 0x0d4f 3921#define mmDC_PERFMON12_PERFMON_CNTL_BASE_IDX 2 3922#define mmDC_PERFMON12_PERFMON_CNTL2 0x0d50 3923#define mmDC_PERFMON12_PERFMON_CNTL2_BASE_IDX 2 3924#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC 0x0d51 3925#define mmDC_PERFMON12_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 3926#define mmDC_PERFMON12_PERFMON_CVALUE_LOW 0x0d52 3927#define mmDC_PERFMON12_PERFMON_CVALUE_LOW_BASE_IDX 2 3928#define mmDC_PERFMON12_PERFMON_HI 0x0d53 3929#define mmDC_PERFMON12_PERFMON_HI_BASE_IDX 2 3930#define mmDC_PERFMON12_PERFMON_LOW 0x0d54 3931#define mmDC_PERFMON12_PERFMON_LOW_BASE_IDX 2 3932 3933 3934// addressBlock: dce_dc_dpp1_dispdec_dpp_top_dispdec 3935// base address: 0x46c 3936#define mmDPP_TOP1_DPP_CONTROL 0x0d58 3937#define mmDPP_TOP1_DPP_CONTROL_BASE_IDX 2 3938#define mmDPP_TOP1_DPP_SOFT_RESET 0x0d59 3939#define mmDPP_TOP1_DPP_SOFT_RESET_BASE_IDX 2 3940#define mmDPP_TOP1_DPP_CRC_VAL_R_G 0x0d5a 3941#define mmDPP_TOP1_DPP_CRC_VAL_R_G_BASE_IDX 2 3942#define mmDPP_TOP1_DPP_CRC_VAL_B_A 0x0d5b 3943#define mmDPP_TOP1_DPP_CRC_VAL_B_A_BASE_IDX 2 3944#define mmDPP_TOP1_DPP_CRC_CTRL 0x0d5c 3945#define mmDPP_TOP1_DPP_CRC_CTRL_BASE_IDX 2 3946#define mmDPP_TOP1_HOST_READ_CONTROL 0x0d5d 3947#define mmDPP_TOP1_HOST_READ_CONTROL_BASE_IDX 2 3948 3949 3950// addressBlock: dce_dc_dpp1_dispdec_cnvc_cfg_dispdec 3951// base address: 0x46c 3952#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT 0x0d62 3953#define mmCNVC_CFG1_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 3954#define mmCNVC_CFG1_FORMAT_CONTROL 0x0d63 3955#define mmCNVC_CFG1_FORMAT_CONTROL_BASE_IDX 2 3956#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS 0x0d64 3957#define mmCNVC_CFG1_FCNV_FP_SCALE_BIAS_BASE_IDX 2 3958#define mmCNVC_CFG1_DENORM_CONTROL 0x0d65 3959#define mmCNVC_CFG1_DENORM_CONTROL_BASE_IDX 2 3960#define mmCNVC_CFG1_COLOR_KEYER_CONTROL 0x0d67 3961#define mmCNVC_CFG1_COLOR_KEYER_CONTROL_BASE_IDX 2 3962#define mmCNVC_CFG1_COLOR_KEYER_ALPHA 0x0d68 3963#define mmCNVC_CFG1_COLOR_KEYER_ALPHA_BASE_IDX 2 3964#define mmCNVC_CFG1_COLOR_KEYER_RED 0x0d69 3965#define mmCNVC_CFG1_COLOR_KEYER_RED_BASE_IDX 2 3966#define mmCNVC_CFG1_COLOR_KEYER_GREEN 0x0d6a 3967#define mmCNVC_CFG1_COLOR_KEYER_GREEN_BASE_IDX 2 3968#define mmCNVC_CFG1_COLOR_KEYER_BLUE 0x0d6b 3969#define mmCNVC_CFG1_COLOR_KEYER_BLUE_BASE_IDX 2 3970 3971 3972// addressBlock: dce_dc_dpp1_dispdec_cnvc_cur_dispdec 3973// base address: 0x46c 3974#define mmCNVC_CUR1_CURSOR0_CONTROL 0x0d73 3975#define mmCNVC_CUR1_CURSOR0_CONTROL_BASE_IDX 2 3976#define mmCNVC_CUR1_CURSOR0_COLOR0 0x0d74 3977#define mmCNVC_CUR1_CURSOR0_COLOR0_BASE_IDX 2 3978#define mmCNVC_CUR1_CURSOR0_COLOR1 0x0d75 3979#define mmCNVC_CUR1_CURSOR0_COLOR1_BASE_IDX 2 3980#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS 0x0d76 3981#define mmCNVC_CUR1_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 3982 3983 3984// addressBlock: dce_dc_dpp1_dispdec_dscl_dispdec 3985// base address: 0x46c 3986#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT 0x0d7d 3987#define mmDSCL1_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 3988#define mmDSCL1_SCL_COEF_RAM_TAP_DATA 0x0d7e 3989#define mmDSCL1_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 3990#define mmDSCL1_SCL_MODE 0x0d7f 3991#define mmDSCL1_SCL_MODE_BASE_IDX 2 3992#define mmDSCL1_SCL_TAP_CONTROL 0x0d80 3993#define mmDSCL1_SCL_TAP_CONTROL_BASE_IDX 2 3994#define mmDSCL1_DSCL_CONTROL 0x0d81 3995#define mmDSCL1_DSCL_CONTROL_BASE_IDX 2 3996#define mmDSCL1_DSCL_2TAP_CONTROL 0x0d82 3997#define mmDSCL1_DSCL_2TAP_CONTROL_BASE_IDX 2 3998#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL 0x0d83 3999#define mmDSCL1_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4000#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO 0x0d84
4001#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4002#define mmDSCL1_SCL_HORZ_FILTER_INIT 0x0d85 4003#define mmDSCL1_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4004#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0d86 4005#define mmDSCL1_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4006#define mmDSCL1_SCL_HORZ_FILTER_INIT_C 0x0d87 4007#define mmDSCL1_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4008#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO 0x0d88 4009#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4010#define mmDSCL1_SCL_VERT_FILTER_INIT 0x0d89 4011#define mmDSCL1_SCL_VERT_FILTER_INIT_BASE_IDX 2 4012#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT 0x0d8a 4013#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4014#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C 0x0d8b 4015#define mmDSCL1_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4016#define mmDSCL1_SCL_VERT_FILTER_INIT_C 0x0d8c 4017#define mmDSCL1_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4018#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C 0x0d8d 4019#define mmDSCL1_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4020#define mmDSCL1_SCL_BLACK_OFFSET 0x0d8e 4021#define mmDSCL1_SCL_BLACK_OFFSET_BASE_IDX 2 4022#define mmDSCL1_DSCL_UPDATE 0x0d8f 4023#define mmDSCL1_DSCL_UPDATE_BASE_IDX 2 4024#define mmDSCL1_DSCL_AUTOCAL 0x0d90 4025#define mmDSCL1_DSCL_AUTOCAL_BASE_IDX 2 4026#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0d91 4027#define mmDSCL1_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4028#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0d92 4029#define mmDSCL1_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4030#define mmDSCL1_OTG_H_BLANK 0x0d93 4031#define mmDSCL1_OTG_H_BLANK_BASE_IDX 2 4032#define mmDSCL1_OTG_V_BLANK 0x0d94 4033#define mmDSCL1_OTG_V_BLANK_BASE_IDX 2 4034#define mmDSCL1_RECOUT_START 0x0d95 4035#define mmDSCL1_RECOUT_START_BASE_IDX 2 4036#define mmDSCL1_RECOUT_SIZE 0x0d96 4037#define mmDSCL1_RECOUT_SIZE_BASE_IDX 2 4038#define mmDSCL1_MPC_SIZE 0x0d97 4039#define mmDSCL1_MPC_SIZE_BASE_IDX 2 4040#define mmDSCL1_LB_DATA_FORMAT 0x0d98 4041#define mmDSCL1_LB_DATA_FORMAT_BASE_IDX 2 4042#define mmDSCL1_LB_MEMORY_CTRL 0x0d99 4043#define mmDSCL1_LB_MEMORY_CTRL_BASE_IDX 2 4044#define mmDSCL1_LB_V_COUNTER 0x0d9a 4045#define mmDSCL1_LB_V_COUNTER_BASE_IDX 2 4046#define mmDSCL1_DSCL_MEM_PWR_CTRL 0x0d9b 4047#define mmDSCL1_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4048#define mmDSCL1_DSCL_MEM_PWR_STATUS 0x0d9c 4049#define mmDSCL1_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4050#define mmDSCL1_OBUF_CONTROL 0x0d9d 4051#define mmDSCL1_OBUF_CONTROL_BASE_IDX 2 4052#define mmDSCL1_OBUF_MEM_PWR_CTRL 0x0d9e 4053#define mmDSCL1_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4054 4055 4056// addressBlock: dce_dc_dpp1_dispdec_cm_dispdec 4057// base address: 0x46c 4058#define mmCM1_CM_CONTROL 0x0dad 4059#define mmCM1_CM_CONTROL_BASE_IDX 2 4060#define mmCM1_CM_COMA_C11_C12 0x0dae 4061#define mmCM1_CM_COMA_C11_C12_BASE_IDX 2 4062#define mmCM1_CM_COMA_C13_C14 0x0daf 4063#define mmCM1_CM_COMA_C13_C14_BASE_IDX 2 4064#define mmCM1_CM_COMA_C21_C22 0x0db0 4065#define mmCM1_CM_COMA_C21_C22_BASE_IDX 2 4066#define mmCM1_CM_COMA_C23_C24 0x0db1 4067#define mmCM1_CM_COMA_C23_C24_BASE_IDX 2 4068#define mmCM1_CM_COMA_C31_C32 0x0db2 4069#define mmCM1_CM_COMA_C31_C32_BASE_IDX 2 4070#define mmCM1_CM_COMA_C33_C34 0x0db3 4071#define mmCM1_CM_COMA_C33_C34_BASE_IDX 2 4072#define mmCM1_CM_COMB_C11_C12 0x0db4 4073#define mmCM1_CM_COMB_C11_C12_BASE_IDX 2 4074#define mmCM1_CM_COMB_C13_C14 0x0db5 4075#define mmCM1_CM_COMB_C13_C14_BASE_IDX 2 4076#define mmCM1_CM_COMB_C21_C22 0x0db6 4077#define mmCM1_CM_COMB_C21_C22_BASE_IDX 2 4078#define mmCM1_CM_COMB_C23_C24 0x0db7 4079#define mmCM1_CM_COMB_C23_C24_BASE_IDX 2 4080#define mmCM1_CM_COMB_C31_C32 0x0db8 4081#define mmCM1_CM_COMB_C31_C32_BASE_IDX 2 4082#define mmCM1_CM_COMB_C33_C34 0x0db9 4083#define mmCM1_CM_COMB_C33_C34_BASE_IDX 2 4084#define mmCM1_CM_IGAM_CONTROL 0x0dba 4085#define mmCM1_CM_IGAM_CONTROL_BASE_IDX 2 4086#define mmCM1_CM_IGAM_LUT_RW_CONTROL 0x0dbb 4087#define mmCM1_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 4088#define mmCM1_CM_IGAM_LUT_RW_INDEX 0x0dbc 4089#define mmCM1_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 4090#define mmCM1_CM_IGAM_LUT_SEQ_COLOR 0x0dbd 4091#define mmCM1_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 4092#define mmCM1_CM_IGAM_LUT_30_COLOR 0x0dbe 4093#define mmCM1_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 4094#define mmCM1_CM_IGAM_LUT_PWL_DATA 0x0dbf 4095#define mmCM1_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 4096#define mmCM1_CM_IGAM_LUT_AUTOFILL 0x0dc0 4097#define mmCM1_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 4098#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0dc1 4099#define mmCM1_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 4100#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0dc2 4101#define mmCM1_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 4102#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED 0x0dc3 4103#define mmCM1_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 4104#define mmCM1_CM_ICSC_CONTROL 0x0dc4 4105#define mmCM1_CM_ICSC_CONTROL_BASE_IDX 2 4106#define mmCM1_CM_ICSC_C11_C12 0x0dc5 4107#define mmCM1_CM_ICSC_C11_C12_BASE_IDX 2 4108#define mmCM1_CM_ICSC_C13_C14 0x0dc6 4109#define mmCM1_CM_ICSC_C13_C14_BASE_IDX 2 4110#define mmCM1_CM_ICSC_C21_C22 0x0dc7 4111#define mmCM1_CM_ICSC_C21_C22_BASE_IDX 2 4112#define mmCM1_CM_ICSC_C23_C24 0x0dc8 4113#define mmCM1_CM_ICSC_C23_C24_BASE_IDX 2 4114#define mmCM1_CM_ICSC_C31_C32 0x0dc9 4115#define mmCM1_CM_ICSC_C31_C32_BASE_IDX 2 4116#define mmCM1_CM_ICSC_C33_C34 0x0dca 4117#define mmCM1_CM_ICSC_C33_C34_BASE_IDX 2 4118#define mmCM1_CM_GAMUT_REMAP_CONTROL 0x0dcb 4119#define mmCM1_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4120#define mmCM1_CM_GAMUT_REMAP_C11_C12 0x0dcc 4121#define mmCM1_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4122#define mmCM1_CM_GAMUT_REMAP_C13_C14 0x0dcd 4123#define mmCM1_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4124#define mmCM1_CM_GAMUT_REMAP_C21_C22 0x0dce 4125#define mmCM1_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4126#define mmCM1_CM_GAMUT_REMAP_C23_C24 0x0dcf 4127#define mmCM1_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4128#define mmCM1_CM_GAMUT_REMAP_C31_C32 0x0dd0 4129#define mmCM1_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4130#define mmCM1_CM_GAMUT_REMAP_C33_C34 0x0dd1 4131#define mmCM1_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4132#define mmCM1_CM_OCSC_CONTROL 0x0dd2 4133#define mmCM1_CM_OCSC_CONTROL_BASE_IDX 2 4134#define mmCM1_CM_OCSC_C11_C12 0x0dd3 4135#define mmCM1_CM_OCSC_C11_C12_BASE_IDX 2 4136#define mmCM1_CM_OCSC_C13_C14 0x0dd4 4137#define mmCM1_CM_OCSC_C13_C14_BASE_IDX 2 4138#define mmCM1_CM_OCSC_C21_C22 0x0dd5 4139#define mmCM1_CM_OCSC_C21_C22_BASE_IDX 2 4140#define mmCM1_CM_OCSC_C23_C24 0x0dd6 4141#define mmCM1_CM_OCSC_C23_C24_BASE_IDX 2 4142#define mmCM1_CM_OCSC_C31_C32 0x0dd7 4143#define mmCM1_CM_OCSC_C31_C32_BASE_IDX 2 4144#define mmCM1_CM_OCSC_C33_C34 0x0dd8 4145#define mmCM1_CM_OCSC_C33_C34_BASE_IDX 2 4146#define mmCM1_CM_BNS_VALUES_R 0x0dd9 4147#define mmCM1_CM_BNS_VALUES_R_BASE_IDX 2 4148#define mmCM1_CM_BNS_VALUES_G 0x0dda 4149#define mmCM1_CM_BNS_VALUES_G_BASE_IDX 2 4150#define mmCM1_CM_BNS_VALUES_B 0x0ddb 4151#define mmCM1_CM_BNS_VALUES_B_BASE_IDX 2 4152#define mmCM1_CM_DGAM_CONTROL 0x0ddc 4153#define mmCM1_CM_DGAM_CONTROL_BASE_IDX 2 4154#define mmCM1_CM_DGAM_LUT_INDEX 0x0ddd 4155#define mmCM1_CM_DGAM_LUT_INDEX_BASE_IDX 2 4156#define mmCM1_CM_DGAM_LUT_DATA 0x0dde 4157#define mmCM1_CM_DGAM_LUT_DATA_BASE_IDX 2 4158#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK 0x0ddf 4159#define mmCM1_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 4160#define mmCM1_CM_DGAM_RAMA_START_CNTL_B 0x0de0 4161#define mmCM1_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 4162#define mmCM1_CM_DGAM_RAMA_START_CNTL_G 0x0de1 4163#define mmCM1_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 4164#define mmCM1_CM_DGAM_RAMA_START_CNTL_R 0x0de2 4165#define mmCM1_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 4166#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0de3 4167#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 4168#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0de4 4169#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 4170#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0de5 4171#define mmCM1_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 4172#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B 0x0de6 4173#define mmCM1_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4174#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B 0x0de7 4175#define mmCM1_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4176#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G 0x0de8 4177#define mmCM1_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4178#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G 0x0de9 4179#define mmCM1_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4180#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R 0x0dea 4181#define mmCM1_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4182#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R 0x0deb 4183#define mmCM1_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4184#define mmCM1_CM_DGAM_RAMA_REGION_0_1 0x0dec 4185#define mmCM1_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 4186#define mmCM1_CM_DGAM_RAMA_REGION_2_3 0x0ded 4187#define mmCM1_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 4188#define mmCM1_CM_DGAM_RAMA_REGION_4_5 0x0dee 4189#define mmCM1_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 4190#define mmCM1_CM_DGAM_RAMA_REGION_6_7 0x0def 4191#define mmCM1_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 4192#define mmCM1_CM_DGAM_RAMA_REGION_8_9 0x0df0 4193#define mmCM1_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 4194#define mmCM1_CM_DGAM_RAMA_REGION_10_11 0x0df1 4195#define mmCM1_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 4196#define mmCM1_CM_DGAM_RAMA_REGION_12_13 0x0df2 4197#define mmCM1_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 4198#define mmCM1_CM_DGAM_RAMA_REGION_14_15 0x0df3 4199#define mmCM1_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 4200#define mmCM1_CM_DGAM_RAMB_START_CNTL_B 0x0df4 4201#define mmCM1_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 4202#define mmCM1_CM_DGAM_RAMB_START_CNTL_G 0x0df5 4203#define mmCM1_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 4204#define mmCM1_CM_DGAM_RAMB_START_CNTL_R 0x0df6 4205#define mmCM1_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 4206#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0df7 4207#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 4208#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0df8 4209#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 4210#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0df9 4211#define mmCM1_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 4212#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B 0x0dfa 4213#define mmCM1_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4214#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B 0x0dfb 4215#define mmCM1_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4216#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G 0x0dfc 4217#define mmCM1_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4218#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G 0x0dfd 4219#define mmCM1_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4220#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R 0x0dfe 4221#define mmCM1_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4222#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R 0x0dff 4223#define mmCM1_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4224#define mmCM1_CM_DGAM_RAMB_REGION_0_1 0x0e00 4225#define mmCM1_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 4226#define mmCM1_CM_DGAM_RAMB_REGION_2_3 0x0e01 4227#define mmCM1_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 4228#define mmCM1_CM_DGAM_RAMB_REGION_4_5 0x0e02 4229#define mmCM1_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 4230#define mmCM1_CM_DGAM_RAMB_REGION_6_7 0x0e03 4231#define mmCM1_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 4232#define mmCM1_CM_DGAM_RAMB_REGION_8_9 0x0e04 4233#define mmCM1_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 4234#define mmCM1_CM_DGAM_RAMB_REGION_10_11 0x0e05 4235#define mmCM1_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 4236#define mmCM1_CM_DGAM_RAMB_REGION_12_13 0x0e06 4237#define mmCM1_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 4238#define mmCM1_CM_DGAM_RAMB_REGION_14_15 0x0e07 4239#define mmCM1_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 4240#define mmCM1_CM_RGAM_CONTROL 0x0e08 4241#define mmCM1_CM_RGAM_CONTROL_BASE_IDX 2 4242#define mmCM1_CM_RGAM_LUT_INDEX 0x0e09 4243#define mmCM1_CM_RGAM_LUT_INDEX_BASE_IDX 2 4244#define mmCM1_CM_RGAM_LUT_DATA 0x0e0a 4245#define mmCM1_CM_RGAM_LUT_DATA_BASE_IDX 2 4246#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK 0x0e0b 4247#define mmCM1_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 4248#define mmCM1_CM_RGAM_RAMA_START_CNTL_B 0x0e0c 4249#define mmCM1_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 4250#define mmCM1_CM_RGAM_RAMA_START_CNTL_G 0x0e0d 4251#define mmCM1_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 4252#define mmCM1_CM_RGAM_RAMA_START_CNTL_R 0x0e0e 4253#define mmCM1_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 4254#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0e0f 4255#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 4256#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0e10 4257#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 4258#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0e11 4259#define mmCM1_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 4260#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B 0x0e12 4261#define mmCM1_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4262#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B 0x0e13 4263#define mmCM1_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4264#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G 0x0e14 4265#define mmCM1_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4266#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G 0x0e15 4267#define mmCM1_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4268#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R 0x0e16 4269#define mmCM1_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4270#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R 0x0e17 4271#define mmCM1_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4272#define mmCM1_CM_RGAM_RAMA_REGION_0_1 0x0e18 4273#define mmCM1_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 4274#define mmCM1_CM_RGAM_RAMA_REGION_2_3 0x0e19 4275#define mmCM1_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 4276#define mmCM1_CM_RGAM_RAMA_REGION_4_5 0x0e1a 4277#define mmCM1_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 4278#define mmCM1_CM_RGAM_RAMA_REGION_6_7 0x0e1b 4279#define mmCM1_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 4280#define mmCM1_CM_RGAM_RAMA_REGION_8_9 0x0e1c 4281#define mmCM1_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 4282#define mmCM1_CM_RGAM_RAMA_REGION_10_11 0x0e1d 4283#define mmCM1_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 4284#define mmCM1_CM_RGAM_RAMA_REGION_12_13 0x0e1e 4285#define mmCM1_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 4286#define mmCM1_CM_RGAM_RAMA_REGION_14_15 0x0e1f 4287#define mmCM1_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 4288#define mmCM1_CM_RGAM_RAMA_REGION_16_17 0x0e20 4289#define mmCM1_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 4290#define mmCM1_CM_RGAM_RAMA_REGION_18_19 0x0e21 4291#define mmCM1_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 4292#define mmCM1_CM_RGAM_RAMA_REGION_20_21 0x0e22 4293#define mmCM1_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 4294#define mmCM1_CM_RGAM_RAMA_REGION_22_23 0x0e23 4295#define mmCM1_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 4296#define mmCM1_CM_RGAM_RAMA_REGION_24_25 0x0e24 4297#define mmCM1_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 4298#define mmCM1_CM_RGAM_RAMA_REGION_26_27 0x0e25 4299#define mmCM1_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 4300#define mmCM1_CM_RGAM_RAMA_REGION_28_29 0x0e26 4301#define mmCM1_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 4302#define mmCM1_CM_RGAM_RAMA_REGION_30_31 0x0e27 4303#define mmCM1_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 4304#define mmCM1_CM_RGAM_RAMA_REGION_32_33 0x0e28 4305#define mmCM1_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 4306#define mmCM1_CM_RGAM_RAMB_START_CNTL_B 0x0e29 4307#define mmCM1_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 4308#define mmCM1_CM_RGAM_RAMB_START_CNTL_G 0x0e2a 4309#define mmCM1_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 4310#define mmCM1_CM_RGAM_RAMB_START_CNTL_R 0x0e2b 4311#define mmCM1_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 4312#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0e2c 4313#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 4314#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0e2d 4315#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 4316#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0e2e 4317#define mmCM1_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 4318#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B 0x0e2f 4319#define mmCM1_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4320#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B 0x0e30 4321#define mmCM1_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4322#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G 0x0e31 4323#define mmCM1_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4324#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G 0x0e32 4325#define mmCM1_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4326#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R 0x0e33 4327#define mmCM1_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4328#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R 0x0e34 4329#define mmCM1_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4330#define mmCM1_CM_RGAM_RAMB_REGION_0_1 0x0e35 4331#define mmCM1_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 4332#define mmCM1_CM_RGAM_RAMB_REGION_2_3 0x0e36 4333#define mmCM1_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 4334#define mmCM1_CM_RGAM_RAMB_REGION_4_5 0x0e37 4335#define mmCM1_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 4336#define mmCM1_CM_RGAM_RAMB_REGION_6_7 0x0e38 4337#define mmCM1_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 4338#define mmCM1_CM_RGAM_RAMB_REGION_8_9 0x0e39 4339#define mmCM1_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 4340#define mmCM1_CM_RGAM_RAMB_REGION_10_11 0x0e3a 4341#define mmCM1_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 4342#define mmCM1_CM_RGAM_RAMB_REGION_12_13 0x0e3b 4343#define mmCM1_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 4344#define mmCM1_CM_RGAM_RAMB_REGION_14_15 0x0e3c 4345#define mmCM1_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 4346#define mmCM1_CM_RGAM_RAMB_REGION_16_17 0x0e3d 4347#define mmCM1_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 4348#define mmCM1_CM_RGAM_RAMB_REGION_18_19 0x0e3e 4349#define mmCM1_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 4350#define mmCM1_CM_RGAM_RAMB_REGION_20_21 0x0e3f 4351#define mmCM1_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 4352#define mmCM1_CM_RGAM_RAMB_REGION_22_23 0x0e40 4353#define mmCM1_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 4354#define mmCM1_CM_RGAM_RAMB_REGION_24_25 0x0e41 4355#define mmCM1_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 4356#define mmCM1_CM_RGAM_RAMB_REGION_26_27 0x0e42 4357#define mmCM1_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 4358#define mmCM1_CM_RGAM_RAMB_REGION_28_29 0x0e43 4359#define mmCM1_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 4360#define mmCM1_CM_RGAM_RAMB_REGION_30_31 0x0e44 4361#define mmCM1_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 4362#define mmCM1_CM_RGAM_RAMB_REGION_32_33 0x0e45 4363#define mmCM1_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 4364#define mmCM1_CM_HDR_MULT_COEF 0x0e46 4365#define mmCM1_CM_HDR_MULT_COEF_BASE_IDX 2 4366#define mmCM1_CM_RANGE_CLAMP_CONTROL_R 0x0e47 4367#define mmCM1_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 4368#define mmCM1_CM_RANGE_CLAMP_CONTROL_G 0x0e48 4369#define mmCM1_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 4370#define mmCM1_CM_RANGE_CLAMP_CONTROL_B 0x0e49 4371#define mmCM1_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 4372#define mmCM1_CM_DENORM_CONTROL 0x0e4a 4373#define mmCM1_CM_DENORM_CONTROL_BASE_IDX 2 4374#define mmCM1_CM_CMOUT_CONTROL 0x0e4b 4375#define mmCM1_CM_CMOUT_CONTROL_BASE_IDX 2 4376#define mmCM1_CM_CMOUT_RANDOM_SEEDS 0x0e4c 4377#define mmCM1_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 4378#define mmCM1_CM_MEM_PWR_CTRL 0x0e4d 4379#define mmCM1_CM_MEM_PWR_CTRL_BASE_IDX 2 4380#define mmCM1_CM_MEM_PWR_STATUS 0x0e4e 4381#define mmCM1_CM_MEM_PWR_STATUS_BASE_IDX 2 4382#define mmCM1_CM_TEST_DEBUG_INDEX 0x0e50 4383#define mmCM1_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4384#define mmCM1_CM_TEST_DEBUG_DATA 0x0e51 4385#define mmCM1_CM_TEST_DEBUG_DATA_BASE_IDX 2 4386 4387// addressBlock: dce_dc_dpp1_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4388// base address: 0x399c 4389#define mmDC_PERFMON13_PERFCOUNTER_CNTL 0x0e67 4390#define mmDC_PERFMON13_PERFCOUNTER_CNTL_BASE_IDX 2 4391#define mmDC_PERFMON13_PERFCOUNTER_CNTL2 0x0e68 4392#define mmDC_PERFMON13_PERFCOUNTER_CNTL2_BASE_IDX 2 4393#define mmDC_PERFMON13_PERFCOUNTER_STATE 0x0e69 4394#define mmDC_PERFMON13_PERFCOUNTER_STATE_BASE_IDX 2 4395#define mmDC_PERFMON13_PERFMON_CNTL 0x0e6a 4396#define mmDC_PERFMON13_PERFMON_CNTL_BASE_IDX 2 4397#define mmDC_PERFMON13_PERFMON_CNTL2 0x0e6b 4398#define mmDC_PERFMON13_PERFMON_CNTL2_BASE_IDX 2 4399#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC 0x0e6c 4400#define mmDC_PERFMON13_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4401#define mmDC_PERFMON13_PERFMON_CVALUE_LOW 0x0e6d 4402#define mmDC_PERFMON13_PERFMON_CVALUE_LOW_BASE_IDX 2 4403#define mmDC_PERFMON13_PERFMON_HI 0x0e6e 4404#define mmDC_PERFMON13_PERFMON_HI_BASE_IDX 2 4405#define mmDC_PERFMON13_PERFMON_LOW 0x0e6f 4406#define mmDC_PERFMON13_PERFMON_LOW_BASE_IDX 2 4407 4408 4409// addressBlock: dce_dc_dpp2_dispdec_dpp_top_dispdec 4410// base address: 0x8d8 4411#define mmDPP_TOP2_DPP_CONTROL 0x0e73 4412#define mmDPP_TOP2_DPP_CONTROL_BASE_IDX 2 4413#define mmDPP_TOP2_DPP_SOFT_RESET 0x0e74 4414#define mmDPP_TOP2_DPP_SOFT_RESET_BASE_IDX 2 4415#define mmDPP_TOP2_DPP_CRC_VAL_R_G 0x0e75 4416#define mmDPP_TOP2_DPP_CRC_VAL_R_G_BASE_IDX 2 4417#define mmDPP_TOP2_DPP_CRC_VAL_B_A 0x0e76 4418#define mmDPP_TOP2_DPP_CRC_VAL_B_A_BASE_IDX 2 4419#define mmDPP_TOP2_DPP_CRC_CTRL 0x0e77 4420#define mmDPP_TOP2_DPP_CRC_CTRL_BASE_IDX 2 4421#define mmDPP_TOP2_HOST_READ_CONTROL 0x0e78 4422#define mmDPP_TOP2_HOST_READ_CONTROL_BASE_IDX 2 4423 4424 4425// addressBlock: dce_dc_dpp2_dispdec_cnvc_cfg_dispdec 4426// base address: 0x8d8 4427#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT 0x0e7d 4428#define mmCNVC_CFG2_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4429#define mmCNVC_CFG2_FORMAT_CONTROL 0x0e7e 4430#define mmCNVC_CFG2_FORMAT_CONTROL_BASE_IDX 2 4431#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS 0x0e7f 4432#define mmCNVC_CFG2_FCNV_FP_SCALE_BIAS_BASE_IDX 2 4433#define mmCNVC_CFG2_DENORM_CONTROL 0x0e80 4434#define mmCNVC_CFG2_DENORM_CONTROL_BASE_IDX 2 4435#define mmCNVC_CFG2_COLOR_KEYER_CONTROL 0x0e82 4436#define mmCNVC_CFG2_COLOR_KEYER_CONTROL_BASE_IDX 2 4437#define mmCNVC_CFG2_COLOR_KEYER_ALPHA 0x0e83 4438#define mmCNVC_CFG2_COLOR_KEYER_ALPHA_BASE_IDX 2 4439#define mmCNVC_CFG2_COLOR_KEYER_RED 0x0e84 4440#define mmCNVC_CFG2_COLOR_KEYER_RED_BASE_IDX 2 4441#define mmCNVC_CFG2_COLOR_KEYER_GREEN 0x0e85 4442#define mmCNVC_CFG2_COLOR_KEYER_GREEN_BASE_IDX 2 4443#define mmCNVC_CFG2_COLOR_KEYER_BLUE 0x0e86 4444#define mmCNVC_CFG2_COLOR_KEYER_BLUE_BASE_IDX 2 4445 4446 4447// addressBlock: dce_dc_dpp2_dispdec_cnvc_cur_dispdec 4448// base address: 0x8d8 4449#define mmCNVC_CUR2_CURSOR0_CONTROL 0x0e8e 4450#define mmCNVC_CUR2_CURSOR0_CONTROL_BASE_IDX 2 4451#define mmCNVC_CUR2_CURSOR0_COLOR0 0x0e8f 4452#define mmCNVC_CUR2_CURSOR0_COLOR0_BASE_IDX 2 4453#define mmCNVC_CUR2_CURSOR0_COLOR1 0x0e90 4454#define mmCNVC_CUR2_CURSOR0_COLOR1_BASE_IDX 2 4455#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS 0x0e91 4456#define mmCNVC_CUR2_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4457 4458 4459// addressBlock: dce_dc_dpp2_dispdec_dscl_dispdec 4460// base address: 0x8d8 4461#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT 0x0e98 4462#define mmDSCL2_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4463#define mmDSCL2_SCL_COEF_RAM_TAP_DATA 0x0e99 4464#define mmDSCL2_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4465#define mmDSCL2_SCL_MODE 0x0e9a 4466#define mmDSCL2_SCL_MODE_BASE_IDX 2 4467#define mmDSCL2_SCL_TAP_CONTROL 0x0e9b 4468#define mmDSCL2_SCL_TAP_CONTROL_BASE_IDX 2 4469#define mmDSCL2_DSCL_CONTROL 0x0e9c 4470#define mmDSCL2_DSCL_CONTROL_BASE_IDX 2 4471#define mmDSCL2_DSCL_2TAP_CONTROL 0x0e9d 4472#define mmDSCL2_DSCL_2TAP_CONTROL_BASE_IDX 2 4473#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL 0x0e9e 4474#define mmDSCL2_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4475#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO 0x0e9f 4476#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4477#define mmDSCL2_SCL_HORZ_FILTER_INIT 0x0ea0 4478#define mmDSCL2_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4479#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0ea1 4480#define mmDSCL2_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4481#define mmDSCL2_SCL_HORZ_FILTER_INIT_C 0x0ea2 4482#define mmDSCL2_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4483#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO 0x0ea3 4484#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4485#define mmDSCL2_SCL_VERT_FILTER_INIT 0x0ea4 4486#define mmDSCL2_SCL_VERT_FILTER_INIT_BASE_IDX 2 4487#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT 0x0ea5 4488#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4489#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C 0x0ea6 4490#define mmDSCL2_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4491#define mmDSCL2_SCL_VERT_FILTER_INIT_C 0x0ea7 4492#define mmDSCL2_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4493#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C 0x0ea8 4494#define mmDSCL2_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4495#define mmDSCL2_SCL_BLACK_OFFSET 0x0ea9 4496#define mmDSCL2_SCL_BLACK_OFFSET_BASE_IDX 2 4497#define mmDSCL2_DSCL_UPDATE 0x0eaa 4498#define mmDSCL2_DSCL_UPDATE_BASE_IDX 2 4499#define mmDSCL2_DSCL_AUTOCAL 0x0eab 4500#define mmDSCL2_DSCL_AUTOCAL_BASE_IDX 2 4501#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0eac 4502#define mmDSCL2_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4503#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0ead 4504#define mmDSCL2_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4505#define mmDSCL2_OTG_H_BLANK 0x0eae 4506#define mmDSCL2_OTG_H_BLANK_BASE_IDX 2 4507#define mmDSCL2_OTG_V_BLANK 0x0eaf 4508#define mmDSCL2_OTG_V_BLANK_BASE_IDX 2 4509#define mmDSCL2_RECOUT_START 0x0eb0 4510#define mmDSCL2_RECOUT_START_BASE_IDX 2 4511#define mmDSCL2_RECOUT_SIZE 0x0eb1 4512#define mmDSCL2_RECOUT_SIZE_BASE_IDX 2 4513#define mmDSCL2_MPC_SIZE 0x0eb2 4514#define mmDSCL2_MPC_SIZE_BASE_IDX 2 4515#define mmDSCL2_LB_DATA_FORMAT 0x0eb3 4516#define mmDSCL2_LB_DATA_FORMAT_BASE_IDX 2 4517#define mmDSCL2_LB_MEMORY_CTRL 0x0eb4 4518#define mmDSCL2_LB_MEMORY_CTRL_BASE_IDX 2 4519#define mmDSCL2_LB_V_COUNTER 0x0eb5 4520#define mmDSCL2_LB_V_COUNTER_BASE_IDX 2 4521#define mmDSCL2_DSCL_MEM_PWR_CTRL 0x0eb6 4522#define mmDSCL2_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4523#define mmDSCL2_DSCL_MEM_PWR_STATUS 0x0eb7 4524#define mmDSCL2_DSCL_MEM_PWR_STATUS_BASE_IDX 2 4525#define mmDSCL2_OBUF_CONTROL 0x0eb8 4526#define mmDSCL2_OBUF_CONTROL_BASE_IDX 2 4527#define mmDSCL2_OBUF_MEM_PWR_CTRL 0x0eb9 4528#define mmDSCL2_OBUF_MEM_PWR_CTRL_BASE_IDX 2 4529 4530 4531// addressBlock: dce_dc_dpp2_dispdec_cm_dispdec 4532// base address: 0x8d8 4533#define mmCM2_CM_CONTROL 0x0ec8 4534#define mmCM2_CM_CONTROL_BASE_IDX 2 4535#define mmCM2_CM_COMA_C11_C12 0x0ec9 4536#define mmCM2_CM_COMA_C11_C12_BASE_IDX 2 4537#define mmCM2_CM_COMA_C13_C14 0x0eca 4538#define mmCM2_CM_COMA_C13_C14_BASE_IDX 2 4539#define mmCM2_CM_COMA_C21_C22 0x0ecb 4540#define mmCM2_CM_COMA_C21_C22_BASE_IDX 2 4541#define mmCM2_CM_COMA_C23_C24 0x0ecc 4542#define mmCM2_CM_COMA_C23_C24_BASE_IDX 2 4543#define mmCM2_CM_COMA_C31_C32 0x0ecd 4544#define mmCM2_CM_COMA_C31_C32_BASE_IDX 2 4545#define mmCM2_CM_COMA_C33_C34 0x0ece 4546#define mmCM2_CM_COMA_C33_C34_BASE_IDX 2 4547#define mmCM2_CM_COMB_C11_C12 0x0ecf 4548#define mmCM2_CM_COMB_C11_C12_BASE_IDX 2 4549#define mmCM2_CM_COMB_C13_C14 0x0ed0 4550#define mmCM2_CM_COMB_C13_C14_BASE_IDX 2 4551#define mmCM2_CM_COMB_C21_C22 0x0ed1 4552#define mmCM2_CM_COMB_C21_C22_BASE_IDX 2 4553#define mmCM2_CM_COMB_C23_C24 0x0ed2 4554#define mmCM2_CM_COMB_C23_C24_BASE_IDX 2 4555#define mmCM2_CM_COMB_C31_C32 0x0ed3 4556#define mmCM2_CM_COMB_C31_C32_BASE_IDX 2 4557#define mmCM2_CM_COMB_C33_C34 0x0ed4 4558#define mmCM2_CM_COMB_C33_C34_BASE_IDX 2 4559#define mmCM2_CM_IGAM_CONTROL 0x0ed5 4560#define mmCM2_CM_IGAM_CONTROL_BASE_IDX 2 4561#define mmCM2_CM_IGAM_LUT_RW_CONTROL 0x0ed6 4562#define mmCM2_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 4563#define mmCM2_CM_IGAM_LUT_RW_INDEX 0x0ed7 4564#define mmCM2_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 4565#define mmCM2_CM_IGAM_LUT_SEQ_COLOR 0x0ed8 4566#define mmCM2_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 4567#define mmCM2_CM_IGAM_LUT_30_COLOR 0x0ed9 4568#define mmCM2_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 4569#define mmCM2_CM_IGAM_LUT_PWL_DATA 0x0eda 4570#define mmCM2_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 4571#define mmCM2_CM_IGAM_LUT_AUTOFILL 0x0edb 4572#define mmCM2_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 4573#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0edc 4574#define mmCM2_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 4575#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0edd 4576#define mmCM2_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 4577#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED 0x0ede 4578#define mmCM2_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 4579#define mmCM2_CM_ICSC_CONTROL 0x0edf 4580#define mmCM2_CM_ICSC_CONTROL_BASE_IDX 2 4581#define mmCM2_CM_ICSC_C11_C12 0x0ee0 4582#define mmCM2_CM_ICSC_C11_C12_BASE_IDX 2 4583#define mmCM2_CM_ICSC_C13_C14 0x0ee1 4584#define mmCM2_CM_ICSC_C13_C14_BASE_IDX 2 4585#define mmCM2_CM_ICSC_C21_C22 0x0ee2 4586#define mmCM2_CM_ICSC_C21_C22_BASE_IDX 2 4587#define mmCM2_CM_ICSC_C23_C24 0x0ee3 4588#define mmCM2_CM_ICSC_C23_C24_BASE_IDX 2 4589#define mmCM2_CM_ICSC_C31_C32 0x0ee4 4590#define mmCM2_CM_ICSC_C31_C32_BASE_IDX 2 4591#define mmCM2_CM_ICSC_C33_C34 0x0ee5 4592#define mmCM2_CM_ICSC_C33_C34_BASE_IDX 2 4593#define mmCM2_CM_GAMUT_REMAP_CONTROL 0x0ee6 4594#define mmCM2_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 4595#define mmCM2_CM_GAMUT_REMAP_C11_C12 0x0ee7 4596#define mmCM2_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 4597#define mmCM2_CM_GAMUT_REMAP_C13_C14 0x0ee8 4598#define mmCM2_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 4599#define mmCM2_CM_GAMUT_REMAP_C21_C22 0x0ee9 4600#define mmCM2_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 4601#define mmCM2_CM_GAMUT_REMAP_C23_C24 0x0eea 4602#define mmCM2_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 4603#define mmCM2_CM_GAMUT_REMAP_C31_C32 0x0eeb 4604#define mmCM2_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 4605#define mmCM2_CM_GAMUT_REMAP_C33_C34 0x0eec 4606#define mmCM2_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 4607#define mmCM2_CM_OCSC_CONTROL 0x0eed 4608#define mmCM2_CM_OCSC_CONTROL_BASE_IDX 2 4609#define mmCM2_CM_OCSC_C11_C12 0x0eee 4610#define mmCM2_CM_OCSC_C11_C12_BASE_IDX 2 4611#define mmCM2_CM_OCSC_C13_C14 0x0eef 4612#define mmCM2_CM_OCSC_C13_C14_BASE_IDX 2 4613#define mmCM2_CM_OCSC_C21_C22 0x0ef0 4614#define mmCM2_CM_OCSC_C21_C22_BASE_IDX 2 4615#define mmCM2_CM_OCSC_C23_C24 0x0ef1 4616#define mmCM2_CM_OCSC_C23_C24_BASE_IDX 2 4617#define mmCM2_CM_OCSC_C31_C32 0x0ef2 4618#define mmCM2_CM_OCSC_C31_C32_BASE_IDX 2 4619#define mmCM2_CM_OCSC_C33_C34 0x0ef3 4620#define mmCM2_CM_OCSC_C33_C34_BASE_IDX 2 4621#define mmCM2_CM_BNS_VALUES_R 0x0ef4 4622#define mmCM2_CM_BNS_VALUES_R_BASE_IDX 2 4623#define mmCM2_CM_BNS_VALUES_G 0x0ef5 4624#define mmCM2_CM_BNS_VALUES_G_BASE_IDX 2 4625#define mmCM2_CM_BNS_VALUES_B 0x0ef6 4626#define mmCM2_CM_BNS_VALUES_B_BASE_IDX 2 4627#define mmCM2_CM_DGAM_CONTROL 0x0ef7 4628#define mmCM2_CM_DGAM_CONTROL_BASE_IDX 2 4629#define mmCM2_CM_DGAM_LUT_INDEX 0x0ef8 4630#define mmCM2_CM_DGAM_LUT_INDEX_BASE_IDX 2 4631#define mmCM2_CM_DGAM_LUT_DATA 0x0ef9 4632#define mmCM2_CM_DGAM_LUT_DATA_BASE_IDX 2 4633#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK 0x0efa 4634#define mmCM2_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 4635#define mmCM2_CM_DGAM_RAMA_START_CNTL_B 0x0efb 4636#define mmCM2_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 4637#define mmCM2_CM_DGAM_RAMA_START_CNTL_G 0x0efc 4638#define mmCM2_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 4639#define mmCM2_CM_DGAM_RAMA_START_CNTL_R 0x0efd 4640#define mmCM2_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 4641#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B 0x0efe 4642#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 4643#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G 0x0eff 4644#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 4645#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R 0x0f00 4646#define mmCM2_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 4647#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B 0x0f01 4648#define mmCM2_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4649#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B 0x0f02 4650#define mmCM2_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4651#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G 0x0f03 4652#define mmCM2_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4653#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G 0x0f04 4654#define mmCM2_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4655#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R 0x0f05 4656#define mmCM2_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4657#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R 0x0f06 4658#define mmCM2_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4659#define mmCM2_CM_DGAM_RAMA_REGION_0_1 0x0f07 4660#define mmCM2_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 4661#define mmCM2_CM_DGAM_RAMA_REGION_2_3 0x0f08 4662#define mmCM2_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 4663#define mmCM2_CM_DGAM_RAMA_REGION_4_5 0x0f09 4664#define mmCM2_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 4665#define mmCM2_CM_DGAM_RAMA_REGION_6_7 0x0f0a 4666#define mmCM2_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 4667#define mmCM2_CM_DGAM_RAMA_REGION_8_9 0x0f0b 4668#define mmCM2_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 4669#define mmCM2_CM_DGAM_RAMA_REGION_10_11 0x0f0c 4670#define mmCM2_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 4671#define mmCM2_CM_DGAM_RAMA_REGION_12_13 0x0f0d 4672#define mmCM2_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 4673#define mmCM2_CM_DGAM_RAMA_REGION_14_15 0x0f0e 4674#define mmCM2_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 4675#define mmCM2_CM_DGAM_RAMB_START_CNTL_B 0x0f0f 4676#define mmCM2_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 4677#define mmCM2_CM_DGAM_RAMB_START_CNTL_G 0x0f10 4678#define mmCM2_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 4679#define mmCM2_CM_DGAM_RAMB_START_CNTL_R 0x0f11 4680#define mmCM2_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 4681#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B 0x0f12 4682#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 4683#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G 0x0f13 4684#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 4685#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R 0x0f14 4686#define mmCM2_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 4687#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B 0x0f15 4688#define mmCM2_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4689#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B 0x0f16 4690#define mmCM2_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4691#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G 0x0f17 4692#define mmCM2_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4693#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G 0x0f18 4694#define mmCM2_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4695#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R 0x0f19 4696#define mmCM2_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4697#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R 0x0f1a 4698#define mmCM2_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4699#define mmCM2_CM_DGAM_RAMB_REGION_0_1 0x0f1b 4700#define mmCM2_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 4701#define mmCM2_CM_DGAM_RAMB_REGION_2_3 0x0f1c 4702#define mmCM2_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 4703#define mmCM2_CM_DGAM_RAMB_REGION_4_5 0x0f1d 4704#define mmCM2_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 4705#define mmCM2_CM_DGAM_RAMB_REGION_6_7 0x0f1e 4706#define mmCM2_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 4707#define mmCM2_CM_DGAM_RAMB_REGION_8_9 0x0f1f 4708#define mmCM2_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 4709#define mmCM2_CM_DGAM_RAMB_REGION_10_11 0x0f20 4710#define mmCM2_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 4711#define mmCM2_CM_DGAM_RAMB_REGION_12_13 0x0f21 4712#define mmCM2_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 4713#define mmCM2_CM_DGAM_RAMB_REGION_14_15 0x0f22 4714#define mmCM2_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 4715#define mmCM2_CM_RGAM_CONTROL 0x0f23 4716#define mmCM2_CM_RGAM_CONTROL_BASE_IDX 2 4717#define mmCM2_CM_RGAM_LUT_INDEX 0x0f24 4718#define mmCM2_CM_RGAM_LUT_INDEX_BASE_IDX 2 4719#define mmCM2_CM_RGAM_LUT_DATA 0x0f25 4720#define mmCM2_CM_RGAM_LUT_DATA_BASE_IDX 2 4721#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK 0x0f26 4722#define mmCM2_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 4723#define mmCM2_CM_RGAM_RAMA_START_CNTL_B 0x0f27 4724#define mmCM2_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 4725#define mmCM2_CM_RGAM_RAMA_START_CNTL_G 0x0f28 4726#define mmCM2_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 4727#define mmCM2_CM_RGAM_RAMA_START_CNTL_R 0x0f29 4728#define mmCM2_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 4729#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B 0x0f2a 4730#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 4731#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G 0x0f2b 4732#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 4733#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R 0x0f2c 4734#define mmCM2_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 4735#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B 0x0f2d 4736#define mmCM2_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 4737#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B 0x0f2e 4738#define mmCM2_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 4739#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G 0x0f2f 4740#define mmCM2_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 4741#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G 0x0f30 4742#define mmCM2_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 4743#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R 0x0f31 4744#define mmCM2_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 4745#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R 0x0f32 4746#define mmCM2_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 4747#define mmCM2_CM_RGAM_RAMA_REGION_0_1 0x0f33 4748#define mmCM2_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 4749#define mmCM2_CM_RGAM_RAMA_REGION_2_3 0x0f34 4750#define mmCM2_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 4751#define mmCM2_CM_RGAM_RAMA_REGION_4_5 0x0f35 4752#define mmCM2_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 4753#define mmCM2_CM_RGAM_RAMA_REGION_6_7 0x0f36 4754#define mmCM2_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 4755#define mmCM2_CM_RGAM_RAMA_REGION_8_9 0x0f37 4756#define mmCM2_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 4757#define mmCM2_CM_RGAM_RAMA_REGION_10_11 0x0f38 4758#define mmCM2_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 4759#define mmCM2_CM_RGAM_RAMA_REGION_12_13 0x0f39 4760#define mmCM2_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 4761#define mmCM2_CM_RGAM_RAMA_REGION_14_15 0x0f3a 4762#define mmCM2_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 4763#define mmCM2_CM_RGAM_RAMA_REGION_16_17 0x0f3b 4764#define mmCM2_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 4765#define mmCM2_CM_RGAM_RAMA_REGION_18_19 0x0f3c 4766#define mmCM2_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 4767#define mmCM2_CM_RGAM_RAMA_REGION_20_21 0x0f3d 4768#define mmCM2_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 4769#define mmCM2_CM_RGAM_RAMA_REGION_22_23 0x0f3e 4770#define mmCM2_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 4771#define mmCM2_CM_RGAM_RAMA_REGION_24_25 0x0f3f 4772#define mmCM2_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 4773#define mmCM2_CM_RGAM_RAMA_REGION_26_27 0x0f40 4774#define mmCM2_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 4775#define mmCM2_CM_RGAM_RAMA_REGION_28_29 0x0f41 4776#define mmCM2_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 4777#define mmCM2_CM_RGAM_RAMA_REGION_30_31 0x0f42 4778#define mmCM2_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 4779#define mmCM2_CM_RGAM_RAMA_REGION_32_33 0x0f43 4780#define mmCM2_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 4781#define mmCM2_CM_RGAM_RAMB_START_CNTL_B 0x0f44 4782#define mmCM2_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 4783#define mmCM2_CM_RGAM_RAMB_START_CNTL_G 0x0f45 4784#define mmCM2_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 4785#define mmCM2_CM_RGAM_RAMB_START_CNTL_R 0x0f46 4786#define mmCM2_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 4787#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B 0x0f47 4788#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 4789#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G 0x0f48 4790#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 4791#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R 0x0f49 4792#define mmCM2_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 4793#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B 0x0f4a 4794#define mmCM2_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 4795#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B 0x0f4b 4796#define mmCM2_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 4797#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G 0x0f4c 4798#define mmCM2_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 4799#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G 0x0f4d 4800#define mmCM2_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 4801#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R 0x0f4e 4802#define mmCM2_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 4803#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R 0x0f4f 4804#define mmCM2_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 4805#define mmCM2_CM_RGAM_RAMB_REGION_0_1 0x0f50 4806#define mmCM2_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 4807#define mmCM2_CM_RGAM_RAMB_REGION_2_3 0x0f51 4808#define mmCM2_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 4809#define mmCM2_CM_RGAM_RAMB_REGION_4_5 0x0f52 4810#define mmCM2_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 4811#define mmCM2_CM_RGAM_RAMB_REGION_6_7 0x0f53 4812#define mmCM2_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 4813#define mmCM2_CM_RGAM_RAMB_REGION_8_9 0x0f54 4814#define mmCM2_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 4815#define mmCM2_CM_RGAM_RAMB_REGION_10_11 0x0f55 4816#define mmCM2_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 4817#define mmCM2_CM_RGAM_RAMB_REGION_12_13 0x0f56 4818#define mmCM2_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 4819#define mmCM2_CM_RGAM_RAMB_REGION_14_15 0x0f57 4820#define mmCM2_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 4821#define mmCM2_CM_RGAM_RAMB_REGION_16_17 0x0f58 4822#define mmCM2_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 4823#define mmCM2_CM_RGAM_RAMB_REGION_18_19 0x0f59 4824#define mmCM2_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 4825#define mmCM2_CM_RGAM_RAMB_REGION_20_21 0x0f5a 4826#define mmCM2_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 4827#define mmCM2_CM_RGAM_RAMB_REGION_22_23 0x0f5b 4828#define mmCM2_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 4829#define mmCM2_CM_RGAM_RAMB_REGION_24_25 0x0f5c 4830#define mmCM2_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 4831#define mmCM2_CM_RGAM_RAMB_REGION_26_27 0x0f5d 4832#define mmCM2_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 4833#define mmCM2_CM_RGAM_RAMB_REGION_28_29 0x0f5e 4834#define mmCM2_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 4835#define mmCM2_CM_RGAM_RAMB_REGION_30_31 0x0f5f 4836#define mmCM2_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 4837#define mmCM2_CM_RGAM_RAMB_REGION_32_33 0x0f60 4838#define mmCM2_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 4839#define mmCM2_CM_HDR_MULT_COEF 0x0f61 4840#define mmCM2_CM_HDR_MULT_COEF_BASE_IDX 2 4841#define mmCM2_CM_RANGE_CLAMP_CONTROL_R 0x0f62 4842#define mmCM2_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 4843#define mmCM2_CM_RANGE_CLAMP_CONTROL_G 0x0f63 4844#define mmCM2_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 4845#define mmCM2_CM_RANGE_CLAMP_CONTROL_B 0x0f64 4846#define mmCM2_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 4847#define mmCM2_CM_DENORM_CONTROL 0x0f65 4848#define mmCM2_CM_DENORM_CONTROL_BASE_IDX 2 4849#define mmCM2_CM_CMOUT_CONTROL 0x0f66 4850#define mmCM2_CM_CMOUT_CONTROL_BASE_IDX 2 4851#define mmCM2_CM_CMOUT_RANDOM_SEEDS 0x0f67 4852#define mmCM2_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 4853#define mmCM2_CM_MEM_PWR_CTRL 0x0f68 4854#define mmCM2_CM_MEM_PWR_CTRL_BASE_IDX 2 4855#define mmCM2_CM_MEM_PWR_STATUS 0x0f69 4856#define mmCM2_CM_MEM_PWR_STATUS_BASE_IDX 2 4857#define mmCM2_CM_TEST_DEBUG_INDEX 0x0f6b 4858#define mmCM2_CM_TEST_DEBUG_INDEX_BASE_IDX 2 4859#define mmCM2_CM_TEST_DEBUG_DATA 0x0f6c 4860#define mmCM2_CM_TEST_DEBUG_DATA_BASE_IDX 2 4861 4862// addressBlock: dce_dc_dpp2_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 4863// base address: 0x3e08 4864#define mmDC_PERFMON14_PERFCOUNTER_CNTL 0x0f82 4865#define mmDC_PERFMON14_PERFCOUNTER_CNTL_BASE_IDX 2 4866#define mmDC_PERFMON14_PERFCOUNTER_CNTL2 0x0f83 4867#define mmDC_PERFMON14_PERFCOUNTER_CNTL2_BASE_IDX 2 4868#define mmDC_PERFMON14_PERFCOUNTER_STATE 0x0f84 4869#define mmDC_PERFMON14_PERFCOUNTER_STATE_BASE_IDX 2 4870#define mmDC_PERFMON14_PERFMON_CNTL 0x0f85 4871#define mmDC_PERFMON14_PERFMON_CNTL_BASE_IDX 2 4872#define mmDC_PERFMON14_PERFMON_CNTL2 0x0f86 4873#define mmDC_PERFMON14_PERFMON_CNTL2_BASE_IDX 2 4874#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC 0x0f87 4875#define mmDC_PERFMON14_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 4876#define mmDC_PERFMON14_PERFMON_CVALUE_LOW 0x0f88 4877#define mmDC_PERFMON14_PERFMON_CVALUE_LOW_BASE_IDX 2 4878#define mmDC_PERFMON14_PERFMON_HI 0x0f89 4879#define mmDC_PERFMON14_PERFMON_HI_BASE_IDX 2 4880#define mmDC_PERFMON14_PERFMON_LOW 0x0f8a 4881#define mmDC_PERFMON14_PERFMON_LOW_BASE_IDX 2 4882 4883 4884// addressBlock: dce_dc_dpp3_dispdec_dpp_top_dispdec 4885// base address: 0xd44 4886#define mmDPP_TOP3_DPP_CONTROL 0x0f8e 4887#define mmDPP_TOP3_DPP_CONTROL_BASE_IDX 2 4888#define mmDPP_TOP3_DPP_SOFT_RESET 0x0f8f 4889#define mmDPP_TOP3_DPP_SOFT_RESET_BASE_IDX 2 4890#define mmDPP_TOP3_DPP_CRC_VAL_R_G 0x0f90 4891#define mmDPP_TOP3_DPP_CRC_VAL_R_G_BASE_IDX 2 4892#define mmDPP_TOP3_DPP_CRC_VAL_B_A 0x0f91 4893#define mmDPP_TOP3_DPP_CRC_VAL_B_A_BASE_IDX 2 4894#define mmDPP_TOP3_DPP_CRC_CTRL 0x0f92 4895#define mmDPP_TOP3_DPP_CRC_CTRL_BASE_IDX 2 4896#define mmDPP_TOP3_HOST_READ_CONTROL 0x0f93 4897#define mmDPP_TOP3_HOST_READ_CONTROL_BASE_IDX 2 4898 4899 4900// addressBlock: dce_dc_dpp3_dispdec_cnvc_cfg_dispdec 4901// base address: 0xd44 4902#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT 0x0f98 4903#define mmCNVC_CFG3_CNVC_SURFACE_PIXEL_FORMAT_BASE_IDX 2 4904#define mmCNVC_CFG3_FORMAT_CONTROL 0x0f99 4905#define mmCNVC_CFG3_FORMAT_CONTROL_BASE_IDX 2 4906#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS 0x0f9a 4907#define mmCNVC_CFG3_FCNV_FP_SCALE_BIAS_BASE_IDX 2 4908#define mmCNVC_CFG3_DENORM_CONTROL 0x0f9b 4909#define mmCNVC_CFG3_DENORM_CONTROL_BASE_IDX 2 4910#define mmCNVC_CFG3_COLOR_KEYER_CONTROL 0x0f9d 4911#define mmCNVC_CFG3_COLOR_KEYER_CONTROL_BASE_IDX 2 4912#define mmCNVC_CFG3_COLOR_KEYER_ALPHA 0x0f9e 4913#define mmCNVC_CFG3_COLOR_KEYER_ALPHA_BASE_IDX 2 4914#define mmCNVC_CFG3_COLOR_KEYER_RED 0x0f9f 4915#define mmCNVC_CFG3_COLOR_KEYER_RED_BASE_IDX 2 4916#define mmCNVC_CFG3_COLOR_KEYER_GREEN 0x0fa0 4917#define mmCNVC_CFG3_COLOR_KEYER_GREEN_BASE_IDX 2 4918#define mmCNVC_CFG3_COLOR_KEYER_BLUE 0x0fa1 4919#define mmCNVC_CFG3_COLOR_KEYER_BLUE_BASE_IDX 2 4920 4921 4922// addressBlock: dce_dc_dpp3_dispdec_cnvc_cur_dispdec 4923// base address: 0xd44 4924#define mmCNVC_CUR3_CURSOR0_CONTROL 0x0fa9 4925#define mmCNVC_CUR3_CURSOR0_CONTROL_BASE_IDX 2 4926#define mmCNVC_CUR3_CURSOR0_COLOR0 0x0faa 4927#define mmCNVC_CUR3_CURSOR0_COLOR0_BASE_IDX 2 4928#define mmCNVC_CUR3_CURSOR0_COLOR1 0x0fab 4929#define mmCNVC_CUR3_CURSOR0_COLOR1_BASE_IDX 2 4930#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS 0x0fac 4931#define mmCNVC_CUR3_CURSOR0_FP_SCALE_BIAS_BASE_IDX 2 4932 4933 4934// addressBlock: dce_dc_dpp3_dispdec_dscl_dispdec 4935// base address: 0xd44 4936#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT 0x0fb3 4937#define mmDSCL3_SCL_COEF_RAM_TAP_SELECT_BASE_IDX 2 4938#define mmDSCL3_SCL_COEF_RAM_TAP_DATA 0x0fb4 4939#define mmDSCL3_SCL_COEF_RAM_TAP_DATA_BASE_IDX 2 4940#define mmDSCL3_SCL_MODE 0x0fb5 4941#define mmDSCL3_SCL_MODE_BASE_IDX 2 4942#define mmDSCL3_SCL_TAP_CONTROL 0x0fb6 4943#define mmDSCL3_SCL_TAP_CONTROL_BASE_IDX 2 4944#define mmDSCL3_DSCL_CONTROL 0x0fb7 4945#define mmDSCL3_DSCL_CONTROL_BASE_IDX 2 4946#define mmDSCL3_DSCL_2TAP_CONTROL 0x0fb8 4947#define mmDSCL3_DSCL_2TAP_CONTROL_BASE_IDX 2 4948#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL 0x0fb9 4949#define mmDSCL3_SCL_MANUAL_REPLICATE_CONTROL_BASE_IDX 2 4950#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO 0x0fba 4951#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_BASE_IDX 2 4952#define mmDSCL3_SCL_HORZ_FILTER_INIT 0x0fbb 4953#define mmDSCL3_SCL_HORZ_FILTER_INIT_BASE_IDX 2 4954#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C 0x0fbc 4955#define mmDSCL3_SCL_HORZ_FILTER_SCALE_RATIO_C_BASE_IDX 2 4956#define mmDSCL3_SCL_HORZ_FILTER_INIT_C 0x0fbd 4957#define mmDSCL3_SCL_HORZ_FILTER_INIT_C_BASE_IDX 2 4958#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO 0x0fbe 4959#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_BASE_IDX 2 4960#define mmDSCL3_SCL_VERT_FILTER_INIT 0x0fbf 4961#define mmDSCL3_SCL_VERT_FILTER_INIT_BASE_IDX 2 4962#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT 0x0fc0 4963#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_BASE_IDX 2 4964#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C 0x0fc1 4965#define mmDSCL3_SCL_VERT_FILTER_SCALE_RATIO_C_BASE_IDX 2 4966#define mmDSCL3_SCL_VERT_FILTER_INIT_C 0x0fc2 4967#define mmDSCL3_SCL_VERT_FILTER_INIT_C_BASE_IDX 2 4968#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C 0x0fc3 4969#define mmDSCL3_SCL_VERT_FILTER_INIT_BOT_C_BASE_IDX 2 4970#define mmDSCL3_SCL_BLACK_OFFSET 0x0fc4 4971#define mmDSCL3_SCL_BLACK_OFFSET_BASE_IDX 2 4972#define mmDSCL3_DSCL_UPDATE 0x0fc5 4973#define mmDSCL3_DSCL_UPDATE_BASE_IDX 2 4974#define mmDSCL3_DSCL_AUTOCAL 0x0fc6 4975#define mmDSCL3_DSCL_AUTOCAL_BASE_IDX 2 4976#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT 0x0fc7 4977#define mmDSCL3_DSCL_EXT_OVERSCAN_LEFT_RIGHT_BASE_IDX 2 4978#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM 0x0fc8 4979#define mmDSCL3_DSCL_EXT_OVERSCAN_TOP_BOTTOM_BASE_IDX 2 4980#define mmDSCL3_OTG_H_BLANK 0x0fc9 4981#define mmDSCL3_OTG_H_BLANK_BASE_IDX 2 4982#define mmDSCL3_OTG_V_BLANK 0x0fca 4983#define mmDSCL3_OTG_V_BLANK_BASE_IDX 2 4984#define mmDSCL3_RECOUT_START 0x0fcb 4985#define mmDSCL3_RECOUT_START_BASE_IDX 2 4986#define mmDSCL3_RECOUT_SIZE 0x0fcc 4987#define mmDSCL3_RECOUT_SIZE_BASE_IDX 2 4988#define mmDSCL3_MPC_SIZE 0x0fcd 4989#define mmDSCL3_MPC_SIZE_BASE_IDX 2 4990#define mmDSCL3_LB_DATA_FORMAT 0x0fce 4991#define mmDSCL3_LB_DATA_FORMAT_BASE_IDX 2 4992#define mmDSCL3_LB_MEMORY_CTRL 0x0fcf 4993#define mmDSCL3_LB_MEMORY_CTRL_BASE_IDX 2 4994#define mmDSCL3_LB_V_COUNTER 0x0fd0 4995#define mmDSCL3_LB_V_COUNTER_BASE_IDX 2 4996#define mmDSCL3_DSCL_MEM_PWR_CTRL 0x0fd1 4997#define mmDSCL3_DSCL_MEM_PWR_CTRL_BASE_IDX 2 4998#define mmDSCL3_DSCL_MEM_PWR_STATUS 0x0fd2 4999#define mmDSCL3_DSCL_MEM_PWR_STATUS_BASE_IDX 2 5000#define mmDSCL3_OBUF_CONTROL 0x0fd3
5001#define mmDSCL3_OBUF_CONTROL_BASE_IDX 2 5002#define mmDSCL3_OBUF_MEM_PWR_CTRL 0x0fd4 5003#define mmDSCL3_OBUF_MEM_PWR_CTRL_BASE_IDX 2 5004 5005 5006// addressBlock: dce_dc_dpp3_dispdec_cm_dispdec 5007// base address: 0xd44 5008#define mmCM3_CM_CONTROL 0x0fe3 5009#define mmCM3_CM_CONTROL_BASE_IDX 2 5010#define mmCM3_CM_COMA_C11_C12 0x0fe4 5011#define mmCM3_CM_COMA_C11_C12_BASE_IDX 2 5012#define mmCM3_CM_COMA_C13_C14 0x0fe5 5013#define mmCM3_CM_COMA_C13_C14_BASE_IDX 2 5014#define mmCM3_CM_COMA_C21_C22 0x0fe6 5015#define mmCM3_CM_COMA_C21_C22_BASE_IDX 2 5016#define mmCM3_CM_COMA_C23_C24 0x0fe7 5017#define mmCM3_CM_COMA_C23_C24_BASE_IDX 2 5018#define mmCM3_CM_COMA_C31_C32 0x0fe8 5019#define mmCM3_CM_COMA_C31_C32_BASE_IDX 2 5020#define mmCM3_CM_COMA_C33_C34 0x0fe9 5021#define mmCM3_CM_COMA_C33_C34_BASE_IDX 2 5022#define mmCM3_CM_COMB_C11_C12 0x0fea 5023#define mmCM3_CM_COMB_C11_C12_BASE_IDX 2 5024#define mmCM3_CM_COMB_C13_C14 0x0feb 5025#define mmCM3_CM_COMB_C13_C14_BASE_IDX 2 5026#define mmCM3_CM_COMB_C21_C22 0x0fec 5027#define mmCM3_CM_COMB_C21_C22_BASE_IDX 2 5028#define mmCM3_CM_COMB_C23_C24 0x0fed 5029#define mmCM3_CM_COMB_C23_C24_BASE_IDX 2 5030#define mmCM3_CM_COMB_C31_C32 0x0fee 5031#define mmCM3_CM_COMB_C31_C32_BASE_IDX 2 5032#define mmCM3_CM_COMB_C33_C34 0x0fef 5033#define mmCM3_CM_COMB_C33_C34_BASE_IDX 2 5034#define mmCM3_CM_IGAM_CONTROL 0x0ff0 5035#define mmCM3_CM_IGAM_CONTROL_BASE_IDX 2 5036#define mmCM3_CM_IGAM_LUT_RW_CONTROL 0x0ff1 5037#define mmCM3_CM_IGAM_LUT_RW_CONTROL_BASE_IDX 2 5038#define mmCM3_CM_IGAM_LUT_RW_INDEX 0x0ff2 5039#define mmCM3_CM_IGAM_LUT_RW_INDEX_BASE_IDX 2 5040#define mmCM3_CM_IGAM_LUT_SEQ_COLOR 0x0ff3 5041#define mmCM3_CM_IGAM_LUT_SEQ_COLOR_BASE_IDX 2 5042#define mmCM3_CM_IGAM_LUT_30_COLOR 0x0ff4 5043#define mmCM3_CM_IGAM_LUT_30_COLOR_BASE_IDX 2 5044#define mmCM3_CM_IGAM_LUT_PWL_DATA 0x0ff5 5045#define mmCM3_CM_IGAM_LUT_PWL_DATA_BASE_IDX 2 5046#define mmCM3_CM_IGAM_LUT_AUTOFILL 0x0ff6 5047#define mmCM3_CM_IGAM_LUT_AUTOFILL_BASE_IDX 2 5048#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE 0x0ff7 5049#define mmCM3_CM_IGAM_LUT_BW_OFFSET_BLUE_BASE_IDX 2 5050#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN 0x0ff8 5051#define mmCM3_CM_IGAM_LUT_BW_OFFSET_GREEN_BASE_IDX 2 5052#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED 0x0ff9 5053#define mmCM3_CM_IGAM_LUT_BW_OFFSET_RED_BASE_IDX 2 5054#define mmCM3_CM_ICSC_CONTROL 0x0ffa 5055#define mmCM3_CM_ICSC_CONTROL_BASE_IDX 2 5056#define mmCM3_CM_ICSC_C11_C12 0x0ffb 5057#define mmCM3_CM_ICSC_C11_C12_BASE_IDX 2 5058#define mmCM3_CM_ICSC_C13_C14 0x0ffc 5059#define mmCM3_CM_ICSC_C13_C14_BASE_IDX 2 5060#define mmCM3_CM_ICSC_C21_C22 0x0ffd 5061#define mmCM3_CM_ICSC_C21_C22_BASE_IDX 2 5062#define mmCM3_CM_ICSC_C23_C24 0x0ffe 5063#define mmCM3_CM_ICSC_C23_C24_BASE_IDX 2 5064#define mmCM3_CM_ICSC_C31_C32 0x0fff 5065#define mmCM3_CM_ICSC_C31_C32_BASE_IDX 2 5066#define mmCM3_CM_ICSC_C33_C34 0x1000 5067#define mmCM3_CM_ICSC_C33_C34_BASE_IDX 2 5068#define mmCM3_CM_GAMUT_REMAP_CONTROL 0x1001 5069#define mmCM3_CM_GAMUT_REMAP_CONTROL_BASE_IDX 2 5070#define mmCM3_CM_GAMUT_REMAP_C11_C12 0x1002 5071#define mmCM3_CM_GAMUT_REMAP_C11_C12_BASE_IDX 2 5072#define mmCM3_CM_GAMUT_REMAP_C13_C14 0x1003 5073#define mmCM3_CM_GAMUT_REMAP_C13_C14_BASE_IDX 2 5074#define mmCM3_CM_GAMUT_REMAP_C21_C22 0x1004 5075#define mmCM3_CM_GAMUT_REMAP_C21_C22_BASE_IDX 2 5076#define mmCM3_CM_GAMUT_REMAP_C23_C24 0x1005 5077#define mmCM3_CM_GAMUT_REMAP_C23_C24_BASE_IDX 2 5078#define mmCM3_CM_GAMUT_REMAP_C31_C32 0x1006 5079#define mmCM3_CM_GAMUT_REMAP_C31_C32_BASE_IDX 2 5080#define mmCM3_CM_GAMUT_REMAP_C33_C34 0x1007 5081#define mmCM3_CM_GAMUT_REMAP_C33_C34_BASE_IDX 2 5082#define mmCM3_CM_OCSC_CONTROL 0x1008 5083#define mmCM3_CM_OCSC_CONTROL_BASE_IDX 2 5084#define mmCM3_CM_OCSC_C11_C12 0x1009 5085#define mmCM3_CM_OCSC_C11_C12_BASE_IDX 2 5086#define mmCM3_CM_OCSC_C13_C14 0x100a 5087#define mmCM3_CM_OCSC_C13_C14_BASE_IDX 2 5088#define mmCM3_CM_OCSC_C21_C22 0x100b 5089#define mmCM3_CM_OCSC_C21_C22_BASE_IDX 2 5090#define mmCM3_CM_OCSC_C23_C24 0x100c 5091#define mmCM3_CM_OCSC_C23_C24_BASE_IDX 2 5092#define mmCM3_CM_OCSC_C31_C32 0x100d 5093#define mmCM3_CM_OCSC_C31_C32_BASE_IDX 2 5094#define mmCM3_CM_OCSC_C33_C34 0x100e 5095#define mmCM3_CM_OCSC_C33_C34_BASE_IDX 2 5096#define mmCM3_CM_BNS_VALUES_R 0x100f 5097#define mmCM3_CM_BNS_VALUES_R_BASE_IDX 2 5098#define mmCM3_CM_BNS_VALUES_G 0x1010 5099#define mmCM3_CM_BNS_VALUES_G_BASE_IDX 2 5100#define mmCM3_CM_BNS_VALUES_B 0x1011 5101#define mmCM3_CM_BNS_VALUES_B_BASE_IDX 2 5102#define mmCM3_CM_DGAM_CONTROL 0x1012 5103#define mmCM3_CM_DGAM_CONTROL_BASE_IDX 2 5104#define mmCM3_CM_DGAM_LUT_INDEX 0x1013 5105#define mmCM3_CM_DGAM_LUT_INDEX_BASE_IDX 2 5106#define mmCM3_CM_DGAM_LUT_DATA 0x1014 5107#define mmCM3_CM_DGAM_LUT_DATA_BASE_IDX 2 5108#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK 0x1015 5109#define mmCM3_CM_DGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 5110#define mmCM3_CM_DGAM_RAMA_START_CNTL_B 0x1016 5111#define mmCM3_CM_DGAM_RAMA_START_CNTL_B_BASE_IDX 2 5112#define mmCM3_CM_DGAM_RAMA_START_CNTL_G 0x1017 5113#define mmCM3_CM_DGAM_RAMA_START_CNTL_G_BASE_IDX 2 5114#define mmCM3_CM_DGAM_RAMA_START_CNTL_R 0x1018 5115#define mmCM3_CM_DGAM_RAMA_START_CNTL_R_BASE_IDX 2 5116#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B 0x1019 5117#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 5118#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G 0x101a 5119#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 5120#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R 0x101b 5121#define mmCM3_CM_DGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 5122#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B 0x101c 5123#define mmCM3_CM_DGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5124#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B 0x101d 5125#define mmCM3_CM_DGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5126#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G 0x101e 5127#define mmCM3_CM_DGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5128#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G 0x101f 5129#define mmCM3_CM_DGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5130#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R 0x1020 5131#define mmCM3_CM_DGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5132#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R 0x1021 5133#define mmCM3_CM_DGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5134#define mmCM3_CM_DGAM_RAMA_REGION_0_1 0x1022 5135#define mmCM3_CM_DGAM_RAMA_REGION_0_1_BASE_IDX 2 5136#define mmCM3_CM_DGAM_RAMA_REGION_2_3 0x1023 5137#define mmCM3_CM_DGAM_RAMA_REGION_2_3_BASE_IDX 2 5138#define mmCM3_CM_DGAM_RAMA_REGION_4_5 0x1024 5139#define mmCM3_CM_DGAM_RAMA_REGION_4_5_BASE_IDX 2 5140#define mmCM3_CM_DGAM_RAMA_REGION_6_7 0x1025 5141#define mmCM3_CM_DGAM_RAMA_REGION_6_7_BASE_IDX 2 5142#define mmCM3_CM_DGAM_RAMA_REGION_8_9 0x1026 5143#define mmCM3_CM_DGAM_RAMA_REGION_8_9_BASE_IDX 2 5144#define mmCM3_CM_DGAM_RAMA_REGION_10_11 0x1027 5145#define mmCM3_CM_DGAM_RAMA_REGION_10_11_BASE_IDX 2 5146#define mmCM3_CM_DGAM_RAMA_REGION_12_13 0x1028 5147#define mmCM3_CM_DGAM_RAMA_REGION_12_13_BASE_IDX 2 5148#define mmCM3_CM_DGAM_RAMA_REGION_14_15 0x1029 5149#define mmCM3_CM_DGAM_RAMA_REGION_14_15_BASE_IDX 2 5150#define mmCM3_CM_DGAM_RAMB_START_CNTL_B 0x102a 5151#define mmCM3_CM_DGAM_RAMB_START_CNTL_B_BASE_IDX 2 5152#define mmCM3_CM_DGAM_RAMB_START_CNTL_G 0x102b 5153#define mmCM3_CM_DGAM_RAMB_START_CNTL_G_BASE_IDX 2 5154#define mmCM3_CM_DGAM_RAMB_START_CNTL_R 0x102c 5155#define mmCM3_CM_DGAM_RAMB_START_CNTL_R_BASE_IDX 2 5156#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B 0x102d 5157#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 5158#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G 0x102e 5159#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 5160#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R 0x102f 5161#define mmCM3_CM_DGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 5162#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B 0x1030 5163#define mmCM3_CM_DGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5164#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B 0x1031 5165#define mmCM3_CM_DGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5166#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G 0x1032 5167#define mmCM3_CM_DGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5168#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G 0x1033 5169#define mmCM3_CM_DGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5170#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R 0x1034 5171#define mmCM3_CM_DGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5172#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R 0x1035 5173#define mmCM3_CM_DGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5174#define mmCM3_CM_DGAM_RAMB_REGION_0_1 0x1036 5175#define mmCM3_CM_DGAM_RAMB_REGION_0_1_BASE_IDX 2 5176#define mmCM3_CM_DGAM_RAMB_REGION_2_3 0x1037 5177#define mmCM3_CM_DGAM_RAMB_REGION_2_3_BASE_IDX 2 5178#define mmCM3_CM_DGAM_RAMB_REGION_4_5 0x1038 5179#define mmCM3_CM_DGAM_RAMB_REGION_4_5_BASE_IDX 2 5180#define mmCM3_CM_DGAM_RAMB_REGION_6_7 0x1039 5181#define mmCM3_CM_DGAM_RAMB_REGION_6_7_BASE_IDX 2 5182#define mmCM3_CM_DGAM_RAMB_REGION_8_9 0x103a 5183#define mmCM3_CM_DGAM_RAMB_REGION_8_9_BASE_IDX 2 5184#define mmCM3_CM_DGAM_RAMB_REGION_10_11 0x103b 5185#define mmCM3_CM_DGAM_RAMB_REGION_10_11_BASE_IDX 2 5186#define mmCM3_CM_DGAM_RAMB_REGION_12_13 0x103c 5187#define mmCM3_CM_DGAM_RAMB_REGION_12_13_BASE_IDX 2 5188#define mmCM3_CM_DGAM_RAMB_REGION_14_15 0x103d 5189#define mmCM3_CM_DGAM_RAMB_REGION_14_15_BASE_IDX 2 5190#define mmCM3_CM_RGAM_CONTROL 0x103e 5191#define mmCM3_CM_RGAM_CONTROL_BASE_IDX 2 5192#define mmCM3_CM_RGAM_LUT_INDEX 0x103f 5193#define mmCM3_CM_RGAM_LUT_INDEX_BASE_IDX 2 5194#define mmCM3_CM_RGAM_LUT_DATA 0x1040 5195#define mmCM3_CM_RGAM_LUT_DATA_BASE_IDX 2 5196#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK 0x1041 5197#define mmCM3_CM_RGAM_LUT_WRITE_EN_MASK_BASE_IDX 2 5198#define mmCM3_CM_RGAM_RAMA_START_CNTL_B 0x1042 5199#define mmCM3_CM_RGAM_RAMA_START_CNTL_B_BASE_IDX 2 5200#define mmCM3_CM_RGAM_RAMA_START_CNTL_G 0x1043 5201#define mmCM3_CM_RGAM_RAMA_START_CNTL_G_BASE_IDX 2 5202#define mmCM3_CM_RGAM_RAMA_START_CNTL_R 0x1044 5203#define mmCM3_CM_RGAM_RAMA_START_CNTL_R_BASE_IDX 2 5204#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B 0x1045 5205#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_B_BASE_IDX 2 5206#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G 0x1046 5207#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_G_BASE_IDX 2 5208#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R 0x1047 5209#define mmCM3_CM_RGAM_RAMA_SLOPE_CNTL_R_BASE_IDX 2 5210#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B 0x1048 5211#define mmCM3_CM_RGAM_RAMA_END_CNTL1_B_BASE_IDX 2 5212#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B 0x1049 5213#define mmCM3_CM_RGAM_RAMA_END_CNTL2_B_BASE_IDX 2 5214#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G 0x104a 5215#define mmCM3_CM_RGAM_RAMA_END_CNTL1_G_BASE_IDX 2 5216#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G 0x104b 5217#define mmCM3_CM_RGAM_RAMA_END_CNTL2_G_BASE_IDX 2 5218#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R 0x104c 5219#define mmCM3_CM_RGAM_RAMA_END_CNTL1_R_BASE_IDX 2 5220#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R 0x104d 5221#define mmCM3_CM_RGAM_RAMA_END_CNTL2_R_BASE_IDX 2 5222#define mmCM3_CM_RGAM_RAMA_REGION_0_1 0x104e 5223#define mmCM3_CM_RGAM_RAMA_REGION_0_1_BASE_IDX 2 5224#define mmCM3_CM_RGAM_RAMA_REGION_2_3 0x104f 5225#define mmCM3_CM_RGAM_RAMA_REGION_2_3_BASE_IDX 2 5226#define mmCM3_CM_RGAM_RAMA_REGION_4_5 0x1050 5227#define mmCM3_CM_RGAM_RAMA_REGION_4_5_BASE_IDX 2 5228#define mmCM3_CM_RGAM_RAMA_REGION_6_7 0x1051 5229#define mmCM3_CM_RGAM_RAMA_REGION_6_7_BASE_IDX 2 5230#define mmCM3_CM_RGAM_RAMA_REGION_8_9 0x1052 5231#define mmCM3_CM_RGAM_RAMA_REGION_8_9_BASE_IDX 2 5232#define mmCM3_CM_RGAM_RAMA_REGION_10_11 0x1053 5233#define mmCM3_CM_RGAM_RAMA_REGION_10_11_BASE_IDX 2 5234#define mmCM3_CM_RGAM_RAMA_REGION_12_13 0x1054 5235#define mmCM3_CM_RGAM_RAMA_REGION_12_13_BASE_IDX 2 5236#define mmCM3_CM_RGAM_RAMA_REGION_14_15 0x1055 5237#define mmCM3_CM_RGAM_RAMA_REGION_14_15_BASE_IDX 2 5238#define mmCM3_CM_RGAM_RAMA_REGION_16_17 0x1056 5239#define mmCM3_CM_RGAM_RAMA_REGION_16_17_BASE_IDX 2 5240#define mmCM3_CM_RGAM_RAMA_REGION_18_19 0x1057 5241#define mmCM3_CM_RGAM_RAMA_REGION_18_19_BASE_IDX 2 5242#define mmCM3_CM_RGAM_RAMA_REGION_20_21 0x1058 5243#define mmCM3_CM_RGAM_RAMA_REGION_20_21_BASE_IDX 2 5244#define mmCM3_CM_RGAM_RAMA_REGION_22_23 0x1059 5245#define mmCM3_CM_RGAM_RAMA_REGION_22_23_BASE_IDX 2 5246#define mmCM3_CM_RGAM_RAMA_REGION_24_25 0x105a 5247#define mmCM3_CM_RGAM_RAMA_REGION_24_25_BASE_IDX 2 5248#define mmCM3_CM_RGAM_RAMA_REGION_26_27 0x105b 5249#define mmCM3_CM_RGAM_RAMA_REGION_26_27_BASE_IDX 2 5250#define mmCM3_CM_RGAM_RAMA_REGION_28_29 0x105c 5251#define mmCM3_CM_RGAM_RAMA_REGION_28_29_BASE_IDX 2 5252#define mmCM3_CM_RGAM_RAMA_REGION_30_31 0x105d 5253#define mmCM3_CM_RGAM_RAMA_REGION_30_31_BASE_IDX 2 5254#define mmCM3_CM_RGAM_RAMA_REGION_32_33 0x105e 5255#define mmCM3_CM_RGAM_RAMA_REGION_32_33_BASE_IDX 2 5256#define mmCM3_CM_RGAM_RAMB_START_CNTL_B 0x105f 5257#define mmCM3_CM_RGAM_RAMB_START_CNTL_B_BASE_IDX 2 5258#define mmCM3_CM_RGAM_RAMB_START_CNTL_G 0x1060 5259#define mmCM3_CM_RGAM_RAMB_START_CNTL_G_BASE_IDX 2 5260#define mmCM3_CM_RGAM_RAMB_START_CNTL_R 0x1061 5261#define mmCM3_CM_RGAM_RAMB_START_CNTL_R_BASE_IDX 2 5262#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B 0x1062 5263#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_B_BASE_IDX 2 5264#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G 0x1063 5265#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_G_BASE_IDX 2 5266#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R 0x1064 5267#define mmCM3_CM_RGAM_RAMB_SLOPE_CNTL_R_BASE_IDX 2 5268#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B 0x1065 5269#define mmCM3_CM_RGAM_RAMB_END_CNTL1_B_BASE_IDX 2 5270#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B 0x1066 5271#define mmCM3_CM_RGAM_RAMB_END_CNTL2_B_BASE_IDX 2 5272#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G 0x1067 5273#define mmCM3_CM_RGAM_RAMB_END_CNTL1_G_BASE_IDX 2 5274#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G 0x1068 5275#define mmCM3_CM_RGAM_RAMB_END_CNTL2_G_BASE_IDX 2 5276#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R 0x1069 5277#define mmCM3_CM_RGAM_RAMB_END_CNTL1_R_BASE_IDX 2 5278#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R 0x106a 5279#define mmCM3_CM_RGAM_RAMB_END_CNTL2_R_BASE_IDX 2 5280#define mmCM3_CM_RGAM_RAMB_REGION_0_1 0x106b 5281#define mmCM3_CM_RGAM_RAMB_REGION_0_1_BASE_IDX 2 5282#define mmCM3_CM_RGAM_RAMB_REGION_2_3 0x106c 5283#define mmCM3_CM_RGAM_RAMB_REGION_2_3_BASE_IDX 2 5284#define mmCM3_CM_RGAM_RAMB_REGION_4_5 0x106d 5285#define mmCM3_CM_RGAM_RAMB_REGION_4_5_BASE_IDX 2 5286#define mmCM3_CM_RGAM_RAMB_REGION_6_7 0x106e 5287#define mmCM3_CM_RGAM_RAMB_REGION_6_7_BASE_IDX 2 5288#define mmCM3_CM_RGAM_RAMB_REGION_8_9 0x106f 5289#define mmCM3_CM_RGAM_RAMB_REGION_8_9_BASE_IDX 2 5290#define mmCM3_CM_RGAM_RAMB_REGION_10_11 0x1070 5291#define mmCM3_CM_RGAM_RAMB_REGION_10_11_BASE_IDX 2 5292#define mmCM3_CM_RGAM_RAMB_REGION_12_13 0x1071 5293#define mmCM3_CM_RGAM_RAMB_REGION_12_13_BASE_IDX 2 5294#define mmCM3_CM_RGAM_RAMB_REGION_14_15 0x1072 5295#define mmCM3_CM_RGAM_RAMB_REGION_14_15_BASE_IDX 2 5296#define mmCM3_CM_RGAM_RAMB_REGION_16_17 0x1073 5297#define mmCM3_CM_RGAM_RAMB_REGION_16_17_BASE_IDX 2 5298#define mmCM3_CM_RGAM_RAMB_REGION_18_19 0x1074 5299#define mmCM3_CM_RGAM_RAMB_REGION_18_19_BASE_IDX 2 5300#define mmCM3_CM_RGAM_RAMB_REGION_20_21 0x1075 5301#define mmCM3_CM_RGAM_RAMB_REGION_20_21_BASE_IDX 2 5302#define mmCM3_CM_RGAM_RAMB_REGION_22_23 0x1076 5303#define mmCM3_CM_RGAM_RAMB_REGION_22_23_BASE_IDX 2 5304#define mmCM3_CM_RGAM_RAMB_REGION_24_25 0x1077 5305#define mmCM3_CM_RGAM_RAMB_REGION_24_25_BASE_IDX 2 5306#define mmCM3_CM_RGAM_RAMB_REGION_26_27 0x1078 5307#define mmCM3_CM_RGAM_RAMB_REGION_26_27_BASE_IDX 2 5308#define mmCM3_CM_RGAM_RAMB_REGION_28_29 0x1079 5309#define mmCM3_CM_RGAM_RAMB_REGION_28_29_BASE_IDX 2 5310#define mmCM3_CM_RGAM_RAMB_REGION_30_31 0x107a 5311#define mmCM3_CM_RGAM_RAMB_REGION_30_31_BASE_IDX 2 5312#define mmCM3_CM_RGAM_RAMB_REGION_32_33 0x107b 5313#define mmCM3_CM_RGAM_RAMB_REGION_32_33_BASE_IDX 2 5314#define mmCM3_CM_HDR_MULT_COEF 0x107c 5315#define mmCM3_CM_HDR_MULT_COEF_BASE_IDX 2 5316#define mmCM3_CM_RANGE_CLAMP_CONTROL_R 0x107d 5317#define mmCM3_CM_RANGE_CLAMP_CONTROL_R_BASE_IDX 2 5318#define mmCM3_CM_RANGE_CLAMP_CONTROL_G 0x107e 5319#define mmCM3_CM_RANGE_CLAMP_CONTROL_G_BASE_IDX 2 5320#define mmCM3_CM_RANGE_CLAMP_CONTROL_B 0x107f 5321#define mmCM3_CM_RANGE_CLAMP_CONTROL_B_BASE_IDX 2 5322#define mmCM3_CM_DENORM_CONTROL 0x1080 5323#define mmCM3_CM_DENORM_CONTROL_BASE_IDX 2 5324#define mmCM3_CM_CMOUT_CONTROL 0x1081 5325#define mmCM3_CM_CMOUT_CONTROL_BASE_IDX 2 5326#define mmCM3_CM_CMOUT_RANDOM_SEEDS 0x1082 5327#define mmCM3_CM_CMOUT_RANDOM_SEEDS_BASE_IDX 2 5328#define mmCM3_CM_MEM_PWR_CTRL 0x1083 5329#define mmCM3_CM_MEM_PWR_CTRL_BASE_IDX 2 5330#define mmCM3_CM_MEM_PWR_STATUS 0x1084 5331#define mmCM3_CM_MEM_PWR_STATUS_BASE_IDX 2 5332#define mmCM3_CM_TEST_DEBUG_INDEX 0x1086 5333#define mmCM3_CM_TEST_DEBUG_INDEX_BASE_IDX 2 5334#define mmCM3_CM_TEST_DEBUG_DATA 0x1087 5335#define mmCM3_CM_TEST_DEBUG_DATA_BASE_IDX 2 5336 5337// addressBlock: dce_dc_dpp3_dispdec_dpp_dcperfmon_dc_perfmon_dispdec 5338// base address: 0x4274 5339#define mmDC_PERFMON15_PERFCOUNTER_CNTL 0x109d 5340#define mmDC_PERFMON15_PERFCOUNTER_CNTL_BASE_IDX 2 5341#define mmDC_PERFMON15_PERFCOUNTER_CNTL2 0x109e 5342#define mmDC_PERFMON15_PERFCOUNTER_CNTL2_BASE_IDX 2 5343#define mmDC_PERFMON15_PERFCOUNTER_STATE 0x109f 5344#define mmDC_PERFMON15_PERFCOUNTER_STATE_BASE_IDX 2 5345#define mmDC_PERFMON15_PERFMON_CNTL 0x10a0 5346#define mmDC_PERFMON15_PERFMON_CNTL_BASE_IDX 2 5347#define mmDC_PERFMON15_PERFMON_CNTL2 0x10a1 5348#define mmDC_PERFMON15_PERFMON_CNTL2_BASE_IDX 2 5349#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC 0x10a2 5350#define mmDC_PERFMON15_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5351#define mmDC_PERFMON15_PERFMON_CVALUE_LOW 0x10a3 5352#define mmDC_PERFMON15_PERFMON_CVALUE_LOW_BASE_IDX 2 5353#define mmDC_PERFMON15_PERFMON_HI 0x10a4 5354#define mmDC_PERFMON15_PERFMON_HI_BASE_IDX 2 5355#define mmDC_PERFMON15_PERFMON_LOW 0x10a5 5356#define mmDC_PERFMON15_PERFMON_LOW_BASE_IDX 2 5357 5358 5359// addressBlock: dce_dc_mpc_mpcc0_dispdec 5360// base address: 0x0 5361#define mmMPCC0_MPCC_TOP_SEL 0x1630 5362#define mmMPCC0_MPCC_TOP_SEL_BASE_IDX 2 5363#define mmMPCC0_MPCC_BOT_SEL 0x1631 5364#define mmMPCC0_MPCC_BOT_SEL_BASE_IDX 2 5365#define mmMPCC0_MPCC_OPP_ID 0x1632 5366#define mmMPCC0_MPCC_OPP_ID_BASE_IDX 2 5367#define mmMPCC0_MPCC_CONTROL 0x1633 5368#define mmMPCC0_MPCC_CONTROL_BASE_IDX 2 5369#define mmMPCC0_MPCC_SM_CONTROL 0x1634 5370#define mmMPCC0_MPCC_SM_CONTROL_BASE_IDX 2 5371#define mmMPCC0_MPCC_UPDATE_LOCK_SEL 0x1635 5372#define mmMPCC0_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 5373#define mmMPCC0_MPCC_TOP_OFFSET 0x1636 5374#define mmMPCC0_MPCC_TOP_OFFSET_BASE_IDX 2 5375#define mmMPCC0_MPCC_BOT_OFFSET 0x1637 5376#define mmMPCC0_MPCC_BOT_OFFSET_BASE_IDX 2 5377#define mmMPCC0_MPCC_OFFSET 0x1638 5378#define mmMPCC0_MPCC_OFFSET_BASE_IDX 2 5379#define mmMPCC0_MPCC_BG_R_CR 0x1639 5380#define mmMPCC0_MPCC_BG_R_CR_BASE_IDX 2 5381#define mmMPCC0_MPCC_BG_G_Y 0x163a 5382#define mmMPCC0_MPCC_BG_G_Y_BASE_IDX 2 5383#define mmMPCC0_MPCC_BG_B_CB 0x163b 5384#define mmMPCC0_MPCC_BG_B_CB_BASE_IDX 2 5385#define mmMPCC0_MPCC_STALL_STATUS 0x163c 5386#define mmMPCC0_MPCC_STALL_STATUS_BASE_IDX 2 5387#define mmMPCC0_MPCC_STATUS 0x163d 5388#define mmMPCC0_MPCC_STATUS_BASE_IDX 2 5389 5390 5391// addressBlock: dce_dc_mpc_mpcc1_dispdec 5392// base address: 0x6c 5393#define mmMPCC1_MPCC_TOP_SEL 0x164b 5394#define mmMPCC1_MPCC_TOP_SEL_BASE_IDX 2 5395#define mmMPCC1_MPCC_BOT_SEL 0x164c 5396#define mmMPCC1_MPCC_BOT_SEL_BASE_IDX 2 5397#define mmMPCC1_MPCC_OPP_ID 0x164d 5398#define mmMPCC1_MPCC_OPP_ID_BASE_IDX 2 5399#define mmMPCC1_MPCC_CONTROL 0x164e 5400#define mmMPCC1_MPCC_CONTROL_BASE_IDX 2 5401#define mmMPCC1_MPCC_SM_CONTROL 0x164f 5402#define mmMPCC1_MPCC_SM_CONTROL_BASE_IDX 2 5403#define mmMPCC1_MPCC_UPDATE_LOCK_SEL 0x1650 5404#define mmMPCC1_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 5405#define mmMPCC1_MPCC_TOP_OFFSET 0x1651 5406#define mmMPCC1_MPCC_TOP_OFFSET_BASE_IDX 2 5407#define mmMPCC1_MPCC_BOT_OFFSET 0x1652 5408#define mmMPCC1_MPCC_BOT_OFFSET_BASE_IDX 2 5409#define mmMPCC1_MPCC_OFFSET 0x1653 5410#define mmMPCC1_MPCC_OFFSET_BASE_IDX 2 5411#define mmMPCC1_MPCC_BG_R_CR 0x1654 5412#define mmMPCC1_MPCC_BG_R_CR_BASE_IDX 2 5413#define mmMPCC1_MPCC_BG_G_Y 0x1655 5414#define mmMPCC1_MPCC_BG_G_Y_BASE_IDX 2 5415#define mmMPCC1_MPCC_BG_B_CB 0x1656 5416#define mmMPCC1_MPCC_BG_B_CB_BASE_IDX 2 5417#define mmMPCC1_MPCC_STALL_STATUS 0x1657 5418#define mmMPCC1_MPCC_STALL_STATUS_BASE_IDX 2 5419#define mmMPCC1_MPCC_STATUS 0x1658 5420#define mmMPCC1_MPCC_STATUS_BASE_IDX 2 5421 5422 5423// addressBlock: dce_dc_mpc_mpcc2_dispdec 5424// base address: 0xd8 5425#define mmMPCC2_MPCC_TOP_SEL 0x1666 5426#define mmMPCC2_MPCC_TOP_SEL_BASE_IDX 2 5427#define mmMPCC2_MPCC_BOT_SEL 0x1667 5428#define mmMPCC2_MPCC_BOT_SEL_BASE_IDX 2 5429#define mmMPCC2_MPCC_OPP_ID 0x1668 5430#define mmMPCC2_MPCC_OPP_ID_BASE_IDX 2 5431#define mmMPCC2_MPCC_CONTROL 0x1669 5432#define mmMPCC2_MPCC_CONTROL_BASE_IDX 2 5433#define mmMPCC2_MPCC_SM_CONTROL 0x166a 5434#define mmMPCC2_MPCC_SM_CONTROL_BASE_IDX 2 5435#define mmMPCC2_MPCC_UPDATE_LOCK_SEL 0x166b 5436#define mmMPCC2_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 5437#define mmMPCC2_MPCC_TOP_OFFSET 0x166c 5438#define mmMPCC2_MPCC_TOP_OFFSET_BASE_IDX 2 5439#define mmMPCC2_MPCC_BOT_OFFSET 0x166d 5440#define mmMPCC2_MPCC_BOT_OFFSET_BASE_IDX 2 5441#define mmMPCC2_MPCC_OFFSET 0x166e 5442#define mmMPCC2_MPCC_OFFSET_BASE_IDX 2 5443#define mmMPCC2_MPCC_BG_R_CR 0x166f 5444#define mmMPCC2_MPCC_BG_R_CR_BASE_IDX 2 5445#define mmMPCC2_MPCC_BG_G_Y 0x1670 5446#define mmMPCC2_MPCC_BG_G_Y_BASE_IDX 2 5447#define mmMPCC2_MPCC_BG_B_CB 0x1671 5448#define mmMPCC2_MPCC_BG_B_CB_BASE_IDX 2 5449#define mmMPCC2_MPCC_STALL_STATUS 0x1672 5450#define mmMPCC2_MPCC_STALL_STATUS_BASE_IDX 2 5451#define mmMPCC2_MPCC_STATUS 0x1673 5452#define mmMPCC2_MPCC_STATUS_BASE_IDX 2 5453 5454 5455// addressBlock: dce_dc_mpc_mpcc3_dispdec 5456// base address: 0x144 5457#define mmMPCC3_MPCC_TOP_SEL 0x1681 5458#define mmMPCC3_MPCC_TOP_SEL_BASE_IDX 2 5459#define mmMPCC3_MPCC_BOT_SEL 0x1682 5460#define mmMPCC3_MPCC_BOT_SEL_BASE_IDX 2 5461#define mmMPCC3_MPCC_OPP_ID 0x1683 5462#define mmMPCC3_MPCC_OPP_ID_BASE_IDX 2 5463#define mmMPCC3_MPCC_CONTROL 0x1684 5464#define mmMPCC3_MPCC_CONTROL_BASE_IDX 2 5465#define mmMPCC3_MPCC_SM_CONTROL 0x1685 5466#define mmMPCC3_MPCC_SM_CONTROL_BASE_IDX 2 5467#define mmMPCC3_MPCC_UPDATE_LOCK_SEL 0x1686 5468#define mmMPCC3_MPCC_UPDATE_LOCK_SEL_BASE_IDX 2 5469#define mmMPCC3_MPCC_TOP_OFFSET 0x1687 5470#define mmMPCC3_MPCC_TOP_OFFSET_BASE_IDX 2 5471#define mmMPCC3_MPCC_BOT_OFFSET 0x1688 5472#define mmMPCC3_MPCC_BOT_OFFSET_BASE_IDX 2 5473#define mmMPCC3_MPCC_OFFSET 0x1689 5474#define mmMPCC3_MPCC_OFFSET_BASE_IDX 2 5475#define mmMPCC3_MPCC_BG_R_CR 0x168a 5476#define mmMPCC3_MPCC_BG_R_CR_BASE_IDX 2 5477#define mmMPCC3_MPCC_BG_G_Y 0x168b 5478#define mmMPCC3_MPCC_BG_G_Y_BASE_IDX 2 5479#define mmMPCC3_MPCC_BG_B_CB 0x168c 5480#define mmMPCC3_MPCC_BG_B_CB_BASE_IDX 2 5481#define mmMPCC3_MPCC_STALL_STATUS 0x168d 5482#define mmMPCC3_MPCC_STALL_STATUS_BASE_IDX 2 5483#define mmMPCC3_MPCC_STATUS 0x168e 5484#define mmMPCC3_MPCC_STATUS_BASE_IDX 2 5485 5486 5487// addressBlock: dce_dc_mpc_mpc_cfg_dispdec 5488// base address: 0x0 5489#define mmMPC_CLOCK_CONTROL 0x1723 5490#define mmMPC_CLOCK_CONTROL_BASE_IDX 2 5491#define mmMPC_SOFT_RESET 0x1724 5492#define mmMPC_SOFT_RESET_BASE_IDX 2 5493#define mmMPC_CRC_CTRL 0x1725 5494#define mmMPC_CRC_CTRL_BASE_IDX 2 5495#define mmMPC_CRC_SEL_CONTROL 0x1726 5496#define mmMPC_CRC_SEL_CONTROL_BASE_IDX 2 5497#define mmMPC_CRC_RESULT_AR 0x1727 5498#define mmMPC_CRC_RESULT_AR_BASE_IDX 2 5499#define mmMPC_CRC_RESULT_GB 0x1728 5500#define mmMPC_CRC_RESULT_GB_BASE_IDX 2 5501#define mmMPC_CRC_RESULT_C 0x1729 5502#define mmMPC_CRC_RESULT_C_BASE_IDX 2 5503#define mmMPC_PERFMON_EVENT_CTRL 0x172c 5504#define mmMPC_PERFMON_EVENT_CTRL_BASE_IDX 2 5505#define mmMPC_BYPASS_BG_AR 0x172d 5506#define mmMPC_BYPASS_BG_AR_BASE_IDX 2 5507#define mmMPC_BYPASS_BG_GB 0x172e 5508#define mmMPC_BYPASS_BG_GB_BASE_IDX 2 5509#define mmMPC_OUT0_MUX 0x172f 5510#define mmMPC_OUT0_MUX_BASE_IDX 2 5511#define mmMPC_OUT1_MUX 0x1730 5512#define mmMPC_OUT1_MUX_BASE_IDX 2 5513#define mmMPC_OUT2_MUX 0x1731 5514#define mmMPC_OUT2_MUX_BASE_IDX 2 5515#define mmMPC_OUT3_MUX 0x1732 5516#define mmMPC_OUT3_MUX_BASE_IDX 2 5517#define mmMPC_STALL_GRACE_WINDOW 0x1756 5518#define mmMPC_STALL_GRACE_WINDOW_BASE_IDX 2 5519#define mmADR_CFG_VUPDATE_LOCK_SET0 0x175b 5520#define mmADR_CFG_VUPDATE_LOCK_SET0_BASE_IDX 2 5521#define mmADR_VUPDATE_LOCK_SET0 0x175c 5522#define mmADR_VUPDATE_LOCK_SET0_BASE_IDX 2 5523#define mmCUR0_VUPDATE_LOCK_SET0 0x175d 5524#define mmCUR0_VUPDATE_LOCK_SET0_BASE_IDX 2 5525#define mmCUR1_VUPDATE_LOCK_SET0 0x175e 5526#define mmCUR1_VUPDATE_LOCK_SET0_BASE_IDX 2 5527#define mmADR_CFG_VUPDATE_LOCK_SET1 0x175f 5528#define mmADR_CFG_VUPDATE_LOCK_SET1_BASE_IDX 2 5529#define mmADR_VUPDATE_LOCK_SET1 0x1760 5530#define mmADR_VUPDATE_LOCK_SET1_BASE_IDX 2 5531#define mmCUR0_VUPDATE_LOCK_SET1 0x1761 5532#define mmCUR0_VUPDATE_LOCK_SET1_BASE_IDX 2 5533#define mmCUR1_VUPDATE_LOCK_SET1 0x1762 5534#define mmCUR1_VUPDATE_LOCK_SET1_BASE_IDX 2 5535#define mmADR_CFG_VUPDATE_LOCK_SET2 0x1763 5536#define mmADR_CFG_VUPDATE_LOCK_SET2_BASE_IDX 2 5537#define mmADR_VUPDATE_LOCK_SET2 0x1764 5538#define mmADR_VUPDATE_LOCK_SET2_BASE_IDX 2 5539#define mmCUR0_VUPDATE_LOCK_SET2 0x1765 5540#define mmCUR0_VUPDATE_LOCK_SET2_BASE_IDX 2 5541#define mmCUR1_VUPDATE_LOCK_SET2 0x1766 5542#define mmCUR1_VUPDATE_LOCK_SET2_BASE_IDX 2 5543#define mmADR_CFG_VUPDATE_LOCK_SET3 0x1767 5544#define mmADR_CFG_VUPDATE_LOCK_SET3_BASE_IDX 2 5545#define mmADR_VUPDATE_LOCK_SET3 0x1768 5546#define mmADR_VUPDATE_LOCK_SET3_BASE_IDX 2 5547#define mmCUR0_VUPDATE_LOCK_SET3 0x1769 5548#define mmCUR0_VUPDATE_LOCK_SET3_BASE_IDX 2 5549#define mmCUR1_VUPDATE_LOCK_SET3 0x176a 5550#define mmCUR1_VUPDATE_LOCK_SET3_BASE_IDX 2 5551 5552 5553// addressBlock: dce_dc_mpc_mpc_dcperfmon_dc_perfmon_dispdec 5554// base address: 0x5e90 5555#define mmDC_PERFMON16_PERFCOUNTER_CNTL 0x17a4 5556#define mmDC_PERFMON16_PERFCOUNTER_CNTL_BASE_IDX 2 5557#define mmDC_PERFMON16_PERFCOUNTER_CNTL2 0x17a5 5558#define mmDC_PERFMON16_PERFCOUNTER_CNTL2_BASE_IDX 2 5559#define mmDC_PERFMON16_PERFCOUNTER_STATE 0x17a6 5560#define mmDC_PERFMON16_PERFCOUNTER_STATE_BASE_IDX 2 5561#define mmDC_PERFMON16_PERFMON_CNTL 0x17a7 5562#define mmDC_PERFMON16_PERFMON_CNTL_BASE_IDX 2 5563#define mmDC_PERFMON16_PERFMON_CNTL2 0x17a8 5564#define mmDC_PERFMON16_PERFMON_CNTL2_BASE_IDX 2 5565#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC 0x17a9 5566#define mmDC_PERFMON16_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 5567#define mmDC_PERFMON16_PERFMON_CVALUE_LOW 0x17aa 5568#define mmDC_PERFMON16_PERFMON_CVALUE_LOW_BASE_IDX 2 5569#define mmDC_PERFMON16_PERFMON_HI 0x17ab 5570#define mmDC_PERFMON16_PERFMON_HI_BASE_IDX 2 5571#define mmDC_PERFMON16_PERFMON_LOW 0x17ac 5572#define mmDC_PERFMON16_PERFMON_LOW_BASE_IDX 2 5573 5574 5575// addressBlock: dce_dc_opp_abm0_dispdec 5576// base address: 0x0 5577#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17b0 5578#define mmABM0_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2 5579#define mmABM0_BL1_PWM_USER_LEVEL 0x17b1 5580#define mmABM0_BL1_PWM_USER_LEVEL_BASE_IDX 2 5581#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL 0x17b2 5582#define mmABM0_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2 5583#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL 0x17b3 5584#define mmABM0_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2 5585#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE 0x17b4 5586#define mmABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2 5587#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17b5 5588#define mmABM0_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2 5589#define mmABM0_BL1_PWM_ABM_CNTL 0x17b6 5590#define mmABM0_BL1_PWM_ABM_CNTL_BASE_IDX 2 5591#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17b7 5592#define mmABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2 5593#define mmABM0_BL1_PWM_GRP2_REG_LOCK 0x17b8 5594#define mmABM0_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2 5595#define mmABM0_DC_ABM1_CNTL 0x17b9 5596#define mmABM0_DC_ABM1_CNTL_BASE_IDX 2 5597#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL 0x17ba 5598#define mmABM0_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2 5599#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0 0x17bb 5600#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2 5601#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1 0x17bc 5602#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2 5603#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2 0x17bd 5604#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2 5605#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3 0x17be 5606#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2 5607#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4 0x17bf 5608#define mmABM0_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2 5609#define mmABM0_DC_ABM1_ACE_THRES_12 0x17c0 5610#define mmABM0_DC_ABM1_ACE_THRES_12_BASE_IDX 2 5611#define mmABM0_DC_ABM1_ACE_THRES_34 0x17c1 5612#define mmABM0_DC_ABM1_ACE_THRES_34_BASE_IDX 2 5613#define mmABM0_DC_ABM1_ACE_CNTL_MISC 0x17c2 5614#define mmABM0_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2 5615#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS 0x17c4 5616#define mmABM0_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2 5617#define mmABM0_DC_ABM1_HG_MISC_CTRL 0x17c5 5618#define mmABM0_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2 5619#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA 0x17c6 5620#define mmABM0_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2 5621#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA 0x17c7 5622#define mmABM0_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2 5623#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x17c8 5624#define mmABM0_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2 5625#define mmABM0_DC_ABM1_LS_PIXEL_COUNT 0x17c9 5626#define mmABM0_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2 5627#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x17ca 5628#define mmABM0_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2 5629#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x17cb 5630#define mmABM0_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2 5631#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x17cc 5632#define mmABM0_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2 5633#define mmABM0_DC_ABM1_HG_SAMPLE_RATE 0x17cd 5634#define mmABM0_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2 5635#define mmABM0_DC_ABM1_LS_SAMPLE_RATE 0x17ce 5636#define mmABM0_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2 5637#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x17cf 5638#define mmABM0_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2 5639#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x17d0 5640#define mmABM0_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2 5641#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x17d1 5642#define mmABM0_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2 5643#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x17d2 5644#define mmABM0_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2 5645#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x17d3 5646#define mmABM0_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2 5647#define mmABM0_DC_ABM1_HG_RESULT_1 0x17d4 5648#define mmABM0_DC_ABM1_HG_RESULT_1_BASE_IDX 2 5649#define mmABM0_DC_ABM1_HG_RESULT_2 0x17d5 5650#define mmABM0_DC_ABM1_HG_RESULT_2_BASE_IDX 2 5651#define mmABM0_DC_ABM1_HG_RESULT_3 0x17d6 5652#define mmABM0_DC_ABM1_HG_RESULT_3_BASE_IDX 2 5653#define mmABM0_DC_ABM1_HG_RESULT_4 0x17d7 5654#define mmABM0_DC_ABM1_HG_RESULT_4_BASE_IDX 2 5655#define mmABM0_DC_ABM1_HG_RESULT_5 0x17d8 5656#define mmABM0_DC_ABM1_HG_RESULT_5_BASE_IDX 2 5657#define mmABM0_DC_ABM1_HG_RESULT_6 0x17d9 5658#define mmABM0_DC_ABM1_HG_RESULT_6_BASE_IDX 2 5659#define mmABM0_DC_ABM1_HG_RESULT_7 0x17da 5660#define mmABM0_DC_ABM1_HG_RESULT_7_BASE_IDX 2 5661#define mmABM0_DC_ABM1_HG_RESULT_8 0x17db 5662#define mmABM0_DC_ABM1_HG_RESULT_8_BASE_IDX 2 5663#define mmABM0_DC_ABM1_HG_RESULT_9 0x17dc 5664#define mmABM0_DC_ABM1_HG_RESULT_9_BASE_IDX 2 5665#define mmABM0_DC_ABM1_HG_RESULT_10 0x17dd 5666#define mmABM0_DC_ABM1_HG_RESULT_10_BASE_IDX 2 5667#define mmABM0_DC_ABM1_HG_RESULT_11 0x17de 5668#define mmABM0_DC_ABM1_HG_RESULT_11_BASE_IDX 2 5669#define mmABM0_DC_ABM1_HG_RESULT_12 0x17df 5670#define mmABM0_DC_ABM1_HG_RESULT_12_BASE_IDX 2 5671#define mmABM0_DC_ABM1_HG_RESULT_13 0x17e0 5672#define mmABM0_DC_ABM1_HG_RESULT_13_BASE_IDX 2 5673#define mmABM0_DC_ABM1_HG_RESULT_14 0x17e1 5674#define mmABM0_DC_ABM1_HG_RESULT_14_BASE_IDX 2 5675#define mmABM0_DC_ABM1_HG_RESULT_15 0x17e2 5676#define mmABM0_DC_ABM1_HG_RESULT_15_BASE_IDX 2 5677#define mmABM0_DC_ABM1_HG_RESULT_16 0x17e3 5678#define mmABM0_DC_ABM1_HG_RESULT_16_BASE_IDX 2 5679#define mmABM0_DC_ABM1_HG_RESULT_17 0x17e4 5680#define mmABM0_DC_ABM1_HG_RESULT_17_BASE_IDX 2 5681#define mmABM0_DC_ABM1_HG_RESULT_18 0x17e5 5682#define mmABM0_DC_ABM1_HG_RESULT_18_BASE_IDX 2 5683#define mmABM0_DC_ABM1_HG_RESULT_19 0x17e6 5684#define mmABM0_DC_ABM1_HG_RESULT_19_BASE_IDX 2 5685#define mmABM0_DC_ABM1_HG_RESULT_20 0x17e7 5686#define mmABM0_DC_ABM1_HG_RESULT_20_BASE_IDX 2 5687#define mmABM0_DC_ABM1_HG_RESULT_21 0x17e8 5688#define mmABM0_DC_ABM1_HG_RESULT_21_BASE_IDX 2 5689#define mmABM0_DC_ABM1_HG_RESULT_22 0x17e9 5690#define mmABM0_DC_ABM1_HG_RESULT_22_BASE_IDX 2 5691#define mmABM0_DC_ABM1_HG_RESULT_23 0x17ea 5692#define mmABM0_DC_ABM1_HG_RESULT_23_BASE_IDX 2 5693#define mmABM0_DC_ABM1_HG_RESULT_24 0x17eb 5694#define mmABM0_DC_ABM1_HG_RESULT_24_BASE_IDX 2 5695#define mmABM0_DC_ABM1_BL_MASTER_LOCK 0x17ec 5696#define mmABM0_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2 5697 5698 5699// addressBlock: dce_dc_opp_abm1_dispdec 5700// base address: 0x118 5701#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL 0x17f6 5702#define mmABM1_BL1_PWM_AMBIENT_LIGHT_LEVEL_BASE_IDX 2 5703#define mmABM1_BL1_PWM_USER_LEVEL 0x17f7 5704#define mmABM1_BL1_PWM_USER_LEVEL_BASE_IDX 2 5705#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL 0x17f8 5706#define mmABM1_BL1_PWM_TARGET_ABM_LEVEL_BASE_IDX 2 5707#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL 0x17f9 5708#define mmABM1_BL1_PWM_CURRENT_ABM_LEVEL_BASE_IDX 2 5709#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE 0x17fa 5710#define mmABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX 2 5711#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE 0x17fb 5712#define mmABM1_BL1_PWM_MINIMUM_DUTY_CYCLE_BASE_IDX 2 5713#define mmABM1_BL1_PWM_ABM_CNTL 0x17fc 5714#define mmABM1_BL1_PWM_ABM_CNTL_BASE_IDX 2 5715#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE 0x17fd 5716#define mmABM1_BL1_PWM_BL_UPDATE_SAMPLE_RATE_BASE_IDX 2 5717#define mmABM1_BL1_PWM_GRP2_REG_LOCK 0x17fe 5718#define mmABM1_BL1_PWM_GRP2_REG_LOCK_BASE_IDX 2 5719#define mmABM1_DC_ABM1_CNTL 0x17ff 5720#define mmABM1_DC_ABM1_CNTL_BASE_IDX 2 5721#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL 0x1800 5722#define mmABM1_DC_ABM1_IPCSC_COEFF_SEL_BASE_IDX 2 5723#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0 0x1801 5724#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_0_BASE_IDX 2 5725#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1 0x1802 5726#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_1_BASE_IDX 2 5727#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2 0x1803 5728#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_2_BASE_IDX 2 5729#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3 0x1804 5730#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_3_BASE_IDX 2 5731#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4 0x1805 5732#define mmABM1_DC_ABM1_ACE_OFFSET_SLOPE_4_BASE_IDX 2 5733#define mmABM1_DC_ABM1_ACE_THRES_12 0x1806 5734#define mmABM1_DC_ABM1_ACE_THRES_12_BASE_IDX 2 5735#define mmABM1_DC_ABM1_ACE_THRES_34 0x1807 5736#define mmABM1_DC_ABM1_ACE_THRES_34_BASE_IDX 2 5737#define mmABM1_DC_ABM1_ACE_CNTL_MISC 0x1808 5738#define mmABM1_DC_ABM1_ACE_CNTL_MISC_BASE_IDX 2 5739#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS 0x180a 5740#define mmABM1_DC_ABM1_HGLS_REG_READ_PROGRESS_BASE_IDX 2 5741#define mmABM1_DC_ABM1_HG_MISC_CTRL 0x180b 5742#define mmABM1_DC_ABM1_HG_MISC_CTRL_BASE_IDX 2 5743#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA 0x180c 5744#define mmABM1_DC_ABM1_LS_SUM_OF_LUMA_BASE_IDX 2 5745#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA 0x180d 5746#define mmABM1_DC_ABM1_LS_MIN_MAX_LUMA_BASE_IDX 2 5747#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA 0x180e 5748#define mmABM1_DC_ABM1_LS_FILTERED_MIN_MAX_LUMA_BASE_IDX 2 5749#define mmABM1_DC_ABM1_LS_PIXEL_COUNT 0x180f 5750#define mmABM1_DC_ABM1_LS_PIXEL_COUNT_BASE_IDX 2 5751#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES 0x1810 5752#define mmABM1_DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES_BASE_IDX 2 5753#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT 0x1811 5754#define mmABM1_DC_ABM1_LS_MIN_PIXEL_VALUE_COUNT_BASE_IDX 2 5755#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT 0x1812 5756#define mmABM1_DC_ABM1_LS_MAX_PIXEL_VALUE_COUNT_BASE_IDX 2 5757#define mmABM1_DC_ABM1_HG_SAMPLE_RATE 0x1813 5758#define mmABM1_DC_ABM1_HG_SAMPLE_RATE_BASE_IDX 2 5759#define mmABM1_DC_ABM1_LS_SAMPLE_RATE 0x1814 5760#define mmABM1_DC_ABM1_LS_SAMPLE_RATE_BASE_IDX 2 5761#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG 0x1815 5762#define mmABM1_DC_ABM1_HG_BIN_1_32_SHIFT_FLAG_BASE_IDX 2 5763#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX 0x1816 5764#define mmABM1_DC_ABM1_HG_BIN_1_8_SHIFT_INDEX_BASE_IDX 2 5765#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX 0x1817 5766#define mmABM1_DC_ABM1_HG_BIN_9_16_SHIFT_INDEX_BASE_IDX 2 5767#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX 0x1818 5768#define mmABM1_DC_ABM1_HG_BIN_17_24_SHIFT_INDEX_BASE_IDX 2 5769#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX 0x1819 5770#define mmABM1_DC_ABM1_HG_BIN_25_32_SHIFT_INDEX_BASE_IDX 2 5771#define mmABM1_DC_ABM1_HG_RESULT_1 0x181a 5772#define mmABM1_DC_ABM1_HG_RESULT_1_BASE_IDX 2 5773#define mmABM1_DC_ABM1_HG_RESULT_2 0x181b 5774#define mmABM1_DC_ABM1_HG_RESULT_2_BASE_IDX 2 5775#define mmABM1_DC_ABM1_HG_RESULT_3 0x181c 5776#define mmABM1_DC_ABM1_HG_RESULT_3_BASE_IDX 2 5777#define mmABM1_DC_ABM1_HG_RESULT_4 0x181d 5778#define mmABM1_DC_ABM1_HG_RESULT_4_BASE_IDX 2 5779#define mmABM1_DC_ABM1_HG_RESULT_5 0x181e 5780#define mmABM1_DC_ABM1_HG_RESULT_5_BASE_IDX 2 5781#define mmABM1_DC_ABM1_HG_RESULT_6 0x181f 5782#define mmABM1_DC_ABM1_HG_RESULT_6_BASE_IDX 2 5783#define mmABM1_DC_ABM1_HG_RESULT_7 0x1820 5784#define mmABM1_DC_ABM1_HG_RESULT_7_BASE_IDX 2 5785#define mmABM1_DC_ABM1_HG_RESULT_8 0x1821 5786#define mmABM1_DC_ABM1_HG_RESULT_8_BASE_IDX 2 5787#define mmABM1_DC_ABM1_HG_RESULT_9 0x1822 5788#define mmABM1_DC_ABM1_HG_RESULT_9_BASE_IDX 2 5789#define mmABM1_DC_ABM1_HG_RESULT_10 0x1823 5790#define mmABM1_DC_ABM1_HG_RESULT_10_BASE_IDX 2 5791#define mmABM1_DC_ABM1_HG_RESULT_11 0x1824 5792#define mmABM1_DC_ABM1_HG_RESULT_11_BASE_IDX 2 5793#define mmABM1_DC_ABM1_HG_RESULT_12 0x1825 5794#define mmABM1_DC_ABM1_HG_RESULT_12_BASE_IDX 2 5795#define mmABM1_DC_ABM1_HG_RESULT_13 0x1826 5796#define mmABM1_DC_ABM1_HG_RESULT_13_BASE_IDX 2 5797#define mmABM1_DC_ABM1_HG_RESULT_14 0x1827 5798#define mmABM1_DC_ABM1_HG_RESULT_14_BASE_IDX 2 5799#define mmABM1_DC_ABM1_HG_RESULT_15 0x1828 5800#define mmABM1_DC_ABM1_HG_RESULT_15_BASE_IDX 2 5801#define mmABM1_DC_ABM1_HG_RESULT_16 0x1829 5802#define mmABM1_DC_ABM1_HG_RESULT_16_BASE_IDX 2 5803#define mmABM1_DC_ABM1_HG_RESULT_17 0x182a 5804#define mmABM1_DC_ABM1_HG_RESULT_17_BASE_IDX 2 5805#define mmABM1_DC_ABM1_HG_RESULT_18 0x182b 5806#define mmABM1_DC_ABM1_HG_RESULT_18_BASE_IDX 2 5807#define mmABM1_DC_ABM1_HG_RESULT_19 0x182c 5808#define mmABM1_DC_ABM1_HG_RESULT_19_BASE_IDX 2 5809#define mmABM1_DC_ABM1_HG_RESULT_20 0x182d 5810#define mmABM1_DC_ABM1_HG_RESULT_20_BASE_IDX 2 5811#define mmABM1_DC_ABM1_HG_RESULT_21 0x182e 5812#define mmABM1_DC_ABM1_HG_RESULT_21_BASE_IDX 2 5813#define mmABM1_DC_ABM1_HG_RESULT_22 0x182f 5814#define mmABM1_DC_ABM1_HG_RESULT_22_BASE_IDX 2 5815#define mmABM1_DC_ABM1_HG_RESULT_23 0x1830 5816#define mmABM1_DC_ABM1_HG_RESULT_23_BASE_IDX 2 5817#define mmABM1_DC_ABM1_HG_RESULT_24 0x1831 5818#define mmABM1_DC_ABM1_HG_RESULT_24_BASE_IDX 2 5819#define mmABM1_DC_ABM1_BL_MASTER_LOCK 0x1832 5820#define mmABM1_DC_ABM1_BL_MASTER_LOCK_BASE_IDX 2 5821 5822 5823// addressBlock: dce_dc_opp_fmt0_dispdec 5824// base address: 0x0 5825#define mmFMT0_FMT_CLAMP_COMPONENT_R 0x183c 5826#define mmFMT0_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 5827#define mmFMT0_FMT_CLAMP_COMPONENT_G 0x183d 5828#define mmFMT0_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 5829#define mmFMT0_FMT_CLAMP_COMPONENT_B 0x183e 5830#define mmFMT0_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 5831#define mmFMT0_FMT_DYNAMIC_EXP_CNTL 0x183f 5832#define mmFMT0_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 5833#define mmFMT0_FMT_CONTROL 0x1840 5834#define mmFMT0_FMT_CONTROL_BASE_IDX 2 5835#define mmFMT0_FMT_BIT_DEPTH_CONTROL 0x1841 5836#define mmFMT0_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 5837#define mmFMT0_FMT_DITHER_RAND_R_SEED 0x1842 5838#define mmFMT0_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 5839#define mmFMT0_FMT_DITHER_RAND_G_SEED 0x1843 5840#define mmFMT0_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 5841#define mmFMT0_FMT_DITHER_RAND_B_SEED 0x1844 5842#define mmFMT0_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 5843#define mmFMT0_FMT_CLAMP_CNTL 0x1848 5844#define mmFMT0_FMT_CLAMP_CNTL_BASE_IDX 2 5845#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1849 5846#define mmFMT0_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 5847#define mmFMT0_FMT_MAP420_MEMORY_CONTROL 0x184a 5848#define mmFMT0_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 5849 5850 5851// addressBlock: dce_dc_opp_oppbuf0_dispdec 5852// base address: 0x0 5853#define mmOPPBUF0_OPPBUF_CONTROL 0x1884 5854#define mmOPPBUF0_OPPBUF_CONTROL_BASE_IDX 2 5855#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0 0x1885 5856#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 5857#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1 0x1886 5858#define mmOPPBUF0_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 5859 5860 5861// addressBlock: dce_dc_opp_opp_pipe0_dispdec 5862// base address: 0x0 5863#define mmOPP_PIPE0_OPP_PIPE_CONTROL 0x188c 5864#define mmOPP_PIPE0_OPP_PIPE_CONTROL_BASE_IDX 2 5865 5866 5867// addressBlock: dce_dc_opp_opp_pipe_crc0_dispdec 5868// base address: 0x0 5869#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL 0x1891 5870#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 5871#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK 0x1892 5872#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_MASK_BASE_IDX 2 5873#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0 0x1893 5874#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 5875#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1 0x1894 5876#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 5877#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2 0x1895 5878#define mmOPP_PIPE_CRC0_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 5879 5880 5881// addressBlock: dce_dc_opp_fmt1_dispdec 5882// base address: 0x168 5883#define mmFMT1_FMT_CLAMP_COMPONENT_R 0x1896 5884#define mmFMT1_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 5885#define mmFMT1_FMT_CLAMP_COMPONENT_G 0x1897 5886#define mmFMT1_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 5887#define mmFMT1_FMT_CLAMP_COMPONENT_B 0x1898 5888#define mmFMT1_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 5889#define mmFMT1_FMT_DYNAMIC_EXP_CNTL 0x1899 5890#define mmFMT1_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 5891#define mmFMT1_FMT_CONTROL 0x189a 5892#define mmFMT1_FMT_CONTROL_BASE_IDX 2 5893#define mmFMT1_FMT_BIT_DEPTH_CONTROL 0x189b 5894#define mmFMT1_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 5895#define mmFMT1_FMT_DITHER_RAND_R_SEED 0x189c 5896#define mmFMT1_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 5897#define mmFMT1_FMT_DITHER_RAND_G_SEED 0x189d 5898#define mmFMT1_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 5899#define mmFMT1_FMT_DITHER_RAND_B_SEED 0x189e 5900#define mmFMT1_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 5901#define mmFMT1_FMT_CLAMP_CNTL 0x18a2 5902#define mmFMT1_FMT_CLAMP_CNTL_BASE_IDX 2 5903#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18a3 5904#define mmFMT1_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 5905#define mmFMT1_FMT_MAP420_MEMORY_CONTROL 0x18a4 5906#define mmFMT1_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 5907 5908 5909// addressBlock: dce_dc_opp_oppbuf1_dispdec 5910// base address: 0x168 5911#define mmOPPBUF1_OPPBUF_CONTROL 0x18de 5912#define mmOPPBUF1_OPPBUF_CONTROL_BASE_IDX 2 5913#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0 0x18df 5914#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 5915#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1 0x18e0 5916#define mmOPPBUF1_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 5917 5918 5919// addressBlock: dce_dc_opp_opp_pipe1_dispdec 5920// base address: 0x168 5921#define mmOPP_PIPE1_OPP_PIPE_CONTROL 0x18e6 5922#define mmOPP_PIPE1_OPP_PIPE_CONTROL_BASE_IDX 2 5923 5924 5925// addressBlock: dce_dc_opp_opp_pipe_crc1_dispdec 5926// base address: 0x168 5927#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL 0x18eb 5928#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 5929#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK 0x18ec 5930#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_MASK_BASE_IDX 2 5931#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0 0x18ed 5932#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 5933#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1 0x18ee 5934#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 5935#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2 0x18ef 5936#define mmOPP_PIPE_CRC1_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 5937 5938 5939// addressBlock: dce_dc_opp_fmt2_dispdec 5940// base address: 0x2d0 5941#define mmFMT2_FMT_CLAMP_COMPONENT_R 0x18f0 5942#define mmFMT2_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 5943#define mmFMT2_FMT_CLAMP_COMPONENT_G 0x18f1 5944#define mmFMT2_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 5945#define mmFMT2_FMT_CLAMP_COMPONENT_B 0x18f2 5946#define mmFMT2_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 5947#define mmFMT2_FMT_DYNAMIC_EXP_CNTL 0x18f3 5948#define mmFMT2_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 5949#define mmFMT2_FMT_CONTROL 0x18f4 5950#define mmFMT2_FMT_CONTROL_BASE_IDX 2 5951#define mmFMT2_FMT_BIT_DEPTH_CONTROL 0x18f5 5952#define mmFMT2_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 5953#define mmFMT2_FMT_DITHER_RAND_R_SEED 0x18f6 5954#define mmFMT2_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 5955#define mmFMT2_FMT_DITHER_RAND_G_SEED 0x18f7 5956#define mmFMT2_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 5957#define mmFMT2_FMT_DITHER_RAND_B_SEED 0x18f8 5958#define mmFMT2_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 5959#define mmFMT2_FMT_CLAMP_CNTL 0x18fc 5960#define mmFMT2_FMT_CLAMP_CNTL_BASE_IDX 2 5961#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x18fd 5962#define mmFMT2_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 5963#define mmFMT2_FMT_MAP420_MEMORY_CONTROL 0x18fe 5964#define mmFMT2_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 5965 5966 5967// addressBlock: dce_dc_opp_oppbuf2_dispdec 5968// base address: 0x2d0 5969#define mmOPPBUF2_OPPBUF_CONTROL 0x1938 5970#define mmOPPBUF2_OPPBUF_CONTROL_BASE_IDX 2 5971#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0 0x1939 5972#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 5973#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1 0x193a 5974#define mmOPPBUF2_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 5975 5976 5977// addressBlock: dce_dc_opp_opp_pipe2_dispdec 5978// base address: 0x2d0 5979#define mmOPP_PIPE2_OPP_PIPE_CONTROL 0x1940 5980#define mmOPP_PIPE2_OPP_PIPE_CONTROL_BASE_IDX 2 5981 5982 5983// addressBlock: dce_dc_opp_opp_pipe_crc2_dispdec 5984// base address: 0x2d0 5985#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL 0x1945 5986#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 5987#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK 0x1946 5988#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_MASK_BASE_IDX 2 5989#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0 0x1947 5990#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 5991#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1 0x1948 5992#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 5993#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2 0x1949 5994#define mmOPP_PIPE_CRC2_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 5995 5996 5997// addressBlock: dce_dc_opp_fmt3_dispdec 5998// base address: 0x438 5999#define mmFMT3_FMT_CLAMP_COMPONENT_R 0x194a 6000#define mmFMT3_FMT_CLAMP_COMPONENT_R_BASE_IDX 2
6001#define mmFMT3_FMT_CLAMP_COMPONENT_G 0x194b 6002#define mmFMT3_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 6003#define mmFMT3_FMT_CLAMP_COMPONENT_B 0x194c 6004#define mmFMT3_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 6005#define mmFMT3_FMT_DYNAMIC_EXP_CNTL 0x194d 6006#define mmFMT3_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 6007#define mmFMT3_FMT_CONTROL 0x194e 6008#define mmFMT3_FMT_CONTROL_BASE_IDX 2 6009#define mmFMT3_FMT_BIT_DEPTH_CONTROL 0x194f 6010#define mmFMT3_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 6011#define mmFMT3_FMT_DITHER_RAND_R_SEED 0x1950 6012#define mmFMT3_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 6013#define mmFMT3_FMT_DITHER_RAND_G_SEED 0x1951 6014#define mmFMT3_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 6015#define mmFMT3_FMT_DITHER_RAND_B_SEED 0x1952 6016#define mmFMT3_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 6017#define mmFMT3_FMT_CLAMP_CNTL 0x1956 6018#define mmFMT3_FMT_CLAMP_CNTL_BASE_IDX 2 6019#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1957 6020#define mmFMT3_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 6021#define mmFMT3_FMT_MAP420_MEMORY_CONTROL 0x1958 6022#define mmFMT3_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 6023 6024 6025// addressBlock: dce_dc_opp_oppbuf3_dispdec 6026// base address: 0x438 6027#define mmOPPBUF3_OPPBUF_CONTROL 0x1992 6028#define mmOPPBUF3_OPPBUF_CONTROL_BASE_IDX 2 6029#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0 0x1993 6030#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 6031#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1 0x1994 6032#define mmOPPBUF3_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 6033 6034 6035// addressBlock: dce_dc_opp_opp_pipe3_dispdec 6036// base address: 0x438 6037#define mmOPP_PIPE3_OPP_PIPE_CONTROL 0x199a 6038#define mmOPP_PIPE3_OPP_PIPE_CONTROL_BASE_IDX 2 6039 6040 6041// addressBlock: dce_dc_opp_opp_pipe_crc3_dispdec 6042// base address: 0x438 6043#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL 0x199f 6044#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 6045#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK 0x19a0 6046#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_MASK_BASE_IDX 2 6047#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0 0x19a1 6048#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 6049#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1 0x19a2 6050#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 6051#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2 0x19a3 6052#define mmOPP_PIPE_CRC3_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 6053 6054 6055// addressBlock: dce_dc_opp_fmt4_dispdec 6056// base address: 0x5a0 6057#define mmFMT4_FMT_CLAMP_COMPONENT_R 0x19a4 6058#define mmFMT4_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 6059#define mmFMT4_FMT_CLAMP_COMPONENT_G 0x19a5 6060#define mmFMT4_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 6061#define mmFMT4_FMT_CLAMP_COMPONENT_B 0x19a6 6062#define mmFMT4_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 6063#define mmFMT4_FMT_DYNAMIC_EXP_CNTL 0x19a7 6064#define mmFMT4_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 6065#define mmFMT4_FMT_CONTROL 0x19a8 6066#define mmFMT4_FMT_CONTROL_BASE_IDX 2 6067#define mmFMT4_FMT_BIT_DEPTH_CONTROL 0x19a9 6068#define mmFMT4_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 6069#define mmFMT4_FMT_DITHER_RAND_R_SEED 0x19aa 6070#define mmFMT4_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 6071#define mmFMT4_FMT_DITHER_RAND_G_SEED 0x19ab 6072#define mmFMT4_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 6073#define mmFMT4_FMT_DITHER_RAND_B_SEED 0x19ac 6074#define mmFMT4_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 6075#define mmFMT4_FMT_CLAMP_CNTL 0x19b0 6076#define mmFMT4_FMT_CLAMP_CNTL_BASE_IDX 2 6077#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x19b1 6078#define mmFMT4_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 6079#define mmFMT4_FMT_MAP420_MEMORY_CONTROL 0x19b2 6080#define mmFMT4_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 6081 6082 6083// addressBlock: dce_dc_opp_oppbuf4_dispdec 6084// base address: 0x5a0 6085#define mmOPPBUF4_OPPBUF_CONTROL 0x19ec 6086#define mmOPPBUF4_OPPBUF_CONTROL_BASE_IDX 2 6087#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0 0x19ed 6088#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 6089#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1 0x19ee 6090#define mmOPPBUF4_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 6091 6092 6093// addressBlock: dce_dc_opp_opp_pipe4_dispdec 6094// base address: 0x5a0 6095#define mmOPP_PIPE4_OPP_PIPE_CONTROL 0x19f4 6096#define mmOPP_PIPE4_OPP_PIPE_CONTROL_BASE_IDX 2 6097 6098 6099// addressBlock: dce_dc_opp_opp_pipe_crc4_dispdec 6100// base address: 0x5a0 6101#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL 0x19f9 6102#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 6103#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK 0x19fa 6104#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_MASK_BASE_IDX 2 6105#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0 0x19fb 6106#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 6107#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1 0x19fc 6108#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 6109#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2 0x19fd 6110#define mmOPP_PIPE_CRC4_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 6111 6112 6113// addressBlock: dce_dc_opp_fmt5_dispdec 6114// base address: 0x708 6115#define mmFMT5_FMT_CLAMP_COMPONENT_R 0x19fe 6116#define mmFMT5_FMT_CLAMP_COMPONENT_R_BASE_IDX 2 6117#define mmFMT5_FMT_CLAMP_COMPONENT_G 0x19ff 6118#define mmFMT5_FMT_CLAMP_COMPONENT_G_BASE_IDX 2 6119#define mmFMT5_FMT_CLAMP_COMPONENT_B 0x1a00 6120#define mmFMT5_FMT_CLAMP_COMPONENT_B_BASE_IDX 2 6121#define mmFMT5_FMT_DYNAMIC_EXP_CNTL 0x1a01 6122#define mmFMT5_FMT_DYNAMIC_EXP_CNTL_BASE_IDX 2 6123#define mmFMT5_FMT_CONTROL 0x1a02 6124#define mmFMT5_FMT_CONTROL_BASE_IDX 2 6125#define mmFMT5_FMT_BIT_DEPTH_CONTROL 0x1a03 6126#define mmFMT5_FMT_BIT_DEPTH_CONTROL_BASE_IDX 2 6127#define mmFMT5_FMT_DITHER_RAND_R_SEED 0x1a04 6128#define mmFMT5_FMT_DITHER_RAND_R_SEED_BASE_IDX 2 6129#define mmFMT5_FMT_DITHER_RAND_G_SEED 0x1a05 6130#define mmFMT5_FMT_DITHER_RAND_G_SEED_BASE_IDX 2 6131#define mmFMT5_FMT_DITHER_RAND_B_SEED 0x1a06 6132#define mmFMT5_FMT_DITHER_RAND_B_SEED_BASE_IDX 2 6133#define mmFMT5_FMT_CLAMP_CNTL 0x1a0a 6134#define mmFMT5_FMT_CLAMP_CNTL_BASE_IDX 2 6135#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL 0x1a0b 6136#define mmFMT5_FMT_SIDE_BY_SIDE_STEREO_CONTROL_BASE_IDX 2 6137#define mmFMT5_FMT_MAP420_MEMORY_CONTROL 0x1a0c 6138#define mmFMT5_FMT_MAP420_MEMORY_CONTROL_BASE_IDX 2 6139 6140 6141// addressBlock: dce_dc_opp_oppbuf5_dispdec 6142// base address: 0x708 6143#define mmOPPBUF5_OPPBUF_CONTROL 0x1a46 6144#define mmOPPBUF5_OPPBUF_CONTROL_BASE_IDX 2 6145#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0 0x1a47 6146#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_0_BASE_IDX 2 6147#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1 0x1a48 6148#define mmOPPBUF5_OPPBUF_3D_PARAMETERS_1_BASE_IDX 2 6149 6150 6151// addressBlock: dce_dc_opp_opp_pipe5_dispdec 6152// base address: 0x708 6153#define mmOPP_PIPE5_OPP_PIPE_CONTROL 0x1a4e 6154#define mmOPP_PIPE5_OPP_PIPE_CONTROL_BASE_IDX 2 6155 6156 6157// addressBlock: dce_dc_opp_opp_pipe_crc5_dispdec 6158// base address: 0x708 6159#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL 0x1a53 6160#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_CONTROL_BASE_IDX 2 6161#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK 0x1a54 6162#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_MASK_BASE_IDX 2 6163#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0 0x1a55 6164#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT0_BASE_IDX 2 6165#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1 0x1a56 6166#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT1_BASE_IDX 2 6167#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2 0x1a57 6168#define mmOPP_PIPE_CRC5_OPP_PIPE_CRC_RESULT2_BASE_IDX 2 6169 6170 6171// addressBlock: dce_dc_opp_opp_top_dispdec 6172// base address: 0x0 6173#define mmOPP_TOP_CLK_CONTROL 0x1a5e 6174#define mmOPP_TOP_CLK_CONTROL_BASE_IDX 2 6175 6176 6177// addressBlock: dce_dc_opp_opp_dcperfmon_dc_perfmon_dispdec 6178// base address: 0x6af8 6179#define mmDC_PERFMON17_PERFCOUNTER_CNTL 0x1abe 6180#define mmDC_PERFMON17_PERFCOUNTER_CNTL_BASE_IDX 2 6181#define mmDC_PERFMON17_PERFCOUNTER_CNTL2 0x1abf 6182#define mmDC_PERFMON17_PERFCOUNTER_CNTL2_BASE_IDX 2 6183#define mmDC_PERFMON17_PERFCOUNTER_STATE 0x1ac0 6184#define mmDC_PERFMON17_PERFCOUNTER_STATE_BASE_IDX 2 6185#define mmDC_PERFMON17_PERFMON_CNTL 0x1ac1 6186#define mmDC_PERFMON17_PERFMON_CNTL_BASE_IDX 2 6187#define mmDC_PERFMON17_PERFMON_CNTL2 0x1ac2 6188#define mmDC_PERFMON17_PERFMON_CNTL2_BASE_IDX 2 6189#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC 0x1ac3 6190#define mmDC_PERFMON17_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 6191#define mmDC_PERFMON17_PERFMON_CVALUE_LOW 0x1ac4 6192#define mmDC_PERFMON17_PERFMON_CVALUE_LOW_BASE_IDX 2 6193#define mmDC_PERFMON17_PERFMON_HI 0x1ac5 6194#define mmDC_PERFMON17_PERFMON_HI_BASE_IDX 2 6195#define mmDC_PERFMON17_PERFMON_LOW 0x1ac6 6196#define mmDC_PERFMON17_PERFMON_LOW_BASE_IDX 2 6197 6198 6199// addressBlock: dce_dc_optc_odm0_dispdec 6200// base address: 0x0 6201#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL 0x1aca 6202#define mmODM0_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6203#define mmODM0_OPTC_DATA_SOURCE_SELECT 0x1acb 6204#define mmODM0_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6205#define mmODM0_OPTC_INPUT_CLOCK_CONTROL 0x1acd 6206#define mmODM0_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6207#define mmODM0_OPTC_INPUT_SPARE_REGISTER 0x1acf 6208#define mmODM0_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6209 6210 6211// addressBlock: dce_dc_optc_odm1_dispdec 6212// base address: 0x40 6213#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL 0x1ada 6214#define mmODM1_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6215#define mmODM1_OPTC_DATA_SOURCE_SELECT 0x1adb 6216#define mmODM1_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6217#define mmODM1_OPTC_INPUT_CLOCK_CONTROL 0x1add 6218#define mmODM1_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6219#define mmODM1_OPTC_INPUT_SPARE_REGISTER 0x1adf 6220#define mmODM1_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6221 6222 6223// addressBlock: dce_dc_optc_odm2_dispdec 6224// base address: 0x80 6225#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL 0x1aea 6226#define mmODM2_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6227#define mmODM2_OPTC_DATA_SOURCE_SELECT 0x1aeb 6228#define mmODM2_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6229#define mmODM2_OPTC_INPUT_CLOCK_CONTROL 0x1aed 6230#define mmODM2_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6231#define mmODM2_OPTC_INPUT_SPARE_REGISTER 0x1aef 6232#define mmODM2_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6233 6234 6235// addressBlock: dce_dc_optc_odm3_dispdec 6236// base address: 0xc0 6237#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL 0x1afa 6238#define mmODM3_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6239#define mmODM3_OPTC_DATA_SOURCE_SELECT 0x1afb 6240#define mmODM3_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6241#define mmODM3_OPTC_INPUT_CLOCK_CONTROL 0x1afd 6242#define mmODM3_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6243#define mmODM3_OPTC_INPUT_SPARE_REGISTER 0x1aff 6244#define mmODM3_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6245 6246 6247// addressBlock: dce_dc_optc_odm4_dispdec 6248// base address: 0x100 6249#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL 0x1b0a 6250#define mmODM4_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6251#define mmODM4_OPTC_DATA_SOURCE_SELECT 0x1b0b 6252#define mmODM4_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6253#define mmODM4_OPTC_INPUT_CLOCK_CONTROL 0x1b0d 6254#define mmODM4_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6255#define mmODM4_OPTC_INPUT_SPARE_REGISTER 0x1b0f 6256#define mmODM4_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6257 6258 6259// addressBlock: dce_dc_optc_odm5_dispdec 6260// base address: 0x140 6261#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL 0x1b1a 6262#define mmODM5_OPTC_INPUT_GLOBAL_CONTROL_BASE_IDX 2 6263#define mmODM5_OPTC_DATA_SOURCE_SELECT 0x1b1b 6264#define mmODM5_OPTC_DATA_SOURCE_SELECT_BASE_IDX 2 6265#define mmODM5_OPTC_INPUT_CLOCK_CONTROL 0x1b1d 6266#define mmODM5_OPTC_INPUT_CLOCK_CONTROL_BASE_IDX 2 6267#define mmODM5_OPTC_INPUT_SPARE_REGISTER 0x1b1f 6268#define mmODM5_OPTC_INPUT_SPARE_REGISTER_BASE_IDX 2 6269 6270 6271// addressBlock: dce_dc_optc_otg0_dispdec 6272// base address: 0x0 6273#define mmOTG0_OTG_H_TOTAL 0x1b2a 6274#define mmOTG0_OTG_H_TOTAL_BASE_IDX 2 6275#define mmOTG0_OTG_H_BLANK_START_END 0x1b2b 6276#define mmOTG0_OTG_H_BLANK_START_END_BASE_IDX 2 6277#define mmOTG0_OTG_H_SYNC_A 0x1b2c 6278#define mmOTG0_OTG_H_SYNC_A_BASE_IDX 2 6279#define mmOTG0_OTG_H_SYNC_A_CNTL 0x1b2d 6280#define mmOTG0_OTG_H_SYNC_A_CNTL_BASE_IDX 2 6281#define mmOTG0_OTG_H_TIMING_CNTL 0x1b2e 6282#define mmOTG0_OTG_H_TIMING_CNTL_BASE_IDX 2 6283#define mmOTG0_OTG_V_TOTAL 0x1b2f 6284#define mmOTG0_OTG_V_TOTAL_BASE_IDX 2 6285#define mmOTG0_OTG_V_TOTAL_MIN 0x1b30 6286#define mmOTG0_OTG_V_TOTAL_MIN_BASE_IDX 2 6287#define mmOTG0_OTG_V_TOTAL_MAX 0x1b31 6288#define mmOTG0_OTG_V_TOTAL_MAX_BASE_IDX 2 6289#define mmOTG0_OTG_V_TOTAL_MID 0x1b32 6290#define mmOTG0_OTG_V_TOTAL_MID_BASE_IDX 2 6291#define mmOTG0_OTG_V_TOTAL_CONTROL 0x1b33 6292#define mmOTG0_OTG_V_TOTAL_CONTROL_BASE_IDX 2 6293#define mmOTG0_OTG_V_TOTAL_INT_STATUS 0x1b34 6294#define mmOTG0_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 6295#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS 0x1b35 6296#define mmOTG0_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 6297#define mmOTG0_OTG_V_BLANK_START_END 0x1b36 6298#define mmOTG0_OTG_V_BLANK_START_END_BASE_IDX 2 6299#define mmOTG0_OTG_V_SYNC_A 0x1b37 6300#define mmOTG0_OTG_V_SYNC_A_BASE_IDX 2 6301#define mmOTG0_OTG_V_SYNC_A_CNTL 0x1b38 6302#define mmOTG0_OTG_V_SYNC_A_CNTL_BASE_IDX 2 6303#define mmOTG0_OTG_TRIGA_CNTL 0x1b39 6304#define mmOTG0_OTG_TRIGA_CNTL_BASE_IDX 2 6305#define mmOTG0_OTG_TRIGA_MANUAL_TRIG 0x1b3a 6306#define mmOTG0_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 6307#define mmOTG0_OTG_TRIGB_CNTL 0x1b3b 6308#define mmOTG0_OTG_TRIGB_CNTL_BASE_IDX 2 6309#define mmOTG0_OTG_TRIGB_MANUAL_TRIG 0x1b3c 6310#define mmOTG0_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 6311#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL 0x1b3d 6312#define mmOTG0_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 6313#define mmOTG0_OTG_FLOW_CONTROL 0x1b3e 6314#define mmOTG0_OTG_FLOW_CONTROL_BASE_IDX 2 6315#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE 0x1b3f 6316#define mmOTG0_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 6317#define mmOTG0_OTG_AVSYNC_COUNTER 0x1b40 6318#define mmOTG0_OTG_AVSYNC_COUNTER_BASE_IDX 2 6319#define mmOTG0_OTG_CONTROL 0x1b41 6320#define mmOTG0_OTG_CONTROL_BASE_IDX 2 6321#define mmOTG0_OTG_BLANK_CONTROL 0x1b42 6322#define mmOTG0_OTG_BLANK_CONTROL_BASE_IDX 2 6323#define mmOTG0_OTG_PIPE_ABORT_CONTROL 0x1b43 6324#define mmOTG0_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 6325#define mmOTG0_OTG_INTERLACE_CONTROL 0x1b44 6326#define mmOTG0_OTG_INTERLACE_CONTROL_BASE_IDX 2 6327#define mmOTG0_OTG_INTERLACE_STATUS 0x1b45 6328#define mmOTG0_OTG_INTERLACE_STATUS_BASE_IDX 2 6329#define mmOTG0_OTG_FIELD_INDICATION_CONTROL 0x1b46 6330#define mmOTG0_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 6331#define mmOTG0_OTG_PIXEL_DATA_READBACK0 0x1b47 6332#define mmOTG0_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 6333#define mmOTG0_OTG_PIXEL_DATA_READBACK1 0x1b48 6334#define mmOTG0_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 6335#define mmOTG0_OTG_STATUS 0x1b49 6336#define mmOTG0_OTG_STATUS_BASE_IDX 2 6337#define mmOTG0_OTG_STATUS_POSITION 0x1b4a 6338#define mmOTG0_OTG_STATUS_POSITION_BASE_IDX 2 6339#define mmOTG0_OTG_NOM_VERT_POSITION 0x1b4b 6340#define mmOTG0_OTG_NOM_VERT_POSITION_BASE_IDX 2 6341#define mmOTG0_OTG_STATUS_FRAME_COUNT 0x1b4c 6342#define mmOTG0_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 6343#define mmOTG0_OTG_STATUS_VF_COUNT 0x1b4d 6344#define mmOTG0_OTG_STATUS_VF_COUNT_BASE_IDX 2 6345#define mmOTG0_OTG_STATUS_HV_COUNT 0x1b4e 6346#define mmOTG0_OTG_STATUS_HV_COUNT_BASE_IDX 2 6347#define mmOTG0_OTG_COUNT_CONTROL 0x1b4f 6348#define mmOTG0_OTG_COUNT_CONTROL_BASE_IDX 2 6349#define mmOTG0_OTG_COUNT_RESET 0x1b50 6350#define mmOTG0_OTG_COUNT_RESET_BASE_IDX 2 6351#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1b51 6352#define mmOTG0_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 6353#define mmOTG0_OTG_VERT_SYNC_CONTROL 0x1b52 6354#define mmOTG0_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 6355#define mmOTG0_OTG_STEREO_STATUS 0x1b53 6356#define mmOTG0_OTG_STEREO_STATUS_BASE_IDX 2 6357#define mmOTG0_OTG_STEREO_CONTROL 0x1b54 6358#define mmOTG0_OTG_STEREO_CONTROL_BASE_IDX 2 6359#define mmOTG0_OTG_SNAPSHOT_STATUS 0x1b55 6360#define mmOTG0_OTG_SNAPSHOT_STATUS_BASE_IDX 2 6361#define mmOTG0_OTG_SNAPSHOT_CONTROL 0x1b56 6362#define mmOTG0_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 6363#define mmOTG0_OTG_SNAPSHOT_POSITION 0x1b57 6364#define mmOTG0_OTG_SNAPSHOT_POSITION_BASE_IDX 2 6365#define mmOTG0_OTG_SNAPSHOT_FRAME 0x1b58 6366#define mmOTG0_OTG_SNAPSHOT_FRAME_BASE_IDX 2 6367#define mmOTG0_OTG_INTERRUPT_CONTROL 0x1b59 6368#define mmOTG0_OTG_INTERRUPT_CONTROL_BASE_IDX 2 6369#define mmOTG0_OTG_UPDATE_LOCK 0x1b5a 6370#define mmOTG0_OTG_UPDATE_LOCK_BASE_IDX 2 6371#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL 0x1b5b 6372#define mmOTG0_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 6373#define mmOTG0_OTG_TEST_PATTERN_CONTROL 0x1b5c 6374#define mmOTG0_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 6375#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS 0x1b5d 6376#define mmOTG0_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 6377#define mmOTG0_OTG_TEST_PATTERN_COLOR 0x1b5e 6378#define mmOTG0_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 6379#define mmOTG0_OTG_MASTER_EN 0x1b5f 6380#define mmOTG0_OTG_MASTER_EN_BASE_IDX 2 6381#define mmOTG0_OTG_BLANK_DATA_COLOR 0x1b61 6382#define mmOTG0_OTG_BLANK_DATA_COLOR_BASE_IDX 2 6383#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT 0x1b62 6384#define mmOTG0_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 6385#define mmOTG0_OTG_BLACK_COLOR 0x1b63 6386#define mmOTG0_OTG_BLACK_COLOR_BASE_IDX 2 6387#define mmOTG0_OTG_BLACK_COLOR_EXT 0x1b64 6388#define mmOTG0_OTG_BLACK_COLOR_EXT_BASE_IDX 2 6389#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION 0x1b65 6390#define mmOTG0_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 6391#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1b66 6392#define mmOTG0_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 6393#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION 0x1b67 6394#define mmOTG0_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 6395#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1b68 6396#define mmOTG0_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 6397#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION 0x1b69 6398#define mmOTG0_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 6399#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1b6a 6400#define mmOTG0_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 6401#define mmOTG0_OTG_CRC_CNTL 0x1b6b 6402#define mmOTG0_OTG_CRC_CNTL_BASE_IDX 2 6403#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL 0x1b6c 6404#define mmOTG0_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 6405#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL 0x1b6d 6406#define mmOTG0_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 6407#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL 0x1b6e 6408#define mmOTG0_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 6409#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL 0x1b6f 6410#define mmOTG0_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 6411#define mmOTG0_OTG_CRC0_DATA_RG 0x1b70 6412#define mmOTG0_OTG_CRC0_DATA_RG_BASE_IDX 2 6413#define mmOTG0_OTG_CRC0_DATA_B 0x1b71 6414#define mmOTG0_OTG_CRC0_DATA_B_BASE_IDX 2 6415#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL 0x1b72 6416#define mmOTG0_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 6417#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL 0x1b73 6418#define mmOTG0_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 6419#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL 0x1b74 6420#define mmOTG0_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 6421#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL 0x1b75 6422#define mmOTG0_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 6423#define mmOTG0_OTG_CRC1_DATA_RG 0x1b76 6424#define mmOTG0_OTG_CRC1_DATA_RG_BASE_IDX 2 6425#define mmOTG0_OTG_CRC1_DATA_B 0x1b77 6426#define mmOTG0_OTG_CRC1_DATA_B_BASE_IDX 2 6427#define mmOTG0_OTG_CRC2_DATA_RG 0x1b78 6428#define mmOTG0_OTG_CRC2_DATA_RG_BASE_IDX 2 6429#define mmOTG0_OTG_CRC2_DATA_B 0x1b79 6430#define mmOTG0_OTG_CRC2_DATA_B_BASE_IDX 2 6431#define mmOTG0_OTG_CRC3_DATA_RG 0x1b7a 6432#define mmOTG0_OTG_CRC3_DATA_RG_BASE_IDX 2 6433#define mmOTG0_OTG_CRC3_DATA_B 0x1b7b 6434#define mmOTG0_OTG_CRC3_DATA_B_BASE_IDX 2 6435#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK 0x1b7c 6436#define mmOTG0_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 6437#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1b7d 6438#define mmOTG0_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 6439#define mmOTG0_OTG_STATIC_SCREEN_CONTROL 0x1b84 6440#define mmOTG0_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 6441#define mmOTG0_OTG_3D_STRUCTURE_CONTROL 0x1b85 6442#define mmOTG0_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 6443#define mmOTG0_OTG_GSL_VSYNC_GAP 0x1b86 6444#define mmOTG0_OTG_GSL_VSYNC_GAP_BASE_IDX 2 6445#define mmOTG0_OTG_MASTER_UPDATE_MODE 0x1b87 6446#define mmOTG0_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 6447#define mmOTG0_OTG_CLOCK_CONTROL 0x1b88 6448#define mmOTG0_OTG_CLOCK_CONTROL_BASE_IDX 2 6449#define mmOTG0_OTG_VSTARTUP_PARAM 0x1b89 6450#define mmOTG0_OTG_VSTARTUP_PARAM_BASE_IDX 2 6451#define mmOTG0_OTG_VUPDATE_PARAM 0x1b8a 6452#define mmOTG0_OTG_VUPDATE_PARAM_BASE_IDX 2 6453#define mmOTG0_OTG_VREADY_PARAM 0x1b8b 6454#define mmOTG0_OTG_VREADY_PARAM_BASE_IDX 2 6455#define mmOTG0_OTG_GLOBAL_SYNC_STATUS 0x1b8c 6456#define mmOTG0_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 6457#define mmOTG0_OTG_MASTER_UPDATE_LOCK 0x1b8d 6458#define mmOTG0_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 6459#define mmOTG0_OTG_GSL_CONTROL 0x1b8e 6460#define mmOTG0_OTG_GSL_CONTROL_BASE_IDX 2 6461#define mmOTG0_OTG_GSL_WINDOW_X 0x1b8f 6462#define mmOTG0_OTG_GSL_WINDOW_X_BASE_IDX 2 6463#define mmOTG0_OTG_GSL_WINDOW_Y 0x1b90 6464#define mmOTG0_OTG_GSL_WINDOW_Y_BASE_IDX 2 6465#define mmOTG0_OTG_VUPDATE_KEEPOUT 0x1b91 6466#define mmOTG0_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 6467#define mmOTG0_OTG_GLOBAL_CONTROL0 0x1b92 6468#define mmOTG0_OTG_GLOBAL_CONTROL0_BASE_IDX 2 6469#define mmOTG0_OTG_GLOBAL_CONTROL1 0x1b93 6470#define mmOTG0_OTG_GLOBAL_CONTROL1_BASE_IDX 2 6471#define mmOTG0_OTG_GLOBAL_CONTROL2 0x1b94 6472#define mmOTG0_OTG_GLOBAL_CONTROL2_BASE_IDX 2 6473#define mmOTG0_OTG_GLOBAL_CONTROL3 0x1b95 6474#define mmOTG0_OTG_GLOBAL_CONTROL3_BASE_IDX 2 6475#define mmOTG0_OTG_TRIG_MANUAL_CONTROL 0x1b96 6476#define mmOTG0_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 6477#define mmOTG0_OTG_MANUAL_FLOW_CONTROL 0x1b97 6478#define mmOTG0_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 6479#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS 0x1b98 6480#define mmOTG0_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 6481#define mmOTG0_OTG_DRR_CONTROL 0x1b99 6482#define mmOTG0_OTG_DRR_CONTROL_BASE_IDX 2 6483#define mmOTG0_OTG_REQUEST_CONTROL 0x1b9a 6484#define mmOTG0_OTG_REQUEST_CONTROL_BASE_IDX 2 6485#define mmOTG0_OTG_SPARE_REGISTER 0x1b9b 6486#define mmOTG0_OTG_SPARE_REGISTER_BASE_IDX 2 6487 6488 6489// addressBlock: dce_dc_optc_otg1_dispdec 6490// base address: 0x200 6491#define mmOTG1_OTG_H_TOTAL 0x1baa 6492#define mmOTG1_OTG_H_TOTAL_BASE_IDX 2 6493#define mmOTG1_OTG_H_BLANK_START_END 0x1bab 6494#define mmOTG1_OTG_H_BLANK_START_END_BASE_IDX 2 6495#define mmOTG1_OTG_H_SYNC_A 0x1bac 6496#define mmOTG1_OTG_H_SYNC_A_BASE_IDX 2 6497#define mmOTG1_OTG_H_SYNC_A_CNTL 0x1bad 6498#define mmOTG1_OTG_H_SYNC_A_CNTL_BASE_IDX 2 6499#define mmOTG1_OTG_H_TIMING_CNTL 0x1bae 6500#define mmOTG1_OTG_H_TIMING_CNTL_BASE_IDX 2 6501#define mmOTG1_OTG_V_TOTAL 0x1baf 6502#define mmOTG1_OTG_V_TOTAL_BASE_IDX 2 6503#define mmOTG1_OTG_V_TOTAL_MIN 0x1bb0 6504#define mmOTG1_OTG_V_TOTAL_MIN_BASE_IDX 2 6505#define mmOTG1_OTG_V_TOTAL_MAX 0x1bb1 6506#define mmOTG1_OTG_V_TOTAL_MAX_BASE_IDX 2 6507#define mmOTG1_OTG_V_TOTAL_MID 0x1bb2 6508#define mmOTG1_OTG_V_TOTAL_MID_BASE_IDX 2 6509#define mmOTG1_OTG_V_TOTAL_CONTROL 0x1bb3 6510#define mmOTG1_OTG_V_TOTAL_CONTROL_BASE_IDX 2 6511#define mmOTG1_OTG_V_TOTAL_INT_STATUS 0x1bb4 6512#define mmOTG1_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 6513#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS 0x1bb5 6514#define mmOTG1_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 6515#define mmOTG1_OTG_V_BLANK_START_END 0x1bb6 6516#define mmOTG1_OTG_V_BLANK_START_END_BASE_IDX 2 6517#define mmOTG1_OTG_V_SYNC_A 0x1bb7 6518#define mmOTG1_OTG_V_SYNC_A_BASE_IDX 2 6519#define mmOTG1_OTG_V_SYNC_A_CNTL 0x1bb8 6520#define mmOTG1_OTG_V_SYNC_A_CNTL_BASE_IDX 2 6521#define mmOTG1_OTG_TRIGA_CNTL 0x1bb9 6522#define mmOTG1_OTG_TRIGA_CNTL_BASE_IDX 2 6523#define mmOTG1_OTG_TRIGA_MANUAL_TRIG 0x1bba 6524#define mmOTG1_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 6525#define mmOTG1_OTG_TRIGB_CNTL 0x1bbb 6526#define mmOTG1_OTG_TRIGB_CNTL_BASE_IDX 2 6527#define mmOTG1_OTG_TRIGB_MANUAL_TRIG 0x1bbc 6528#define mmOTG1_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 6529#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL 0x1bbd 6530#define mmOTG1_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 6531#define mmOTG1_OTG_FLOW_CONTROL 0x1bbe 6532#define mmOTG1_OTG_FLOW_CONTROL_BASE_IDX 2 6533#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE 0x1bbf 6534#define mmOTG1_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 6535#define mmOTG1_OTG_AVSYNC_COUNTER 0x1bc0 6536#define mmOTG1_OTG_AVSYNC_COUNTER_BASE_IDX 2 6537#define mmOTG1_OTG_CONTROL 0x1bc1 6538#define mmOTG1_OTG_CONTROL_BASE_IDX 2 6539#define mmOTG1_OTG_BLANK_CONTROL 0x1bc2 6540#define mmOTG1_OTG_BLANK_CONTROL_BASE_IDX 2 6541#define mmOTG1_OTG_PIPE_ABORT_CONTROL 0x1bc3 6542#define mmOTG1_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 6543#define mmOTG1_OTG_INTERLACE_CONTROL 0x1bc4 6544#define mmOTG1_OTG_INTERLACE_CONTROL_BASE_IDX 2 6545#define mmOTG1_OTG_INTERLACE_STATUS 0x1bc5 6546#define mmOTG1_OTG_INTERLACE_STATUS_BASE_IDX 2 6547#define mmOTG1_OTG_FIELD_INDICATION_CONTROL 0x1bc6 6548#define mmOTG1_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 6549#define mmOTG1_OTG_PIXEL_DATA_READBACK0 0x1bc7 6550#define mmOTG1_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 6551#define mmOTG1_OTG_PIXEL_DATA_READBACK1 0x1bc8 6552#define mmOTG1_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 6553#define mmOTG1_OTG_STATUS 0x1bc9 6554#define mmOTG1_OTG_STATUS_BASE_IDX 2 6555#define mmOTG1_OTG_STATUS_POSITION 0x1bca 6556#define mmOTG1_OTG_STATUS_POSITION_BASE_IDX 2 6557#define mmOTG1_OTG_NOM_VERT_POSITION 0x1bcb 6558#define mmOTG1_OTG_NOM_VERT_POSITION_BASE_IDX 2 6559#define mmOTG1_OTG_STATUS_FRAME_COUNT 0x1bcc 6560#define mmOTG1_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 6561#define mmOTG1_OTG_STATUS_VF_COUNT 0x1bcd 6562#define mmOTG1_OTG_STATUS_VF_COUNT_BASE_IDX 2 6563#define mmOTG1_OTG_STATUS_HV_COUNT 0x1bce 6564#define mmOTG1_OTG_STATUS_HV_COUNT_BASE_IDX 2 6565#define mmOTG1_OTG_COUNT_CONTROL 0x1bcf 6566#define mmOTG1_OTG_COUNT_CONTROL_BASE_IDX 2 6567#define mmOTG1_OTG_COUNT_RESET 0x1bd0 6568#define mmOTG1_OTG_COUNT_RESET_BASE_IDX 2 6569#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1bd1 6570#define mmOTG1_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 6571#define mmOTG1_OTG_VERT_SYNC_CONTROL 0x1bd2 6572#define mmOTG1_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 6573#define mmOTG1_OTG_STEREO_STATUS 0x1bd3 6574#define mmOTG1_OTG_STEREO_STATUS_BASE_IDX 2 6575#define mmOTG1_OTG_STEREO_CONTROL 0x1bd4 6576#define mmOTG1_OTG_STEREO_CONTROL_BASE_IDX 2 6577#define mmOTG1_OTG_SNAPSHOT_STATUS 0x1bd5 6578#define mmOTG1_OTG_SNAPSHOT_STATUS_BASE_IDX 2 6579#define mmOTG1_OTG_SNAPSHOT_CONTROL 0x1bd6 6580#define mmOTG1_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 6581#define mmOTG1_OTG_SNAPSHOT_POSITION 0x1bd7 6582#define mmOTG1_OTG_SNAPSHOT_POSITION_BASE_IDX 2 6583#define mmOTG1_OTG_SNAPSHOT_FRAME 0x1bd8 6584#define mmOTG1_OTG_SNAPSHOT_FRAME_BASE_IDX 2 6585#define mmOTG1_OTG_INTERRUPT_CONTROL 0x1bd9 6586#define mmOTG1_OTG_INTERRUPT_CONTROL_BASE_IDX 2 6587#define mmOTG1_OTG_UPDATE_LOCK 0x1bda 6588#define mmOTG1_OTG_UPDATE_LOCK_BASE_IDX 2 6589#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL 0x1bdb 6590#define mmOTG1_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 6591#define mmOTG1_OTG_TEST_PATTERN_CONTROL 0x1bdc 6592#define mmOTG1_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 6593#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS 0x1bdd 6594#define mmOTG1_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 6595#define mmOTG1_OTG_TEST_PATTERN_COLOR 0x1bde 6596#define mmOTG1_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 6597#define mmOTG1_OTG_MASTER_EN 0x1bdf 6598#define mmOTG1_OTG_MASTER_EN_BASE_IDX 2 6599#define mmOTG1_OTG_BLANK_DATA_COLOR 0x1be1 6600#define mmOTG1_OTG_BLANK_DATA_COLOR_BASE_IDX 2 6601#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT 0x1be2 6602#define mmOTG1_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 6603#define mmOTG1_OTG_BLACK_COLOR 0x1be3 6604#define mmOTG1_OTG_BLACK_COLOR_BASE_IDX 2 6605#define mmOTG1_OTG_BLACK_COLOR_EXT 0x1be4 6606#define mmOTG1_OTG_BLACK_COLOR_EXT_BASE_IDX 2 6607#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION 0x1be5 6608#define mmOTG1_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 6609#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1be6 6610#define mmOTG1_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 6611#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION 0x1be7 6612#define mmOTG1_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 6613#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1be8 6614#define mmOTG1_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 6615#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION 0x1be9 6616#define mmOTG1_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 6617#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1bea 6618#define mmOTG1_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 6619#define mmOTG1_OTG_CRC_CNTL 0x1beb 6620#define mmOTG1_OTG_CRC_CNTL_BASE_IDX 2 6621#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL 0x1bec 6622#define mmOTG1_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 6623#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL 0x1bed 6624#define mmOTG1_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 6625#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL 0x1bee 6626#define mmOTG1_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 6627#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL 0x1bef 6628#define mmOTG1_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 6629#define mmOTG1_OTG_CRC0_DATA_RG 0x1bf0 6630#define mmOTG1_OTG_CRC0_DATA_RG_BASE_IDX 2 6631#define mmOTG1_OTG_CRC0_DATA_B 0x1bf1 6632#define mmOTG1_OTG_CRC0_DATA_B_BASE_IDX 2 6633#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL 0x1bf2 6634#define mmOTG1_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 6635#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL 0x1bf3 6636#define mmOTG1_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 6637#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL 0x1bf4 6638#define mmOTG1_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 6639#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL 0x1bf5 6640#define mmOTG1_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 6641#define mmOTG1_OTG_CRC1_DATA_RG 0x1bf6 6642#define mmOTG1_OTG_CRC1_DATA_RG_BASE_IDX 2 6643#define mmOTG1_OTG_CRC1_DATA_B 0x1bf7 6644#define mmOTG1_OTG_CRC1_DATA_B_BASE_IDX 2 6645#define mmOTG1_OTG_CRC2_DATA_RG 0x1bf8 6646#define mmOTG1_OTG_CRC2_DATA_RG_BASE_IDX 2 6647#define mmOTG1_OTG_CRC2_DATA_B 0x1bf9 6648#define mmOTG1_OTG_CRC2_DATA_B_BASE_IDX 2 6649#define mmOTG1_OTG_CRC3_DATA_RG 0x1bfa 6650#define mmOTG1_OTG_CRC3_DATA_RG_BASE_IDX 2 6651#define mmOTG1_OTG_CRC3_DATA_B 0x1bfb 6652#define mmOTG1_OTG_CRC3_DATA_B_BASE_IDX 2 6653#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK 0x1bfc 6654#define mmOTG1_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 6655#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1bfd 6656#define mmOTG1_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 6657#define mmOTG1_OTG_STATIC_SCREEN_CONTROL 0x1c04 6658#define mmOTG1_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 6659#define mmOTG1_OTG_3D_STRUCTURE_CONTROL 0x1c05 6660#define mmOTG1_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 6661#define mmOTG1_OTG_GSL_VSYNC_GAP 0x1c06 6662#define mmOTG1_OTG_GSL_VSYNC_GAP_BASE_IDX 2 6663#define mmOTG1_OTG_MASTER_UPDATE_MODE 0x1c07 6664#define mmOTG1_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 6665#define mmOTG1_OTG_CLOCK_CONTROL 0x1c08 6666#define mmOTG1_OTG_CLOCK_CONTROL_BASE_IDX 2 6667#define mmOTG1_OTG_VSTARTUP_PARAM 0x1c09 6668#define mmOTG1_OTG_VSTARTUP_PARAM_BASE_IDX 2 6669#define mmOTG1_OTG_VUPDATE_PARAM 0x1c0a 6670#define mmOTG1_OTG_VUPDATE_PARAM_BASE_IDX 2 6671#define mmOTG1_OTG_VREADY_PARAM 0x1c0b 6672#define mmOTG1_OTG_VREADY_PARAM_BASE_IDX 2 6673#define mmOTG1_OTG_GLOBAL_SYNC_STATUS 0x1c0c 6674#define mmOTG1_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 6675#define mmOTG1_OTG_MASTER_UPDATE_LOCK 0x1c0d 6676#define mmOTG1_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 6677#define mmOTG1_OTG_GSL_CONTROL 0x1c0e 6678#define mmOTG1_OTG_GSL_CONTROL_BASE_IDX 2 6679#define mmOTG1_OTG_GSL_WINDOW_X 0x1c0f 6680#define mmOTG1_OTG_GSL_WINDOW_X_BASE_IDX 2 6681#define mmOTG1_OTG_GSL_WINDOW_Y 0x1c10 6682#define mmOTG1_OTG_GSL_WINDOW_Y_BASE_IDX 2 6683#define mmOTG1_OTG_VUPDATE_KEEPOUT 0x1c11 6684#define mmOTG1_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 6685#define mmOTG1_OTG_GLOBAL_CONTROL0 0x1c12 6686#define mmOTG1_OTG_GLOBAL_CONTROL0_BASE_IDX 2 6687#define mmOTG1_OTG_GLOBAL_CONTROL1 0x1c13 6688#define mmOTG1_OTG_GLOBAL_CONTROL1_BASE_IDX 2 6689#define mmOTG1_OTG_GLOBAL_CONTROL2 0x1c14 6690#define mmOTG1_OTG_GLOBAL_CONTROL2_BASE_IDX 2 6691#define mmOTG1_OTG_GLOBAL_CONTROL3 0x1c15 6692#define mmOTG1_OTG_GLOBAL_CONTROL3_BASE_IDX 2 6693#define mmOTG1_OTG_TRIG_MANUAL_CONTROL 0x1c16 6694#define mmOTG1_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 6695#define mmOTG1_OTG_MANUAL_FLOW_CONTROL 0x1c17 6696#define mmOTG1_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 6697#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS 0x1c18 6698#define mmOTG1_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 6699#define mmOTG1_OTG_DRR_CONTROL 0x1c19 6700#define mmOTG1_OTG_DRR_CONTROL_BASE_IDX 2 6701#define mmOTG1_OTG_REQUEST_CONTROL 0x1c1a 6702#define mmOTG1_OTG_REQUEST_CONTROL_BASE_IDX 2 6703#define mmOTG1_OTG_SPARE_REGISTER 0x1c1b 6704#define mmOTG1_OTG_SPARE_REGISTER_BASE_IDX 2 6705 6706 6707// addressBlock: dce_dc_optc_otg2_dispdec 6708// base address: 0x400 6709#define mmOTG2_OTG_H_TOTAL 0x1c2a 6710#define mmOTG2_OTG_H_TOTAL_BASE_IDX 2 6711#define mmOTG2_OTG_H_BLANK_START_END 0x1c2b 6712#define mmOTG2_OTG_H_BLANK_START_END_BASE_IDX 2 6713#define mmOTG2_OTG_H_SYNC_A 0x1c2c 6714#define mmOTG2_OTG_H_SYNC_A_BASE_IDX 2 6715#define mmOTG2_OTG_H_SYNC_A_CNTL 0x1c2d 6716#define mmOTG2_OTG_H_SYNC_A_CNTL_BASE_IDX 2 6717#define mmOTG2_OTG_H_TIMING_CNTL 0x1c2e 6718#define mmOTG2_OTG_H_TIMING_CNTL_BASE_IDX 2 6719#define mmOTG2_OTG_V_TOTAL 0x1c2f 6720#define mmOTG2_OTG_V_TOTAL_BASE_IDX 2 6721#define mmOTG2_OTG_V_TOTAL_MIN 0x1c30 6722#define mmOTG2_OTG_V_TOTAL_MIN_BASE_IDX 2 6723#define mmOTG2_OTG_V_TOTAL_MAX 0x1c31 6724#define mmOTG2_OTG_V_TOTAL_MAX_BASE_IDX 2 6725#define mmOTG2_OTG_V_TOTAL_MID 0x1c32 6726#define mmOTG2_OTG_V_TOTAL_MID_BASE_IDX 2 6727#define mmOTG2_OTG_V_TOTAL_CONTROL 0x1c33 6728#define mmOTG2_OTG_V_TOTAL_CONTROL_BASE_IDX 2 6729#define mmOTG2_OTG_V_TOTAL_INT_STATUS 0x1c34 6730#define mmOTG2_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 6731#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS 0x1c35 6732#define mmOTG2_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 6733#define mmOTG2_OTG_V_BLANK_START_END 0x1c36 6734#define mmOTG2_OTG_V_BLANK_START_END_BASE_IDX 2 6735#define mmOTG2_OTG_V_SYNC_A 0x1c37 6736#define mmOTG2_OTG_V_SYNC_A_BASE_IDX 2 6737#define mmOTG2_OTG_V_SYNC_A_CNTL 0x1c38 6738#define mmOTG2_OTG_V_SYNC_A_CNTL_BASE_IDX 2 6739#define mmOTG2_OTG_TRIGA_CNTL 0x1c39 6740#define mmOTG2_OTG_TRIGA_CNTL_BASE_IDX 2 6741#define mmOTG2_OTG_TRIGA_MANUAL_TRIG 0x1c3a 6742#define mmOTG2_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 6743#define mmOTG2_OTG_TRIGB_CNTL 0x1c3b 6744#define mmOTG2_OTG_TRIGB_CNTL_BASE_IDX 2 6745#define mmOTG2_OTG_TRIGB_MANUAL_TRIG 0x1c3c 6746#define mmOTG2_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 6747#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL 0x1c3d 6748#define mmOTG2_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 6749#define mmOTG2_OTG_FLOW_CONTROL 0x1c3e 6750#define mmOTG2_OTG_FLOW_CONTROL_BASE_IDX 2 6751#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE 0x1c3f 6752#define mmOTG2_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 6753#define mmOTG2_OTG_AVSYNC_COUNTER 0x1c40 6754#define mmOTG2_OTG_AVSYNC_COUNTER_BASE_IDX 2 6755#define mmOTG2_OTG_CONTROL 0x1c41 6756#define mmOTG2_OTG_CONTROL_BASE_IDX 2 6757#define mmOTG2_OTG_BLANK_CONTROL 0x1c42 6758#define mmOTG2_OTG_BLANK_CONTROL_BASE_IDX 2 6759#define mmOTG2_OTG_PIPE_ABORT_CONTROL 0x1c43 6760#define mmOTG2_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 6761#define mmOTG2_OTG_INTERLACE_CONTROL 0x1c44 6762#define mmOTG2_OTG_INTERLACE_CONTROL_BASE_IDX 2 6763#define mmOTG2_OTG_INTERLACE_STATUS 0x1c45 6764#define mmOTG2_OTG_INTERLACE_STATUS_BASE_IDX 2 6765#define mmOTG2_OTG_FIELD_INDICATION_CONTROL 0x1c46 6766#define mmOTG2_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 6767#define mmOTG2_OTG_PIXEL_DATA_READBACK0 0x1c47 6768#define mmOTG2_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 6769#define mmOTG2_OTG_PIXEL_DATA_READBACK1 0x1c48 6770#define mmOTG2_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 6771#define mmOTG2_OTG_STATUS 0x1c49 6772#define mmOTG2_OTG_STATUS_BASE_IDX 2 6773#define mmOTG2_OTG_STATUS_POSITION 0x1c4a 6774#define mmOTG2_OTG_STATUS_POSITION_BASE_IDX 2 6775#define mmOTG2_OTG_NOM_VERT_POSITION 0x1c4b 6776#define mmOTG2_OTG_NOM_VERT_POSITION_BASE_IDX 2 6777#define mmOTG2_OTG_STATUS_FRAME_COUNT 0x1c4c 6778#define mmOTG2_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 6779#define mmOTG2_OTG_STATUS_VF_COUNT 0x1c4d 6780#define mmOTG2_OTG_STATUS_VF_COUNT_BASE_IDX 2 6781#define mmOTG2_OTG_STATUS_HV_COUNT 0x1c4e 6782#define mmOTG2_OTG_STATUS_HV_COUNT_BASE_IDX 2 6783#define mmOTG2_OTG_COUNT_CONTROL 0x1c4f 6784#define mmOTG2_OTG_COUNT_CONTROL_BASE_IDX 2 6785#define mmOTG2_OTG_COUNT_RESET 0x1c50 6786#define mmOTG2_OTG_COUNT_RESET_BASE_IDX 2 6787#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1c51 6788#define mmOTG2_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 6789#define mmOTG2_OTG_VERT_SYNC_CONTROL 0x1c52 6790#define mmOTG2_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 6791#define mmOTG2_OTG_STEREO_STATUS 0x1c53 6792#define mmOTG2_OTG_STEREO_STATUS_BASE_IDX 2 6793#define mmOTG2_OTG_STEREO_CONTROL 0x1c54 6794#define mmOTG2_OTG_STEREO_CONTROL_BASE_IDX 2 6795#define mmOTG2_OTG_SNAPSHOT_STATUS 0x1c55 6796#define mmOTG2_OTG_SNAPSHOT_STATUS_BASE_IDX 2 6797#define mmOTG2_OTG_SNAPSHOT_CONTROL 0x1c56 6798#define mmOTG2_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 6799#define mmOTG2_OTG_SNAPSHOT_POSITION 0x1c57 6800#define mmOTG2_OTG_SNAPSHOT_POSITION_BASE_IDX 2 6801#define mmOTG2_OTG_SNAPSHOT_FRAME 0x1c58 6802#define mmOTG2_OTG_SNAPSHOT_FRAME_BASE_IDX 2 6803#define mmOTG2_OTG_INTERRUPT_CONTROL 0x1c59 6804#define mmOTG2_OTG_INTERRUPT_CONTROL_BASE_IDX 2 6805#define mmOTG2_OTG_UPDATE_LOCK 0x1c5a 6806#define mmOTG2_OTG_UPDATE_LOCK_BASE_IDX 2 6807#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL 0x1c5b 6808#define mmOTG2_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 6809#define mmOTG2_OTG_TEST_PATTERN_CONTROL 0x1c5c 6810#define mmOTG2_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 6811#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS 0x1c5d 6812#define mmOTG2_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 6813#define mmOTG2_OTG_TEST_PATTERN_COLOR 0x1c5e 6814#define mmOTG2_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 6815#define mmOTG2_OTG_MASTER_EN 0x1c5f 6816#define mmOTG2_OTG_MASTER_EN_BASE_IDX 2 6817#define mmOTG2_OTG_BLANK_DATA_COLOR 0x1c61 6818#define mmOTG2_OTG_BLANK_DATA_COLOR_BASE_IDX 2 6819#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT 0x1c62 6820#define mmOTG2_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 6821#define mmOTG2_OTG_BLACK_COLOR 0x1c63 6822#define mmOTG2_OTG_BLACK_COLOR_BASE_IDX 2 6823#define mmOTG2_OTG_BLACK_COLOR_EXT 0x1c64 6824#define mmOTG2_OTG_BLACK_COLOR_EXT_BASE_IDX 2 6825#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION 0x1c65 6826#define mmOTG2_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 6827#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1c66 6828#define mmOTG2_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 6829#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION 0x1c67 6830#define mmOTG2_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 6831#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1c68 6832#define mmOTG2_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 6833#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION 0x1c69 6834#define mmOTG2_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 6835#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1c6a 6836#define mmOTG2_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 6837#define mmOTG2_OTG_CRC_CNTL 0x1c6b 6838#define mmOTG2_OTG_CRC_CNTL_BASE_IDX 2 6839#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL 0x1c6c 6840#define mmOTG2_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 6841#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL 0x1c6d 6842#define mmOTG2_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 6843#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL 0x1c6e 6844#define mmOTG2_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 6845#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL 0x1c6f 6846#define mmOTG2_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 6847#define mmOTG2_OTG_CRC0_DATA_RG 0x1c70 6848#define mmOTG2_OTG_CRC0_DATA_RG_BASE_IDX 2 6849#define mmOTG2_OTG_CRC0_DATA_B 0x1c71 6850#define mmOTG2_OTG_CRC0_DATA_B_BASE_IDX 2 6851#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL 0x1c72 6852#define mmOTG2_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 6853#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL 0x1c73 6854#define mmOTG2_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 6855#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL 0x1c74 6856#define mmOTG2_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 6857#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL 0x1c75 6858#define mmOTG2_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 6859#define mmOTG2_OTG_CRC1_DATA_RG 0x1c76 6860#define mmOTG2_OTG_CRC1_DATA_RG_BASE_IDX 2 6861#define mmOTG2_OTG_CRC1_DATA_B 0x1c77 6862#define mmOTG2_OTG_CRC1_DATA_B_BASE_IDX 2 6863#define mmOTG2_OTG_CRC2_DATA_RG 0x1c78 6864#define mmOTG2_OTG_CRC2_DATA_RG_BASE_IDX 2 6865#define mmOTG2_OTG_CRC2_DATA_B 0x1c79 6866#define mmOTG2_OTG_CRC2_DATA_B_BASE_IDX 2 6867#define mmOTG2_OTG_CRC3_DATA_RG 0x1c7a 6868#define mmOTG2_OTG_CRC3_DATA_RG_BASE_IDX 2 6869#define mmOTG2_OTG_CRC3_DATA_B 0x1c7b 6870#define mmOTG2_OTG_CRC3_DATA_B_BASE_IDX 2 6871#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK 0x1c7c 6872#define mmOTG2_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 6873#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1c7d 6874#define mmOTG2_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 6875#define mmOTG2_OTG_STATIC_SCREEN_CONTROL 0x1c84 6876#define mmOTG2_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 6877#define mmOTG2_OTG_3D_STRUCTURE_CONTROL 0x1c85 6878#define mmOTG2_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 6879#define mmOTG2_OTG_GSL_VSYNC_GAP 0x1c86 6880#define mmOTG2_OTG_GSL_VSYNC_GAP_BASE_IDX 2 6881#define mmOTG2_OTG_MASTER_UPDATE_MODE 0x1c87 6882#define mmOTG2_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 6883#define mmOTG2_OTG_CLOCK_CONTROL 0x1c88 6884#define mmOTG2_OTG_CLOCK_CONTROL_BASE_IDX 2 6885#define mmOTG2_OTG_VSTARTUP_PARAM 0x1c89 6886#define mmOTG2_OTG_VSTARTUP_PARAM_BASE_IDX 2 6887#define mmOTG2_OTG_VUPDATE_PARAM 0x1c8a 6888#define mmOTG2_OTG_VUPDATE_PARAM_BASE_IDX 2 6889#define mmOTG2_OTG_VREADY_PARAM 0x1c8b 6890#define mmOTG2_OTG_VREADY_PARAM_BASE_IDX 2 6891#define mmOTG2_OTG_GLOBAL_SYNC_STATUS 0x1c8c 6892#define mmOTG2_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 6893#define mmOTG2_OTG_MASTER_UPDATE_LOCK 0x1c8d 6894#define mmOTG2_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 6895#define mmOTG2_OTG_GSL_CONTROL 0x1c8e 6896#define mmOTG2_OTG_GSL_CONTROL_BASE_IDX 2 6897#define mmOTG2_OTG_GSL_WINDOW_X 0x1c8f 6898#define mmOTG2_OTG_GSL_WINDOW_X_BASE_IDX 2 6899#define mmOTG2_OTG_GSL_WINDOW_Y 0x1c90 6900#define mmOTG2_OTG_GSL_WINDOW_Y_BASE_IDX 2 6901#define mmOTG2_OTG_VUPDATE_KEEPOUT 0x1c91 6902#define mmOTG2_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 6903#define mmOTG2_OTG_GLOBAL_CONTROL0 0x1c92 6904#define mmOTG2_OTG_GLOBAL_CONTROL0_BASE_IDX 2 6905#define mmOTG2_OTG_GLOBAL_CONTROL1 0x1c93 6906#define mmOTG2_OTG_GLOBAL_CONTROL1_BASE_IDX 2 6907#define mmOTG2_OTG_GLOBAL_CONTROL2 0x1c94 6908#define mmOTG2_OTG_GLOBAL_CONTROL2_BASE_IDX 2 6909#define mmOTG2_OTG_GLOBAL_CONTROL3 0x1c95 6910#define mmOTG2_OTG_GLOBAL_CONTROL3_BASE_IDX 2 6911#define mmOTG2_OTG_TRIG_MANUAL_CONTROL 0x1c96 6912#define mmOTG2_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 6913#define mmOTG2_OTG_MANUAL_FLOW_CONTROL 0x1c97 6914#define mmOTG2_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 6915#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS 0x1c98 6916#define mmOTG2_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 6917#define mmOTG2_OTG_DRR_CONTROL 0x1c99 6918#define mmOTG2_OTG_DRR_CONTROL_BASE_IDX 2 6919#define mmOTG2_OTG_REQUEST_CONTROL 0x1c9a 6920#define mmOTG2_OTG_REQUEST_CONTROL_BASE_IDX 2 6921#define mmOTG2_OTG_SPARE_REGISTER 0x1c9b 6922#define mmOTG2_OTG_SPARE_REGISTER_BASE_IDX 2 6923 6924 6925// addressBlock: dce_dc_optc_otg3_dispdec 6926// base address: 0x600 6927#define mmOTG3_OTG_H_TOTAL 0x1caa 6928#define mmOTG3_OTG_H_TOTAL_BASE_IDX 2 6929#define mmOTG3_OTG_H_BLANK_START_END 0x1cab 6930#define mmOTG3_OTG_H_BLANK_START_END_BASE_IDX 2 6931#define mmOTG3_OTG_H_SYNC_A 0x1cac 6932#define mmOTG3_OTG_H_SYNC_A_BASE_IDX 2 6933#define mmOTG3_OTG_H_SYNC_A_CNTL 0x1cad 6934#define mmOTG3_OTG_H_SYNC_A_CNTL_BASE_IDX 2 6935#define mmOTG3_OTG_H_TIMING_CNTL 0x1cae 6936#define mmOTG3_OTG_H_TIMING_CNTL_BASE_IDX 2 6937#define mmOTG3_OTG_V_TOTAL 0x1caf 6938#define mmOTG3_OTG_V_TOTAL_BASE_IDX 2 6939#define mmOTG3_OTG_V_TOTAL_MIN 0x1cb0 6940#define mmOTG3_OTG_V_TOTAL_MIN_BASE_IDX 2 6941#define mmOTG3_OTG_V_TOTAL_MAX 0x1cb1 6942#define mmOTG3_OTG_V_TOTAL_MAX_BASE_IDX 2 6943#define mmOTG3_OTG_V_TOTAL_MID 0x1cb2 6944#define mmOTG3_OTG_V_TOTAL_MID_BASE_IDX 2 6945#define mmOTG3_OTG_V_TOTAL_CONTROL 0x1cb3 6946#define mmOTG3_OTG_V_TOTAL_CONTROL_BASE_IDX 2 6947#define mmOTG3_OTG_V_TOTAL_INT_STATUS 0x1cb4 6948#define mmOTG3_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 6949#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS 0x1cb5 6950#define mmOTG3_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 6951#define mmOTG3_OTG_V_BLANK_START_END 0x1cb6 6952#define mmOTG3_OTG_V_BLANK_START_END_BASE_IDX 2 6953#define mmOTG3_OTG_V_SYNC_A 0x1cb7 6954#define mmOTG3_OTG_V_SYNC_A_BASE_IDX 2 6955#define mmOTG3_OTG_V_SYNC_A_CNTL 0x1cb8 6956#define mmOTG3_OTG_V_SYNC_A_CNTL_BASE_IDX 2 6957#define mmOTG3_OTG_TRIGA_CNTL 0x1cb9 6958#define mmOTG3_OTG_TRIGA_CNTL_BASE_IDX 2 6959#define mmOTG3_OTG_TRIGA_MANUAL_TRIG 0x1cba 6960#define mmOTG3_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 6961#define mmOTG3_OTG_TRIGB_CNTL 0x1cbb 6962#define mmOTG3_OTG_TRIGB_CNTL_BASE_IDX 2 6963#define mmOTG3_OTG_TRIGB_MANUAL_TRIG 0x1cbc 6964#define mmOTG3_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 6965#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL 0x1cbd 6966#define mmOTG3_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 6967#define mmOTG3_OTG_FLOW_CONTROL 0x1cbe 6968#define mmOTG3_OTG_FLOW_CONTROL_BASE_IDX 2 6969#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE 0x1cbf 6970#define mmOTG3_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 6971#define mmOTG3_OTG_AVSYNC_COUNTER 0x1cc0 6972#define mmOTG3_OTG_AVSYNC_COUNTER_BASE_IDX 2 6973#define mmOTG3_OTG_CONTROL 0x1cc1 6974#define mmOTG3_OTG_CONTROL_BASE_IDX 2 6975#define mmOTG3_OTG_BLANK_CONTROL 0x1cc2 6976#define mmOTG3_OTG_BLANK_CONTROL_BASE_IDX 2 6977#define mmOTG3_OTG_PIPE_ABORT_CONTROL 0x1cc3 6978#define mmOTG3_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 6979#define mmOTG3_OTG_INTERLACE_CONTROL 0x1cc4 6980#define mmOTG3_OTG_INTERLACE_CONTROL_BASE_IDX 2 6981#define mmOTG3_OTG_INTERLACE_STATUS 0x1cc5 6982#define mmOTG3_OTG_INTERLACE_STATUS_BASE_IDX 2 6983#define mmOTG3_OTG_FIELD_INDICATION_CONTROL 0x1cc6 6984#define mmOTG3_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 6985#define mmOTG3_OTG_PIXEL_DATA_READBACK0 0x1cc7 6986#define mmOTG3_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 6987#define mmOTG3_OTG_PIXEL_DATA_READBACK1 0x1cc8 6988#define mmOTG3_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 6989#define mmOTG3_OTG_STATUS 0x1cc9 6990#define mmOTG3_OTG_STATUS_BASE_IDX 2 6991#define mmOTG3_OTG_STATUS_POSITION 0x1cca 6992#define mmOTG3_OTG_STATUS_POSITION_BASE_IDX 2 6993#define mmOTG3_OTG_NOM_VERT_POSITION 0x1ccb 6994#define mmOTG3_OTG_NOM_VERT_POSITION_BASE_IDX 2 6995#define mmOTG3_OTG_STATUS_FRAME_COUNT 0x1ccc 6996#define mmOTG3_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 6997#define mmOTG3_OTG_STATUS_VF_COUNT 0x1ccd 6998#define mmOTG3_OTG_STATUS_VF_COUNT_BASE_IDX 2 6999#define mmOTG3_OTG_STATUS_HV_COUNT 0x1cce 7000#define mmOTG3_OTG_STATUS_HV_COUNT_BASE_IDX 2
7001#define mmOTG3_OTG_COUNT_CONTROL 0x1ccf 7002#define mmOTG3_OTG_COUNT_CONTROL_BASE_IDX 2 7003#define mmOTG3_OTG_COUNT_RESET 0x1cd0 7004#define mmOTG3_OTG_COUNT_RESET_BASE_IDX 2 7005#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1cd1 7006#define mmOTG3_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 7007#define mmOTG3_OTG_VERT_SYNC_CONTROL 0x1cd2 7008#define mmOTG3_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 7009#define mmOTG3_OTG_STEREO_STATUS 0x1cd3 7010#define mmOTG3_OTG_STEREO_STATUS_BASE_IDX 2 7011#define mmOTG3_OTG_STEREO_CONTROL 0x1cd4 7012#define mmOTG3_OTG_STEREO_CONTROL_BASE_IDX 2 7013#define mmOTG3_OTG_SNAPSHOT_STATUS 0x1cd5 7014#define mmOTG3_OTG_SNAPSHOT_STATUS_BASE_IDX 2 7015#define mmOTG3_OTG_SNAPSHOT_CONTROL 0x1cd6 7016#define mmOTG3_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 7017#define mmOTG3_OTG_SNAPSHOT_POSITION 0x1cd7 7018#define mmOTG3_OTG_SNAPSHOT_POSITION_BASE_IDX 2 7019#define mmOTG3_OTG_SNAPSHOT_FRAME 0x1cd8 7020#define mmOTG3_OTG_SNAPSHOT_FRAME_BASE_IDX 2 7021#define mmOTG3_OTG_INTERRUPT_CONTROL 0x1cd9 7022#define mmOTG3_OTG_INTERRUPT_CONTROL_BASE_IDX 2 7023#define mmOTG3_OTG_UPDATE_LOCK 0x1cda 7024#define mmOTG3_OTG_UPDATE_LOCK_BASE_IDX 2 7025#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL 0x1cdb 7026#define mmOTG3_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 7027#define mmOTG3_OTG_TEST_PATTERN_CONTROL 0x1cdc 7028#define mmOTG3_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 7029#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS 0x1cdd 7030#define mmOTG3_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 7031#define mmOTG3_OTG_TEST_PATTERN_COLOR 0x1cde 7032#define mmOTG3_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 7033#define mmOTG3_OTG_MASTER_EN 0x1cdf 7034#define mmOTG3_OTG_MASTER_EN_BASE_IDX 2 7035#define mmOTG3_OTG_BLANK_DATA_COLOR 0x1ce1 7036#define mmOTG3_OTG_BLANK_DATA_COLOR_BASE_IDX 2 7037#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT 0x1ce2 7038#define mmOTG3_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 7039#define mmOTG3_OTG_BLACK_COLOR 0x1ce3 7040#define mmOTG3_OTG_BLACK_COLOR_BASE_IDX 2 7041#define mmOTG3_OTG_BLACK_COLOR_EXT 0x1ce4 7042#define mmOTG3_OTG_BLACK_COLOR_EXT_BASE_IDX 2 7043#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION 0x1ce5 7044#define mmOTG3_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 7045#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1ce6 7046#define mmOTG3_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 7047#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION 0x1ce7 7048#define mmOTG3_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 7049#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1ce8 7050#define mmOTG3_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 7051#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION 0x1ce9 7052#define mmOTG3_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 7053#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1cea 7054#define mmOTG3_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 7055#define mmOTG3_OTG_CRC_CNTL 0x1ceb 7056#define mmOTG3_OTG_CRC_CNTL_BASE_IDX 2 7057#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL 0x1cec 7058#define mmOTG3_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 7059#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ced 7060#define mmOTG3_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 7061#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL 0x1cee 7062#define mmOTG3_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 7063#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL 0x1cef 7064#define mmOTG3_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 7065#define mmOTG3_OTG_CRC0_DATA_RG 0x1cf0 7066#define mmOTG3_OTG_CRC0_DATA_RG_BASE_IDX 2 7067#define mmOTG3_OTG_CRC0_DATA_B 0x1cf1 7068#define mmOTG3_OTG_CRC0_DATA_B_BASE_IDX 2 7069#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL 0x1cf2 7070#define mmOTG3_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 7071#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL 0x1cf3 7072#define mmOTG3_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 7073#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL 0x1cf4 7074#define mmOTG3_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 7075#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL 0x1cf5 7076#define mmOTG3_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 7077#define mmOTG3_OTG_CRC1_DATA_RG 0x1cf6 7078#define mmOTG3_OTG_CRC1_DATA_RG_BASE_IDX 2 7079#define mmOTG3_OTG_CRC1_DATA_B 0x1cf7 7080#define mmOTG3_OTG_CRC1_DATA_B_BASE_IDX 2 7081#define mmOTG3_OTG_CRC2_DATA_RG 0x1cf8 7082#define mmOTG3_OTG_CRC2_DATA_RG_BASE_IDX 2 7083#define mmOTG3_OTG_CRC2_DATA_B 0x1cf9 7084#define mmOTG3_OTG_CRC2_DATA_B_BASE_IDX 2 7085#define mmOTG3_OTG_CRC3_DATA_RG 0x1cfa 7086#define mmOTG3_OTG_CRC3_DATA_RG_BASE_IDX 2 7087#define mmOTG3_OTG_CRC3_DATA_B 0x1cfb 7088#define mmOTG3_OTG_CRC3_DATA_B_BASE_IDX 2 7089#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK 0x1cfc 7090#define mmOTG3_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 7091#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1cfd 7092#define mmOTG3_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 7093#define mmOTG3_OTG_STATIC_SCREEN_CONTROL 0x1d04 7094#define mmOTG3_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 7095#define mmOTG3_OTG_3D_STRUCTURE_CONTROL 0x1d05 7096#define mmOTG3_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 7097#define mmOTG3_OTG_GSL_VSYNC_GAP 0x1d06 7098#define mmOTG3_OTG_GSL_VSYNC_GAP_BASE_IDX 2 7099#define mmOTG3_OTG_MASTER_UPDATE_MODE 0x1d07 7100#define mmOTG3_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 7101#define mmOTG3_OTG_CLOCK_CONTROL 0x1d08 7102#define mmOTG3_OTG_CLOCK_CONTROL_BASE_IDX 2 7103#define mmOTG3_OTG_VSTARTUP_PARAM 0x1d09 7104#define mmOTG3_OTG_VSTARTUP_PARAM_BASE_IDX 2 7105#define mmOTG3_OTG_VUPDATE_PARAM 0x1d0a 7106#define mmOTG3_OTG_VUPDATE_PARAM_BASE_IDX 2 7107#define mmOTG3_OTG_VREADY_PARAM 0x1d0b 7108#define mmOTG3_OTG_VREADY_PARAM_BASE_IDX 2 7109#define mmOTG3_OTG_GLOBAL_SYNC_STATUS 0x1d0c 7110#define mmOTG3_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 7111#define mmOTG3_OTG_MASTER_UPDATE_LOCK 0x1d0d 7112#define mmOTG3_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 7113#define mmOTG3_OTG_GSL_CONTROL 0x1d0e 7114#define mmOTG3_OTG_GSL_CONTROL_BASE_IDX 2 7115#define mmOTG3_OTG_GSL_WINDOW_X 0x1d0f 7116#define mmOTG3_OTG_GSL_WINDOW_X_BASE_IDX 2 7117#define mmOTG3_OTG_GSL_WINDOW_Y 0x1d10 7118#define mmOTG3_OTG_GSL_WINDOW_Y_BASE_IDX 2 7119#define mmOTG3_OTG_VUPDATE_KEEPOUT 0x1d11 7120#define mmOTG3_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 7121#define mmOTG3_OTG_GLOBAL_CONTROL0 0x1d12 7122#define mmOTG3_OTG_GLOBAL_CONTROL0_BASE_IDX 2 7123#define mmOTG3_OTG_GLOBAL_CONTROL1 0x1d13 7124#define mmOTG3_OTG_GLOBAL_CONTROL1_BASE_IDX 2 7125#define mmOTG3_OTG_GLOBAL_CONTROL2 0x1d14 7126#define mmOTG3_OTG_GLOBAL_CONTROL2_BASE_IDX 2 7127#define mmOTG3_OTG_GLOBAL_CONTROL3 0x1d15 7128#define mmOTG3_OTG_GLOBAL_CONTROL3_BASE_IDX 2 7129#define mmOTG3_OTG_TRIG_MANUAL_CONTROL 0x1d16 7130#define mmOTG3_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 7131#define mmOTG3_OTG_MANUAL_FLOW_CONTROL 0x1d17 7132#define mmOTG3_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 7133#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS 0x1d18 7134#define mmOTG3_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 7135#define mmOTG3_OTG_DRR_CONTROL 0x1d19 7136#define mmOTG3_OTG_DRR_CONTROL_BASE_IDX 2 7137#define mmOTG3_OTG_REQUEST_CONTROL 0x1d1a 7138#define mmOTG3_OTG_REQUEST_CONTROL_BASE_IDX 2 7139#define mmOTG3_OTG_SPARE_REGISTER 0x1d1b 7140#define mmOTG3_OTG_SPARE_REGISTER_BASE_IDX 2 7141 7142 7143// addressBlock: dce_dc_optc_otg4_dispdec 7144// base address: 0x800 7145#define mmOTG4_OTG_H_TOTAL 0x1d2a 7146#define mmOTG4_OTG_H_TOTAL_BASE_IDX 2 7147#define mmOTG4_OTG_H_BLANK_START_END 0x1d2b 7148#define mmOTG4_OTG_H_BLANK_START_END_BASE_IDX 2 7149#define mmOTG4_OTG_H_SYNC_A 0x1d2c 7150#define mmOTG4_OTG_H_SYNC_A_BASE_IDX 2 7151#define mmOTG4_OTG_H_SYNC_A_CNTL 0x1d2d 7152#define mmOTG4_OTG_H_SYNC_A_CNTL_BASE_IDX 2 7153#define mmOTG4_OTG_H_TIMING_CNTL 0x1d2e 7154#define mmOTG4_OTG_H_TIMING_CNTL_BASE_IDX 2 7155#define mmOTG4_OTG_V_TOTAL 0x1d2f 7156#define mmOTG4_OTG_V_TOTAL_BASE_IDX 2 7157#define mmOTG4_OTG_V_TOTAL_MIN 0x1d30 7158#define mmOTG4_OTG_V_TOTAL_MIN_BASE_IDX 2 7159#define mmOTG4_OTG_V_TOTAL_MAX 0x1d31 7160#define mmOTG4_OTG_V_TOTAL_MAX_BASE_IDX 2 7161#define mmOTG4_OTG_V_TOTAL_MID 0x1d32 7162#define mmOTG4_OTG_V_TOTAL_MID_BASE_IDX 2 7163#define mmOTG4_OTG_V_TOTAL_CONTROL 0x1d33 7164#define mmOTG4_OTG_V_TOTAL_CONTROL_BASE_IDX 2 7165#define mmOTG4_OTG_V_TOTAL_INT_STATUS 0x1d34 7166#define mmOTG4_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 7167#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS 0x1d35 7168#define mmOTG4_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 7169#define mmOTG4_OTG_V_BLANK_START_END 0x1d36 7170#define mmOTG4_OTG_V_BLANK_START_END_BASE_IDX 2 7171#define mmOTG4_OTG_V_SYNC_A 0x1d37 7172#define mmOTG4_OTG_V_SYNC_A_BASE_IDX 2 7173#define mmOTG4_OTG_V_SYNC_A_CNTL 0x1d38 7174#define mmOTG4_OTG_V_SYNC_A_CNTL_BASE_IDX 2 7175#define mmOTG4_OTG_TRIGA_CNTL 0x1d39 7176#define mmOTG4_OTG_TRIGA_CNTL_BASE_IDX 2 7177#define mmOTG4_OTG_TRIGA_MANUAL_TRIG 0x1d3a 7178#define mmOTG4_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 7179#define mmOTG4_OTG_TRIGB_CNTL 0x1d3b 7180#define mmOTG4_OTG_TRIGB_CNTL_BASE_IDX 2 7181#define mmOTG4_OTG_TRIGB_MANUAL_TRIG 0x1d3c 7182#define mmOTG4_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 7183#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL 0x1d3d 7184#define mmOTG4_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 7185#define mmOTG4_OTG_FLOW_CONTROL 0x1d3e 7186#define mmOTG4_OTG_FLOW_CONTROL_BASE_IDX 2 7187#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE 0x1d3f 7188#define mmOTG4_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 7189#define mmOTG4_OTG_AVSYNC_COUNTER 0x1d40 7190#define mmOTG4_OTG_AVSYNC_COUNTER_BASE_IDX 2 7191#define mmOTG4_OTG_CONTROL 0x1d41 7192#define mmOTG4_OTG_CONTROL_BASE_IDX 2 7193#define mmOTG4_OTG_BLANK_CONTROL 0x1d42 7194#define mmOTG4_OTG_BLANK_CONTROL_BASE_IDX 2 7195#define mmOTG4_OTG_PIPE_ABORT_CONTROL 0x1d43 7196#define mmOTG4_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 7197#define mmOTG4_OTG_INTERLACE_CONTROL 0x1d44 7198#define mmOTG4_OTG_INTERLACE_CONTROL_BASE_IDX 2 7199#define mmOTG4_OTG_INTERLACE_STATUS 0x1d45 7200#define mmOTG4_OTG_INTERLACE_STATUS_BASE_IDX 2 7201#define mmOTG4_OTG_FIELD_INDICATION_CONTROL 0x1d46 7202#define mmOTG4_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 7203#define mmOTG4_OTG_PIXEL_DATA_READBACK0 0x1d47 7204#define mmOTG4_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 7205#define mmOTG4_OTG_PIXEL_DATA_READBACK1 0x1d48 7206#define mmOTG4_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 7207#define mmOTG4_OTG_STATUS 0x1d49 7208#define mmOTG4_OTG_STATUS_BASE_IDX 2 7209#define mmOTG4_OTG_STATUS_POSITION 0x1d4a 7210#define mmOTG4_OTG_STATUS_POSITION_BASE_IDX 2 7211#define mmOTG4_OTG_NOM_VERT_POSITION 0x1d4b 7212#define mmOTG4_OTG_NOM_VERT_POSITION_BASE_IDX 2 7213#define mmOTG4_OTG_STATUS_FRAME_COUNT 0x1d4c 7214#define mmOTG4_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 7215#define mmOTG4_OTG_STATUS_VF_COUNT 0x1d4d 7216#define mmOTG4_OTG_STATUS_VF_COUNT_BASE_IDX 2 7217#define mmOTG4_OTG_STATUS_HV_COUNT 0x1d4e 7218#define mmOTG4_OTG_STATUS_HV_COUNT_BASE_IDX 2 7219#define mmOTG4_OTG_COUNT_CONTROL 0x1d4f 7220#define mmOTG4_OTG_COUNT_CONTROL_BASE_IDX 2 7221#define mmOTG4_OTG_COUNT_RESET 0x1d50 7222#define mmOTG4_OTG_COUNT_RESET_BASE_IDX 2 7223#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1d51 7224#define mmOTG4_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 7225#define mmOTG4_OTG_VERT_SYNC_CONTROL 0x1d52 7226#define mmOTG4_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 7227#define mmOTG4_OTG_STEREO_STATUS 0x1d53 7228#define mmOTG4_OTG_STEREO_STATUS_BASE_IDX 2 7229#define mmOTG4_OTG_STEREO_CONTROL 0x1d54 7230#define mmOTG4_OTG_STEREO_CONTROL_BASE_IDX 2 7231#define mmOTG4_OTG_SNAPSHOT_STATUS 0x1d55 7232#define mmOTG4_OTG_SNAPSHOT_STATUS_BASE_IDX 2 7233#define mmOTG4_OTG_SNAPSHOT_CONTROL 0x1d56 7234#define mmOTG4_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 7235#define mmOTG4_OTG_SNAPSHOT_POSITION 0x1d57 7236#define mmOTG4_OTG_SNAPSHOT_POSITION_BASE_IDX 2 7237#define mmOTG4_OTG_SNAPSHOT_FRAME 0x1d58 7238#define mmOTG4_OTG_SNAPSHOT_FRAME_BASE_IDX 2 7239#define mmOTG4_OTG_INTERRUPT_CONTROL 0x1d59 7240#define mmOTG4_OTG_INTERRUPT_CONTROL_BASE_IDX 2 7241#define mmOTG4_OTG_UPDATE_LOCK 0x1d5a 7242#define mmOTG4_OTG_UPDATE_LOCK_BASE_IDX 2 7243#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL 0x1d5b 7244#define mmOTG4_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 7245#define mmOTG4_OTG_TEST_PATTERN_CONTROL 0x1d5c 7246#define mmOTG4_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 7247#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS 0x1d5d 7248#define mmOTG4_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 7249#define mmOTG4_OTG_TEST_PATTERN_COLOR 0x1d5e 7250#define mmOTG4_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 7251#define mmOTG4_OTG_MASTER_EN 0x1d5f 7252#define mmOTG4_OTG_MASTER_EN_BASE_IDX 2 7253#define mmOTG4_OTG_BLANK_DATA_COLOR 0x1d61 7254#define mmOTG4_OTG_BLANK_DATA_COLOR_BASE_IDX 2 7255#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT 0x1d62 7256#define mmOTG4_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 7257#define mmOTG4_OTG_BLACK_COLOR 0x1d63 7258#define mmOTG4_OTG_BLACK_COLOR_BASE_IDX 2 7259#define mmOTG4_OTG_BLACK_COLOR_EXT 0x1d64 7260#define mmOTG4_OTG_BLACK_COLOR_EXT_BASE_IDX 2 7261#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION 0x1d65 7262#define mmOTG4_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 7263#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1d66 7264#define mmOTG4_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 7265#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION 0x1d67 7266#define mmOTG4_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 7267#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1d68 7268#define mmOTG4_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 7269#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION 0x1d69 7270#define mmOTG4_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 7271#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1d6a 7272#define mmOTG4_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 7273#define mmOTG4_OTG_CRC_CNTL 0x1d6b 7274#define mmOTG4_OTG_CRC_CNTL_BASE_IDX 2 7275#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL 0x1d6c 7276#define mmOTG4_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 7277#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL 0x1d6d 7278#define mmOTG4_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 7279#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL 0x1d6e 7280#define mmOTG4_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 7281#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL 0x1d6f 7282#define mmOTG4_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 7283#define mmOTG4_OTG_CRC0_DATA_RG 0x1d70 7284#define mmOTG4_OTG_CRC0_DATA_RG_BASE_IDX 2 7285#define mmOTG4_OTG_CRC0_DATA_B 0x1d71 7286#define mmOTG4_OTG_CRC0_DATA_B_BASE_IDX 2 7287#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL 0x1d72 7288#define mmOTG4_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 7289#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL 0x1d73 7290#define mmOTG4_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 7291#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL 0x1d74 7292#define mmOTG4_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 7293#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL 0x1d75 7294#define mmOTG4_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 7295#define mmOTG4_OTG_CRC1_DATA_RG 0x1d76 7296#define mmOTG4_OTG_CRC1_DATA_RG_BASE_IDX 2 7297#define mmOTG4_OTG_CRC1_DATA_B 0x1d77 7298#define mmOTG4_OTG_CRC1_DATA_B_BASE_IDX 2 7299#define mmOTG4_OTG_CRC2_DATA_RG 0x1d78 7300#define mmOTG4_OTG_CRC2_DATA_RG_BASE_IDX 2 7301#define mmOTG4_OTG_CRC2_DATA_B 0x1d79 7302#define mmOTG4_OTG_CRC2_DATA_B_BASE_IDX 2 7303#define mmOTG4_OTG_CRC3_DATA_RG 0x1d7a 7304#define mmOTG4_OTG_CRC3_DATA_RG_BASE_IDX 2 7305#define mmOTG4_OTG_CRC3_DATA_B 0x1d7b 7306#define mmOTG4_OTG_CRC3_DATA_B_BASE_IDX 2 7307#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK 0x1d7c 7308#define mmOTG4_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 7309#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1d7d 7310#define mmOTG4_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 7311#define mmOTG4_OTG_STATIC_SCREEN_CONTROL 0x1d84 7312#define mmOTG4_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 7313#define mmOTG4_OTG_3D_STRUCTURE_CONTROL 0x1d85 7314#define mmOTG4_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 7315#define mmOTG4_OTG_GSL_VSYNC_GAP 0x1d86 7316#define mmOTG4_OTG_GSL_VSYNC_GAP_BASE_IDX 2 7317#define mmOTG4_OTG_MASTER_UPDATE_MODE 0x1d87 7318#define mmOTG4_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 7319#define mmOTG4_OTG_CLOCK_CONTROL 0x1d88 7320#define mmOTG4_OTG_CLOCK_CONTROL_BASE_IDX 2 7321#define mmOTG4_OTG_VSTARTUP_PARAM 0x1d89 7322#define mmOTG4_OTG_VSTARTUP_PARAM_BASE_IDX 2 7323#define mmOTG4_OTG_VUPDATE_PARAM 0x1d8a 7324#define mmOTG4_OTG_VUPDATE_PARAM_BASE_IDX 2 7325#define mmOTG4_OTG_VREADY_PARAM 0x1d8b 7326#define mmOTG4_OTG_VREADY_PARAM_BASE_IDX 2 7327#define mmOTG4_OTG_GLOBAL_SYNC_STATUS 0x1d8c 7328#define mmOTG4_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 7329#define mmOTG4_OTG_MASTER_UPDATE_LOCK 0x1d8d 7330#define mmOTG4_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 7331#define mmOTG4_OTG_GSL_CONTROL 0x1d8e 7332#define mmOTG4_OTG_GSL_CONTROL_BASE_IDX 2 7333#define mmOTG4_OTG_GSL_WINDOW_X 0x1d8f 7334#define mmOTG4_OTG_GSL_WINDOW_X_BASE_IDX 2 7335#define mmOTG4_OTG_GSL_WINDOW_Y 0x1d90 7336#define mmOTG4_OTG_GSL_WINDOW_Y_BASE_IDX 2 7337#define mmOTG4_OTG_VUPDATE_KEEPOUT 0x1d91 7338#define mmOTG4_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 7339#define mmOTG4_OTG_GLOBAL_CONTROL0 0x1d92 7340#define mmOTG4_OTG_GLOBAL_CONTROL0_BASE_IDX 2 7341#define mmOTG4_OTG_GLOBAL_CONTROL1 0x1d93 7342#define mmOTG4_OTG_GLOBAL_CONTROL1_BASE_IDX 2 7343#define mmOTG4_OTG_GLOBAL_CONTROL2 0x1d94 7344#define mmOTG4_OTG_GLOBAL_CONTROL2_BASE_IDX 2 7345#define mmOTG4_OTG_GLOBAL_CONTROL3 0x1d95 7346#define mmOTG4_OTG_GLOBAL_CONTROL3_BASE_IDX 2 7347#define mmOTG4_OTG_TRIG_MANUAL_CONTROL 0x1d96 7348#define mmOTG4_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 7349#define mmOTG4_OTG_MANUAL_FLOW_CONTROL 0x1d97 7350#define mmOTG4_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 7351#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS 0x1d98 7352#define mmOTG4_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 7353#define mmOTG4_OTG_DRR_CONTROL 0x1d99 7354#define mmOTG4_OTG_DRR_CONTROL_BASE_IDX 2 7355#define mmOTG4_OTG_REQUEST_CONTROL 0x1d9a 7356#define mmOTG4_OTG_REQUEST_CONTROL_BASE_IDX 2 7357#define mmOTG4_OTG_SPARE_REGISTER 0x1d9b 7358#define mmOTG4_OTG_SPARE_REGISTER_BASE_IDX 2 7359 7360 7361// addressBlock: dce_dc_optc_otg5_dispdec 7362// base address: 0xa00 7363#define mmOTG5_OTG_H_TOTAL 0x1daa 7364#define mmOTG5_OTG_H_TOTAL_BASE_IDX 2 7365#define mmOTG5_OTG_H_BLANK_START_END 0x1dab 7366#define mmOTG5_OTG_H_BLANK_START_END_BASE_IDX 2 7367#define mmOTG5_OTG_H_SYNC_A 0x1dac 7368#define mmOTG5_OTG_H_SYNC_A_BASE_IDX 2 7369#define mmOTG5_OTG_H_SYNC_A_CNTL 0x1dad 7370#define mmOTG5_OTG_H_SYNC_A_CNTL_BASE_IDX 2 7371#define mmOTG5_OTG_H_TIMING_CNTL 0x1dae 7372#define mmOTG5_OTG_H_TIMING_CNTL_BASE_IDX 2 7373#define mmOTG5_OTG_V_TOTAL 0x1daf 7374#define mmOTG5_OTG_V_TOTAL_BASE_IDX 2 7375#define mmOTG5_OTG_V_TOTAL_MIN 0x1db0 7376#define mmOTG5_OTG_V_TOTAL_MIN_BASE_IDX 2 7377#define mmOTG5_OTG_V_TOTAL_MAX 0x1db1 7378#define mmOTG5_OTG_V_TOTAL_MAX_BASE_IDX 2 7379#define mmOTG5_OTG_V_TOTAL_MID 0x1db2 7380#define mmOTG5_OTG_V_TOTAL_MID_BASE_IDX 2 7381#define mmOTG5_OTG_V_TOTAL_CONTROL 0x1db3 7382#define mmOTG5_OTG_V_TOTAL_CONTROL_BASE_IDX 2 7383#define mmOTG5_OTG_V_TOTAL_INT_STATUS 0x1db4 7384#define mmOTG5_OTG_V_TOTAL_INT_STATUS_BASE_IDX 2 7385#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS 0x1db5 7386#define mmOTG5_OTG_VSYNC_NOM_INT_STATUS_BASE_IDX 2 7387#define mmOTG5_OTG_V_BLANK_START_END 0x1db6 7388#define mmOTG5_OTG_V_BLANK_START_END_BASE_IDX 2 7389#define mmOTG5_OTG_V_SYNC_A 0x1db7 7390#define mmOTG5_OTG_V_SYNC_A_BASE_IDX 2 7391#define mmOTG5_OTG_V_SYNC_A_CNTL 0x1db8 7392#define mmOTG5_OTG_V_SYNC_A_CNTL_BASE_IDX 2 7393#define mmOTG5_OTG_TRIGA_CNTL 0x1db9 7394#define mmOTG5_OTG_TRIGA_CNTL_BASE_IDX 2 7395#define mmOTG5_OTG_TRIGA_MANUAL_TRIG 0x1dba 7396#define mmOTG5_OTG_TRIGA_MANUAL_TRIG_BASE_IDX 2 7397#define mmOTG5_OTG_TRIGB_CNTL 0x1dbb 7398#define mmOTG5_OTG_TRIGB_CNTL_BASE_IDX 2 7399#define mmOTG5_OTG_TRIGB_MANUAL_TRIG 0x1dbc 7400#define mmOTG5_OTG_TRIGB_MANUAL_TRIG_BASE_IDX 2 7401#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL 0x1dbd 7402#define mmOTG5_OTG_FORCE_COUNT_NOW_CNTL_BASE_IDX 2 7403#define mmOTG5_OTG_FLOW_CONTROL 0x1dbe 7404#define mmOTG5_OTG_FLOW_CONTROL_BASE_IDX 2 7405#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE 0x1dbf 7406#define mmOTG5_OTG_STEREO_FORCE_NEXT_EYE_BASE_IDX 2 7407#define mmOTG5_OTG_AVSYNC_COUNTER 0x1dc0 7408#define mmOTG5_OTG_AVSYNC_COUNTER_BASE_IDX 2 7409#define mmOTG5_OTG_CONTROL 0x1dc1 7410#define mmOTG5_OTG_CONTROL_BASE_IDX 2 7411#define mmOTG5_OTG_BLANK_CONTROL 0x1dc2 7412#define mmOTG5_OTG_BLANK_CONTROL_BASE_IDX 2 7413#define mmOTG5_OTG_PIPE_ABORT_CONTROL 0x1dc3 7414#define mmOTG5_OTG_PIPE_ABORT_CONTROL_BASE_IDX 2 7415#define mmOTG5_OTG_INTERLACE_CONTROL 0x1dc4 7416#define mmOTG5_OTG_INTERLACE_CONTROL_BASE_IDX 2 7417#define mmOTG5_OTG_INTERLACE_STATUS 0x1dc5 7418#define mmOTG5_OTG_INTERLACE_STATUS_BASE_IDX 2 7419#define mmOTG5_OTG_FIELD_INDICATION_CONTROL 0x1dc6 7420#define mmOTG5_OTG_FIELD_INDICATION_CONTROL_BASE_IDX 2 7421#define mmOTG5_OTG_PIXEL_DATA_READBACK0 0x1dc7 7422#define mmOTG5_OTG_PIXEL_DATA_READBACK0_BASE_IDX 2 7423#define mmOTG5_OTG_PIXEL_DATA_READBACK1 0x1dc8 7424#define mmOTG5_OTG_PIXEL_DATA_READBACK1_BASE_IDX 2 7425#define mmOTG5_OTG_STATUS 0x1dc9 7426#define mmOTG5_OTG_STATUS_BASE_IDX 2 7427#define mmOTG5_OTG_STATUS_POSITION 0x1dca 7428#define mmOTG5_OTG_STATUS_POSITION_BASE_IDX 2 7429#define mmOTG5_OTG_NOM_VERT_POSITION 0x1dcb 7430#define mmOTG5_OTG_NOM_VERT_POSITION_BASE_IDX 2 7431#define mmOTG5_OTG_STATUS_FRAME_COUNT 0x1dcc 7432#define mmOTG5_OTG_STATUS_FRAME_COUNT_BASE_IDX 2 7433#define mmOTG5_OTG_STATUS_VF_COUNT 0x1dcd 7434#define mmOTG5_OTG_STATUS_VF_COUNT_BASE_IDX 2 7435#define mmOTG5_OTG_STATUS_HV_COUNT 0x1dce 7436#define mmOTG5_OTG_STATUS_HV_COUNT_BASE_IDX 2 7437#define mmOTG5_OTG_COUNT_CONTROL 0x1dcf 7438#define mmOTG5_OTG_COUNT_CONTROL_BASE_IDX 2 7439#define mmOTG5_OTG_COUNT_RESET 0x1dd0 7440#define mmOTG5_OTG_COUNT_RESET_BASE_IDX 2 7441#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE 0x1dd1 7442#define mmOTG5_OTG_MANUAL_FORCE_VSYNC_NEXT_LINE_BASE_IDX 2 7443#define mmOTG5_OTG_VERT_SYNC_CONTROL 0x1dd2 7444#define mmOTG5_OTG_VERT_SYNC_CONTROL_BASE_IDX 2 7445#define mmOTG5_OTG_STEREO_STATUS 0x1dd3 7446#define mmOTG5_OTG_STEREO_STATUS_BASE_IDX 2 7447#define mmOTG5_OTG_STEREO_CONTROL 0x1dd4 7448#define mmOTG5_OTG_STEREO_CONTROL_BASE_IDX 2 7449#define mmOTG5_OTG_SNAPSHOT_STATUS 0x1dd5 7450#define mmOTG5_OTG_SNAPSHOT_STATUS_BASE_IDX 2 7451#define mmOTG5_OTG_SNAPSHOT_CONTROL 0x1dd6 7452#define mmOTG5_OTG_SNAPSHOT_CONTROL_BASE_IDX 2 7453#define mmOTG5_OTG_SNAPSHOT_POSITION 0x1dd7 7454#define mmOTG5_OTG_SNAPSHOT_POSITION_BASE_IDX 2 7455#define mmOTG5_OTG_SNAPSHOT_FRAME 0x1dd8 7456#define mmOTG5_OTG_SNAPSHOT_FRAME_BASE_IDX 2 7457#define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 7458#define mmOTG5_OTG_INTERRUPT_CONTROL_BASE_IDX 2 7459#define mmOTG5_OTG_UPDATE_LOCK 0x1dda 7460#define mmOTG5_OTG_UPDATE_LOCK_BASE_IDX 2 7461#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL 0x1ddb 7462#define mmOTG5_OTG_DOUBLE_BUFFER_CONTROL_BASE_IDX 2 7463#define mmOTG5_OTG_TEST_PATTERN_CONTROL 0x1ddc 7464#define mmOTG5_OTG_TEST_PATTERN_CONTROL_BASE_IDX 2 7465#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS 0x1ddd 7466#define mmOTG5_OTG_TEST_PATTERN_PARAMETERS_BASE_IDX 2 7467#define mmOTG5_OTG_TEST_PATTERN_COLOR 0x1dde 7468#define mmOTG5_OTG_TEST_PATTERN_COLOR_BASE_IDX 2 7469#define mmOTG5_OTG_MASTER_EN 0x1ddf 7470#define mmOTG5_OTG_MASTER_EN_BASE_IDX 2 7471#define mmOTG5_OTG_BLANK_DATA_COLOR 0x1de1 7472#define mmOTG5_OTG_BLANK_DATA_COLOR_BASE_IDX 2 7473#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT 0x1de2 7474#define mmOTG5_OTG_BLANK_DATA_COLOR_EXT_BASE_IDX 2 7475#define mmOTG5_OTG_BLACK_COLOR 0x1de3 7476#define mmOTG5_OTG_BLACK_COLOR_BASE_IDX 2 7477#define mmOTG5_OTG_BLACK_COLOR_EXT 0x1de4 7478#define mmOTG5_OTG_BLACK_COLOR_EXT_BASE_IDX 2 7479#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION 0x1de5 7480#define mmOTG5_OTG_VERTICAL_INTERRUPT0_POSITION_BASE_IDX 2 7481#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL 0x1de6 7482#define mmOTG5_OTG_VERTICAL_INTERRUPT0_CONTROL_BASE_IDX 2 7483#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION 0x1de7 7484#define mmOTG5_OTG_VERTICAL_INTERRUPT1_POSITION_BASE_IDX 2 7485#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL 0x1de8 7486#define mmOTG5_OTG_VERTICAL_INTERRUPT1_CONTROL_BASE_IDX 2 7487#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION 0x1de9 7488#define mmOTG5_OTG_VERTICAL_INTERRUPT2_POSITION_BASE_IDX 2 7489#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL 0x1dea 7490#define mmOTG5_OTG_VERTICAL_INTERRUPT2_CONTROL_BASE_IDX 2 7491#define mmOTG5_OTG_CRC_CNTL 0x1deb 7492#define mmOTG5_OTG_CRC_CNTL_BASE_IDX 2 7493#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL 0x1dec 7494#define mmOTG5_OTG_CRC0_WINDOWA_X_CONTROL_BASE_IDX 2 7495#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL 0x1ded 7496#define mmOTG5_OTG_CRC0_WINDOWA_Y_CONTROL_BASE_IDX 2 7497#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL 0x1dee 7498#define mmOTG5_OTG_CRC0_WINDOWB_X_CONTROL_BASE_IDX 2 7499#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL 0x1def 7500#define mmOTG5_OTG_CRC0_WINDOWB_Y_CONTROL_BASE_IDX 2 7501#define mmOTG5_OTG_CRC0_DATA_RG 0x1df0 7502#define mmOTG5_OTG_CRC0_DATA_RG_BASE_IDX 2 7503#define mmOTG5_OTG_CRC0_DATA_B 0x1df1 7504#define mmOTG5_OTG_CRC0_DATA_B_BASE_IDX 2 7505#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL 0x1df2 7506#define mmOTG5_OTG_CRC1_WINDOWA_X_CONTROL_BASE_IDX 2 7507#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL 0x1df3 7508#define mmOTG5_OTG_CRC1_WINDOWA_Y_CONTROL_BASE_IDX 2 7509#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL 0x1df4 7510#define mmOTG5_OTG_CRC1_WINDOWB_X_CONTROL_BASE_IDX 2 7511#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL 0x1df5 7512#define mmOTG5_OTG_CRC1_WINDOWB_Y_CONTROL_BASE_IDX 2 7513#define mmOTG5_OTG_CRC1_DATA_RG 0x1df6 7514#define mmOTG5_OTG_CRC1_DATA_RG_BASE_IDX 2 7515#define mmOTG5_OTG_CRC1_DATA_B 0x1df7 7516#define mmOTG5_OTG_CRC1_DATA_B_BASE_IDX 2 7517#define mmOTG5_OTG_CRC2_DATA_RG 0x1df8 7518#define mmOTG5_OTG_CRC2_DATA_RG_BASE_IDX 2 7519#define mmOTG5_OTG_CRC2_DATA_B 0x1df9 7520#define mmOTG5_OTG_CRC2_DATA_B_BASE_IDX 2 7521#define mmOTG5_OTG_CRC3_DATA_RG 0x1dfa 7522#define mmOTG5_OTG_CRC3_DATA_RG_BASE_IDX 2 7523#define mmOTG5_OTG_CRC3_DATA_B 0x1dfb 7524#define mmOTG5_OTG_CRC3_DATA_B_BASE_IDX 2 7525#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK 0x1dfc 7526#define mmOTG5_OTG_CRC_SIG_RED_GREEN_MASK_BASE_IDX 2 7527#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK 0x1dfd 7528#define mmOTG5_OTG_CRC_SIG_BLUE_CONTROL_MASK_BASE_IDX 2 7529#define mmOTG5_OTG_STATIC_SCREEN_CONTROL 0x1e04 7530#define mmOTG5_OTG_STATIC_SCREEN_CONTROL_BASE_IDX 2 7531#define mmOTG5_OTG_3D_STRUCTURE_CONTROL 0x1e05 7532#define mmOTG5_OTG_3D_STRUCTURE_CONTROL_BASE_IDX 2 7533#define mmOTG5_OTG_GSL_VSYNC_GAP 0x1e06 7534#define mmOTG5_OTG_GSL_VSYNC_GAP_BASE_IDX 2 7535#define mmOTG5_OTG_MASTER_UPDATE_MODE 0x1e07 7536#define mmOTG5_OTG_MASTER_UPDATE_MODE_BASE_IDX 2 7537#define mmOTG5_OTG_CLOCK_CONTROL 0x1e08 7538#define mmOTG5_OTG_CLOCK_CONTROL_BASE_IDX 2 7539#define mmOTG5_OTG_VSTARTUP_PARAM 0x1e09 7540#define mmOTG5_OTG_VSTARTUP_PARAM_BASE_IDX 2 7541#define mmOTG5_OTG_VUPDATE_PARAM 0x1e0a 7542#define mmOTG5_OTG_VUPDATE_PARAM_BASE_IDX 2 7543#define mmOTG5_OTG_VREADY_PARAM 0x1e0b 7544#define mmOTG5_OTG_VREADY_PARAM_BASE_IDX 2 7545#define mmOTG5_OTG_GLOBAL_SYNC_STATUS 0x1e0c 7546#define mmOTG5_OTG_GLOBAL_SYNC_STATUS_BASE_IDX 2 7547#define mmOTG5_OTG_MASTER_UPDATE_LOCK 0x1e0d 7548#define mmOTG5_OTG_MASTER_UPDATE_LOCK_BASE_IDX 2 7549#define mmOTG5_OTG_GSL_CONTROL 0x1e0e 7550#define mmOTG5_OTG_GSL_CONTROL_BASE_IDX 2 7551#define mmOTG5_OTG_GSL_WINDOW_X 0x1e0f 7552#define mmOTG5_OTG_GSL_WINDOW_X_BASE_IDX 2 7553#define mmOTG5_OTG_GSL_WINDOW_Y 0x1e10 7554#define mmOTG5_OTG_GSL_WINDOW_Y_BASE_IDX 2 7555#define mmOTG5_OTG_VUPDATE_KEEPOUT 0x1e11 7556#define mmOTG5_OTG_VUPDATE_KEEPOUT_BASE_IDX 2 7557#define mmOTG5_OTG_GLOBAL_CONTROL0 0x1e12 7558#define mmOTG5_OTG_GLOBAL_CONTROL0_BASE_IDX 2 7559#define mmOTG5_OTG_GLOBAL_CONTROL1 0x1e13 7560#define mmOTG5_OTG_GLOBAL_CONTROL1_BASE_IDX 2 7561#define mmOTG5_OTG_GLOBAL_CONTROL2 0x1e14 7562#define mmOTG5_OTG_GLOBAL_CONTROL2_BASE_IDX 2 7563#define mmOTG5_OTG_GLOBAL_CONTROL3 0x1e15 7564#define mmOTG5_OTG_GLOBAL_CONTROL3_BASE_IDX 2 7565#define mmOTG5_OTG_TRIG_MANUAL_CONTROL 0x1e16 7566#define mmOTG5_OTG_TRIG_MANUAL_CONTROL_BASE_IDX 2 7567#define mmOTG5_OTG_MANUAL_FLOW_CONTROL 0x1e17 7568#define mmOTG5_OTG_MANUAL_FLOW_CONTROL_BASE_IDX 2 7569#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS 0x1e18 7570#define mmOTG5_OTG_RANGE_TIMING_INT_STATUS_BASE_IDX 2 7571#define mmOTG5_OTG_DRR_CONTROL 0x1e19 7572#define mmOTG5_OTG_DRR_CONTROL_BASE_IDX 2 7573#define mmOTG5_OTG_REQUEST_CONTROL 0x1e1a 7574#define mmOTG5_OTG_REQUEST_CONTROL_BASE_IDX 2 7575#define mmOTG5_OTG_SPARE_REGISTER 0x1e1b 7576#define mmOTG5_OTG_SPARE_REGISTER_BASE_IDX 2 7577 7578 7579// addressBlock: dce_dc_optc_optc_misc_dispdec 7580// base address: 0x0 7581#define mmDWB_SOURCE_SELECT 0x1e2a 7582#define mmDWB_SOURCE_SELECT_BASE_IDX 2 7583#define mmGSL_SOURCE_SELECT 0x1e2b 7584#define mmGSL_SOURCE_SELECT_BASE_IDX 2 7585#define mmOPTC_CLOCK_CONTROL 0x1e2c 7586#define mmOPTC_CLOCK_CONTROL_BASE_IDX 2 7587#define mmOPTC_MISC_SPARE_REGISTER 0x1e2d 7588#define mmOPTC_MISC_SPARE_REGISTER_BASE_IDX 2 7589 7590 7591// addressBlock: dce_dc_optc_optc_dcperfmon_dc_perfmon_dispdec 7592// base address: 0x79a8 7593#define mmDC_PERFMON18_PERFCOUNTER_CNTL 0x1e6a 7594#define mmDC_PERFMON18_PERFCOUNTER_CNTL_BASE_IDX 2 7595#define mmDC_PERFMON18_PERFCOUNTER_CNTL2 0x1e6b 7596#define mmDC_PERFMON18_PERFCOUNTER_CNTL2_BASE_IDX 2 7597#define mmDC_PERFMON18_PERFCOUNTER_STATE 0x1e6c 7598#define mmDC_PERFMON18_PERFCOUNTER_STATE_BASE_IDX 2 7599#define mmDC_PERFMON18_PERFMON_CNTL 0x1e6d 7600#define mmDC_PERFMON18_PERFMON_CNTL_BASE_IDX 2 7601#define mmDC_PERFMON18_PERFMON_CNTL2 0x1e6e 7602#define mmDC_PERFMON18_PERFMON_CNTL2_BASE_IDX 2 7603#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC 0x1e6f 7604#define mmDC_PERFMON18_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7605#define mmDC_PERFMON18_PERFMON_CVALUE_LOW 0x1e70 7606#define mmDC_PERFMON18_PERFMON_CVALUE_LOW_BASE_IDX 2 7607#define mmDC_PERFMON18_PERFMON_HI 0x1e71 7608#define mmDC_PERFMON18_PERFMON_HI_BASE_IDX 2 7609#define mmDC_PERFMON18_PERFMON_LOW 0x1e72 7610#define mmDC_PERFMON18_PERFMON_LOW_BASE_IDX 2 7611 7612 7613// addressBlock: dce_dc_dio_dac_dispdec 7614// base address: 0x0 7615#define mmDAC_ENABLE 0x1e76 7616#define mmDAC_ENABLE_BASE_IDX 2 7617#define mmDAC_SOURCE_SELECT 0x1e77 7618#define mmDAC_SOURCE_SELECT_BASE_IDX 2 7619#define mmDAC_CRC_EN 0x1e78 7620#define mmDAC_CRC_EN_BASE_IDX 2 7621#define mmDAC_CRC_CONTROL 0x1e79 7622#define mmDAC_CRC_CONTROL_BASE_IDX 2 7623#define mmDAC_CRC_SIG_RGB_MASK 0x1e7a 7624#define mmDAC_CRC_SIG_RGB_MASK_BASE_IDX 2 7625#define mmDAC_CRC_SIG_CONTROL_MASK 0x1e7b 7626#define mmDAC_CRC_SIG_CONTROL_MASK_BASE_IDX 2 7627#define mmDAC_CRC_SIG_RGB 0x1e7c 7628#define mmDAC_CRC_SIG_RGB_BASE_IDX 2 7629#define mmDAC_CRC_SIG_CONTROL 0x1e7d 7630#define mmDAC_CRC_SIG_CONTROL_BASE_IDX 2 7631#define mmDAC_SYNC_TRISTATE_CONTROL 0x1e7e 7632#define mmDAC_SYNC_TRISTATE_CONTROL_BASE_IDX 2 7633#define mmDAC_STEREOSYNC_SELECT 0x1e7f 7634#define mmDAC_STEREOSYNC_SELECT_BASE_IDX 2 7635#define mmDAC_AUTODETECT_CONTROL 0x1e80 7636#define mmDAC_AUTODETECT_CONTROL_BASE_IDX 2 7637#define mmDAC_AUTODETECT_CONTROL2 0x1e81 7638#define mmDAC_AUTODETECT_CONTROL2_BASE_IDX 2 7639#define mmDAC_AUTODETECT_CONTROL3 0x1e82 7640#define mmDAC_AUTODETECT_CONTROL3_BASE_IDX 2 7641#define mmDAC_AUTODETECT_STATUS 0x1e83 7642#define mmDAC_AUTODETECT_STATUS_BASE_IDX 2 7643#define mmDAC_AUTODETECT_INT_CONTROL 0x1e84 7644#define mmDAC_AUTODETECT_INT_CONTROL_BASE_IDX 2 7645#define mmDAC_FORCE_OUTPUT_CNTL 0x1e85 7646#define mmDAC_FORCE_OUTPUT_CNTL_BASE_IDX 2 7647#define mmDAC_FORCE_DATA 0x1e86 7648#define mmDAC_FORCE_DATA_BASE_IDX 2 7649#define mmDAC_POWERDOWN 0x1e87 7650#define mmDAC_POWERDOWN_BASE_IDX 2 7651#define mmDAC_CONTROL 0x1e88 7652#define mmDAC_CONTROL_BASE_IDX 2 7653#define mmDAC_COMPARATOR_ENABLE 0x1e89 7654#define mmDAC_COMPARATOR_ENABLE_BASE_IDX 2 7655#define mmDAC_COMPARATOR_OUTPUT 0x1e8a 7656#define mmDAC_COMPARATOR_OUTPUT_BASE_IDX 2 7657#define mmDAC_PWR_CNTL 0x1e8b 7658#define mmDAC_PWR_CNTL_BASE_IDX 2 7659#define mmDAC_DFT_CONFIG 0x1e8c 7660#define mmDAC_DFT_CONFIG_BASE_IDX 2 7661#define mmDAC_FIFO_STATUS 0x1e8d 7662#define mmDAC_FIFO_STATUS_BASE_IDX 2 7663 7664 7665// addressBlock: dce_dc_dio_dout_i2c_dispdec 7666// base address: 0x0 7667#define mmDC_I2C_CONTROL 0x1e98 7668#define mmDC_I2C_CONTROL_BASE_IDX 2 7669#define mmDC_I2C_ARBITRATION 0x1e99 7670#define mmDC_I2C_ARBITRATION_BASE_IDX 2 7671#define mmDC_I2C_INTERRUPT_CONTROL 0x1e9a 7672#define mmDC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 7673#define mmDC_I2C_SW_STATUS 0x1e9b 7674#define mmDC_I2C_SW_STATUS_BASE_IDX 2 7675#define mmDC_I2C_DDC1_HW_STATUS 0x1e9c 7676#define mmDC_I2C_DDC1_HW_STATUS_BASE_IDX 2 7677#define mmDC_I2C_DDC2_HW_STATUS 0x1e9d 7678#define mmDC_I2C_DDC2_HW_STATUS_BASE_IDX 2 7679#define mmDC_I2C_DDC3_HW_STATUS 0x1e9e 7680#define mmDC_I2C_DDC3_HW_STATUS_BASE_IDX 2 7681#define mmDC_I2C_DDC4_HW_STATUS 0x1e9f 7682#define mmDC_I2C_DDC4_HW_STATUS_BASE_IDX 2 7683#define mmDC_I2C_DDC5_HW_STATUS 0x1ea0 7684#define mmDC_I2C_DDC5_HW_STATUS_BASE_IDX 2 7685#define mmDC_I2C_DDC6_HW_STATUS 0x1ea1 7686#define mmDC_I2C_DDC6_HW_STATUS_BASE_IDX 2 7687#define mmDC_I2C_DDC1_SPEED 0x1ea2 7688#define mmDC_I2C_DDC1_SPEED_BASE_IDX 2 7689#define mmDC_I2C_DDC1_SETUP 0x1ea3 7690#define mmDC_I2C_DDC1_SETUP_BASE_IDX 2 7691#define mmDC_I2C_DDC2_SPEED 0x1ea4 7692#define mmDC_I2C_DDC2_SPEED_BASE_IDX 2 7693#define mmDC_I2C_DDC2_SETUP 0x1ea5 7694#define mmDC_I2C_DDC2_SETUP_BASE_IDX 2 7695#define mmDC_I2C_DDC3_SPEED 0x1ea6 7696#define mmDC_I2C_DDC3_SPEED_BASE_IDX 2 7697#define mmDC_I2C_DDC3_SETUP 0x1ea7 7698#define mmDC_I2C_DDC3_SETUP_BASE_IDX 2 7699#define mmDC_I2C_DDC4_SPEED 0x1ea8 7700#define mmDC_I2C_DDC4_SPEED_BASE_IDX 2 7701#define mmDC_I2C_DDC4_SETUP 0x1ea9 7702#define mmDC_I2C_DDC4_SETUP_BASE_IDX 2 7703#define mmDC_I2C_DDC5_SPEED 0x1eaa 7704#define mmDC_I2C_DDC5_SPEED_BASE_IDX 2 7705#define mmDC_I2C_DDC5_SETUP 0x1eab 7706#define mmDC_I2C_DDC5_SETUP_BASE_IDX 2 7707#define mmDC_I2C_DDC6_SPEED 0x1eac 7708#define mmDC_I2C_DDC6_SPEED_BASE_IDX 2 7709#define mmDC_I2C_DDC6_SETUP 0x1ead 7710#define mmDC_I2C_DDC6_SETUP_BASE_IDX 2 7711#define mmDC_I2C_TRANSACTION0 0x1eae 7712#define mmDC_I2C_TRANSACTION0_BASE_IDX 2 7713#define mmDC_I2C_TRANSACTION1 0x1eaf 7714#define mmDC_I2C_TRANSACTION1_BASE_IDX 2 7715#define mmDC_I2C_TRANSACTION2 0x1eb0 7716#define mmDC_I2C_TRANSACTION2_BASE_IDX 2 7717#define mmDC_I2C_TRANSACTION3 0x1eb1 7718#define mmDC_I2C_TRANSACTION3_BASE_IDX 2 7719#define mmDC_I2C_DATA 0x1eb2 7720#define mmDC_I2C_DATA_BASE_IDX 2 7721#define mmDC_I2C_DDCVGA_HW_STATUS 0x1eb3 7722#define mmDC_I2C_DDCVGA_HW_STATUS_BASE_IDX 2 7723#define mmDC_I2C_DDCVGA_SPEED 0x1eb4 7724#define mmDC_I2C_DDCVGA_SPEED_BASE_IDX 2 7725#define mmDC_I2C_DDCVGA_SETUP 0x1eb5 7726#define mmDC_I2C_DDCVGA_SETUP_BASE_IDX 2 7727#define mmDC_I2C_EDID_DETECT_CTRL 0x1eb6 7728#define mmDC_I2C_EDID_DETECT_CTRL_BASE_IDX 2 7729#define mmDC_I2C_READ_REQUEST_INTERRUPT 0x1eb7 7730#define mmDC_I2C_READ_REQUEST_INTERRUPT_BASE_IDX 2 7731 7732 7733// addressBlock: dce_dc_dio_generic_i2c_dispdec 7734// base address: 0x0 7735#define mmGENERIC_I2C_CONTROL 0x1eb8 7736#define mmGENERIC_I2C_CONTROL_BASE_IDX 2 7737#define mmGENERIC_I2C_INTERRUPT_CONTROL 0x1eb9 7738#define mmGENERIC_I2C_INTERRUPT_CONTROL_BASE_IDX 2 7739#define mmGENERIC_I2C_STATUS 0x1eba 7740#define mmGENERIC_I2C_STATUS_BASE_IDX 2 7741#define mmGENERIC_I2C_SPEED 0x1ebb 7742#define mmGENERIC_I2C_SPEED_BASE_IDX 2 7743#define mmGENERIC_I2C_SETUP 0x1ebc 7744#define mmGENERIC_I2C_SETUP_BASE_IDX 2 7745#define mmGENERIC_I2C_TRANSACTION 0x1ebd 7746#define mmGENERIC_I2C_TRANSACTION_BASE_IDX 2 7747#define mmGENERIC_I2C_DATA 0x1ebe 7748#define mmGENERIC_I2C_DATA_BASE_IDX 2 7749#define mmGENERIC_I2C_PIN_SELECTION 0x1ebf 7750#define mmGENERIC_I2C_PIN_SELECTION_BASE_IDX 2 7751 7752 7753// addressBlock: dce_dc_dio_dio_misc_dispdec 7754// base address: 0x0 7755#define mmDIO_SCRATCH0 0x1eca 7756#define mmDIO_SCRATCH0_BASE_IDX 2 7757#define mmDIO_SCRATCH1 0x1ecb 7758#define mmDIO_SCRATCH1_BASE_IDX 2 7759#define mmDIO_SCRATCH2 0x1ecc 7760#define mmDIO_SCRATCH2_BASE_IDX 2 7761#define mmDIO_SCRATCH3 0x1ecd 7762#define mmDIO_SCRATCH3_BASE_IDX 2 7763#define mmDIO_SCRATCH4 0x1ece 7764#define mmDIO_SCRATCH4_BASE_IDX 2 7765#define mmDIO_SCRATCH5 0x1ecf 7766#define mmDIO_SCRATCH5_BASE_IDX 2 7767#define mmDIO_SCRATCH6 0x1ed0 7768#define mmDIO_SCRATCH6_BASE_IDX 2 7769#define mmDIO_SCRATCH7 0x1ed1 7770#define mmDIO_SCRATCH7_BASE_IDX 2 7771#define mmDCE_VCE_CONTROL 0x1ed2 7772#define mmDCE_VCE_CONTROL_BASE_IDX 2 7773#define mmDIO_MEM_PWR_STATUS 0x1edd 7774#define mmDIO_MEM_PWR_STATUS_BASE_IDX 2 7775#define mmDIO_MEM_PWR_CTRL 0x1ede 7776#define mmDIO_MEM_PWR_CTRL_BASE_IDX 2 7777#define mmDIO_MEM_PWR_CTRL2 0x1edf 7778#define mmDIO_MEM_PWR_CTRL2_BASE_IDX 2 7779#define mmDIO_CLK_CNTL 0x1ee0 7780#define mmDIO_CLK_CNTL_BASE_IDX 2 7781#define mmDIO_POWER_MANAGEMENT_CNTL 0x1ee4 7782#define mmDIO_POWER_MANAGEMENT_CNTL_BASE_IDX 2 7783#define mmDIO_STEREOSYNC_SEL 0x1eea 7784#define mmDIO_STEREOSYNC_SEL_BASE_IDX 2 7785#define mmDIO_SOFT_RESET 0x1eed 7786#define mmDIO_SOFT_RESET_BASE_IDX 2 7787#define mmDIG_SOFT_RESET 0x1eee 7788#define mmDIG_SOFT_RESET_BASE_IDX 2 7789#define mmDIO_MEM_PWR_STATUS1 0x1ef0 7790#define mmDIO_MEM_PWR_STATUS1_BASE_IDX 2 7791#define mmDIO_CLK_CNTL2 0x1ef2 7792#define mmDIO_CLK_CNTL2_BASE_IDX 2 7793#define mmDIO_CLK_CNTL3 0x1ef3 7794#define mmDIO_CLK_CNTL3_BASE_IDX 2 7795#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL 0x1eff 7796#define mmDIO_HDMI_RXSTATUS_TIMER_CONTROL_BASE_IDX 2 7797#define mmDIO_PSP_INTERRUPT_STATUS 0x1f00 7798#define mmDIO_PSP_INTERRUPT_STATUS_BASE_IDX 2 7799#define mmDIO_PSP_INTERRUPT_CLEAR 0x1f01 7800#define mmDIO_PSP_INTERRUPT_CLEAR_BASE_IDX 2 7801#define mmDIO_GENERIC_INTERRUPT_MESSAGE 0x1f02 7802#define mmDIO_GENERIC_INTERRUPT_MESSAGE_BASE_IDX 2 7803#define mmDIO_GENERIC_INTERRUPT_CLEAR 0x1f03 7804#define mmDIO_GENERIC_INTERRUPT_CLEAR_BASE_IDX 2 7805 7806 7807// addressBlock: dce_dc_dio_hpd0_dispdec 7808// base address: 0x0 7809#define mmHPD0_DC_HPD_INT_STATUS 0x1f14 7810#define mmHPD0_DC_HPD_INT_STATUS_BASE_IDX 2 7811#define mmHPD0_DC_HPD_INT_CONTROL 0x1f15 7812#define mmHPD0_DC_HPD_INT_CONTROL_BASE_IDX 2 7813#define mmHPD0_DC_HPD_CONTROL 0x1f16 7814#define mmHPD0_DC_HPD_CONTROL_BASE_IDX 2 7815#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL 0x1f17 7816#define mmHPD0_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7817#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL 0x1f18 7818#define mmHPD0_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7819 7820 7821// addressBlock: dce_dc_dio_hpd1_dispdec 7822// base address: 0x20 7823#define mmHPD1_DC_HPD_INT_STATUS 0x1f1c 7824#define mmHPD1_DC_HPD_INT_STATUS_BASE_IDX 2 7825#define mmHPD1_DC_HPD_INT_CONTROL 0x1f1d 7826#define mmHPD1_DC_HPD_INT_CONTROL_BASE_IDX 2 7827#define mmHPD1_DC_HPD_CONTROL 0x1f1e 7828#define mmHPD1_DC_HPD_CONTROL_BASE_IDX 2 7829#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL 0x1f1f 7830#define mmHPD1_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7831#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL 0x1f20 7832#define mmHPD1_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7833 7834 7835// addressBlock: dce_dc_dio_hpd2_dispdec 7836// base address: 0x40 7837#define mmHPD2_DC_HPD_INT_STATUS 0x1f24 7838#define mmHPD2_DC_HPD_INT_STATUS_BASE_IDX 2 7839#define mmHPD2_DC_HPD_INT_CONTROL 0x1f25 7840#define mmHPD2_DC_HPD_INT_CONTROL_BASE_IDX 2 7841#define mmHPD2_DC_HPD_CONTROL 0x1f26 7842#define mmHPD2_DC_HPD_CONTROL_BASE_IDX 2 7843#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL 0x1f27 7844#define mmHPD2_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7845#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL 0x1f28 7846#define mmHPD2_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7847 7848 7849// addressBlock: dce_dc_dio_hpd3_dispdec 7850// base address: 0x60 7851#define mmHPD3_DC_HPD_INT_STATUS 0x1f2c 7852#define mmHPD3_DC_HPD_INT_STATUS_BASE_IDX 2 7853#define mmHPD3_DC_HPD_INT_CONTROL 0x1f2d 7854#define mmHPD3_DC_HPD_INT_CONTROL_BASE_IDX 2 7855#define mmHPD3_DC_HPD_CONTROL 0x1f2e 7856#define mmHPD3_DC_HPD_CONTROL_BASE_IDX 2 7857#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL 0x1f2f 7858#define mmHPD3_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7859#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL 0x1f30 7860#define mmHPD3_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7861 7862 7863// addressBlock: dce_dc_dio_hpd4_dispdec 7864// base address: 0x80 7865#define mmHPD4_DC_HPD_INT_STATUS 0x1f34 7866#define mmHPD4_DC_HPD_INT_STATUS_BASE_IDX 2 7867#define mmHPD4_DC_HPD_INT_CONTROL 0x1f35 7868#define mmHPD4_DC_HPD_INT_CONTROL_BASE_IDX 2 7869#define mmHPD4_DC_HPD_CONTROL 0x1f36 7870#define mmHPD4_DC_HPD_CONTROL_BASE_IDX 2 7871#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL 0x1f37 7872#define mmHPD4_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7873#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL 0x1f38 7874#define mmHPD4_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7875 7876 7877// addressBlock: dce_dc_dio_hpd5_dispdec 7878// base address: 0xa0 7879#define mmHPD5_DC_HPD_INT_STATUS 0x1f3c 7880#define mmHPD5_DC_HPD_INT_STATUS_BASE_IDX 2 7881#define mmHPD5_DC_HPD_INT_CONTROL 0x1f3d 7882#define mmHPD5_DC_HPD_INT_CONTROL_BASE_IDX 2 7883#define mmHPD5_DC_HPD_CONTROL 0x1f3e 7884#define mmHPD5_DC_HPD_CONTROL_BASE_IDX 2 7885#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL 0x1f3f 7886#define mmHPD5_DC_HPD_FAST_TRAIN_CNTL_BASE_IDX 2 7887#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL 0x1f40 7888#define mmHPD5_DC_HPD_TOGGLE_FILT_CNTL_BASE_IDX 2 7889 7890 7891// addressBlock: dce_dc_dio_dio_dcperfmon_dc_perfmon_dispdec 7892// base address: 0x7d10 7893#define mmDC_PERFMON19_PERFCOUNTER_CNTL 0x1f44 7894#define mmDC_PERFMON19_PERFCOUNTER_CNTL_BASE_IDX 2 7895#define mmDC_PERFMON19_PERFCOUNTER_CNTL2 0x1f45 7896#define mmDC_PERFMON19_PERFCOUNTER_CNTL2_BASE_IDX 2 7897#define mmDC_PERFMON19_PERFCOUNTER_STATE 0x1f46 7898#define mmDC_PERFMON19_PERFCOUNTER_STATE_BASE_IDX 2 7899#define mmDC_PERFMON19_PERFMON_CNTL 0x1f47 7900#define mmDC_PERFMON19_PERFMON_CNTL_BASE_IDX 2 7901#define mmDC_PERFMON19_PERFMON_CNTL2 0x1f48 7902#define mmDC_PERFMON19_PERFMON_CNTL2_BASE_IDX 2 7903#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC 0x1f49 7904#define mmDC_PERFMON19_PERFMON_CVALUE_INT_MISC_BASE_IDX 2 7905#define mmDC_PERFMON19_PERFMON_CVALUE_LOW 0x1f4a 7906#define mmDC_PERFMON19_PERFMON_CVALUE_LOW_BASE_IDX 2 7907#define mmDC_PERFMON19_PERFMON_HI 0x1f4b 7908#define mmDC_PERFMON19_PERFMON_HI_BASE_IDX 2 7909#define mmDC_PERFMON19_PERFMON_LOW 0x1f4c 7910#define mmDC_PERFMON19_PERFMON_LOW_BASE_IDX 2 7911 7912 7913// addressBlock: dce_dc_dio_dp_aux0_dispdec 7914// base address: 0x0 7915#define mmDP_AUX0_AUX_CONTROL 0x1f50 7916#define mmDP_AUX0_AUX_CONTROL_BASE_IDX 2 7917#define mmDP_AUX0_AUX_SW_CONTROL 0x1f51 7918#define mmDP_AUX0_AUX_SW_CONTROL_BASE_IDX 2 7919#define mmDP_AUX0_AUX_ARB_CONTROL 0x1f52 7920#define mmDP_AUX0_AUX_ARB_CONTROL_BASE_IDX 2 7921#define mmDP_AUX0_AUX_INTERRUPT_CONTROL 0x1f53 7922#define mmDP_AUX0_AUX_INTERRUPT_CONTROL_BASE_IDX 2 7923#define mmDP_AUX0_AUX_SW_STATUS 0x1f54 7924#define mmDP_AUX0_AUX_SW_STATUS_BASE_IDX 2 7925#define mmDP_AUX0_AUX_LS_STATUS 0x1f55 7926#define mmDP_AUX0_AUX_LS_STATUS_BASE_IDX 2 7927#define mmDP_AUX0_AUX_SW_DATA 0x1f56 7928#define mmDP_AUX0_AUX_SW_DATA_BASE_IDX 2 7929#define mmDP_AUX0_AUX_LS_DATA 0x1f57 7930#define mmDP_AUX0_AUX_LS_DATA_BASE_IDX 2 7931#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL 0x1f58 7932#define mmDP_AUX0_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 7933#define mmDP_AUX0_AUX_DPHY_TX_CONTROL 0x1f59 7934#define mmDP_AUX0_AUX_DPHY_TX_CONTROL_BASE_IDX 2 7935#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0 0x1f5a 7936#define mmDP_AUX0_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 7937#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1 0x1f5b 7938#define mmDP_AUX0_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 7939#define mmDP_AUX0_AUX_DPHY_TX_STATUS 0x1f5c 7940#define mmDP_AUX0_AUX_DPHY_TX_STATUS_BASE_IDX 2 7941#define mmDP_AUX0_AUX_DPHY_RX_STATUS 0x1f5d 7942#define mmDP_AUX0_AUX_DPHY_RX_STATUS_BASE_IDX 2 7943#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL 0x1f5f 7944#define mmDP_AUX0_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 7945#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f60 7946#define mmDP_AUX0_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 7947#define mmDP_AUX0_AUX_GTC_SYNC_STATUS 0x1f61 7948#define mmDP_AUX0_AUX_GTC_SYNC_STATUS_BASE_IDX 2 7949 7950 7951// addressBlock: dce_dc_dio_dp_aux1_dispdec 7952// base address: 0x70 7953#define mmDP_AUX1_AUX_CONTROL 0x1f6c 7954#define mmDP_AUX1_AUX_CONTROL_BASE_IDX 2 7955#define mmDP_AUX1_AUX_SW_CONTROL 0x1f6d 7956#define mmDP_AUX1_AUX_SW_CONTROL_BASE_IDX 2 7957#define mmDP_AUX1_AUX_ARB_CONTROL 0x1f6e 7958#define mmDP_AUX1_AUX_ARB_CONTROL_BASE_IDX 2 7959#define mmDP_AUX1_AUX_INTERRUPT_CONTROL 0x1f6f 7960#define mmDP_AUX1_AUX_INTERRUPT_CONTROL_BASE_IDX 2 7961#define mmDP_AUX1_AUX_SW_STATUS 0x1f70 7962#define mmDP_AUX1_AUX_SW_STATUS_BASE_IDX 2 7963#define mmDP_AUX1_AUX_LS_STATUS 0x1f71 7964#define mmDP_AUX1_AUX_LS_STATUS_BASE_IDX 2 7965#define mmDP_AUX1_AUX_SW_DATA 0x1f72 7966#define mmDP_AUX1_AUX_SW_DATA_BASE_IDX 2 7967#define mmDP_AUX1_AUX_LS_DATA 0x1f73 7968#define mmDP_AUX1_AUX_LS_DATA_BASE_IDX 2 7969#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL 0x1f74 7970#define mmDP_AUX1_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 7971#define mmDP_AUX1_AUX_DPHY_TX_CONTROL 0x1f75 7972#define mmDP_AUX1_AUX_DPHY_TX_CONTROL_BASE_IDX 2 7973#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0 0x1f76 7974#define mmDP_AUX1_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 7975#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1 0x1f77 7976#define mmDP_AUX1_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 7977#define mmDP_AUX1_AUX_DPHY_TX_STATUS 0x1f78 7978#define mmDP_AUX1_AUX_DPHY_TX_STATUS_BASE_IDX 2 7979#define mmDP_AUX1_AUX_DPHY_RX_STATUS 0x1f79 7980#define mmDP_AUX1_AUX_DPHY_RX_STATUS_BASE_IDX 2 7981#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL 0x1f7b 7982#define mmDP_AUX1_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 7983#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f7c 7984#define mmDP_AUX1_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 7985#define mmDP_AUX1_AUX_GTC_SYNC_STATUS 0x1f7d 7986#define mmDP_AUX1_AUX_GTC_SYNC_STATUS_BASE_IDX 2 7987 7988 7989// addressBlock: dce_dc_dio_dp_aux2_dispdec 7990// base address: 0xe0 7991#define mmDP_AUX2_AUX_CONTROL 0x1f88 7992#define mmDP_AUX2_AUX_CONTROL_BASE_IDX 2 7993#define mmDP_AUX2_AUX_SW_CONTROL 0x1f89 7994#define mmDP_AUX2_AUX_SW_CONTROL_BASE_IDX 2 7995#define mmDP_AUX2_AUX_ARB_CONTROL 0x1f8a 7996#define mmDP_AUX2_AUX_ARB_CONTROL_BASE_IDX 2 7997#define mmDP_AUX2_AUX_INTERRUPT_CONTROL 0x1f8b 7998#define mmDP_AUX2_AUX_INTERRUPT_CONTROL_BASE_IDX 2 7999#define mmDP_AUX2_AUX_SW_STATUS 0x1f8c 8000#define mmDP_AUX2_AUX_SW_STATUS_BASE_IDX 2
8001#define mmDP_AUX2_AUX_LS_STATUS 0x1f8d 8002#define mmDP_AUX2_AUX_LS_STATUS_BASE_IDX 2 8003#define mmDP_AUX2_AUX_SW_DATA 0x1f8e 8004#define mmDP_AUX2_AUX_SW_DATA_BASE_IDX 2 8005#define mmDP_AUX2_AUX_LS_DATA 0x1f8f 8006#define mmDP_AUX2_AUX_LS_DATA_BASE_IDX 2 8007#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL 0x1f90 8008#define mmDP_AUX2_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 8009#define mmDP_AUX2_AUX_DPHY_TX_CONTROL 0x1f91 8010#define mmDP_AUX2_AUX_DPHY_TX_CONTROL_BASE_IDX 2 8011#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0 0x1f92 8012#define mmDP_AUX2_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 8013#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1 0x1f93 8014#define mmDP_AUX2_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 8015#define mmDP_AUX2_AUX_DPHY_TX_STATUS 0x1f94 8016#define mmDP_AUX2_AUX_DPHY_TX_STATUS_BASE_IDX 2 8017#define mmDP_AUX2_AUX_DPHY_RX_STATUS 0x1f95 8018#define mmDP_AUX2_AUX_DPHY_RX_STATUS_BASE_IDX 2 8019#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL 0x1f97 8020#define mmDP_AUX2_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 8021#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1f98 8022#define mmDP_AUX2_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 8023#define mmDP_AUX2_AUX_GTC_SYNC_STATUS 0x1f99 8024#define mmDP_AUX2_AUX_GTC_SYNC_STATUS_BASE_IDX 2 8025 8026 8027// addressBlock: dce_dc_dio_dp_aux3_dispdec 8028// base address: 0x150 8029#define mmDP_AUX3_AUX_CONTROL 0x1fa4 8030#define mmDP_AUX3_AUX_CONTROL_BASE_IDX 2 8031#define mmDP_AUX3_AUX_SW_CONTROL 0x1fa5 8032#define mmDP_AUX3_AUX_SW_CONTROL_BASE_IDX 2 8033#define mmDP_AUX3_AUX_ARB_CONTROL 0x1fa6 8034#define mmDP_AUX3_AUX_ARB_CONTROL_BASE_IDX 2 8035#define mmDP_AUX3_AUX_INTERRUPT_CONTROL 0x1fa7 8036#define mmDP_AUX3_AUX_INTERRUPT_CONTROL_BASE_IDX 2 8037#define mmDP_AUX3_AUX_SW_STATUS 0x1fa8 8038#define mmDP_AUX3_AUX_SW_STATUS_BASE_IDX 2 8039#define mmDP_AUX3_AUX_LS_STATUS 0x1fa9 8040#define mmDP_AUX3_AUX_LS_STATUS_BASE_IDX 2 8041#define mmDP_AUX3_AUX_SW_DATA 0x1faa 8042#define mmDP_AUX3_AUX_SW_DATA_BASE_IDX 2 8043#define mmDP_AUX3_AUX_LS_DATA 0x1fab 8044#define mmDP_AUX3_AUX_LS_DATA_BASE_IDX 2 8045#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL 0x1fac 8046#define mmDP_AUX3_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 8047#define mmDP_AUX3_AUX_DPHY_TX_CONTROL 0x1fad 8048#define mmDP_AUX3_AUX_DPHY_TX_CONTROL_BASE_IDX 2 8049#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0 0x1fae 8050#define mmDP_AUX3_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 8051#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1 0x1faf 8052#define mmDP_AUX3_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 8053#define mmDP_AUX3_AUX_DPHY_TX_STATUS 0x1fb0 8054#define mmDP_AUX3_AUX_DPHY_TX_STATUS_BASE_IDX 2 8055#define mmDP_AUX3_AUX_DPHY_RX_STATUS 0x1fb1 8056#define mmDP_AUX3_AUX_DPHY_RX_STATUS_BASE_IDX 2 8057#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL 0x1fb3 8058#define mmDP_AUX3_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 8059#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fb4 8060#define mmDP_AUX3_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 8061#define mmDP_AUX3_AUX_GTC_SYNC_STATUS 0x1fb5 8062#define mmDP_AUX3_AUX_GTC_SYNC_STATUS_BASE_IDX 2 8063 8064 8065// addressBlock: dce_dc_dio_dp_aux4_dispdec 8066// base address: 0x1c0 8067#define mmDP_AUX4_AUX_CONTROL 0x1fc0 8068#define mmDP_AUX4_AUX_CONTROL_BASE_IDX 2 8069#define mmDP_AUX4_AUX_SW_CONTROL 0x1fc1 8070#define mmDP_AUX4_AUX_SW_CONTROL_BASE_IDX 2 8071#define mmDP_AUX4_AUX_ARB_CONTROL 0x1fc2 8072#define mmDP_AUX4_AUX_ARB_CONTROL_BASE_IDX 2 8073#define mmDP_AUX4_AUX_INTERRUPT_CONTROL 0x1fc3 8074#define mmDP_AUX4_AUX_INTERRUPT_CONTROL_BASE_IDX 2 8075#define mmDP_AUX4_AUX_SW_STATUS 0x1fc4 8076#define mmDP_AUX4_AUX_SW_STATUS_BASE_IDX 2 8077#define mmDP_AUX4_AUX_LS_STATUS 0x1fc5 8078#define mmDP_AUX4_AUX_LS_STATUS_BASE_IDX 2 8079#define mmDP_AUX4_AUX_SW_DATA 0x1fc6 8080#define mmDP_AUX4_AUX_SW_DATA_BASE_IDX 2 8081#define mmDP_AUX4_AUX_LS_DATA 0x1fc7 8082#define mmDP_AUX4_AUX_LS_DATA_BASE_IDX 2 8083#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL 0x1fc8 8084#define mmDP_AUX4_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 8085#define mmDP_AUX4_AUX_DPHY_TX_CONTROL 0x1fc9 8086#define mmDP_AUX4_AUX_DPHY_TX_CONTROL_BASE_IDX 2 8087#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0 0x1fca 8088#define mmDP_AUX4_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 8089#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1 0x1fcb 8090#define mmDP_AUX4_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 8091#define mmDP_AUX4_AUX_DPHY_TX_STATUS 0x1fcc 8092#define mmDP_AUX4_AUX_DPHY_TX_STATUS_BASE_IDX 2 8093#define mmDP_AUX4_AUX_DPHY_RX_STATUS 0x1fcd 8094#define mmDP_AUX4_AUX_DPHY_RX_STATUS_BASE_IDX 2 8095#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL 0x1fcf 8096#define mmDP_AUX4_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 8097#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fd0 8098#define mmDP_AUX4_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 8099#define mmDP_AUX4_AUX_GTC_SYNC_STATUS 0x1fd1 8100#define mmDP_AUX4_AUX_GTC_SYNC_STATUS_BASE_IDX 2 8101 8102 8103// addressBlock: dce_dc_dio_dp_aux5_dispdec 8104// base address: 0x230 8105#define mmDP_AUX5_AUX_CONTROL 0x1fdc 8106#define mmDP_AUX5_AUX_CONTROL_BASE_IDX 2 8107#define mmDP_AUX5_AUX_SW_CONTROL 0x1fdd 8108#define mmDP_AUX5_AUX_SW_CONTROL_BASE_IDX 2 8109#define mmDP_AUX5_AUX_ARB_CONTROL 0x1fde 8110#define mmDP_AUX5_AUX_ARB_CONTROL_BASE_IDX 2 8111#define mmDP_AUX5_AUX_INTERRUPT_CONTROL 0x1fdf 8112#define mmDP_AUX5_AUX_INTERRUPT_CONTROL_BASE_IDX 2 8113#define mmDP_AUX5_AUX_SW_STATUS 0x1fe0 8114#define mmDP_AUX5_AUX_SW_STATUS_BASE_IDX 2 8115#define mmDP_AUX5_AUX_LS_STATUS 0x1fe1 8116#define mmDP_AUX5_AUX_LS_STATUS_BASE_IDX 2 8117#define mmDP_AUX5_AUX_SW_DATA 0x1fe2 8118#define mmDP_AUX5_AUX_SW_DATA_BASE_IDX 2 8119#define mmDP_AUX5_AUX_LS_DATA 0x1fe3 8120#define mmDP_AUX5_AUX_LS_DATA_BASE_IDX 2 8121#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL 0x1fe4 8122#define mmDP_AUX5_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 8123#define mmDP_AUX5_AUX_DPHY_TX_CONTROL 0x1fe5 8124#define mmDP_AUX5_AUX_DPHY_TX_CONTROL_BASE_IDX 2 8125#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0 0x1fe6 8126#define mmDP_AUX5_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 8127#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1 0x1fe7 8128#define mmDP_AUX5_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 8129#define mmDP_AUX5_AUX_DPHY_TX_STATUS 0x1fe8 8130#define mmDP_AUX5_AUX_DPHY_TX_STATUS_BASE_IDX 2 8131#define mmDP_AUX5_AUX_DPHY_RX_STATUS 0x1fe9 8132#define mmDP_AUX5_AUX_DPHY_RX_STATUS_BASE_IDX 2 8133#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL 0x1feb 8134#define mmDP_AUX5_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 8135#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS 0x1fec 8136#define mmDP_AUX5_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 8137#define mmDP_AUX5_AUX_GTC_SYNC_STATUS 0x1fed 8138#define mmDP_AUX5_AUX_GTC_SYNC_STATUS_BASE_IDX 2 8139 8140 8141// addressBlock: dce_dc_dio_dp_aux6_dispdec 8142// base address: 0x2a0 8143#define mmDP_AUX6_AUX_CONTROL 0x1ff8 8144#define mmDP_AUX6_AUX_CONTROL_BASE_IDX 2 8145#define mmDP_AUX6_AUX_SW_CONTROL 0x1ff9 8146#define mmDP_AUX6_AUX_SW_CONTROL_BASE_IDX 2 8147#define mmDP_AUX6_AUX_ARB_CONTROL 0x1ffa 8148#define mmDP_AUX6_AUX_ARB_CONTROL_BASE_IDX 2 8149#define mmDP_AUX6_AUX_INTERRUPT_CONTROL 0x1ffb 8150#define mmDP_AUX6_AUX_INTERRUPT_CONTROL_BASE_IDX 2 8151#define mmDP_AUX6_AUX_SW_STATUS 0x1ffc 8152#define mmDP_AUX6_AUX_SW_STATUS_BASE_IDX 2 8153#define mmDP_AUX6_AUX_LS_STATUS 0x1ffd 8154#define mmDP_AUX6_AUX_LS_STATUS_BASE_IDX 2 8155#define mmDP_AUX6_AUX_SW_DATA 0x1ffe 8156#define mmDP_AUX6_AUX_SW_DATA_BASE_IDX 2 8157#define mmDP_AUX6_AUX_LS_DATA 0x1fff 8158#define mmDP_AUX6_AUX_LS_DATA_BASE_IDX 2 8159#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL 0x2000 8160#define mmDP_AUX6_AUX_DPHY_TX_REF_CONTROL_BASE_IDX 2 8161#define mmDP_AUX6_AUX_DPHY_TX_CONTROL 0x2001 8162#define mmDP_AUX6_AUX_DPHY_TX_CONTROL_BASE_IDX 2 8163#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0 0x2002 8164#define mmDP_AUX6_AUX_DPHY_RX_CONTROL0_BASE_IDX 2 8165#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1 0x2003 8166#define mmDP_AUX6_AUX_DPHY_RX_CONTROL1_BASE_IDX 2 8167#define mmDP_AUX6_AUX_DPHY_TX_STATUS 0x2004 8168#define mmDP_AUX6_AUX_DPHY_TX_STATUS_BASE_IDX 2 8169#define mmDP_AUX6_AUX_DPHY_RX_STATUS 0x2005 8170#define mmDP_AUX6_AUX_DPHY_RX_STATUS_BASE_IDX 2 8171#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL 0x2007 8172#define mmDP_AUX6_AUX_GTC_SYNC_ERROR_CONTROL_BASE_IDX 2 8173#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS 0x2008 8174#define mmDP_AUX6_AUX_GTC_SYNC_CONTROLLER_STATUS_BASE_IDX 2 8175#define mmDP_AUX6_AUX_GTC_SYNC_STATUS 0x2009 8176#define mmDP_AUX6_AUX_GTC_SYNC_STATUS_BASE_IDX 2 8177 8178 8179// addressBlock: dce_dc_dio_dig0_dispdec 8180// base address: 0x0 8181#define mmDIG0_DIG_FE_CNTL 0x2068 8182#define mmDIG0_DIG_FE_CNTL_BASE_IDX 2 8183#define mmDIG0_DIG_OUTPUT_CRC_CNTL 0x2069 8184#define mmDIG0_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 8185#define mmDIG0_DIG_OUTPUT_CRC_RESULT 0x206a 8186#define mmDIG0_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 8187#define mmDIG0_DIG_CLOCK_PATTERN 0x206b 8188#define mmDIG0_DIG_CLOCK_PATTERN_BASE_IDX 2 8189#define mmDIG0_DIG_TEST_PATTERN 0x206c 8190#define mmDIG0_DIG_TEST_PATTERN_BASE_IDX 2 8191#define mmDIG0_DIG_RANDOM_PATTERN_SEED 0x206d 8192#define mmDIG0_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 8193#define mmDIG0_DIG_FIFO_STATUS 0x206e 8194#define mmDIG0_DIG_FIFO_STATUS_BASE_IDX 2 8195#define mmDIG0_HDMI_CONTROL 0x2071 8196#define mmDIG0_HDMI_CONTROL_BASE_IDX 2 8197#define mmDIG0_HDMI_STATUS 0x2072 8198#define mmDIG0_HDMI_STATUS_BASE_IDX 2 8199#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL 0x2073 8200#define mmDIG0_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 8201#define mmDIG0_HDMI_ACR_PACKET_CONTROL 0x2074 8202#define mmDIG0_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 8203#define mmDIG0_HDMI_VBI_PACKET_CONTROL 0x2075 8204#define mmDIG0_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 8205#define mmDIG0_HDMI_INFOFRAME_CONTROL0 0x2076 8206#define mmDIG0_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 8207#define mmDIG0_HDMI_INFOFRAME_CONTROL1 0x2077 8208#define mmDIG0_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 8209#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0 0x2078 8210#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 8211#define mmDIG0_AFMT_INTERRUPT_STATUS 0x2079 8212#define mmDIG0_AFMT_INTERRUPT_STATUS_BASE_IDX 2 8213#define mmDIG0_HDMI_GC 0x207b 8214#define mmDIG0_HDMI_GC_BASE_IDX 2 8215#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2 0x207c 8216#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 8217#define mmDIG0_AFMT_ISRC1_0 0x207d 8218#define mmDIG0_AFMT_ISRC1_0_BASE_IDX 2 8219#define mmDIG0_AFMT_ISRC1_1 0x207e 8220#define mmDIG0_AFMT_ISRC1_1_BASE_IDX 2 8221#define mmDIG0_AFMT_ISRC1_2 0x207f 8222#define mmDIG0_AFMT_ISRC1_2_BASE_IDX 2 8223#define mmDIG0_AFMT_ISRC1_3 0x2080 8224#define mmDIG0_AFMT_ISRC1_3_BASE_IDX 2 8225#define mmDIG0_AFMT_ISRC1_4 0x2081 8226#define mmDIG0_AFMT_ISRC1_4_BASE_IDX 2 8227#define mmDIG0_AFMT_ISRC2_0 0x2082 8228#define mmDIG0_AFMT_ISRC2_0_BASE_IDX 2 8229#define mmDIG0_AFMT_ISRC2_1 0x2083 8230#define mmDIG0_AFMT_ISRC2_1_BASE_IDX 2 8231#define mmDIG0_AFMT_ISRC2_2 0x2084 8232#define mmDIG0_AFMT_ISRC2_2_BASE_IDX 2 8233#define mmDIG0_AFMT_ISRC2_3 0x2085 8234#define mmDIG0_AFMT_ISRC2_3_BASE_IDX 2 8235#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2 0x2086 8236#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 8237#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3 0x2087 8238#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 8239#define mmDIG0_HDMI_DB_CONTROL 0x2088 8240#define mmDIG0_HDMI_DB_CONTROL_BASE_IDX 2 8241#define mmDIG0_AFMT_MPEG_INFO0 0x208a 8242#define mmDIG0_AFMT_MPEG_INFO0_BASE_IDX 2 8243#define mmDIG0_AFMT_MPEG_INFO1 0x208b 8244#define mmDIG0_AFMT_MPEG_INFO1_BASE_IDX 2 8245#define mmDIG0_AFMT_GENERIC_HDR 0x208c 8246#define mmDIG0_AFMT_GENERIC_HDR_BASE_IDX 2 8247#define mmDIG0_AFMT_GENERIC_0 0x208d 8248#define mmDIG0_AFMT_GENERIC_0_BASE_IDX 2 8249#define mmDIG0_AFMT_GENERIC_1 0x208e 8250#define mmDIG0_AFMT_GENERIC_1_BASE_IDX 2 8251#define mmDIG0_AFMT_GENERIC_2 0x208f 8252#define mmDIG0_AFMT_GENERIC_2_BASE_IDX 2 8253#define mmDIG0_AFMT_GENERIC_3 0x2090 8254#define mmDIG0_AFMT_GENERIC_3_BASE_IDX 2 8255#define mmDIG0_AFMT_GENERIC_4 0x2091 8256#define mmDIG0_AFMT_GENERIC_4_BASE_IDX 2 8257#define mmDIG0_AFMT_GENERIC_5 0x2092 8258#define mmDIG0_AFMT_GENERIC_5_BASE_IDX 2 8259#define mmDIG0_AFMT_GENERIC_6 0x2093 8260#define mmDIG0_AFMT_GENERIC_6_BASE_IDX 2 8261#define mmDIG0_AFMT_GENERIC_7 0x2094 8262#define mmDIG0_AFMT_GENERIC_7_BASE_IDX 2 8263#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1 0x2095 8264#define mmDIG0_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 8265#define mmDIG0_HDMI_ACR_32_0 0x2096 8266#define mmDIG0_HDMI_ACR_32_0_BASE_IDX 2 8267#define mmDIG0_HDMI_ACR_32_1 0x2097 8268#define mmDIG0_HDMI_ACR_32_1_BASE_IDX 2 8269#define mmDIG0_HDMI_ACR_44_0 0x2098 8270#define mmDIG0_HDMI_ACR_44_0_BASE_IDX 2 8271#define mmDIG0_HDMI_ACR_44_1 0x2099 8272#define mmDIG0_HDMI_ACR_44_1_BASE_IDX 2 8273#define mmDIG0_HDMI_ACR_48_0 0x209a 8274#define mmDIG0_HDMI_ACR_48_0_BASE_IDX 2 8275#define mmDIG0_HDMI_ACR_48_1 0x209b 8276#define mmDIG0_HDMI_ACR_48_1_BASE_IDX 2 8277#define mmDIG0_HDMI_ACR_STATUS_0 0x209c 8278#define mmDIG0_HDMI_ACR_STATUS_0_BASE_IDX 2 8279#define mmDIG0_HDMI_ACR_STATUS_1 0x209d 8280#define mmDIG0_HDMI_ACR_STATUS_1_BASE_IDX 2 8281#define mmDIG0_AFMT_AUDIO_INFO0 0x209e 8282#define mmDIG0_AFMT_AUDIO_INFO0_BASE_IDX 2 8283#define mmDIG0_AFMT_AUDIO_INFO1 0x209f 8284#define mmDIG0_AFMT_AUDIO_INFO1_BASE_IDX 2 8285#define mmDIG0_AFMT_60958_0 0x20a0 8286#define mmDIG0_AFMT_60958_0_BASE_IDX 2 8287#define mmDIG0_AFMT_60958_1 0x20a1 8288#define mmDIG0_AFMT_60958_1_BASE_IDX 2 8289#define mmDIG0_AFMT_AUDIO_CRC_CONTROL 0x20a2 8290#define mmDIG0_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 8291#define mmDIG0_AFMT_RAMP_CONTROL0 0x20a3 8292#define mmDIG0_AFMT_RAMP_CONTROL0_BASE_IDX 2 8293#define mmDIG0_AFMT_RAMP_CONTROL1 0x20a4 8294#define mmDIG0_AFMT_RAMP_CONTROL1_BASE_IDX 2 8295#define mmDIG0_AFMT_RAMP_CONTROL2 0x20a5 8296#define mmDIG0_AFMT_RAMP_CONTROL2_BASE_IDX 2 8297#define mmDIG0_AFMT_RAMP_CONTROL3 0x20a6 8298#define mmDIG0_AFMT_RAMP_CONTROL3_BASE_IDX 2 8299#define mmDIG0_AFMT_60958_2 0x20a7 8300#define mmDIG0_AFMT_60958_2_BASE_IDX 2 8301#define mmDIG0_AFMT_AUDIO_CRC_RESULT 0x20a8 8302#define mmDIG0_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 8303#define mmDIG0_AFMT_STATUS 0x20a9 8304#define mmDIG0_AFMT_STATUS_BASE_IDX 2 8305#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL 0x20aa 8306#define mmDIG0_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 8307#define mmDIG0_AFMT_VBI_PACKET_CONTROL 0x20ab 8308#define mmDIG0_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 8309#define mmDIG0_AFMT_INFOFRAME_CONTROL0 0x20ac 8310#define mmDIG0_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 8311#define mmDIG0_AFMT_AUDIO_SRC_CONTROL 0x20ad 8312#define mmDIG0_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 8313#define mmDIG0_DIG_BE_CNTL 0x20af 8314#define mmDIG0_DIG_BE_CNTL_BASE_IDX 2 8315#define mmDIG0_DIG_BE_EN_CNTL 0x20b0 8316#define mmDIG0_DIG_BE_EN_CNTL_BASE_IDX 2 8317#define mmDIG0_TMDS_CNTL 0x20d3 8318#define mmDIG0_TMDS_CNTL_BASE_IDX 2 8319#define mmDIG0_TMDS_CONTROL_CHAR 0x20d4 8320#define mmDIG0_TMDS_CONTROL_CHAR_BASE_IDX 2 8321#define mmDIG0_TMDS_CONTROL0_FEEDBACK 0x20d5 8322#define mmDIG0_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 8323#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL 0x20d6 8324#define mmDIG0_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 8325#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1 0x20d7 8326#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 8327#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3 0x20d8 8328#define mmDIG0_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 8329#define mmDIG0_TMDS_CTL_BITS 0x20da 8330#define mmDIG0_TMDS_CTL_BITS_BASE_IDX 2 8331#define mmDIG0_TMDS_DCBALANCER_CONTROL 0x20db 8332#define mmDIG0_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 8333#define mmDIG0_TMDS_CTL0_1_GEN_CNTL 0x20dd 8334#define mmDIG0_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 8335#define mmDIG0_TMDS_CTL2_3_GEN_CNTL 0x20de 8336#define mmDIG0_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 8337#define mmDIG0_DIG_VERSION 0x20e0 8338#define mmDIG0_DIG_VERSION_BASE_IDX 2 8339#define mmDIG0_DIG_LANE_ENABLE 0x20e1 8340#define mmDIG0_DIG_LANE_ENABLE_BASE_IDX 2 8341#define mmDIG0_AFMT_CNTL 0x20e6 8342#define mmDIG0_AFMT_CNTL_BASE_IDX 2 8343#define mmDIG0_AFMT_VBI_PACKET_CONTROL1 0x20e7 8344#define mmDIG0_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 8345 8346 8347// addressBlock: dce_dc_dio_dp0_dispdec 8348// base address: 0x0 8349#define mmDP0_DP_LINK_CNTL 0x2108 8350#define mmDP0_DP_LINK_CNTL_BASE_IDX 2 8351#define mmDP0_DP_PIXEL_FORMAT 0x2109 8352#define mmDP0_DP_PIXEL_FORMAT_BASE_IDX 2 8353#define mmDP0_DP_MSA_COLORIMETRY 0x210a 8354#define mmDP0_DP_MSA_COLORIMETRY_BASE_IDX 2 8355#define mmDP0_DP_CONFIG 0x210b 8356#define mmDP0_DP_CONFIG_BASE_IDX 2 8357#define mmDP0_DP_VID_STREAM_CNTL 0x210c 8358#define mmDP0_DP_VID_STREAM_CNTL_BASE_IDX 2 8359#define mmDP0_DP_STEER_FIFO 0x210d 8360#define mmDP0_DP_STEER_FIFO_BASE_IDX 2 8361#define mmDP0_DP_MSA_MISC 0x210e 8362#define mmDP0_DP_MSA_MISC_BASE_IDX 2 8363#define mmDP0_DP_VID_TIMING 0x2110 8364#define mmDP0_DP_VID_TIMING_BASE_IDX 2 8365#define mmDP0_DP_VID_N 0x2111 8366#define mmDP0_DP_VID_N_BASE_IDX 2 8367#define mmDP0_DP_VID_M 0x2112 8368#define mmDP0_DP_VID_M_BASE_IDX 2 8369#define mmDP0_DP_LINK_FRAMING_CNTL 0x2113 8370#define mmDP0_DP_LINK_FRAMING_CNTL_BASE_IDX 2 8371#define mmDP0_DP_HBR2_EYE_PATTERN 0x2114 8372#define mmDP0_DP_HBR2_EYE_PATTERN_BASE_IDX 2 8373#define mmDP0_DP_VID_MSA_VBID 0x2115 8374#define mmDP0_DP_VID_MSA_VBID_BASE_IDX 2 8375#define mmDP0_DP_VID_INTERRUPT_CNTL 0x2116 8376#define mmDP0_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 8377#define mmDP0_DP_DPHY_CNTL 0x2117 8378#define mmDP0_DP_DPHY_CNTL_BASE_IDX 2 8379#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL 0x2118 8380#define mmDP0_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 8381#define mmDP0_DP_DPHY_SYM0 0x2119 8382#define mmDP0_DP_DPHY_SYM0_BASE_IDX 2 8383#define mmDP0_DP_DPHY_SYM1 0x211a 8384#define mmDP0_DP_DPHY_SYM1_BASE_IDX 2 8385#define mmDP0_DP_DPHY_SYM2 0x211b 8386#define mmDP0_DP_DPHY_SYM2_BASE_IDX 2 8387#define mmDP0_DP_DPHY_8B10B_CNTL 0x211c 8388#define mmDP0_DP_DPHY_8B10B_CNTL_BASE_IDX 2 8389#define mmDP0_DP_DPHY_PRBS_CNTL 0x211d 8390#define mmDP0_DP_DPHY_PRBS_CNTL_BASE_IDX 2 8391#define mmDP0_DP_DPHY_SCRAM_CNTL 0x211e 8392#define mmDP0_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 8393#define mmDP0_DP_DPHY_CRC_EN 0x211f 8394#define mmDP0_DP_DPHY_CRC_EN_BASE_IDX 2 8395#define mmDP0_DP_DPHY_CRC_CNTL 0x2120 8396#define mmDP0_DP_DPHY_CRC_CNTL_BASE_IDX 2 8397#define mmDP0_DP_DPHY_CRC_RESULT 0x2121 8398#define mmDP0_DP_DPHY_CRC_RESULT_BASE_IDX 2 8399#define mmDP0_DP_DPHY_CRC_MST_CNTL 0x2122 8400#define mmDP0_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 8401#define mmDP0_DP_DPHY_CRC_MST_STATUS 0x2123 8402#define mmDP0_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 8403#define mmDP0_DP_DPHY_FAST_TRAINING 0x2124 8404#define mmDP0_DP_DPHY_FAST_TRAINING_BASE_IDX 2 8405#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS 0x2125 8406#define mmDP0_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 8407#define mmDP0_DP_SEC_CNTL 0x212b 8408#define mmDP0_DP_SEC_CNTL_BASE_IDX 2 8409#define mmDP0_DP_SEC_CNTL1 0x212c 8410#define mmDP0_DP_SEC_CNTL1_BASE_IDX 2 8411#define mmDP0_DP_SEC_FRAMING1 0x212d 8412#define mmDP0_DP_SEC_FRAMING1_BASE_IDX 2 8413#define mmDP0_DP_SEC_FRAMING2 0x212e 8414#define mmDP0_DP_SEC_FRAMING2_BASE_IDX 2 8415#define mmDP0_DP_SEC_FRAMING3 0x212f 8416#define mmDP0_DP_SEC_FRAMING3_BASE_IDX 2 8417#define mmDP0_DP_SEC_FRAMING4 0x2130 8418#define mmDP0_DP_SEC_FRAMING4_BASE_IDX 2 8419#define mmDP0_DP_SEC_AUD_N 0x2131 8420#define mmDP0_DP_SEC_AUD_N_BASE_IDX 2 8421#define mmDP0_DP_SEC_AUD_N_READBACK 0x2132 8422#define mmDP0_DP_SEC_AUD_N_READBACK_BASE_IDX 2 8423#define mmDP0_DP_SEC_AUD_M 0x2133 8424#define mmDP0_DP_SEC_AUD_M_BASE_IDX 2 8425#define mmDP0_DP_SEC_AUD_M_READBACK 0x2134 8426#define mmDP0_DP_SEC_AUD_M_READBACK_BASE_IDX 2 8427#define mmDP0_DP_SEC_TIMESTAMP 0x2135 8428#define mmDP0_DP_SEC_TIMESTAMP_BASE_IDX 2 8429#define mmDP0_DP_SEC_PACKET_CNTL 0x2136 8430#define mmDP0_DP_SEC_PACKET_CNTL_BASE_IDX 2 8431#define mmDP0_DP_MSE_RATE_CNTL 0x2137 8432#define mmDP0_DP_MSE_RATE_CNTL_BASE_IDX 2 8433#define mmDP0_DP_MSE_RATE_UPDATE 0x2139 8434#define mmDP0_DP_MSE_RATE_UPDATE_BASE_IDX 2 8435#define mmDP0_DP_MSE_SAT0 0x213a 8436#define mmDP0_DP_MSE_SAT0_BASE_IDX 2 8437#define mmDP0_DP_MSE_SAT1 0x213b 8438#define mmDP0_DP_MSE_SAT1_BASE_IDX 2 8439#define mmDP0_DP_MSE_SAT2 0x213c 8440#define mmDP0_DP_MSE_SAT2_BASE_IDX 2 8441#define mmDP0_DP_MSE_SAT_UPDATE 0x213d 8442#define mmDP0_DP_MSE_SAT_UPDATE_BASE_IDX 2 8443#define mmDP0_DP_MSE_LINK_TIMING 0x213e 8444#define mmDP0_DP_MSE_LINK_TIMING_BASE_IDX 2 8445#define mmDP0_DP_MSE_MISC_CNTL 0x213f 8446#define mmDP0_DP_MSE_MISC_CNTL_BASE_IDX 2 8447#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x2144 8448#define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 8449#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL 0x2145 8450#define mmDP0_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 8451#define mmDP0_DP_MSE_SAT0_STATUS 0x2147 8452#define mmDP0_DP_MSE_SAT0_STATUS_BASE_IDX 2 8453#define mmDP0_DP_MSE_SAT1_STATUS 0x2148 8454#define mmDP0_DP_MSE_SAT1_STATUS_BASE_IDX 2 8455#define mmDP0_DP_MSE_SAT2_STATUS 0x2149 8456#define mmDP0_DP_MSE_SAT2_STATUS_BASE_IDX 2 8457#define mmDP0_DP_MSA_TIMING_PARAM1 0x214c 8458#define mmDP0_DP_MSA_TIMING_PARAM1_BASE_IDX 2 8459#define mmDP0_DP_MSA_TIMING_PARAM2 0x214d 8460#define mmDP0_DP_MSA_TIMING_PARAM2_BASE_IDX 2 8461#define mmDP0_DP_MSA_TIMING_PARAM3 0x214e 8462#define mmDP0_DP_MSA_TIMING_PARAM3_BASE_IDX 2 8463#define mmDP0_DP_MSA_TIMING_PARAM4 0x214f 8464#define mmDP0_DP_MSA_TIMING_PARAM4_BASE_IDX 2 8465#define mmDP0_DP_MSO_CNTL 0x2150 8466#define mmDP0_DP_MSO_CNTL_BASE_IDX 2 8467#define mmDP0_DP_MSO_CNTL1 0x2151 8468#define mmDP0_DP_MSO_CNTL1_BASE_IDX 2 8469#define mmDP0_DP_DSC_CNTL 0x2152 8470#define mmDP0_DP_DSC_CNTL_BASE_IDX 2 8471#define mmDP0_DP_SEC_CNTL2 0x2153 8472#define mmDP0_DP_SEC_CNTL2_BASE_IDX 2 8473#define mmDP0_DP_SEC_CNTL3 0x2154 8474#define mmDP0_DP_SEC_CNTL3_BASE_IDX 2 8475#define mmDP0_DP_SEC_CNTL4 0x2155 8476#define mmDP0_DP_SEC_CNTL4_BASE_IDX 2 8477#define mmDP0_DP_SEC_CNTL5 0x2156 8478#define mmDP0_DP_SEC_CNTL5_BASE_IDX 2 8479#define mmDP0_DP_SEC_CNTL6 0x2157 8480#define mmDP0_DP_SEC_CNTL6_BASE_IDX 2 8481#define mmDP0_DP_SEC_CNTL7 0x2158 8482#define mmDP0_DP_SEC_CNTL7_BASE_IDX 2 8483#define mmDP0_DP_DB_CNTL 0x2159 8484#define mmDP0_DP_DB_CNTL_BASE_IDX 2 8485#define mmDP0_DP_MSA_VBID_MISC 0x215a 8486#define mmDP0_DP_MSA_VBID_MISC_BASE_IDX 2 8487 8488 8489// addressBlock: dce_dc_dio_dig1_dispdec 8490// base address: 0x400 8491#define mmDIG1_DIG_FE_CNTL 0x2168 8492#define mmDIG1_DIG_FE_CNTL_BASE_IDX 2 8493#define mmDIG1_DIG_OUTPUT_CRC_CNTL 0x2169 8494#define mmDIG1_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 8495#define mmDIG1_DIG_OUTPUT_CRC_RESULT 0x216a 8496#define mmDIG1_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 8497#define mmDIG1_DIG_CLOCK_PATTERN 0x216b 8498#define mmDIG1_DIG_CLOCK_PATTERN_BASE_IDX 2 8499#define mmDIG1_DIG_TEST_PATTERN 0x216c 8500#define mmDIG1_DIG_TEST_PATTERN_BASE_IDX 2 8501#define mmDIG1_DIG_RANDOM_PATTERN_SEED 0x216d 8502#define mmDIG1_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 8503#define mmDIG1_DIG_FIFO_STATUS 0x216e 8504#define mmDIG1_DIG_FIFO_STATUS_BASE_IDX 2 8505#define mmDIG1_HDMI_CONTROL 0x2171 8506#define mmDIG1_HDMI_CONTROL_BASE_IDX 2 8507#define mmDIG1_HDMI_STATUS 0x2172 8508#define mmDIG1_HDMI_STATUS_BASE_IDX 2 8509#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL 0x2173 8510#define mmDIG1_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 8511#define mmDIG1_HDMI_ACR_PACKET_CONTROL 0x2174 8512#define mmDIG1_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 8513#define mmDIG1_HDMI_VBI_PACKET_CONTROL 0x2175 8514#define mmDIG1_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 8515#define mmDIG1_HDMI_INFOFRAME_CONTROL0 0x2176 8516#define mmDIG1_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 8517#define mmDIG1_HDMI_INFOFRAME_CONTROL1 0x2177 8518#define mmDIG1_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 8519#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0 0x2178 8520#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 8521#define mmDIG1_AFMT_INTERRUPT_STATUS 0x2179 8522#define mmDIG1_AFMT_INTERRUPT_STATUS_BASE_IDX 2 8523#define mmDIG1_HDMI_GC 0x217b 8524#define mmDIG1_HDMI_GC_BASE_IDX 2 8525#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2 0x217c 8526#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 8527#define mmDIG1_AFMT_ISRC1_0 0x217d 8528#define mmDIG1_AFMT_ISRC1_0_BASE_IDX 2 8529#define mmDIG1_AFMT_ISRC1_1 0x217e 8530#define mmDIG1_AFMT_ISRC1_1_BASE_IDX 2 8531#define mmDIG1_AFMT_ISRC1_2 0x217f 8532#define mmDIG1_AFMT_ISRC1_2_BASE_IDX 2 8533#define mmDIG1_AFMT_ISRC1_3 0x2180 8534#define mmDIG1_AFMT_ISRC1_3_BASE_IDX 2 8535#define mmDIG1_AFMT_ISRC1_4 0x2181 8536#define mmDIG1_AFMT_ISRC1_4_BASE_IDX 2 8537#define mmDIG1_AFMT_ISRC2_0 0x2182 8538#define mmDIG1_AFMT_ISRC2_0_BASE_IDX 2 8539#define mmDIG1_AFMT_ISRC2_1 0x2183 8540#define mmDIG1_AFMT_ISRC2_1_BASE_IDX 2 8541#define mmDIG1_AFMT_ISRC2_2 0x2184 8542#define mmDIG1_AFMT_ISRC2_2_BASE_IDX 2 8543#define mmDIG1_AFMT_ISRC2_3 0x2185 8544#define mmDIG1_AFMT_ISRC2_3_BASE_IDX 2 8545#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2 0x2186 8546#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 8547#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3 0x2187 8548#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 8549#define mmDIG1_HDMI_DB_CONTROL 0x2188 8550#define mmDIG1_HDMI_DB_CONTROL_BASE_IDX 2 8551#define mmDIG1_AFMT_MPEG_INFO0 0x218a 8552#define mmDIG1_AFMT_MPEG_INFO0_BASE_IDX 2 8553#define mmDIG1_AFMT_MPEG_INFO1 0x218b 8554#define mmDIG1_AFMT_MPEG_INFO1_BASE_IDX 2 8555#define mmDIG1_AFMT_GENERIC_HDR 0x218c 8556#define mmDIG1_AFMT_GENERIC_HDR_BASE_IDX 2 8557#define mmDIG1_AFMT_GENERIC_0 0x218d 8558#define mmDIG1_AFMT_GENERIC_0_BASE_IDX 2 8559#define mmDIG1_AFMT_GENERIC_1 0x218e 8560#define mmDIG1_AFMT_GENERIC_1_BASE_IDX 2 8561#define mmDIG1_AFMT_GENERIC_2 0x218f 8562#define mmDIG1_AFMT_GENERIC_2_BASE_IDX 2 8563#define mmDIG1_AFMT_GENERIC_3 0x2190 8564#define mmDIG1_AFMT_GENERIC_3_BASE_IDX 2 8565#define mmDIG1_AFMT_GENERIC_4 0x2191 8566#define mmDIG1_AFMT_GENERIC_4_BASE_IDX 2 8567#define mmDIG1_AFMT_GENERIC_5 0x2192 8568#define mmDIG1_AFMT_GENERIC_5_BASE_IDX 2 8569#define mmDIG1_AFMT_GENERIC_6 0x2193 8570#define mmDIG1_AFMT_GENERIC_6_BASE_IDX 2 8571#define mmDIG1_AFMT_GENERIC_7 0x2194 8572#define mmDIG1_AFMT_GENERIC_7_BASE_IDX 2 8573#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1 0x2195 8574#define mmDIG1_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 8575#define mmDIG1_HDMI_ACR_32_0 0x2196 8576#define mmDIG1_HDMI_ACR_32_0_BASE_IDX 2 8577#define mmDIG1_HDMI_ACR_32_1 0x2197 8578#define mmDIG1_HDMI_ACR_32_1_BASE_IDX 2 8579#define mmDIG1_HDMI_ACR_44_0 0x2198 8580#define mmDIG1_HDMI_ACR_44_0_BASE_IDX 2 8581#define mmDIG1_HDMI_ACR_44_1 0x2199 8582#define mmDIG1_HDMI_ACR_44_1_BASE_IDX 2 8583#define mmDIG1_HDMI_ACR_48_0 0x219a 8584#define mmDIG1_HDMI_ACR_48_0_BASE_IDX 2 8585#define mmDIG1_HDMI_ACR_48_1 0x219b 8586#define mmDIG1_HDMI_ACR_48_1_BASE_IDX 2 8587#define mmDIG1_HDMI_ACR_STATUS_0 0x219c 8588#define mmDIG1_HDMI_ACR_STATUS_0_BASE_IDX 2 8589#define mmDIG1_HDMI_ACR_STATUS_1 0x219d 8590#define mmDIG1_HDMI_ACR_STATUS_1_BASE_IDX 2 8591#define mmDIG1_AFMT_AUDIO_INFO0 0x219e 8592#define mmDIG1_AFMT_AUDIO_INFO0_BASE_IDX 2 8593#define mmDIG1_AFMT_AUDIO_INFO1 0x219f 8594#define mmDIG1_AFMT_AUDIO_INFO1_BASE_IDX 2 8595#define mmDIG1_AFMT_60958_0 0x21a0 8596#define mmDIG1_AFMT_60958_0_BASE_IDX 2 8597#define mmDIG1_AFMT_60958_1 0x21a1 8598#define mmDIG1_AFMT_60958_1_BASE_IDX 2 8599#define mmDIG1_AFMT_AUDIO_CRC_CONTROL 0x21a2 8600#define mmDIG1_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 8601#define mmDIG1_AFMT_RAMP_CONTROL0 0x21a3 8602#define mmDIG1_AFMT_RAMP_CONTROL0_BASE_IDX 2 8603#define mmDIG1_AFMT_RAMP_CONTROL1 0x21a4 8604#define mmDIG1_AFMT_RAMP_CONTROL1_BASE_IDX 2 8605#define mmDIG1_AFMT_RAMP_CONTROL2 0x21a5 8606#define mmDIG1_AFMT_RAMP_CONTROL2_BASE_IDX 2 8607#define mmDIG1_AFMT_RAMP_CONTROL3 0x21a6 8608#define mmDIG1_AFMT_RAMP_CONTROL3_BASE_IDX 2 8609#define mmDIG1_AFMT_60958_2 0x21a7 8610#define mmDIG1_AFMT_60958_2_BASE_IDX 2 8611#define mmDIG1_AFMT_AUDIO_CRC_RESULT 0x21a8 8612#define mmDIG1_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 8613#define mmDIG1_AFMT_STATUS 0x21a9 8614#define mmDIG1_AFMT_STATUS_BASE_IDX 2 8615#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL 0x21aa 8616#define mmDIG1_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 8617#define mmDIG1_AFMT_VBI_PACKET_CONTROL 0x21ab 8618#define mmDIG1_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 8619#define mmDIG1_AFMT_INFOFRAME_CONTROL0 0x21ac 8620#define mmDIG1_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 8621#define mmDIG1_AFMT_AUDIO_SRC_CONTROL 0x21ad 8622#define mmDIG1_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 8623#define mmDIG1_DIG_BE_CNTL 0x21af 8624#define mmDIG1_DIG_BE_CNTL_BASE_IDX 2 8625#define mmDIG1_DIG_BE_EN_CNTL 0x21b0 8626#define mmDIG1_DIG_BE_EN_CNTL_BASE_IDX 2 8627#define mmDIG1_TMDS_CNTL 0x21d3 8628#define mmDIG1_TMDS_CNTL_BASE_IDX 2 8629#define mmDIG1_TMDS_CONTROL_CHAR 0x21d4 8630#define mmDIG1_TMDS_CONTROL_CHAR_BASE_IDX 2 8631#define mmDIG1_TMDS_CONTROL0_FEEDBACK 0x21d5 8632#define mmDIG1_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 8633#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL 0x21d6 8634#define mmDIG1_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 8635#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1 0x21d7 8636#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 8637#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3 0x21d8 8638#define mmDIG1_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 8639#define mmDIG1_TMDS_CTL_BITS 0x21da 8640#define mmDIG1_TMDS_CTL_BITS_BASE_IDX 2 8641#define mmDIG1_TMDS_DCBALANCER_CONTROL 0x21db 8642#define mmDIG1_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 8643#define mmDIG1_TMDS_CTL0_1_GEN_CNTL 0x21dd 8644#define mmDIG1_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 8645#define mmDIG1_TMDS_CTL2_3_GEN_CNTL 0x21de 8646#define mmDIG1_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 8647#define mmDIG1_DIG_VERSION 0x21e0 8648#define mmDIG1_DIG_VERSION_BASE_IDX 2 8649#define mmDIG1_DIG_LANE_ENABLE 0x21e1 8650#define mmDIG1_DIG_LANE_ENABLE_BASE_IDX 2 8651#define mmDIG1_AFMT_CNTL 0x21e6 8652#define mmDIG1_AFMT_CNTL_BASE_IDX 2 8653#define mmDIG1_AFMT_VBI_PACKET_CONTROL1 0x21e7 8654#define mmDIG1_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 8655 8656 8657// addressBlock: dce_dc_dio_dp1_dispdec 8658// base address: 0x400 8659#define mmDP1_DP_LINK_CNTL 0x2208 8660#define mmDP1_DP_LINK_CNTL_BASE_IDX 2 8661#define mmDP1_DP_PIXEL_FORMAT 0x2209 8662#define mmDP1_DP_PIXEL_FORMAT_BASE_IDX 2 8663#define mmDP1_DP_MSA_COLORIMETRY 0x220a 8664#define mmDP1_DP_MSA_COLORIMETRY_BASE_IDX 2 8665#define mmDP1_DP_CONFIG 0x220b 8666#define mmDP1_DP_CONFIG_BASE_IDX 2 8667#define mmDP1_DP_VID_STREAM_CNTL 0x220c 8668#define mmDP1_DP_VID_STREAM_CNTL_BASE_IDX 2 8669#define mmDP1_DP_STEER_FIFO 0x220d 8670#define mmDP1_DP_STEER_FIFO_BASE_IDX 2 8671#define mmDP1_DP_MSA_MISC 0x220e 8672#define mmDP1_DP_MSA_MISC_BASE_IDX 2 8673#define mmDP1_DP_VID_TIMING 0x2210 8674#define mmDP1_DP_VID_TIMING_BASE_IDX 2 8675#define mmDP1_DP_VID_N 0x2211 8676#define mmDP1_DP_VID_N_BASE_IDX 2 8677#define mmDP1_DP_VID_M 0x2212 8678#define mmDP1_DP_VID_M_BASE_IDX 2 8679#define mmDP1_DP_LINK_FRAMING_CNTL 0x2213 8680#define mmDP1_DP_LINK_FRAMING_CNTL_BASE_IDX 2 8681#define mmDP1_DP_HBR2_EYE_PATTERN 0x2214 8682#define mmDP1_DP_HBR2_EYE_PATTERN_BASE_IDX 2 8683#define mmDP1_DP_VID_MSA_VBID 0x2215 8684#define mmDP1_DP_VID_MSA_VBID_BASE_IDX 2 8685#define mmDP1_DP_VID_INTERRUPT_CNTL 0x2216 8686#define mmDP1_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 8687#define mmDP1_DP_DPHY_CNTL 0x2217 8688#define mmDP1_DP_DPHY_CNTL_BASE_IDX 2 8689#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL 0x2218 8690#define mmDP1_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 8691#define mmDP1_DP_DPHY_SYM0 0x2219 8692#define mmDP1_DP_DPHY_SYM0_BASE_IDX 2 8693#define mmDP1_DP_DPHY_SYM1 0x221a 8694#define mmDP1_DP_DPHY_SYM1_BASE_IDX 2 8695#define mmDP1_DP_DPHY_SYM2 0x221b 8696#define mmDP1_DP_DPHY_SYM2_BASE_IDX 2 8697#define mmDP1_DP_DPHY_8B10B_CNTL 0x221c 8698#define mmDP1_DP_DPHY_8B10B_CNTL_BASE_IDX 2 8699#define mmDP1_DP_DPHY_PRBS_CNTL 0x221d 8700#define mmDP1_DP_DPHY_PRBS_CNTL_BASE_IDX 2 8701#define mmDP1_DP_DPHY_SCRAM_CNTL 0x221e 8702#define mmDP1_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 8703#define mmDP1_DP_DPHY_CRC_EN 0x221f 8704#define mmDP1_DP_DPHY_CRC_EN_BASE_IDX 2 8705#define mmDP1_DP_DPHY_CRC_CNTL 0x2220 8706#define mmDP1_DP_DPHY_CRC_CNTL_BASE_IDX 2 8707#define mmDP1_DP_DPHY_CRC_RESULT 0x2221 8708#define mmDP1_DP_DPHY_CRC_RESULT_BASE_IDX 2 8709#define mmDP1_DP_DPHY_CRC_MST_CNTL 0x2222 8710#define mmDP1_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 8711#define mmDP1_DP_DPHY_CRC_MST_STATUS 0x2223 8712#define mmDP1_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 8713#define mmDP1_DP_DPHY_FAST_TRAINING 0x2224 8714#define mmDP1_DP_DPHY_FAST_TRAINING_BASE_IDX 2 8715#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS 0x2225 8716#define mmDP1_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 8717#define mmDP1_DP_SEC_CNTL 0x222b 8718#define mmDP1_DP_SEC_CNTL_BASE_IDX 2 8719#define mmDP1_DP_SEC_CNTL1 0x222c 8720#define mmDP1_DP_SEC_CNTL1_BASE_IDX 2 8721#define mmDP1_DP_SEC_FRAMING1 0x222d 8722#define mmDP1_DP_SEC_FRAMING1_BASE_IDX 2 8723#define mmDP1_DP_SEC_FRAMING2 0x222e 8724#define mmDP1_DP_SEC_FRAMING2_BASE_IDX 2 8725#define mmDP1_DP_SEC_FRAMING3 0x222f 8726#define mmDP1_DP_SEC_FRAMING3_BASE_IDX 2 8727#define mmDP1_DP_SEC_FRAMING4 0x2230 8728#define mmDP1_DP_SEC_FRAMING4_BASE_IDX 2 8729#define mmDP1_DP_SEC_AUD_N 0x2231 8730#define mmDP1_DP_SEC_AUD_N_BASE_IDX 2 8731#define mmDP1_DP_SEC_AUD_N_READBACK 0x2232 8732#define mmDP1_DP_SEC_AUD_N_READBACK_BASE_IDX 2 8733#define mmDP1_DP_SEC_AUD_M 0x2233 8734#define mmDP1_DP_SEC_AUD_M_BASE_IDX 2 8735#define mmDP1_DP_SEC_AUD_M_READBACK 0x2234 8736#define mmDP1_DP_SEC_AUD_M_READBACK_BASE_IDX 2 8737#define mmDP1_DP_SEC_TIMESTAMP 0x2235 8738#define mmDP1_DP_SEC_TIMESTAMP_BASE_IDX 2 8739#define mmDP1_DP_SEC_PACKET_CNTL 0x2236 8740#define mmDP1_DP_SEC_PACKET_CNTL_BASE_IDX 2 8741#define mmDP1_DP_MSE_RATE_CNTL 0x2237 8742#define mmDP1_DP_MSE_RATE_CNTL_BASE_IDX 2 8743#define mmDP1_DP_MSE_RATE_UPDATE 0x2239 8744#define mmDP1_DP_MSE_RATE_UPDATE_BASE_IDX 2 8745#define mmDP1_DP_MSE_SAT0 0x223a 8746#define mmDP1_DP_MSE_SAT0_BASE_IDX 2 8747#define mmDP1_DP_MSE_SAT1 0x223b 8748#define mmDP1_DP_MSE_SAT1_BASE_IDX 2 8749#define mmDP1_DP_MSE_SAT2 0x223c 8750#define mmDP1_DP_MSE_SAT2_BASE_IDX 2 8751#define mmDP1_DP_MSE_SAT_UPDATE 0x223d 8752#define mmDP1_DP_MSE_SAT_UPDATE_BASE_IDX 2 8753#define mmDP1_DP_MSE_LINK_TIMING 0x223e 8754#define mmDP1_DP_MSE_LINK_TIMING_BASE_IDX 2 8755#define mmDP1_DP_MSE_MISC_CNTL 0x223f 8756#define mmDP1_DP_MSE_MISC_CNTL_BASE_IDX 2 8757#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x2244 8758#define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 8759#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL 0x2245 8760#define mmDP1_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 8761#define mmDP1_DP_MSE_SAT0_STATUS 0x2247 8762#define mmDP1_DP_MSE_SAT0_STATUS_BASE_IDX 2 8763#define mmDP1_DP_MSE_SAT1_STATUS 0x2248 8764#define mmDP1_DP_MSE_SAT1_STATUS_BASE_IDX 2 8765#define mmDP1_DP_MSE_SAT2_STATUS 0x2249 8766#define mmDP1_DP_MSE_SAT2_STATUS_BASE_IDX 2 8767#define mmDP1_DP_MSA_TIMING_PARAM1 0x224c 8768#define mmDP1_DP_MSA_TIMING_PARAM1_BASE_IDX 2 8769#define mmDP1_DP_MSA_TIMING_PARAM2 0x224d 8770#define mmDP1_DP_MSA_TIMING_PARAM2_BASE_IDX 2 8771#define mmDP1_DP_MSA_TIMING_PARAM3 0x224e 8772#define mmDP1_DP_MSA_TIMING_PARAM3_BASE_IDX 2 8773#define mmDP1_DP_MSA_TIMING_PARAM4 0x224f 8774#define mmDP1_DP_MSA_TIMING_PARAM4_BASE_IDX 2 8775#define mmDP1_DP_MSO_CNTL 0x2250 8776#define mmDP1_DP_MSO_CNTL_BASE_IDX 2 8777#define mmDP1_DP_MSO_CNTL1 0x2251 8778#define mmDP1_DP_MSO_CNTL1_BASE_IDX 2 8779#define mmDP1_DP_DSC_CNTL 0x2252 8780#define mmDP1_DP_DSC_CNTL_BASE_IDX 2 8781#define mmDP1_DP_SEC_CNTL2 0x2253 8782#define mmDP1_DP_SEC_CNTL2_BASE_IDX 2 8783#define mmDP1_DP_SEC_CNTL3 0x2254 8784#define mmDP1_DP_SEC_CNTL3_BASE_IDX 2 8785#define mmDP1_DP_SEC_CNTL4 0x2255 8786#define mmDP1_DP_SEC_CNTL4_BASE_IDX 2 8787#define mmDP1_DP_SEC_CNTL5 0x2256 8788#define mmDP1_DP_SEC_CNTL5_BASE_IDX 2 8789#define mmDP1_DP_SEC_CNTL6 0x2257 8790#define mmDP1_DP_SEC_CNTL6_BASE_IDX 2 8791#define mmDP1_DP_SEC_CNTL7 0x2258 8792#define mmDP1_DP_SEC_CNTL7_BASE_IDX 2 8793#define mmDP1_DP_DB_CNTL 0x2259 8794#define mmDP1_DP_DB_CNTL_BASE_IDX 2 8795#define mmDP1_DP_MSA_VBID_MISC 0x225a 8796#define mmDP1_DP_MSA_VBID_MISC_BASE_IDX 2 8797 8798 8799// addressBlock: dce_dc_dio_dig2_dispdec 8800// base address: 0x800 8801#define mmDIG2_DIG_FE_CNTL 0x2268 8802#define mmDIG2_DIG_FE_CNTL_BASE_IDX 2 8803#define mmDIG2_DIG_OUTPUT_CRC_CNTL 0x2269 8804#define mmDIG2_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 8805#define mmDIG2_DIG_OUTPUT_CRC_RESULT 0x226a 8806#define mmDIG2_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 8807#define mmDIG2_DIG_CLOCK_PATTERN 0x226b 8808#define mmDIG2_DIG_CLOCK_PATTERN_BASE_IDX 2 8809#define mmDIG2_DIG_TEST_PATTERN 0x226c 8810#define mmDIG2_DIG_TEST_PATTERN_BASE_IDX 2 8811#define mmDIG2_DIG_RANDOM_PATTERN_SEED 0x226d 8812#define mmDIG2_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 8813#define mmDIG2_DIG_FIFO_STATUS 0x226e 8814#define mmDIG2_DIG_FIFO_STATUS_BASE_IDX 2 8815#define mmDIG2_HDMI_CONTROL 0x2271 8816#define mmDIG2_HDMI_CONTROL_BASE_IDX 2 8817#define mmDIG2_HDMI_STATUS 0x2272 8818#define mmDIG2_HDMI_STATUS_BASE_IDX 2 8819#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL 0x2273 8820#define mmDIG2_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 8821#define mmDIG2_HDMI_ACR_PACKET_CONTROL 0x2274 8822#define mmDIG2_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 8823#define mmDIG2_HDMI_VBI_PACKET_CONTROL 0x2275 8824#define mmDIG2_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 8825#define mmDIG2_HDMI_INFOFRAME_CONTROL0 0x2276 8826#define mmDIG2_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 8827#define mmDIG2_HDMI_INFOFRAME_CONTROL1 0x2277 8828#define mmDIG2_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 8829#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0 0x2278 8830#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 8831#define mmDIG2_AFMT_INTERRUPT_STATUS 0x2279 8832#define mmDIG2_AFMT_INTERRUPT_STATUS_BASE_IDX 2 8833#define mmDIG2_HDMI_GC 0x227b 8834#define mmDIG2_HDMI_GC_BASE_IDX 2 8835#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2 0x227c 8836#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 8837#define mmDIG2_AFMT_ISRC1_0 0x227d 8838#define mmDIG2_AFMT_ISRC1_0_BASE_IDX 2 8839#define mmDIG2_AFMT_ISRC1_1 0x227e 8840#define mmDIG2_AFMT_ISRC1_1_BASE_IDX 2 8841#define mmDIG2_AFMT_ISRC1_2 0x227f 8842#define mmDIG2_AFMT_ISRC1_2_BASE_IDX 2 8843#define mmDIG2_AFMT_ISRC1_3 0x2280 8844#define mmDIG2_AFMT_ISRC1_3_BASE_IDX 2 8845#define mmDIG2_AFMT_ISRC1_4 0x2281 8846#define mmDIG2_AFMT_ISRC1_4_BASE_IDX 2 8847#define mmDIG2_AFMT_ISRC2_0 0x2282 8848#define mmDIG2_AFMT_ISRC2_0_BASE_IDX 2 8849#define mmDIG2_AFMT_ISRC2_1 0x2283 8850#define mmDIG2_AFMT_ISRC2_1_BASE_IDX 2 8851#define mmDIG2_AFMT_ISRC2_2 0x2284 8852#define mmDIG2_AFMT_ISRC2_2_BASE_IDX 2 8853#define mmDIG2_AFMT_ISRC2_3 0x2285 8854#define mmDIG2_AFMT_ISRC2_3_BASE_IDX 2 8855#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2 0x2286 8856#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 8857#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3 0x2287 8858#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 8859#define mmDIG2_HDMI_DB_CONTROL 0x2288 8860#define mmDIG2_HDMI_DB_CONTROL_BASE_IDX 2 8861#define mmDIG2_AFMT_MPEG_INFO0 0x228a 8862#define mmDIG2_AFMT_MPEG_INFO0_BASE_IDX 2 8863#define mmDIG2_AFMT_MPEG_INFO1 0x228b 8864#define mmDIG2_AFMT_MPEG_INFO1_BASE_IDX 2 8865#define mmDIG2_AFMT_GENERIC_HDR 0x228c 8866#define mmDIG2_AFMT_GENERIC_HDR_BASE_IDX 2 8867#define mmDIG2_AFMT_GENERIC_0 0x228d 8868#define mmDIG2_AFMT_GENERIC_0_BASE_IDX 2 8869#define mmDIG2_AFMT_GENERIC_1 0x228e 8870#define mmDIG2_AFMT_GENERIC_1_BASE_IDX 2 8871#define mmDIG2_AFMT_GENERIC_2 0x228f 8872#define mmDIG2_AFMT_GENERIC_2_BASE_IDX 2 8873#define mmDIG2_AFMT_GENERIC_3 0x2290 8874#define mmDIG2_AFMT_GENERIC_3_BASE_IDX 2 8875#define mmDIG2_AFMT_GENERIC_4 0x2291 8876#define mmDIG2_AFMT_GENERIC_4_BASE_IDX 2 8877#define mmDIG2_AFMT_GENERIC_5 0x2292 8878#define mmDIG2_AFMT_GENERIC_5_BASE_IDX 2 8879#define mmDIG2_AFMT_GENERIC_6 0x2293 8880#define mmDIG2_AFMT_GENERIC_6_BASE_IDX 2 8881#define mmDIG2_AFMT_GENERIC_7 0x2294 8882#define mmDIG2_AFMT_GENERIC_7_BASE_IDX 2 8883#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1 0x2295 8884#define mmDIG2_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 8885#define mmDIG2_HDMI_ACR_32_0 0x2296 8886#define mmDIG2_HDMI_ACR_32_0_BASE_IDX 2 8887#define mmDIG2_HDMI_ACR_32_1 0x2297 8888#define mmDIG2_HDMI_ACR_32_1_BASE_IDX 2 8889#define mmDIG2_HDMI_ACR_44_0 0x2298 8890#define mmDIG2_HDMI_ACR_44_0_BASE_IDX 2 8891#define mmDIG2_HDMI_ACR_44_1 0x2299 8892#define mmDIG2_HDMI_ACR_44_1_BASE_IDX 2 8893#define mmDIG2_HDMI_ACR_48_0 0x229a 8894#define mmDIG2_HDMI_ACR_48_0_BASE_IDX 2 8895#define mmDIG2_HDMI_ACR_48_1 0x229b 8896#define mmDIG2_HDMI_ACR_48_1_BASE_IDX 2 8897#define mmDIG2_HDMI_ACR_STATUS_0 0x229c 8898#define mmDIG2_HDMI_ACR_STATUS_0_BASE_IDX 2 8899#define mmDIG2_HDMI_ACR_STATUS_1 0x229d 8900#define mmDIG2_HDMI_ACR_STATUS_1_BASE_IDX 2 8901#define mmDIG2_AFMT_AUDIO_INFO0 0x229e 8902#define mmDIG2_AFMT_AUDIO_INFO0_BASE_IDX 2 8903#define mmDIG2_AFMT_AUDIO_INFO1 0x229f 8904#define mmDIG2_AFMT_AUDIO_INFO1_BASE_IDX 2 8905#define mmDIG2_AFMT_60958_0 0x22a0 8906#define mmDIG2_AFMT_60958_0_BASE_IDX 2 8907#define mmDIG2_AFMT_60958_1 0x22a1 8908#define mmDIG2_AFMT_60958_1_BASE_IDX 2 8909#define mmDIG2_AFMT_AUDIO_CRC_CONTROL 0x22a2 8910#define mmDIG2_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 8911#define mmDIG2_AFMT_RAMP_CONTROL0 0x22a3 8912#define mmDIG2_AFMT_RAMP_CONTROL0_BASE_IDX 2 8913#define mmDIG2_AFMT_RAMP_CONTROL1 0x22a4 8914#define mmDIG2_AFMT_RAMP_CONTROL1_BASE_IDX 2 8915#define mmDIG2_AFMT_RAMP_CONTROL2 0x22a5 8916#define mmDIG2_AFMT_RAMP_CONTROL2_BASE_IDX 2 8917#define mmDIG2_AFMT_RAMP_CONTROL3 0x22a6 8918#define mmDIG2_AFMT_RAMP_CONTROL3_BASE_IDX 2 8919#define mmDIG2_AFMT_60958_2 0x22a7 8920#define mmDIG2_AFMT_60958_2_BASE_IDX 2 8921#define mmDIG2_AFMT_AUDIO_CRC_RESULT 0x22a8 8922#define mmDIG2_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 8923#define mmDIG2_AFMT_STATUS 0x22a9 8924#define mmDIG2_AFMT_STATUS_BASE_IDX 2 8925#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL 0x22aa 8926#define mmDIG2_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 8927#define mmDIG2_AFMT_VBI_PACKET_CONTROL 0x22ab 8928#define mmDIG2_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 8929#define mmDIG2_AFMT_INFOFRAME_CONTROL0 0x22ac 8930#define mmDIG2_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 8931#define mmDIG2_AFMT_AUDIO_SRC_CONTROL 0x22ad 8932#define mmDIG2_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 8933#define mmDIG2_DIG_BE_CNTL 0x22af 8934#define mmDIG2_DIG_BE_CNTL_BASE_IDX 2 8935#define mmDIG2_DIG_BE_EN_CNTL 0x22b0 8936#define mmDIG2_DIG_BE_EN_CNTL_BASE_IDX 2 8937#define mmDIG2_TMDS_CNTL 0x22d3 8938#define mmDIG2_TMDS_CNTL_BASE_IDX 2 8939#define mmDIG2_TMDS_CONTROL_CHAR 0x22d4 8940#define mmDIG2_TMDS_CONTROL_CHAR_BASE_IDX 2 8941#define mmDIG2_TMDS_CONTROL0_FEEDBACK 0x22d5 8942#define mmDIG2_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 8943#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL 0x22d6 8944#define mmDIG2_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 8945#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1 0x22d7 8946#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 8947#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3 0x22d8 8948#define mmDIG2_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 8949#define mmDIG2_TMDS_CTL_BITS 0x22da 8950#define mmDIG2_TMDS_CTL_BITS_BASE_IDX 2 8951#define mmDIG2_TMDS_DCBALANCER_CONTROL 0x22db 8952#define mmDIG2_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 8953#define mmDIG2_TMDS_CTL0_1_GEN_CNTL 0x22dd 8954#define mmDIG2_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 8955#define mmDIG2_TMDS_CTL2_3_GEN_CNTL 0x22de 8956#define mmDIG2_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 8957#define mmDIG2_DIG_VERSION 0x22e0 8958#define mmDIG2_DIG_VERSION_BASE_IDX 2 8959#define mmDIG2_DIG_LANE_ENABLE 0x22e1 8960#define mmDIG2_DIG_LANE_ENABLE_BASE_IDX 2 8961#define mmDIG2_AFMT_CNTL 0x22e6 8962#define mmDIG2_AFMT_CNTL_BASE_IDX 2 8963#define mmDIG2_AFMT_VBI_PACKET_CONTROL1 0x22e7 8964#define mmDIG2_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 8965 8966 8967// addressBlock: dce_dc_dio_dp2_dispdec 8968// base address: 0x800 8969#define mmDP2_DP_LINK_CNTL 0x2308 8970#define mmDP2_DP_LINK_CNTL_BASE_IDX 2 8971#define mmDP2_DP_PIXEL_FORMAT 0x2309 8972#define mmDP2_DP_PIXEL_FORMAT_BASE_IDX 2 8973#define mmDP2_DP_MSA_COLORIMETRY 0x230a 8974#define mmDP2_DP_MSA_COLORIMETRY_BASE_IDX 2 8975#define mmDP2_DP_CONFIG 0x230b 8976#define mmDP2_DP_CONFIG_BASE_IDX 2 8977#define mmDP2_DP_VID_STREAM_CNTL 0x230c 8978#define mmDP2_DP_VID_STREAM_CNTL_BASE_IDX 2 8979#define mmDP2_DP_STEER_FIFO 0x230d 8980#define mmDP2_DP_STEER_FIFO_BASE_IDX 2 8981#define mmDP2_DP_MSA_MISC 0x230e 8982#define mmDP2_DP_MSA_MISC_BASE_IDX 2 8983#define mmDP2_DP_VID_TIMING 0x2310 8984#define mmDP2_DP_VID_TIMING_BASE_IDX 2 8985#define mmDP2_DP_VID_N 0x2311 8986#define mmDP2_DP_VID_N_BASE_IDX 2 8987#define mmDP2_DP_VID_M 0x2312 8988#define mmDP2_DP_VID_M_BASE_IDX 2 8989#define mmDP2_DP_LINK_FRAMING_CNTL 0x2313 8990#define mmDP2_DP_LINK_FRAMING_CNTL_BASE_IDX 2 8991#define mmDP2_DP_HBR2_EYE_PATTERN 0x2314 8992#define mmDP2_DP_HBR2_EYE_PATTERN_BASE_IDX 2 8993#define mmDP2_DP_VID_MSA_VBID 0x2315 8994#define mmDP2_DP_VID_MSA_VBID_BASE_IDX 2 8995#define mmDP2_DP_VID_INTERRUPT_CNTL 0x2316 8996#define mmDP2_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 8997#define mmDP2_DP_DPHY_CNTL 0x2317 8998#define mmDP2_DP_DPHY_CNTL_BASE_IDX 2 8999#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL 0x2318 9000#define mmDP2_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2
9001#define mmDP2_DP_DPHY_SYM0 0x2319 9002#define mmDP2_DP_DPHY_SYM0_BASE_IDX 2 9003#define mmDP2_DP_DPHY_SYM1 0x231a 9004#define mmDP2_DP_DPHY_SYM1_BASE_IDX 2 9005#define mmDP2_DP_DPHY_SYM2 0x231b 9006#define mmDP2_DP_DPHY_SYM2_BASE_IDX 2 9007#define mmDP2_DP_DPHY_8B10B_CNTL 0x231c 9008#define mmDP2_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9009#define mmDP2_DP_DPHY_PRBS_CNTL 0x231d 9010#define mmDP2_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9011#define mmDP2_DP_DPHY_SCRAM_CNTL 0x231e 9012#define mmDP2_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9013#define mmDP2_DP_DPHY_CRC_EN 0x231f 9014#define mmDP2_DP_DPHY_CRC_EN_BASE_IDX 2 9015#define mmDP2_DP_DPHY_CRC_CNTL 0x2320 9016#define mmDP2_DP_DPHY_CRC_CNTL_BASE_IDX 2 9017#define mmDP2_DP_DPHY_CRC_RESULT 0x2321 9018#define mmDP2_DP_DPHY_CRC_RESULT_BASE_IDX 2 9019#define mmDP2_DP_DPHY_CRC_MST_CNTL 0x2322 9020#define mmDP2_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9021#define mmDP2_DP_DPHY_CRC_MST_STATUS 0x2323 9022#define mmDP2_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9023#define mmDP2_DP_DPHY_FAST_TRAINING 0x2324 9024#define mmDP2_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9025#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS 0x2325 9026#define mmDP2_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9027#define mmDP2_DP_SEC_CNTL 0x232b 9028#define mmDP2_DP_SEC_CNTL_BASE_IDX 2 9029#define mmDP2_DP_SEC_CNTL1 0x232c 9030#define mmDP2_DP_SEC_CNTL1_BASE_IDX 2 9031#define mmDP2_DP_SEC_FRAMING1 0x232d 9032#define mmDP2_DP_SEC_FRAMING1_BASE_IDX 2 9033#define mmDP2_DP_SEC_FRAMING2 0x232e 9034#define mmDP2_DP_SEC_FRAMING2_BASE_IDX 2 9035#define mmDP2_DP_SEC_FRAMING3 0x232f 9036#define mmDP2_DP_SEC_FRAMING3_BASE_IDX 2 9037#define mmDP2_DP_SEC_FRAMING4 0x2330 9038#define mmDP2_DP_SEC_FRAMING4_BASE_IDX 2 9039#define mmDP2_DP_SEC_AUD_N 0x2331 9040#define mmDP2_DP_SEC_AUD_N_BASE_IDX 2 9041#define mmDP2_DP_SEC_AUD_N_READBACK 0x2332 9042#define mmDP2_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9043#define mmDP2_DP_SEC_AUD_M 0x2333 9044#define mmDP2_DP_SEC_AUD_M_BASE_IDX 2 9045#define mmDP2_DP_SEC_AUD_M_READBACK 0x2334 9046#define mmDP2_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9047#define mmDP2_DP_SEC_TIMESTAMP 0x2335 9048#define mmDP2_DP_SEC_TIMESTAMP_BASE_IDX 2 9049#define mmDP2_DP_SEC_PACKET_CNTL 0x2336 9050#define mmDP2_DP_SEC_PACKET_CNTL_BASE_IDX 2 9051#define mmDP2_DP_MSE_RATE_CNTL 0x2337 9052#define mmDP2_DP_MSE_RATE_CNTL_BASE_IDX 2 9053#define mmDP2_DP_MSE_RATE_UPDATE 0x2339 9054#define mmDP2_DP_MSE_RATE_UPDATE_BASE_IDX 2 9055#define mmDP2_DP_MSE_SAT0 0x233a 9056#define mmDP2_DP_MSE_SAT0_BASE_IDX 2 9057#define mmDP2_DP_MSE_SAT1 0x233b 9058#define mmDP2_DP_MSE_SAT1_BASE_IDX 2 9059#define mmDP2_DP_MSE_SAT2 0x233c 9060#define mmDP2_DP_MSE_SAT2_BASE_IDX 2 9061#define mmDP2_DP_MSE_SAT_UPDATE 0x233d 9062#define mmDP2_DP_MSE_SAT_UPDATE_BASE_IDX 2 9063#define mmDP2_DP_MSE_LINK_TIMING 0x233e 9064#define mmDP2_DP_MSE_LINK_TIMING_BASE_IDX 2 9065#define mmDP2_DP_MSE_MISC_CNTL 0x233f 9066#define mmDP2_DP_MSE_MISC_CNTL_BASE_IDX 2 9067#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x2344 9068#define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9069#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL 0x2345 9070#define mmDP2_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9071#define mmDP2_DP_MSE_SAT0_STATUS 0x2347 9072#define mmDP2_DP_MSE_SAT0_STATUS_BASE_IDX 2 9073#define mmDP2_DP_MSE_SAT1_STATUS 0x2348 9074#define mmDP2_DP_MSE_SAT1_STATUS_BASE_IDX 2 9075#define mmDP2_DP_MSE_SAT2_STATUS 0x2349 9076#define mmDP2_DP_MSE_SAT2_STATUS_BASE_IDX 2 9077#define mmDP2_DP_MSA_TIMING_PARAM1 0x234c 9078#define mmDP2_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9079#define mmDP2_DP_MSA_TIMING_PARAM2 0x234d 9080#define mmDP2_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9081#define mmDP2_DP_MSA_TIMING_PARAM3 0x234e 9082#define mmDP2_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9083#define mmDP2_DP_MSA_TIMING_PARAM4 0x234f 9084#define mmDP2_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9085#define mmDP2_DP_MSO_CNTL 0x2350 9086#define mmDP2_DP_MSO_CNTL_BASE_IDX 2 9087#define mmDP2_DP_MSO_CNTL1 0x2351 9088#define mmDP2_DP_MSO_CNTL1_BASE_IDX 2 9089#define mmDP2_DP_DSC_CNTL 0x2352 9090#define mmDP2_DP_DSC_CNTL_BASE_IDX 2 9091#define mmDP2_DP_SEC_CNTL2 0x2353 9092#define mmDP2_DP_SEC_CNTL2_BASE_IDX 2 9093#define mmDP2_DP_SEC_CNTL3 0x2354 9094#define mmDP2_DP_SEC_CNTL3_BASE_IDX 2 9095#define mmDP2_DP_SEC_CNTL4 0x2355 9096#define mmDP2_DP_SEC_CNTL4_BASE_IDX 2 9097#define mmDP2_DP_SEC_CNTL5 0x2356 9098#define mmDP2_DP_SEC_CNTL5_BASE_IDX 2 9099#define mmDP2_DP_SEC_CNTL6 0x2357 9100#define mmDP2_DP_SEC_CNTL6_BASE_IDX 2 9101#define mmDP2_DP_SEC_CNTL7 0x2358 9102#define mmDP2_DP_SEC_CNTL7_BASE_IDX 2 9103#define mmDP2_DP_DB_CNTL 0x2359 9104#define mmDP2_DP_DB_CNTL_BASE_IDX 2 9105#define mmDP2_DP_MSA_VBID_MISC 0x235a 9106#define mmDP2_DP_MSA_VBID_MISC_BASE_IDX 2 9107 9108 9109// addressBlock: dce_dc_dio_dig3_dispdec 9110// base address: 0xc00 9111#define mmDIG3_DIG_FE_CNTL 0x2368 9112#define mmDIG3_DIG_FE_CNTL_BASE_IDX 2 9113#define mmDIG3_DIG_OUTPUT_CRC_CNTL 0x2369 9114#define mmDIG3_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9115#define mmDIG3_DIG_OUTPUT_CRC_RESULT 0x236a 9116#define mmDIG3_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9117#define mmDIG3_DIG_CLOCK_PATTERN 0x236b 9118#define mmDIG3_DIG_CLOCK_PATTERN_BASE_IDX 2 9119#define mmDIG3_DIG_TEST_PATTERN 0x236c 9120#define mmDIG3_DIG_TEST_PATTERN_BASE_IDX 2 9121#define mmDIG3_DIG_RANDOM_PATTERN_SEED 0x236d 9122#define mmDIG3_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9123#define mmDIG3_DIG_FIFO_STATUS 0x236e 9124#define mmDIG3_DIG_FIFO_STATUS_BASE_IDX 2 9125#define mmDIG3_HDMI_CONTROL 0x2371 9126#define mmDIG3_HDMI_CONTROL_BASE_IDX 2 9127#define mmDIG3_HDMI_STATUS 0x2372 9128#define mmDIG3_HDMI_STATUS_BASE_IDX 2 9129#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL 0x2373 9130#define mmDIG3_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9131#define mmDIG3_HDMI_ACR_PACKET_CONTROL 0x2374 9132#define mmDIG3_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9133#define mmDIG3_HDMI_VBI_PACKET_CONTROL 0x2375 9134#define mmDIG3_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9135#define mmDIG3_HDMI_INFOFRAME_CONTROL0 0x2376 9136#define mmDIG3_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9137#define mmDIG3_HDMI_INFOFRAME_CONTROL1 0x2377 9138#define mmDIG3_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9139#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0 0x2378 9140#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9141#define mmDIG3_AFMT_INTERRUPT_STATUS 0x2379 9142#define mmDIG3_AFMT_INTERRUPT_STATUS_BASE_IDX 2 9143#define mmDIG3_HDMI_GC 0x237b 9144#define mmDIG3_HDMI_GC_BASE_IDX 2 9145#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2 0x237c 9146#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 9147#define mmDIG3_AFMT_ISRC1_0 0x237d 9148#define mmDIG3_AFMT_ISRC1_0_BASE_IDX 2 9149#define mmDIG3_AFMT_ISRC1_1 0x237e 9150#define mmDIG3_AFMT_ISRC1_1_BASE_IDX 2 9151#define mmDIG3_AFMT_ISRC1_2 0x237f 9152#define mmDIG3_AFMT_ISRC1_2_BASE_IDX 2 9153#define mmDIG3_AFMT_ISRC1_3 0x2380 9154#define mmDIG3_AFMT_ISRC1_3_BASE_IDX 2 9155#define mmDIG3_AFMT_ISRC1_4 0x2381 9156#define mmDIG3_AFMT_ISRC1_4_BASE_IDX 2 9157#define mmDIG3_AFMT_ISRC2_0 0x2382 9158#define mmDIG3_AFMT_ISRC2_0_BASE_IDX 2 9159#define mmDIG3_AFMT_ISRC2_1 0x2383 9160#define mmDIG3_AFMT_ISRC2_1_BASE_IDX 2 9161#define mmDIG3_AFMT_ISRC2_2 0x2384 9162#define mmDIG3_AFMT_ISRC2_2_BASE_IDX 2 9163#define mmDIG3_AFMT_ISRC2_3 0x2385 9164#define mmDIG3_AFMT_ISRC2_3_BASE_IDX 2 9165#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2 0x2386 9166#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9167#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3 0x2387 9168#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9169#define mmDIG3_HDMI_DB_CONTROL 0x2388 9170#define mmDIG3_HDMI_DB_CONTROL_BASE_IDX 2 9171#define mmDIG3_AFMT_MPEG_INFO0 0x238a 9172#define mmDIG3_AFMT_MPEG_INFO0_BASE_IDX 2 9173#define mmDIG3_AFMT_MPEG_INFO1 0x238b 9174#define mmDIG3_AFMT_MPEG_INFO1_BASE_IDX 2 9175#define mmDIG3_AFMT_GENERIC_HDR 0x238c 9176#define mmDIG3_AFMT_GENERIC_HDR_BASE_IDX 2 9177#define mmDIG3_AFMT_GENERIC_0 0x238d 9178#define mmDIG3_AFMT_GENERIC_0_BASE_IDX 2 9179#define mmDIG3_AFMT_GENERIC_1 0x238e 9180#define mmDIG3_AFMT_GENERIC_1_BASE_IDX 2 9181#define mmDIG3_AFMT_GENERIC_2 0x238f 9182#define mmDIG3_AFMT_GENERIC_2_BASE_IDX 2 9183#define mmDIG3_AFMT_GENERIC_3 0x2390 9184#define mmDIG3_AFMT_GENERIC_3_BASE_IDX 2 9185#define mmDIG3_AFMT_GENERIC_4 0x2391 9186#define mmDIG3_AFMT_GENERIC_4_BASE_IDX 2 9187#define mmDIG3_AFMT_GENERIC_5 0x2392 9188#define mmDIG3_AFMT_GENERIC_5_BASE_IDX 2 9189#define mmDIG3_AFMT_GENERIC_6 0x2393 9190#define mmDIG3_AFMT_GENERIC_6_BASE_IDX 2 9191#define mmDIG3_AFMT_GENERIC_7 0x2394 9192#define mmDIG3_AFMT_GENERIC_7_BASE_IDX 2 9193#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1 0x2395 9194#define mmDIG3_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9195#define mmDIG3_HDMI_ACR_32_0 0x2396 9196#define mmDIG3_HDMI_ACR_32_0_BASE_IDX 2 9197#define mmDIG3_HDMI_ACR_32_1 0x2397 9198#define mmDIG3_HDMI_ACR_32_1_BASE_IDX 2 9199#define mmDIG3_HDMI_ACR_44_0 0x2398 9200#define mmDIG3_HDMI_ACR_44_0_BASE_IDX 2 9201#define mmDIG3_HDMI_ACR_44_1 0x2399 9202#define mmDIG3_HDMI_ACR_44_1_BASE_IDX 2 9203#define mmDIG3_HDMI_ACR_48_0 0x239a 9204#define mmDIG3_HDMI_ACR_48_0_BASE_IDX 2 9205#define mmDIG3_HDMI_ACR_48_1 0x239b 9206#define mmDIG3_HDMI_ACR_48_1_BASE_IDX 2 9207#define mmDIG3_HDMI_ACR_STATUS_0 0x239c 9208#define mmDIG3_HDMI_ACR_STATUS_0_BASE_IDX 2 9209#define mmDIG3_HDMI_ACR_STATUS_1 0x239d 9210#define mmDIG3_HDMI_ACR_STATUS_1_BASE_IDX 2 9211#define mmDIG3_AFMT_AUDIO_INFO0 0x239e 9212#define mmDIG3_AFMT_AUDIO_INFO0_BASE_IDX 2 9213#define mmDIG3_AFMT_AUDIO_INFO1 0x239f 9214#define mmDIG3_AFMT_AUDIO_INFO1_BASE_IDX 2 9215#define mmDIG3_AFMT_60958_0 0x23a0 9216#define mmDIG3_AFMT_60958_0_BASE_IDX 2 9217#define mmDIG3_AFMT_60958_1 0x23a1 9218#define mmDIG3_AFMT_60958_1_BASE_IDX 2 9219#define mmDIG3_AFMT_AUDIO_CRC_CONTROL 0x23a2 9220#define mmDIG3_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 9221#define mmDIG3_AFMT_RAMP_CONTROL0 0x23a3 9222#define mmDIG3_AFMT_RAMP_CONTROL0_BASE_IDX 2 9223#define mmDIG3_AFMT_RAMP_CONTROL1 0x23a4 9224#define mmDIG3_AFMT_RAMP_CONTROL1_BASE_IDX 2 9225#define mmDIG3_AFMT_RAMP_CONTROL2 0x23a5 9226#define mmDIG3_AFMT_RAMP_CONTROL2_BASE_IDX 2 9227#define mmDIG3_AFMT_RAMP_CONTROL3 0x23a6 9228#define mmDIG3_AFMT_RAMP_CONTROL3_BASE_IDX 2 9229#define mmDIG3_AFMT_60958_2 0x23a7 9230#define mmDIG3_AFMT_60958_2_BASE_IDX 2 9231#define mmDIG3_AFMT_AUDIO_CRC_RESULT 0x23a8 9232#define mmDIG3_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 9233#define mmDIG3_AFMT_STATUS 0x23a9 9234#define mmDIG3_AFMT_STATUS_BASE_IDX 2 9235#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL 0x23aa 9236#define mmDIG3_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 9237#define mmDIG3_AFMT_VBI_PACKET_CONTROL 0x23ab 9238#define mmDIG3_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 9239#define mmDIG3_AFMT_INFOFRAME_CONTROL0 0x23ac 9240#define mmDIG3_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 9241#define mmDIG3_AFMT_AUDIO_SRC_CONTROL 0x23ad 9242#define mmDIG3_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 9243#define mmDIG3_DIG_BE_CNTL 0x23af 9244#define mmDIG3_DIG_BE_CNTL_BASE_IDX 2 9245#define mmDIG3_DIG_BE_EN_CNTL 0x23b0 9246#define mmDIG3_DIG_BE_EN_CNTL_BASE_IDX 2 9247#define mmDIG3_TMDS_CNTL 0x23d3 9248#define mmDIG3_TMDS_CNTL_BASE_IDX 2 9249#define mmDIG3_TMDS_CONTROL_CHAR 0x23d4 9250#define mmDIG3_TMDS_CONTROL_CHAR_BASE_IDX 2 9251#define mmDIG3_TMDS_CONTROL0_FEEDBACK 0x23d5 9252#define mmDIG3_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9253#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL 0x23d6 9254#define mmDIG3_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9255#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1 0x23d7 9256#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9257#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3 0x23d8 9258#define mmDIG3_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9259#define mmDIG3_TMDS_CTL_BITS 0x23da 9260#define mmDIG3_TMDS_CTL_BITS_BASE_IDX 2 9261#define mmDIG3_TMDS_DCBALANCER_CONTROL 0x23db 9262#define mmDIG3_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9263#define mmDIG3_TMDS_CTL0_1_GEN_CNTL 0x23dd 9264#define mmDIG3_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9265#define mmDIG3_TMDS_CTL2_3_GEN_CNTL 0x23de 9266#define mmDIG3_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9267#define mmDIG3_DIG_VERSION 0x23e0 9268#define mmDIG3_DIG_VERSION_BASE_IDX 2 9269#define mmDIG3_DIG_LANE_ENABLE 0x23e1 9270#define mmDIG3_DIG_LANE_ENABLE_BASE_IDX 2 9271#define mmDIG3_AFMT_CNTL 0x23e6 9272#define mmDIG3_AFMT_CNTL_BASE_IDX 2 9273#define mmDIG3_AFMT_VBI_PACKET_CONTROL1 0x23e7 9274#define mmDIG3_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 9275 9276 9277// addressBlock: dce_dc_dio_dp3_dispdec 9278// base address: 0xc00 9279#define mmDP3_DP_LINK_CNTL 0x2408 9280#define mmDP3_DP_LINK_CNTL_BASE_IDX 2 9281#define mmDP3_DP_PIXEL_FORMAT 0x2409 9282#define mmDP3_DP_PIXEL_FORMAT_BASE_IDX 2 9283#define mmDP3_DP_MSA_COLORIMETRY 0x240a 9284#define mmDP3_DP_MSA_COLORIMETRY_BASE_IDX 2 9285#define mmDP3_DP_CONFIG 0x240b 9286#define mmDP3_DP_CONFIG_BASE_IDX 2 9287#define mmDP3_DP_VID_STREAM_CNTL 0x240c 9288#define mmDP3_DP_VID_STREAM_CNTL_BASE_IDX 2 9289#define mmDP3_DP_STEER_FIFO 0x240d 9290#define mmDP3_DP_STEER_FIFO_BASE_IDX 2 9291#define mmDP3_DP_MSA_MISC 0x240e 9292#define mmDP3_DP_MSA_MISC_BASE_IDX 2 9293#define mmDP3_DP_VID_TIMING 0x2410 9294#define mmDP3_DP_VID_TIMING_BASE_IDX 2 9295#define mmDP3_DP_VID_N 0x2411 9296#define mmDP3_DP_VID_N_BASE_IDX 2 9297#define mmDP3_DP_VID_M 0x2412 9298#define mmDP3_DP_VID_M_BASE_IDX 2 9299#define mmDP3_DP_LINK_FRAMING_CNTL 0x2413 9300#define mmDP3_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9301#define mmDP3_DP_HBR2_EYE_PATTERN 0x2414 9302#define mmDP3_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9303#define mmDP3_DP_VID_MSA_VBID 0x2415 9304#define mmDP3_DP_VID_MSA_VBID_BASE_IDX 2 9305#define mmDP3_DP_VID_INTERRUPT_CNTL 0x2416 9306#define mmDP3_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9307#define mmDP3_DP_DPHY_CNTL 0x2417 9308#define mmDP3_DP_DPHY_CNTL_BASE_IDX 2 9309#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL 0x2418 9310#define mmDP3_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9311#define mmDP3_DP_DPHY_SYM0 0x2419 9312#define mmDP3_DP_DPHY_SYM0_BASE_IDX 2 9313#define mmDP3_DP_DPHY_SYM1 0x241a 9314#define mmDP3_DP_DPHY_SYM1_BASE_IDX 2 9315#define mmDP3_DP_DPHY_SYM2 0x241b 9316#define mmDP3_DP_DPHY_SYM2_BASE_IDX 2 9317#define mmDP3_DP_DPHY_8B10B_CNTL 0x241c 9318#define mmDP3_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9319#define mmDP3_DP_DPHY_PRBS_CNTL 0x241d 9320#define mmDP3_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9321#define mmDP3_DP_DPHY_SCRAM_CNTL 0x241e 9322#define mmDP3_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9323#define mmDP3_DP_DPHY_CRC_EN 0x241f 9324#define mmDP3_DP_DPHY_CRC_EN_BASE_IDX 2 9325#define mmDP3_DP_DPHY_CRC_CNTL 0x2420 9326#define mmDP3_DP_DPHY_CRC_CNTL_BASE_IDX 2 9327#define mmDP3_DP_DPHY_CRC_RESULT 0x2421 9328#define mmDP3_DP_DPHY_CRC_RESULT_BASE_IDX 2 9329#define mmDP3_DP_DPHY_CRC_MST_CNTL 0x2422 9330#define mmDP3_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9331#define mmDP3_DP_DPHY_CRC_MST_STATUS 0x2423 9332#define mmDP3_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9333#define mmDP3_DP_DPHY_FAST_TRAINING 0x2424 9334#define mmDP3_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9335#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS 0x2425 9336#define mmDP3_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9337#define mmDP3_DP_SEC_CNTL 0x242b 9338#define mmDP3_DP_SEC_CNTL_BASE_IDX 2 9339#define mmDP3_DP_SEC_CNTL1 0x242c 9340#define mmDP3_DP_SEC_CNTL1_BASE_IDX 2 9341#define mmDP3_DP_SEC_FRAMING1 0x242d 9342#define mmDP3_DP_SEC_FRAMING1_BASE_IDX 2 9343#define mmDP3_DP_SEC_FRAMING2 0x242e 9344#define mmDP3_DP_SEC_FRAMING2_BASE_IDX 2 9345#define mmDP3_DP_SEC_FRAMING3 0x242f 9346#define mmDP3_DP_SEC_FRAMING3_BASE_IDX 2 9347#define mmDP3_DP_SEC_FRAMING4 0x2430 9348#define mmDP3_DP_SEC_FRAMING4_BASE_IDX 2 9349#define mmDP3_DP_SEC_AUD_N 0x2431 9350#define mmDP3_DP_SEC_AUD_N_BASE_IDX 2 9351#define mmDP3_DP_SEC_AUD_N_READBACK 0x2432 9352#define mmDP3_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9353#define mmDP3_DP_SEC_AUD_M 0x2433 9354#define mmDP3_DP_SEC_AUD_M_BASE_IDX 2 9355#define mmDP3_DP_SEC_AUD_M_READBACK 0x2434 9356#define mmDP3_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9357#define mmDP3_DP_SEC_TIMESTAMP 0x2435 9358#define mmDP3_DP_SEC_TIMESTAMP_BASE_IDX 2 9359#define mmDP3_DP_SEC_PACKET_CNTL 0x2436 9360#define mmDP3_DP_SEC_PACKET_CNTL_BASE_IDX 2 9361#define mmDP3_DP_MSE_RATE_CNTL 0x2437 9362#define mmDP3_DP_MSE_RATE_CNTL_BASE_IDX 2 9363#define mmDP3_DP_MSE_RATE_UPDATE 0x2439 9364#define mmDP3_DP_MSE_RATE_UPDATE_BASE_IDX 2 9365#define mmDP3_DP_MSE_SAT0 0x243a 9366#define mmDP3_DP_MSE_SAT0_BASE_IDX 2 9367#define mmDP3_DP_MSE_SAT1 0x243b 9368#define mmDP3_DP_MSE_SAT1_BASE_IDX 2 9369#define mmDP3_DP_MSE_SAT2 0x243c 9370#define mmDP3_DP_MSE_SAT2_BASE_IDX 2 9371#define mmDP3_DP_MSE_SAT_UPDATE 0x243d 9372#define mmDP3_DP_MSE_SAT_UPDATE_BASE_IDX 2 9373#define mmDP3_DP_MSE_LINK_TIMING 0x243e 9374#define mmDP3_DP_MSE_LINK_TIMING_BASE_IDX 2 9375#define mmDP3_DP_MSE_MISC_CNTL 0x243f 9376#define mmDP3_DP_MSE_MISC_CNTL_BASE_IDX 2 9377#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x2444 9378#define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9379#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL 0x2445 9380#define mmDP3_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9381#define mmDP3_DP_MSE_SAT0_STATUS 0x2447 9382#define mmDP3_DP_MSE_SAT0_STATUS_BASE_IDX 2 9383#define mmDP3_DP_MSE_SAT1_STATUS 0x2448 9384#define mmDP3_DP_MSE_SAT1_STATUS_BASE_IDX 2 9385#define mmDP3_DP_MSE_SAT2_STATUS 0x2449 9386#define mmDP3_DP_MSE_SAT2_STATUS_BASE_IDX 2 9387#define mmDP3_DP_MSA_TIMING_PARAM1 0x244c 9388#define mmDP3_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9389#define mmDP3_DP_MSA_TIMING_PARAM2 0x244d 9390#define mmDP3_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9391#define mmDP3_DP_MSA_TIMING_PARAM3 0x244e 9392#define mmDP3_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9393#define mmDP3_DP_MSA_TIMING_PARAM4 0x244f 9394#define mmDP3_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9395#define mmDP3_DP_MSO_CNTL 0x2450 9396#define mmDP3_DP_MSO_CNTL_BASE_IDX 2 9397#define mmDP3_DP_MSO_CNTL1 0x2451 9398#define mmDP3_DP_MSO_CNTL1_BASE_IDX 2 9399#define mmDP3_DP_DSC_CNTL 0x2452 9400#define mmDP3_DP_DSC_CNTL_BASE_IDX 2 9401#define mmDP3_DP_SEC_CNTL2 0x2453 9402#define mmDP3_DP_SEC_CNTL2_BASE_IDX 2 9403#define mmDP3_DP_SEC_CNTL3 0x2454 9404#define mmDP3_DP_SEC_CNTL3_BASE_IDX 2 9405#define mmDP3_DP_SEC_CNTL4 0x2455 9406#define mmDP3_DP_SEC_CNTL4_BASE_IDX 2 9407#define mmDP3_DP_SEC_CNTL5 0x2456 9408#define mmDP3_DP_SEC_CNTL5_BASE_IDX 2 9409#define mmDP3_DP_SEC_CNTL6 0x2457 9410#define mmDP3_DP_SEC_CNTL6_BASE_IDX 2 9411#define mmDP3_DP_SEC_CNTL7 0x2458 9412#define mmDP3_DP_SEC_CNTL7_BASE_IDX 2 9413#define mmDP3_DP_DB_CNTL 0x2459 9414#define mmDP3_DP_DB_CNTL_BASE_IDX 2 9415#define mmDP3_DP_MSA_VBID_MISC 0x245a 9416#define mmDP3_DP_MSA_VBID_MISC_BASE_IDX 2 9417 9418 9419// addressBlock: dce_dc_dio_dig4_dispdec 9420// base address: 0x1000 9421#define mmDIG4_DIG_FE_CNTL 0x2468 9422#define mmDIG4_DIG_FE_CNTL_BASE_IDX 2 9423#define mmDIG4_DIG_OUTPUT_CRC_CNTL 0x2469 9424#define mmDIG4_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9425#define mmDIG4_DIG_OUTPUT_CRC_RESULT 0x246a 9426#define mmDIG4_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9427#define mmDIG4_DIG_CLOCK_PATTERN 0x246b 9428#define mmDIG4_DIG_CLOCK_PATTERN_BASE_IDX 2 9429#define mmDIG4_DIG_TEST_PATTERN 0x246c 9430#define mmDIG4_DIG_TEST_PATTERN_BASE_IDX 2 9431#define mmDIG4_DIG_RANDOM_PATTERN_SEED 0x246d 9432#define mmDIG4_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9433#define mmDIG4_DIG_FIFO_STATUS 0x246e 9434#define mmDIG4_DIG_FIFO_STATUS_BASE_IDX 2 9435#define mmDIG4_HDMI_CONTROL 0x2471 9436#define mmDIG4_HDMI_CONTROL_BASE_IDX 2 9437#define mmDIG4_HDMI_STATUS 0x2472 9438#define mmDIG4_HDMI_STATUS_BASE_IDX 2 9439#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL 0x2473 9440#define mmDIG4_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9441#define mmDIG4_HDMI_ACR_PACKET_CONTROL 0x2474 9442#define mmDIG4_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9443#define mmDIG4_HDMI_VBI_PACKET_CONTROL 0x2475 9444#define mmDIG4_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9445#define mmDIG4_HDMI_INFOFRAME_CONTROL0 0x2476 9446#define mmDIG4_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9447#define mmDIG4_HDMI_INFOFRAME_CONTROL1 0x2477 9448#define mmDIG4_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9449#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0 0x2478 9450#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9451#define mmDIG4_AFMT_INTERRUPT_STATUS 0x2479 9452#define mmDIG4_AFMT_INTERRUPT_STATUS_BASE_IDX 2 9453#define mmDIG4_HDMI_GC 0x247b 9454#define mmDIG4_HDMI_GC_BASE_IDX 2 9455#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2 0x247c 9456#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 9457#define mmDIG4_AFMT_ISRC1_0 0x247d 9458#define mmDIG4_AFMT_ISRC1_0_BASE_IDX 2 9459#define mmDIG4_AFMT_ISRC1_1 0x247e 9460#define mmDIG4_AFMT_ISRC1_1_BASE_IDX 2 9461#define mmDIG4_AFMT_ISRC1_2 0x247f 9462#define mmDIG4_AFMT_ISRC1_2_BASE_IDX 2 9463#define mmDIG4_AFMT_ISRC1_3 0x2480 9464#define mmDIG4_AFMT_ISRC1_3_BASE_IDX 2 9465#define mmDIG4_AFMT_ISRC1_4 0x2481 9466#define mmDIG4_AFMT_ISRC1_4_BASE_IDX 2 9467#define mmDIG4_AFMT_ISRC2_0 0x2482 9468#define mmDIG4_AFMT_ISRC2_0_BASE_IDX 2 9469#define mmDIG4_AFMT_ISRC2_1 0x2483 9470#define mmDIG4_AFMT_ISRC2_1_BASE_IDX 2 9471#define mmDIG4_AFMT_ISRC2_2 0x2484 9472#define mmDIG4_AFMT_ISRC2_2_BASE_IDX 2 9473#define mmDIG4_AFMT_ISRC2_3 0x2485 9474#define mmDIG4_AFMT_ISRC2_3_BASE_IDX 2 9475#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2 0x2486 9476#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9477#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3 0x2487 9478#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9479#define mmDIG4_HDMI_DB_CONTROL 0x2488 9480#define mmDIG4_HDMI_DB_CONTROL_BASE_IDX 2 9481#define mmDIG4_AFMT_MPEG_INFO0 0x248a 9482#define mmDIG4_AFMT_MPEG_INFO0_BASE_IDX 2 9483#define mmDIG4_AFMT_MPEG_INFO1 0x248b 9484#define mmDIG4_AFMT_MPEG_INFO1_BASE_IDX 2 9485#define mmDIG4_AFMT_GENERIC_HDR 0x248c 9486#define mmDIG4_AFMT_GENERIC_HDR_BASE_IDX 2 9487#define mmDIG4_AFMT_GENERIC_0 0x248d 9488#define mmDIG4_AFMT_GENERIC_0_BASE_IDX 2 9489#define mmDIG4_AFMT_GENERIC_1 0x248e 9490#define mmDIG4_AFMT_GENERIC_1_BASE_IDX 2 9491#define mmDIG4_AFMT_GENERIC_2 0x248f 9492#define mmDIG4_AFMT_GENERIC_2_BASE_IDX 2 9493#define mmDIG4_AFMT_GENERIC_3 0x2490 9494#define mmDIG4_AFMT_GENERIC_3_BASE_IDX 2 9495#define mmDIG4_AFMT_GENERIC_4 0x2491 9496#define mmDIG4_AFMT_GENERIC_4_BASE_IDX 2 9497#define mmDIG4_AFMT_GENERIC_5 0x2492 9498#define mmDIG4_AFMT_GENERIC_5_BASE_IDX 2 9499#define mmDIG4_AFMT_GENERIC_6 0x2493 9500#define mmDIG4_AFMT_GENERIC_6_BASE_IDX 2 9501#define mmDIG4_AFMT_GENERIC_7 0x2494 9502#define mmDIG4_AFMT_GENERIC_7_BASE_IDX 2 9503#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1 0x2495 9504#define mmDIG4_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9505#define mmDIG4_HDMI_ACR_32_0 0x2496 9506#define mmDIG4_HDMI_ACR_32_0_BASE_IDX 2 9507#define mmDIG4_HDMI_ACR_32_1 0x2497 9508#define mmDIG4_HDMI_ACR_32_1_BASE_IDX 2 9509#define mmDIG4_HDMI_ACR_44_0 0x2498 9510#define mmDIG4_HDMI_ACR_44_0_BASE_IDX 2 9511#define mmDIG4_HDMI_ACR_44_1 0x2499 9512#define mmDIG4_HDMI_ACR_44_1_BASE_IDX 2 9513#define mmDIG4_HDMI_ACR_48_0 0x249a 9514#define mmDIG4_HDMI_ACR_48_0_BASE_IDX 2 9515#define mmDIG4_HDMI_ACR_48_1 0x249b 9516#define mmDIG4_HDMI_ACR_48_1_BASE_IDX 2 9517#define mmDIG4_HDMI_ACR_STATUS_0 0x249c 9518#define mmDIG4_HDMI_ACR_STATUS_0_BASE_IDX 2 9519#define mmDIG4_HDMI_ACR_STATUS_1 0x249d 9520#define mmDIG4_HDMI_ACR_STATUS_1_BASE_IDX 2 9521#define mmDIG4_AFMT_AUDIO_INFO0 0x249e 9522#define mmDIG4_AFMT_AUDIO_INFO0_BASE_IDX 2 9523#define mmDIG4_AFMT_AUDIO_INFO1 0x249f 9524#define mmDIG4_AFMT_AUDIO_INFO1_BASE_IDX 2 9525#define mmDIG4_AFMT_60958_0 0x24a0 9526#define mmDIG4_AFMT_60958_0_BASE_IDX 2 9527#define mmDIG4_AFMT_60958_1 0x24a1 9528#define mmDIG4_AFMT_60958_1_BASE_IDX 2 9529#define mmDIG4_AFMT_AUDIO_CRC_CONTROL 0x24a2 9530#define mmDIG4_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 9531#define mmDIG4_AFMT_RAMP_CONTROL0 0x24a3 9532#define mmDIG4_AFMT_RAMP_CONTROL0_BASE_IDX 2 9533#define mmDIG4_AFMT_RAMP_CONTROL1 0x24a4 9534#define mmDIG4_AFMT_RAMP_CONTROL1_BASE_IDX 2 9535#define mmDIG4_AFMT_RAMP_CONTROL2 0x24a5 9536#define mmDIG4_AFMT_RAMP_CONTROL2_BASE_IDX 2 9537#define mmDIG4_AFMT_RAMP_CONTROL3 0x24a6 9538#define mmDIG4_AFMT_RAMP_CONTROL3_BASE_IDX 2 9539#define mmDIG4_AFMT_60958_2 0x24a7 9540#define mmDIG4_AFMT_60958_2_BASE_IDX 2 9541#define mmDIG4_AFMT_AUDIO_CRC_RESULT 0x24a8 9542#define mmDIG4_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 9543#define mmDIG4_AFMT_STATUS 0x24a9 9544#define mmDIG4_AFMT_STATUS_BASE_IDX 2 9545#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL 0x24aa 9546#define mmDIG4_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 9547#define mmDIG4_AFMT_VBI_PACKET_CONTROL 0x24ab 9548#define mmDIG4_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 9549#define mmDIG4_AFMT_INFOFRAME_CONTROL0 0x24ac 9550#define mmDIG4_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 9551#define mmDIG4_AFMT_AUDIO_SRC_CONTROL 0x24ad 9552#define mmDIG4_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 9553#define mmDIG4_DIG_BE_CNTL 0x24af 9554#define mmDIG4_DIG_BE_CNTL_BASE_IDX 2 9555#define mmDIG4_DIG_BE_EN_CNTL 0x24b0 9556#define mmDIG4_DIG_BE_EN_CNTL_BASE_IDX 2 9557#define mmDIG4_TMDS_CNTL 0x24d3 9558#define mmDIG4_TMDS_CNTL_BASE_IDX 2 9559#define mmDIG4_TMDS_CONTROL_CHAR 0x24d4 9560#define mmDIG4_TMDS_CONTROL_CHAR_BASE_IDX 2 9561#define mmDIG4_TMDS_CONTROL0_FEEDBACK 0x24d5 9562#define mmDIG4_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9563#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL 0x24d6 9564#define mmDIG4_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9565#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1 0x24d7 9566#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9567#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3 0x24d8 9568#define mmDIG4_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9569#define mmDIG4_TMDS_CTL_BITS 0x24da 9570#define mmDIG4_TMDS_CTL_BITS_BASE_IDX 2 9571#define mmDIG4_TMDS_DCBALANCER_CONTROL 0x24db 9572#define mmDIG4_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9573#define mmDIG4_TMDS_CTL0_1_GEN_CNTL 0x24dd 9574#define mmDIG4_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9575#define mmDIG4_TMDS_CTL2_3_GEN_CNTL 0x24de 9576#define mmDIG4_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9577#define mmDIG4_DIG_VERSION 0x24e0 9578#define mmDIG4_DIG_VERSION_BASE_IDX 2 9579#define mmDIG4_DIG_LANE_ENABLE 0x24e1 9580#define mmDIG4_DIG_LANE_ENABLE_BASE_IDX 2 9581#define mmDIG4_AFMT_CNTL 0x24e6 9582#define mmDIG4_AFMT_CNTL_BASE_IDX 2 9583#define mmDIG4_AFMT_VBI_PACKET_CONTROL1 0x24e7 9584#define mmDIG4_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 9585 9586 9587// addressBlock: dce_dc_dio_dp4_dispdec 9588// base address: 0x1000 9589#define mmDP4_DP_LINK_CNTL 0x2508 9590#define mmDP4_DP_LINK_CNTL_BASE_IDX 2 9591#define mmDP4_DP_PIXEL_FORMAT 0x2509 9592#define mmDP4_DP_PIXEL_FORMAT_BASE_IDX 2 9593#define mmDP4_DP_MSA_COLORIMETRY 0x250a 9594#define mmDP4_DP_MSA_COLORIMETRY_BASE_IDX 2 9595#define mmDP4_DP_CONFIG 0x250b 9596#define mmDP4_DP_CONFIG_BASE_IDX 2 9597#define mmDP4_DP_VID_STREAM_CNTL 0x250c 9598#define mmDP4_DP_VID_STREAM_CNTL_BASE_IDX 2 9599#define mmDP4_DP_STEER_FIFO 0x250d 9600#define mmDP4_DP_STEER_FIFO_BASE_IDX 2 9601#define mmDP4_DP_MSA_MISC 0x250e 9602#define mmDP4_DP_MSA_MISC_BASE_IDX 2 9603#define mmDP4_DP_VID_TIMING 0x2510 9604#define mmDP4_DP_VID_TIMING_BASE_IDX 2 9605#define mmDP4_DP_VID_N 0x2511 9606#define mmDP4_DP_VID_N_BASE_IDX 2 9607#define mmDP4_DP_VID_M 0x2512 9608#define mmDP4_DP_VID_M_BASE_IDX 2 9609#define mmDP4_DP_LINK_FRAMING_CNTL 0x2513 9610#define mmDP4_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9611#define mmDP4_DP_HBR2_EYE_PATTERN 0x2514 9612#define mmDP4_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9613#define mmDP4_DP_VID_MSA_VBID 0x2515 9614#define mmDP4_DP_VID_MSA_VBID_BASE_IDX 2 9615#define mmDP4_DP_VID_INTERRUPT_CNTL 0x2516 9616#define mmDP4_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9617#define mmDP4_DP_DPHY_CNTL 0x2517 9618#define mmDP4_DP_DPHY_CNTL_BASE_IDX 2 9619#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL 0x2518 9620#define mmDP4_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9621#define mmDP4_DP_DPHY_SYM0 0x2519 9622#define mmDP4_DP_DPHY_SYM0_BASE_IDX 2 9623#define mmDP4_DP_DPHY_SYM1 0x251a 9624#define mmDP4_DP_DPHY_SYM1_BASE_IDX 2 9625#define mmDP4_DP_DPHY_SYM2 0x251b 9626#define mmDP4_DP_DPHY_SYM2_BASE_IDX 2 9627#define mmDP4_DP_DPHY_8B10B_CNTL 0x251c 9628#define mmDP4_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9629#define mmDP4_DP_DPHY_PRBS_CNTL 0x251d 9630#define mmDP4_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9631#define mmDP4_DP_DPHY_SCRAM_CNTL 0x251e 9632#define mmDP4_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9633#define mmDP4_DP_DPHY_CRC_EN 0x251f 9634#define mmDP4_DP_DPHY_CRC_EN_BASE_IDX 2 9635#define mmDP4_DP_DPHY_CRC_CNTL 0x2520 9636#define mmDP4_DP_DPHY_CRC_CNTL_BASE_IDX 2 9637#define mmDP4_DP_DPHY_CRC_RESULT 0x2521 9638#define mmDP4_DP_DPHY_CRC_RESULT_BASE_IDX 2 9639#define mmDP4_DP_DPHY_CRC_MST_CNTL 0x2522 9640#define mmDP4_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9641#define mmDP4_DP_DPHY_CRC_MST_STATUS 0x2523 9642#define mmDP4_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9643#define mmDP4_DP_DPHY_FAST_TRAINING 0x2524 9644#define mmDP4_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9645#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS 0x2525 9646#define mmDP4_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9647#define mmDP4_DP_SEC_CNTL 0x252b 9648#define mmDP4_DP_SEC_CNTL_BASE_IDX 2 9649#define mmDP4_DP_SEC_CNTL1 0x252c 9650#define mmDP4_DP_SEC_CNTL1_BASE_IDX 2 9651#define mmDP4_DP_SEC_FRAMING1 0x252d 9652#define mmDP4_DP_SEC_FRAMING1_BASE_IDX 2 9653#define mmDP4_DP_SEC_FRAMING2 0x252e 9654#define mmDP4_DP_SEC_FRAMING2_BASE_IDX 2 9655#define mmDP4_DP_SEC_FRAMING3 0x252f 9656#define mmDP4_DP_SEC_FRAMING3_BASE_IDX 2 9657#define mmDP4_DP_SEC_FRAMING4 0x2530 9658#define mmDP4_DP_SEC_FRAMING4_BASE_IDX 2 9659#define mmDP4_DP_SEC_AUD_N 0x2531 9660#define mmDP4_DP_SEC_AUD_N_BASE_IDX 2 9661#define mmDP4_DP_SEC_AUD_N_READBACK 0x2532 9662#define mmDP4_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9663#define mmDP4_DP_SEC_AUD_M 0x2533 9664#define mmDP4_DP_SEC_AUD_M_BASE_IDX 2 9665#define mmDP4_DP_SEC_AUD_M_READBACK 0x2534 9666#define mmDP4_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9667#define mmDP4_DP_SEC_TIMESTAMP 0x2535 9668#define mmDP4_DP_SEC_TIMESTAMP_BASE_IDX 2 9669#define mmDP4_DP_SEC_PACKET_CNTL 0x2536 9670#define mmDP4_DP_SEC_PACKET_CNTL_BASE_IDX 2 9671#define mmDP4_DP_MSE_RATE_CNTL 0x2537 9672#define mmDP4_DP_MSE_RATE_CNTL_BASE_IDX 2 9673#define mmDP4_DP_MSE_RATE_UPDATE 0x2539 9674#define mmDP4_DP_MSE_RATE_UPDATE_BASE_IDX 2 9675#define mmDP4_DP_MSE_SAT0 0x253a 9676#define mmDP4_DP_MSE_SAT0_BASE_IDX 2 9677#define mmDP4_DP_MSE_SAT1 0x253b 9678#define mmDP4_DP_MSE_SAT1_BASE_IDX 2 9679#define mmDP4_DP_MSE_SAT2 0x253c 9680#define mmDP4_DP_MSE_SAT2_BASE_IDX 2 9681#define mmDP4_DP_MSE_SAT_UPDATE 0x253d 9682#define mmDP4_DP_MSE_SAT_UPDATE_BASE_IDX 2 9683#define mmDP4_DP_MSE_LINK_TIMING 0x253e 9684#define mmDP4_DP_MSE_LINK_TIMING_BASE_IDX 2 9685#define mmDP4_DP_MSE_MISC_CNTL 0x253f 9686#define mmDP4_DP_MSE_MISC_CNTL_BASE_IDX 2 9687#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x2544 9688#define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9689#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL 0x2545 9690#define mmDP4_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 9691#define mmDP4_DP_MSE_SAT0_STATUS 0x2547 9692#define mmDP4_DP_MSE_SAT0_STATUS_BASE_IDX 2 9693#define mmDP4_DP_MSE_SAT1_STATUS 0x2548 9694#define mmDP4_DP_MSE_SAT1_STATUS_BASE_IDX 2 9695#define mmDP4_DP_MSE_SAT2_STATUS 0x2549 9696#define mmDP4_DP_MSE_SAT2_STATUS_BASE_IDX 2 9697#define mmDP4_DP_MSA_TIMING_PARAM1 0x254c 9698#define mmDP4_DP_MSA_TIMING_PARAM1_BASE_IDX 2 9699#define mmDP4_DP_MSA_TIMING_PARAM2 0x254d 9700#define mmDP4_DP_MSA_TIMING_PARAM2_BASE_IDX 2 9701#define mmDP4_DP_MSA_TIMING_PARAM3 0x254e 9702#define mmDP4_DP_MSA_TIMING_PARAM3_BASE_IDX 2 9703#define mmDP4_DP_MSA_TIMING_PARAM4 0x254f 9704#define mmDP4_DP_MSA_TIMING_PARAM4_BASE_IDX 2 9705#define mmDP4_DP_MSO_CNTL 0x2550 9706#define mmDP4_DP_MSO_CNTL_BASE_IDX 2 9707#define mmDP4_DP_MSO_CNTL1 0x2551 9708#define mmDP4_DP_MSO_CNTL1_BASE_IDX 2 9709#define mmDP4_DP_DSC_CNTL 0x2552 9710#define mmDP4_DP_DSC_CNTL_BASE_IDX 2 9711#define mmDP4_DP_SEC_CNTL2 0x2553 9712#define mmDP4_DP_SEC_CNTL2_BASE_IDX 2 9713#define mmDP4_DP_SEC_CNTL3 0x2554 9714#define mmDP4_DP_SEC_CNTL3_BASE_IDX 2 9715#define mmDP4_DP_SEC_CNTL4 0x2555 9716#define mmDP4_DP_SEC_CNTL4_BASE_IDX 2 9717#define mmDP4_DP_SEC_CNTL5 0x2556 9718#define mmDP4_DP_SEC_CNTL5_BASE_IDX 2 9719#define mmDP4_DP_SEC_CNTL6 0x2557 9720#define mmDP4_DP_SEC_CNTL6_BASE_IDX 2 9721#define mmDP4_DP_SEC_CNTL7 0x2558 9722#define mmDP4_DP_SEC_CNTL7_BASE_IDX 2 9723#define mmDP4_DP_DB_CNTL 0x2559 9724#define mmDP4_DP_DB_CNTL_BASE_IDX 2 9725#define mmDP4_DP_MSA_VBID_MISC 0x255a 9726#define mmDP4_DP_MSA_VBID_MISC_BASE_IDX 2 9727 9728 9729// addressBlock: dce_dc_dio_dig5_dispdec 9730// base address: 0x1400 9731#define mmDIG5_DIG_FE_CNTL 0x2568 9732#define mmDIG5_DIG_FE_CNTL_BASE_IDX 2 9733#define mmDIG5_DIG_OUTPUT_CRC_CNTL 0x2569 9734#define mmDIG5_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 9735#define mmDIG5_DIG_OUTPUT_CRC_RESULT 0x256a 9736#define mmDIG5_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 9737#define mmDIG5_DIG_CLOCK_PATTERN 0x256b 9738#define mmDIG5_DIG_CLOCK_PATTERN_BASE_IDX 2 9739#define mmDIG5_DIG_TEST_PATTERN 0x256c 9740#define mmDIG5_DIG_TEST_PATTERN_BASE_IDX 2 9741#define mmDIG5_DIG_RANDOM_PATTERN_SEED 0x256d 9742#define mmDIG5_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 9743#define mmDIG5_DIG_FIFO_STATUS 0x256e 9744#define mmDIG5_DIG_FIFO_STATUS_BASE_IDX 2 9745#define mmDIG5_HDMI_CONTROL 0x2571 9746#define mmDIG5_HDMI_CONTROL_BASE_IDX 2 9747#define mmDIG5_HDMI_STATUS 0x2572 9748#define mmDIG5_HDMI_STATUS_BASE_IDX 2 9749#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL 0x2573 9750#define mmDIG5_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 9751#define mmDIG5_HDMI_ACR_PACKET_CONTROL 0x2574 9752#define mmDIG5_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 9753#define mmDIG5_HDMI_VBI_PACKET_CONTROL 0x2575 9754#define mmDIG5_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 9755#define mmDIG5_HDMI_INFOFRAME_CONTROL0 0x2576 9756#define mmDIG5_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 9757#define mmDIG5_HDMI_INFOFRAME_CONTROL1 0x2577 9758#define mmDIG5_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 9759#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0 0x2578 9760#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 9761#define mmDIG5_AFMT_INTERRUPT_STATUS 0x2579 9762#define mmDIG5_AFMT_INTERRUPT_STATUS_BASE_IDX 2 9763#define mmDIG5_HDMI_GC 0x257b 9764#define mmDIG5_HDMI_GC_BASE_IDX 2 9765#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2 0x257c 9766#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 9767#define mmDIG5_AFMT_ISRC1_0 0x257d 9768#define mmDIG5_AFMT_ISRC1_0_BASE_IDX 2 9769#define mmDIG5_AFMT_ISRC1_1 0x257e 9770#define mmDIG5_AFMT_ISRC1_1_BASE_IDX 2 9771#define mmDIG5_AFMT_ISRC1_2 0x257f 9772#define mmDIG5_AFMT_ISRC1_2_BASE_IDX 2 9773#define mmDIG5_AFMT_ISRC1_3 0x2580 9774#define mmDIG5_AFMT_ISRC1_3_BASE_IDX 2 9775#define mmDIG5_AFMT_ISRC1_4 0x2581 9776#define mmDIG5_AFMT_ISRC1_4_BASE_IDX 2 9777#define mmDIG5_AFMT_ISRC2_0 0x2582 9778#define mmDIG5_AFMT_ISRC2_0_BASE_IDX 2 9779#define mmDIG5_AFMT_ISRC2_1 0x2583 9780#define mmDIG5_AFMT_ISRC2_1_BASE_IDX 2 9781#define mmDIG5_AFMT_ISRC2_2 0x2584 9782#define mmDIG5_AFMT_ISRC2_2_BASE_IDX 2 9783#define mmDIG5_AFMT_ISRC2_3 0x2585 9784#define mmDIG5_AFMT_ISRC2_3_BASE_IDX 2 9785#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2 0x2586 9786#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 9787#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3 0x2587 9788#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 9789#define mmDIG5_HDMI_DB_CONTROL 0x2588 9790#define mmDIG5_HDMI_DB_CONTROL_BASE_IDX 2 9791#define mmDIG5_AFMT_MPEG_INFO0 0x258a 9792#define mmDIG5_AFMT_MPEG_INFO0_BASE_IDX 2 9793#define mmDIG5_AFMT_MPEG_INFO1 0x258b 9794#define mmDIG5_AFMT_MPEG_INFO1_BASE_IDX 2 9795#define mmDIG5_AFMT_GENERIC_HDR 0x258c 9796#define mmDIG5_AFMT_GENERIC_HDR_BASE_IDX 2 9797#define mmDIG5_AFMT_GENERIC_0 0x258d 9798#define mmDIG5_AFMT_GENERIC_0_BASE_IDX 2 9799#define mmDIG5_AFMT_GENERIC_1 0x258e 9800#define mmDIG5_AFMT_GENERIC_1_BASE_IDX 2 9801#define mmDIG5_AFMT_GENERIC_2 0x258f 9802#define mmDIG5_AFMT_GENERIC_2_BASE_IDX 2 9803#define mmDIG5_AFMT_GENERIC_3 0x2590 9804#define mmDIG5_AFMT_GENERIC_3_BASE_IDX 2 9805#define mmDIG5_AFMT_GENERIC_4 0x2591 9806#define mmDIG5_AFMT_GENERIC_4_BASE_IDX 2 9807#define mmDIG5_AFMT_GENERIC_5 0x2592 9808#define mmDIG5_AFMT_GENERIC_5_BASE_IDX 2 9809#define mmDIG5_AFMT_GENERIC_6 0x2593 9810#define mmDIG5_AFMT_GENERIC_6_BASE_IDX 2 9811#define mmDIG5_AFMT_GENERIC_7 0x2594 9812#define mmDIG5_AFMT_GENERIC_7_BASE_IDX 2 9813#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1 0x2595 9814#define mmDIG5_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 9815#define mmDIG5_HDMI_ACR_32_0 0x2596 9816#define mmDIG5_HDMI_ACR_32_0_BASE_IDX 2 9817#define mmDIG5_HDMI_ACR_32_1 0x2597 9818#define mmDIG5_HDMI_ACR_32_1_BASE_IDX 2 9819#define mmDIG5_HDMI_ACR_44_0 0x2598 9820#define mmDIG5_HDMI_ACR_44_0_BASE_IDX 2 9821#define mmDIG5_HDMI_ACR_44_1 0x2599 9822#define mmDIG5_HDMI_ACR_44_1_BASE_IDX 2 9823#define mmDIG5_HDMI_ACR_48_0 0x259a 9824#define mmDIG5_HDMI_ACR_48_0_BASE_IDX 2 9825#define mmDIG5_HDMI_ACR_48_1 0x259b 9826#define mmDIG5_HDMI_ACR_48_1_BASE_IDX 2 9827#define mmDIG5_HDMI_ACR_STATUS_0 0x259c 9828#define mmDIG5_HDMI_ACR_STATUS_0_BASE_IDX 2 9829#define mmDIG5_HDMI_ACR_STATUS_1 0x259d 9830#define mmDIG5_HDMI_ACR_STATUS_1_BASE_IDX 2 9831#define mmDIG5_AFMT_AUDIO_INFO0 0x259e 9832#define mmDIG5_AFMT_AUDIO_INFO0_BASE_IDX 2 9833#define mmDIG5_AFMT_AUDIO_INFO1 0x259f 9834#define mmDIG5_AFMT_AUDIO_INFO1_BASE_IDX 2 9835#define mmDIG5_AFMT_60958_0 0x25a0 9836#define mmDIG5_AFMT_60958_0_BASE_IDX 2 9837#define mmDIG5_AFMT_60958_1 0x25a1 9838#define mmDIG5_AFMT_60958_1_BASE_IDX 2 9839#define mmDIG5_AFMT_AUDIO_CRC_CONTROL 0x25a2 9840#define mmDIG5_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 9841#define mmDIG5_AFMT_RAMP_CONTROL0 0x25a3 9842#define mmDIG5_AFMT_RAMP_CONTROL0_BASE_IDX 2 9843#define mmDIG5_AFMT_RAMP_CONTROL1 0x25a4 9844#define mmDIG5_AFMT_RAMP_CONTROL1_BASE_IDX 2 9845#define mmDIG5_AFMT_RAMP_CONTROL2 0x25a5 9846#define mmDIG5_AFMT_RAMP_CONTROL2_BASE_IDX 2 9847#define mmDIG5_AFMT_RAMP_CONTROL3 0x25a6 9848#define mmDIG5_AFMT_RAMP_CONTROL3_BASE_IDX 2 9849#define mmDIG5_AFMT_60958_2 0x25a7 9850#define mmDIG5_AFMT_60958_2_BASE_IDX 2 9851#define mmDIG5_AFMT_AUDIO_CRC_RESULT 0x25a8 9852#define mmDIG5_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 9853#define mmDIG5_AFMT_STATUS 0x25a9 9854#define mmDIG5_AFMT_STATUS_BASE_IDX 2 9855#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL 0x25aa 9856#define mmDIG5_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 9857#define mmDIG5_AFMT_VBI_PACKET_CONTROL 0x25ab 9858#define mmDIG5_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 9859#define mmDIG5_AFMT_INFOFRAME_CONTROL0 0x25ac 9860#define mmDIG5_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 9861#define mmDIG5_AFMT_AUDIO_SRC_CONTROL 0x25ad 9862#define mmDIG5_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 9863#define mmDIG5_DIG_BE_CNTL 0x25af 9864#define mmDIG5_DIG_BE_CNTL_BASE_IDX 2 9865#define mmDIG5_DIG_BE_EN_CNTL 0x25b0 9866#define mmDIG5_DIG_BE_EN_CNTL_BASE_IDX 2 9867#define mmDIG5_TMDS_CNTL 0x25d3 9868#define mmDIG5_TMDS_CNTL_BASE_IDX 2 9869#define mmDIG5_TMDS_CONTROL_CHAR 0x25d4 9870#define mmDIG5_TMDS_CONTROL_CHAR_BASE_IDX 2 9871#define mmDIG5_TMDS_CONTROL0_FEEDBACK 0x25d5 9872#define mmDIG5_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 9873#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL 0x25d6 9874#define mmDIG5_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 9875#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1 0x25d7 9876#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 9877#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3 0x25d8 9878#define mmDIG5_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 9879#define mmDIG5_TMDS_CTL_BITS 0x25da 9880#define mmDIG5_TMDS_CTL_BITS_BASE_IDX 2 9881#define mmDIG5_TMDS_DCBALANCER_CONTROL 0x25db 9882#define mmDIG5_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 9883#define mmDIG5_TMDS_CTL0_1_GEN_CNTL 0x25dd 9884#define mmDIG5_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 9885#define mmDIG5_TMDS_CTL2_3_GEN_CNTL 0x25de 9886#define mmDIG5_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 9887#define mmDIG5_DIG_VERSION 0x25e0 9888#define mmDIG5_DIG_VERSION_BASE_IDX 2 9889#define mmDIG5_DIG_LANE_ENABLE 0x25e1 9890#define mmDIG5_DIG_LANE_ENABLE_BASE_IDX 2 9891#define mmDIG5_AFMT_CNTL 0x25e6 9892#define mmDIG5_AFMT_CNTL_BASE_IDX 2 9893#define mmDIG5_AFMT_VBI_PACKET_CONTROL1 0x25e7 9894#define mmDIG5_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 9895 9896 9897// addressBlock: dce_dc_dio_dp5_dispdec 9898// base address: 0x1400 9899#define mmDP5_DP_LINK_CNTL 0x2608 9900#define mmDP5_DP_LINK_CNTL_BASE_IDX 2 9901#define mmDP5_DP_PIXEL_FORMAT 0x2609 9902#define mmDP5_DP_PIXEL_FORMAT_BASE_IDX 2 9903#define mmDP5_DP_MSA_COLORIMETRY 0x260a 9904#define mmDP5_DP_MSA_COLORIMETRY_BASE_IDX 2 9905#define mmDP5_DP_CONFIG 0x260b 9906#define mmDP5_DP_CONFIG_BASE_IDX 2 9907#define mmDP5_DP_VID_STREAM_CNTL 0x260c 9908#define mmDP5_DP_VID_STREAM_CNTL_BASE_IDX 2 9909#define mmDP5_DP_STEER_FIFO 0x260d 9910#define mmDP5_DP_STEER_FIFO_BASE_IDX 2 9911#define mmDP5_DP_MSA_MISC 0x260e 9912#define mmDP5_DP_MSA_MISC_BASE_IDX 2 9913#define mmDP5_DP_VID_TIMING 0x2610 9914#define mmDP5_DP_VID_TIMING_BASE_IDX 2 9915#define mmDP5_DP_VID_N 0x2611 9916#define mmDP5_DP_VID_N_BASE_IDX 2 9917#define mmDP5_DP_VID_M 0x2612 9918#define mmDP5_DP_VID_M_BASE_IDX 2 9919#define mmDP5_DP_LINK_FRAMING_CNTL 0x2613 9920#define mmDP5_DP_LINK_FRAMING_CNTL_BASE_IDX 2 9921#define mmDP5_DP_HBR2_EYE_PATTERN 0x2614 9922#define mmDP5_DP_HBR2_EYE_PATTERN_BASE_IDX 2 9923#define mmDP5_DP_VID_MSA_VBID 0x2615 9924#define mmDP5_DP_VID_MSA_VBID_BASE_IDX 2 9925#define mmDP5_DP_VID_INTERRUPT_CNTL 0x2616 9926#define mmDP5_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 9927#define mmDP5_DP_DPHY_CNTL 0x2617 9928#define mmDP5_DP_DPHY_CNTL_BASE_IDX 2 9929#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL 0x2618 9930#define mmDP5_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 9931#define mmDP5_DP_DPHY_SYM0 0x2619 9932#define mmDP5_DP_DPHY_SYM0_BASE_IDX 2 9933#define mmDP5_DP_DPHY_SYM1 0x261a 9934#define mmDP5_DP_DPHY_SYM1_BASE_IDX 2 9935#define mmDP5_DP_DPHY_SYM2 0x261b 9936#define mmDP5_DP_DPHY_SYM2_BASE_IDX 2 9937#define mmDP5_DP_DPHY_8B10B_CNTL 0x261c 9938#define mmDP5_DP_DPHY_8B10B_CNTL_BASE_IDX 2 9939#define mmDP5_DP_DPHY_PRBS_CNTL 0x261d 9940#define mmDP5_DP_DPHY_PRBS_CNTL_BASE_IDX 2 9941#define mmDP5_DP_DPHY_SCRAM_CNTL 0x261e 9942#define mmDP5_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 9943#define mmDP5_DP_DPHY_CRC_EN 0x261f 9944#define mmDP5_DP_DPHY_CRC_EN_BASE_IDX 2 9945#define mmDP5_DP_DPHY_CRC_CNTL 0x2620 9946#define mmDP5_DP_DPHY_CRC_CNTL_BASE_IDX 2 9947#define mmDP5_DP_DPHY_CRC_RESULT 0x2621 9948#define mmDP5_DP_DPHY_CRC_RESULT_BASE_IDX 2 9949#define mmDP5_DP_DPHY_CRC_MST_CNTL 0x2622 9950#define mmDP5_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 9951#define mmDP5_DP_DPHY_CRC_MST_STATUS 0x2623 9952#define mmDP5_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 9953#define mmDP5_DP_DPHY_FAST_TRAINING 0x2624 9954#define mmDP5_DP_DPHY_FAST_TRAINING_BASE_IDX 2 9955#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS 0x2625 9956#define mmDP5_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 9957#define mmDP5_DP_SEC_CNTL 0x262b 9958#define mmDP5_DP_SEC_CNTL_BASE_IDX 2 9959#define mmDP5_DP_SEC_CNTL1 0x262c 9960#define mmDP5_DP_SEC_CNTL1_BASE_IDX 2 9961#define mmDP5_DP_SEC_FRAMING1 0x262d 9962#define mmDP5_DP_SEC_FRAMING1_BASE_IDX 2 9963#define mmDP5_DP_SEC_FRAMING2 0x262e 9964#define mmDP5_DP_SEC_FRAMING2_BASE_IDX 2 9965#define mmDP5_DP_SEC_FRAMING3 0x262f 9966#define mmDP5_DP_SEC_FRAMING3_BASE_IDX 2 9967#define mmDP5_DP_SEC_FRAMING4 0x2630 9968#define mmDP5_DP_SEC_FRAMING4_BASE_IDX 2 9969#define mmDP5_DP_SEC_AUD_N 0x2631 9970#define mmDP5_DP_SEC_AUD_N_BASE_IDX 2 9971#define mmDP5_DP_SEC_AUD_N_READBACK 0x2632 9972#define mmDP5_DP_SEC_AUD_N_READBACK_BASE_IDX 2 9973#define mmDP5_DP_SEC_AUD_M 0x2633 9974#define mmDP5_DP_SEC_AUD_M_BASE_IDX 2 9975#define mmDP5_DP_SEC_AUD_M_READBACK 0x2634 9976#define mmDP5_DP_SEC_AUD_M_READBACK_BASE_IDX 2 9977#define mmDP5_DP_SEC_TIMESTAMP 0x2635 9978#define mmDP5_DP_SEC_TIMESTAMP_BASE_IDX 2 9979#define mmDP5_DP_SEC_PACKET_CNTL 0x2636 9980#define mmDP5_DP_SEC_PACKET_CNTL_BASE_IDX 2 9981#define mmDP5_DP_MSE_RATE_CNTL 0x2637 9982#define mmDP5_DP_MSE_RATE_CNTL_BASE_IDX 2 9983#define mmDP5_DP_MSE_RATE_UPDATE 0x2639 9984#define mmDP5_DP_MSE_RATE_UPDATE_BASE_IDX 2 9985#define mmDP5_DP_MSE_SAT0 0x263a 9986#define mmDP5_DP_MSE_SAT0_BASE_IDX 2 9987#define mmDP5_DP_MSE_SAT1 0x263b 9988#define mmDP5_DP_MSE_SAT1_BASE_IDX 2 9989#define mmDP5_DP_MSE_SAT2 0x263c 9990#define mmDP5_DP_MSE_SAT2_BASE_IDX 2 9991#define mmDP5_DP_MSE_SAT_UPDATE 0x263d 9992#define mmDP5_DP_MSE_SAT_UPDATE_BASE_IDX 2 9993#define mmDP5_DP_MSE_LINK_TIMING 0x263e 9994#define mmDP5_DP_MSE_LINK_TIMING_BASE_IDX 2 9995#define mmDP5_DP_MSE_MISC_CNTL 0x263f 9996#define mmDP5_DP_MSE_MISC_CNTL_BASE_IDX 2 9997#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x2644 9998#define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 9999#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL 0x2645 10000#define mmDP5_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2
10001#define mmDP5_DP_MSE_SAT0_STATUS 0x2647 10002#define mmDP5_DP_MSE_SAT0_STATUS_BASE_IDX 2 10003#define mmDP5_DP_MSE_SAT1_STATUS 0x2648 10004#define mmDP5_DP_MSE_SAT1_STATUS_BASE_IDX 2 10005#define mmDP5_DP_MSE_SAT2_STATUS 0x2649 10006#define mmDP5_DP_MSE_SAT2_STATUS_BASE_IDX 2 10007#define mmDP5_DP_MSA_TIMING_PARAM1 0x264c 10008#define mmDP5_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10009#define mmDP5_DP_MSA_TIMING_PARAM2 0x264d 10010#define mmDP5_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10011#define mmDP5_DP_MSA_TIMING_PARAM3 0x264e 10012#define mmDP5_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10013#define mmDP5_DP_MSA_TIMING_PARAM4 0x264f 10014#define mmDP5_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10015#define mmDP5_DP_MSO_CNTL 0x2650 10016#define mmDP5_DP_MSO_CNTL_BASE_IDX 2 10017#define mmDP5_DP_MSO_CNTL1 0x2651 10018#define mmDP5_DP_MSO_CNTL1_BASE_IDX 2 10019#define mmDP5_DP_DSC_CNTL 0x2652 10020#define mmDP5_DP_DSC_CNTL_BASE_IDX 2 10021#define mmDP5_DP_SEC_CNTL2 0x2653 10022#define mmDP5_DP_SEC_CNTL2_BASE_IDX 2 10023#define mmDP5_DP_SEC_CNTL3 0x2654 10024#define mmDP5_DP_SEC_CNTL3_BASE_IDX 2 10025#define mmDP5_DP_SEC_CNTL4 0x2655 10026#define mmDP5_DP_SEC_CNTL4_BASE_IDX 2 10027#define mmDP5_DP_SEC_CNTL5 0x2656 10028#define mmDP5_DP_SEC_CNTL5_BASE_IDX 2 10029#define mmDP5_DP_SEC_CNTL6 0x2657 10030#define mmDP5_DP_SEC_CNTL6_BASE_IDX 2 10031#define mmDP5_DP_SEC_CNTL7 0x2658 10032#define mmDP5_DP_SEC_CNTL7_BASE_IDX 2 10033#define mmDP5_DP_DB_CNTL 0x2659 10034#define mmDP5_DP_DB_CNTL_BASE_IDX 2 10035#define mmDP5_DP_MSA_VBID_MISC 0x265a 10036#define mmDP5_DP_MSA_VBID_MISC_BASE_IDX 2 10037 10038 10039// addressBlock: dce_dc_dio_dig6_dispdec 10040// base address: 0x1800 10041#define mmDIG6_DIG_FE_CNTL 0x2668 10042#define mmDIG6_DIG_FE_CNTL_BASE_IDX 2 10043#define mmDIG6_DIG_OUTPUT_CRC_CNTL 0x2669 10044#define mmDIG6_DIG_OUTPUT_CRC_CNTL_BASE_IDX 2 10045#define mmDIG6_DIG_OUTPUT_CRC_RESULT 0x266a 10046#define mmDIG6_DIG_OUTPUT_CRC_RESULT_BASE_IDX 2 10047#define mmDIG6_DIG_CLOCK_PATTERN 0x266b 10048#define mmDIG6_DIG_CLOCK_PATTERN_BASE_IDX 2 10049#define mmDIG6_DIG_TEST_PATTERN 0x266c 10050#define mmDIG6_DIG_TEST_PATTERN_BASE_IDX 2 10051#define mmDIG6_DIG_RANDOM_PATTERN_SEED 0x266d 10052#define mmDIG6_DIG_RANDOM_PATTERN_SEED_BASE_IDX 2 10053#define mmDIG6_DIG_FIFO_STATUS 0x266e 10054#define mmDIG6_DIG_FIFO_STATUS_BASE_IDX 2 10055#define mmDIG6_HDMI_CONTROL 0x2671 10056#define mmDIG6_HDMI_CONTROL_BASE_IDX 2 10057#define mmDIG6_HDMI_STATUS 0x2672 10058#define mmDIG6_HDMI_STATUS_BASE_IDX 2 10059#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL 0x2673 10060#define mmDIG6_HDMI_AUDIO_PACKET_CONTROL_BASE_IDX 2 10061#define mmDIG6_HDMI_ACR_PACKET_CONTROL 0x2674 10062#define mmDIG6_HDMI_ACR_PACKET_CONTROL_BASE_IDX 2 10063#define mmDIG6_HDMI_VBI_PACKET_CONTROL 0x2675 10064#define mmDIG6_HDMI_VBI_PACKET_CONTROL_BASE_IDX 2 10065#define mmDIG6_HDMI_INFOFRAME_CONTROL0 0x2676 10066#define mmDIG6_HDMI_INFOFRAME_CONTROL0_BASE_IDX 2 10067#define mmDIG6_HDMI_INFOFRAME_CONTROL1 0x2677 10068#define mmDIG6_HDMI_INFOFRAME_CONTROL1_BASE_IDX 2 10069#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0 0x2678 10070#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL0_BASE_IDX 2 10071#define mmDIG6_AFMT_INTERRUPT_STATUS 0x2679 10072#define mmDIG6_AFMT_INTERRUPT_STATUS_BASE_IDX 2 10073#define mmDIG6_HDMI_GC 0x267b 10074#define mmDIG6_HDMI_GC_BASE_IDX 2 10075#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2 0x267c 10076#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL2_BASE_IDX 2 10077#define mmDIG6_AFMT_ISRC1_0 0x267d 10078#define mmDIG6_AFMT_ISRC1_0_BASE_IDX 2 10079#define mmDIG6_AFMT_ISRC1_1 0x267e 10080#define mmDIG6_AFMT_ISRC1_1_BASE_IDX 2 10081#define mmDIG6_AFMT_ISRC1_2 0x267f 10082#define mmDIG6_AFMT_ISRC1_2_BASE_IDX 2 10083#define mmDIG6_AFMT_ISRC1_3 0x2680 10084#define mmDIG6_AFMT_ISRC1_3_BASE_IDX 2 10085#define mmDIG6_AFMT_ISRC1_4 0x2681 10086#define mmDIG6_AFMT_ISRC1_4_BASE_IDX 2 10087#define mmDIG6_AFMT_ISRC2_0 0x2682 10088#define mmDIG6_AFMT_ISRC2_0_BASE_IDX 2 10089#define mmDIG6_AFMT_ISRC2_1 0x2683 10090#define mmDIG6_AFMT_ISRC2_1_BASE_IDX 2 10091#define mmDIG6_AFMT_ISRC2_2 0x2684 10092#define mmDIG6_AFMT_ISRC2_2_BASE_IDX 2 10093#define mmDIG6_AFMT_ISRC2_3 0x2685 10094#define mmDIG6_AFMT_ISRC2_3_BASE_IDX 2 10095#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2 0x2686 10096#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL2_BASE_IDX 2 10097#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3 0x2687 10098#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL3_BASE_IDX 2 10099#define mmDIG6_HDMI_DB_CONTROL 0x2688 10100#define mmDIG6_HDMI_DB_CONTROL_BASE_IDX 2 10101#define mmDIG6_AFMT_MPEG_INFO0 0x268a 10102#define mmDIG6_AFMT_MPEG_INFO0_BASE_IDX 2 10103#define mmDIG6_AFMT_MPEG_INFO1 0x268b 10104#define mmDIG6_AFMT_MPEG_INFO1_BASE_IDX 2 10105#define mmDIG6_AFMT_GENERIC_HDR 0x268c 10106#define mmDIG6_AFMT_GENERIC_HDR_BASE_IDX 2 10107#define mmDIG6_AFMT_GENERIC_0 0x268d 10108#define mmDIG6_AFMT_GENERIC_0_BASE_IDX 2 10109#define mmDIG6_AFMT_GENERIC_1 0x268e 10110#define mmDIG6_AFMT_GENERIC_1_BASE_IDX 2 10111#define mmDIG6_AFMT_GENERIC_2 0x268f 10112#define mmDIG6_AFMT_GENERIC_2_BASE_IDX 2 10113#define mmDIG6_AFMT_GENERIC_3 0x2690 10114#define mmDIG6_AFMT_GENERIC_3_BASE_IDX 2 10115#define mmDIG6_AFMT_GENERIC_4 0x2691 10116#define mmDIG6_AFMT_GENERIC_4_BASE_IDX 2 10117#define mmDIG6_AFMT_GENERIC_5 0x2692 10118#define mmDIG6_AFMT_GENERIC_5_BASE_IDX 2 10119#define mmDIG6_AFMT_GENERIC_6 0x2693 10120#define mmDIG6_AFMT_GENERIC_6_BASE_IDX 2 10121#define mmDIG6_AFMT_GENERIC_7 0x2694 10122#define mmDIG6_AFMT_GENERIC_7_BASE_IDX 2 10123#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1 0x2695 10124#define mmDIG6_HDMI_GENERIC_PACKET_CONTROL1_BASE_IDX 2 10125#define mmDIG6_HDMI_ACR_32_0 0x2696 10126#define mmDIG6_HDMI_ACR_32_0_BASE_IDX 2 10127#define mmDIG6_HDMI_ACR_32_1 0x2697 10128#define mmDIG6_HDMI_ACR_32_1_BASE_IDX 2 10129#define mmDIG6_HDMI_ACR_44_0 0x2698 10130#define mmDIG6_HDMI_ACR_44_0_BASE_IDX 2 10131#define mmDIG6_HDMI_ACR_44_1 0x2699 10132#define mmDIG6_HDMI_ACR_44_1_BASE_IDX 2 10133#define mmDIG6_HDMI_ACR_48_0 0x269a 10134#define mmDIG6_HDMI_ACR_48_0_BASE_IDX 2 10135#define mmDIG6_HDMI_ACR_48_1 0x269b 10136#define mmDIG6_HDMI_ACR_48_1_BASE_IDX 2 10137#define mmDIG6_HDMI_ACR_STATUS_0 0x269c 10138#define mmDIG6_HDMI_ACR_STATUS_0_BASE_IDX 2 10139#define mmDIG6_HDMI_ACR_STATUS_1 0x269d 10140#define mmDIG6_HDMI_ACR_STATUS_1_BASE_IDX 2 10141#define mmDIG6_AFMT_AUDIO_INFO0 0x269e 10142#define mmDIG6_AFMT_AUDIO_INFO0_BASE_IDX 2 10143#define mmDIG6_AFMT_AUDIO_INFO1 0x269f 10144#define mmDIG6_AFMT_AUDIO_INFO1_BASE_IDX 2 10145#define mmDIG6_AFMT_60958_0 0x26a0 10146#define mmDIG6_AFMT_60958_0_BASE_IDX 2 10147#define mmDIG6_AFMT_60958_1 0x26a1 10148#define mmDIG6_AFMT_60958_1_BASE_IDX 2 10149#define mmDIG6_AFMT_AUDIO_CRC_CONTROL 0x26a2 10150#define mmDIG6_AFMT_AUDIO_CRC_CONTROL_BASE_IDX 2 10151#define mmDIG6_AFMT_RAMP_CONTROL0 0x26a3 10152#define mmDIG6_AFMT_RAMP_CONTROL0_BASE_IDX 2 10153#define mmDIG6_AFMT_RAMP_CONTROL1 0x26a4 10154#define mmDIG6_AFMT_RAMP_CONTROL1_BASE_IDX 2 10155#define mmDIG6_AFMT_RAMP_CONTROL2 0x26a5 10156#define mmDIG6_AFMT_RAMP_CONTROL2_BASE_IDX 2 10157#define mmDIG6_AFMT_RAMP_CONTROL3 0x26a6 10158#define mmDIG6_AFMT_RAMP_CONTROL3_BASE_IDX 2 10159#define mmDIG6_AFMT_60958_2 0x26a7 10160#define mmDIG6_AFMT_60958_2_BASE_IDX 2 10161#define mmDIG6_AFMT_AUDIO_CRC_RESULT 0x26a8 10162#define mmDIG6_AFMT_AUDIO_CRC_RESULT_BASE_IDX 2 10163#define mmDIG6_AFMT_STATUS 0x26a9 10164#define mmDIG6_AFMT_STATUS_BASE_IDX 2 10165#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL 0x26aa 10166#define mmDIG6_AFMT_AUDIO_PACKET_CONTROL_BASE_IDX 2 10167#define mmDIG6_AFMT_VBI_PACKET_CONTROL 0x26ab 10168#define mmDIG6_AFMT_VBI_PACKET_CONTROL_BASE_IDX 2 10169#define mmDIG6_AFMT_INFOFRAME_CONTROL0 0x26ac 10170#define mmDIG6_AFMT_INFOFRAME_CONTROL0_BASE_IDX 2 10171#define mmDIG6_AFMT_AUDIO_SRC_CONTROL 0x26ad 10172#define mmDIG6_AFMT_AUDIO_SRC_CONTROL_BASE_IDX 2 10173#define mmDIG6_DIG_BE_CNTL 0x26af 10174#define mmDIG6_DIG_BE_CNTL_BASE_IDX 2 10175#define mmDIG6_DIG_BE_EN_CNTL 0x26b0 10176#define mmDIG6_DIG_BE_EN_CNTL_BASE_IDX 2 10177#define mmDIG6_TMDS_CNTL 0x26d3 10178#define mmDIG6_TMDS_CNTL_BASE_IDX 2 10179#define mmDIG6_TMDS_CONTROL_CHAR 0x26d4 10180#define mmDIG6_TMDS_CONTROL_CHAR_BASE_IDX 2 10181#define mmDIG6_TMDS_CONTROL0_FEEDBACK 0x26d5 10182#define mmDIG6_TMDS_CONTROL0_FEEDBACK_BASE_IDX 2 10183#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL 0x26d6 10184#define mmDIG6_TMDS_STEREOSYNC_CTL_SEL_BASE_IDX 2 10185#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1 0x26d7 10186#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_0_1_BASE_IDX 2 10187#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3 0x26d8 10188#define mmDIG6_TMDS_SYNC_CHAR_PATTERN_2_3_BASE_IDX 2 10189#define mmDIG6_TMDS_CTL_BITS 0x26da 10190#define mmDIG6_TMDS_CTL_BITS_BASE_IDX 2 10191#define mmDIG6_TMDS_DCBALANCER_CONTROL 0x26db 10192#define mmDIG6_TMDS_DCBALANCER_CONTROL_BASE_IDX 2 10193#define mmDIG6_TMDS_CTL0_1_GEN_CNTL 0x26dd 10194#define mmDIG6_TMDS_CTL0_1_GEN_CNTL_BASE_IDX 2 10195#define mmDIG6_TMDS_CTL2_3_GEN_CNTL 0x26de 10196#define mmDIG6_TMDS_CTL2_3_GEN_CNTL_BASE_IDX 2 10197#define mmDIG6_DIG_VERSION 0x26e0 10198#define mmDIG6_DIG_VERSION_BASE_IDX 2 10199#define mmDIG6_DIG_LANE_ENABLE 0x26e1 10200#define mmDIG6_DIG_LANE_ENABLE_BASE_IDX 2 10201#define mmDIG6_AFMT_CNTL 0x26e6 10202#define mmDIG6_AFMT_CNTL_BASE_IDX 2 10203#define mmDIG6_AFMT_VBI_PACKET_CONTROL1 0x26e7 10204#define mmDIG6_AFMT_VBI_PACKET_CONTROL1_BASE_IDX 2 10205 10206 10207// addressBlock: dce_dc_dio_dp6_dispdec 10208// base address: 0x1800 10209#define mmDP6_DP_LINK_CNTL 0x2708 10210#define mmDP6_DP_LINK_CNTL_BASE_IDX 2 10211#define mmDP6_DP_PIXEL_FORMAT 0x2709 10212#define mmDP6_DP_PIXEL_FORMAT_BASE_IDX 2 10213#define mmDP6_DP_MSA_COLORIMETRY 0x270a 10214#define mmDP6_DP_MSA_COLORIMETRY_BASE_IDX 2 10215#define mmDP6_DP_CONFIG 0x270b 10216#define mmDP6_DP_CONFIG_BASE_IDX 2 10217#define mmDP6_DP_VID_STREAM_CNTL 0x270c 10218#define mmDP6_DP_VID_STREAM_CNTL_BASE_IDX 2 10219#define mmDP6_DP_STEER_FIFO 0x270d 10220#define mmDP6_DP_STEER_FIFO_BASE_IDX 2 10221#define mmDP6_DP_MSA_MISC 0x270e 10222#define mmDP6_DP_MSA_MISC_BASE_IDX 2 10223#define mmDP6_DP_VID_TIMING 0x2710 10224#define mmDP6_DP_VID_TIMING_BASE_IDX 2 10225#define mmDP6_DP_VID_N 0x2711 10226#define mmDP6_DP_VID_N_BASE_IDX 2 10227#define mmDP6_DP_VID_M 0x2712 10228#define mmDP6_DP_VID_M_BASE_IDX 2 10229#define mmDP6_DP_LINK_FRAMING_CNTL 0x2713 10230#define mmDP6_DP_LINK_FRAMING_CNTL_BASE_IDX 2 10231#define mmDP6_DP_HBR2_EYE_PATTERN 0x2714 10232#define mmDP6_DP_HBR2_EYE_PATTERN_BASE_IDX 2 10233#define mmDP6_DP_VID_MSA_VBID 0x2715 10234#define mmDP6_DP_VID_MSA_VBID_BASE_IDX 2 10235#define mmDP6_DP_VID_INTERRUPT_CNTL 0x2716 10236#define mmDP6_DP_VID_INTERRUPT_CNTL_BASE_IDX 2 10237#define mmDP6_DP_DPHY_CNTL 0x2717 10238#define mmDP6_DP_DPHY_CNTL_BASE_IDX 2 10239#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL 0x2718 10240#define mmDP6_DP_DPHY_TRAINING_PATTERN_SEL_BASE_IDX 2 10241#define mmDP6_DP_DPHY_SYM0 0x2719 10242#define mmDP6_DP_DPHY_SYM0_BASE_IDX 2 10243#define mmDP6_DP_DPHY_SYM1 0x271a 10244#define mmDP6_DP_DPHY_SYM1_BASE_IDX 2 10245#define mmDP6_DP_DPHY_SYM2 0x271b 10246#define mmDP6_DP_DPHY_SYM2_BASE_IDX 2 10247#define mmDP6_DP_DPHY_8B10B_CNTL 0x271c 10248#define mmDP6_DP_DPHY_8B10B_CNTL_BASE_IDX 2 10249#define mmDP6_DP_DPHY_PRBS_CNTL 0x271d 10250#define mmDP6_DP_DPHY_PRBS_CNTL_BASE_IDX 2 10251#define mmDP6_DP_DPHY_SCRAM_CNTL 0x271e 10252#define mmDP6_DP_DPHY_SCRAM_CNTL_BASE_IDX 2 10253#define mmDP6_DP_DPHY_CRC_EN 0x271f 10254#define mmDP6_DP_DPHY_CRC_EN_BASE_IDX 2 10255#define mmDP6_DP_DPHY_CRC_CNTL 0x2720 10256#define mmDP6_DP_DPHY_CRC_CNTL_BASE_IDX 2 10257#define mmDP6_DP_DPHY_CRC_RESULT 0x2721 10258#define mmDP6_DP_DPHY_CRC_RESULT_BASE_IDX 2 10259#define mmDP6_DP_DPHY_CRC_MST_CNTL 0x2722 10260#define mmDP6_DP_DPHY_CRC_MST_CNTL_BASE_IDX 2 10261#define mmDP6_DP_DPHY_CRC_MST_STATUS 0x2723 10262#define mmDP6_DP_DPHY_CRC_MST_STATUS_BASE_IDX 2 10263#define mmDP6_DP_DPHY_FAST_TRAINING 0x2724 10264#define mmDP6_DP_DPHY_FAST_TRAINING_BASE_IDX 2 10265#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS 0x2725 10266#define mmDP6_DP_DPHY_FAST_TRAINING_STATUS_BASE_IDX 2 10267#define mmDP6_DP_SEC_CNTL 0x272b 10268#define mmDP6_DP_SEC_CNTL_BASE_IDX 2 10269#define mmDP6_DP_SEC_CNTL1 0x272c 10270#define mmDP6_DP_SEC_CNTL1_BASE_IDX 2 10271#define mmDP6_DP_SEC_FRAMING1 0x272d 10272#define mmDP6_DP_SEC_FRAMING1_BASE_IDX 2 10273#define mmDP6_DP_SEC_FRAMING2 0x272e 10274#define mmDP6_DP_SEC_FRAMING2_BASE_IDX 2 10275#define mmDP6_DP_SEC_FRAMING3 0x272f 10276#define mmDP6_DP_SEC_FRAMING3_BASE_IDX 2 10277#define mmDP6_DP_SEC_FRAMING4 0x2730 10278#define mmDP6_DP_SEC_FRAMING4_BASE_IDX 2 10279#define mmDP6_DP_SEC_AUD_N 0x2731 10280#define mmDP6_DP_SEC_AUD_N_BASE_IDX 2 10281#define mmDP6_DP_SEC_AUD_N_READBACK 0x2732 10282#define mmDP6_DP_SEC_AUD_N_READBACK_BASE_IDX 2 10283#define mmDP6_DP_SEC_AUD_M 0x2733 10284#define mmDP6_DP_SEC_AUD_M_BASE_IDX 2 10285#define mmDP6_DP_SEC_AUD_M_READBACK 0x2734 10286#define mmDP6_DP_SEC_AUD_M_READBACK_BASE_IDX 2 10287#define mmDP6_DP_SEC_TIMESTAMP 0x2735 10288#define mmDP6_DP_SEC_TIMESTAMP_BASE_IDX 2 10289#define mmDP6_DP_SEC_PACKET_CNTL 0x2736 10290#define mmDP6_DP_SEC_PACKET_CNTL_BASE_IDX 2 10291#define mmDP6_DP_MSE_RATE_CNTL 0x2737 10292#define mmDP6_DP_MSE_RATE_CNTL_BASE_IDX 2 10293#define mmDP6_DP_MSE_RATE_UPDATE 0x2739 10294#define mmDP6_DP_MSE_RATE_UPDATE_BASE_IDX 2 10295#define mmDP6_DP_MSE_SAT0 0x273a 10296#define mmDP6_DP_MSE_SAT0_BASE_IDX 2 10297#define mmDP6_DP_MSE_SAT1 0x273b 10298#define mmDP6_DP_MSE_SAT1_BASE_IDX 2 10299#define mmDP6_DP_MSE_SAT2 0x273c 10300#define mmDP6_DP_MSE_SAT2_BASE_IDX 2 10301#define mmDP6_DP_MSE_SAT_UPDATE 0x273d 10302#define mmDP6_DP_MSE_SAT_UPDATE_BASE_IDX 2 10303#define mmDP6_DP_MSE_LINK_TIMING 0x273e 10304#define mmDP6_DP_MSE_LINK_TIMING_BASE_IDX 2 10305#define mmDP6_DP_MSE_MISC_CNTL 0x273f 10306#define mmDP6_DP_MSE_MISC_CNTL_BASE_IDX 2 10307#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x2744 10308#define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL_BASE_IDX 2 10309#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL 0x2745 10310#define mmDP6_DP_DPHY_HBR2_PATTERN_CONTROL_BASE_IDX 2 10311#define mmDP6_DP_MSE_SAT0_STATUS 0x2747 10312#define mmDP6_DP_MSE_SAT0_STATUS_BASE_IDX 2 10313#define mmDP6_DP_MSE_SAT1_STATUS 0x2748 10314#define mmDP6_DP_MSE_SAT1_STATUS_BASE_IDX 2 10315#define mmDP6_DP_MSE_SAT2_STATUS 0x2749 10316#define mmDP6_DP_MSE_SAT2_STATUS_BASE_IDX 2 10317#define mmDP6_DP_MSA_TIMING_PARAM1 0x274c 10318#define mmDP6_DP_MSA_TIMING_PARAM1_BASE_IDX 2 10319#define mmDP6_DP_MSA_TIMING_PARAM2 0x274d 10320#define mmDP6_DP_MSA_TIMING_PARAM2_BASE_IDX 2 10321#define mmDP6_DP_MSA_TIMING_PARAM3 0x274e 10322#define mmDP6_DP_MSA_TIMING_PARAM3_BASE_IDX 2 10323#define mmDP6_DP_MSA_TIMING_PARAM4 0x274f 10324#define mmDP6_DP_MSA_TIMING_PARAM4_BASE_IDX 2 10325#define mmDP6_DP_MSO_CNTL 0x2750 10326#define mmDP6_DP_MSO_CNTL_BASE_IDX 2 10327#define mmDP6_DP_MSO_CNTL1 0x2751 10328#define mmDP6_DP_MSO_CNTL1_BASE_IDX 2 10329#define mmDP6_DP_DSC_CNTL 0x2752 10330#define mmDP6_DP_DSC_CNTL_BASE_IDX 2 10331#define mmDP6_DP_SEC_CNTL2 0x2753 10332#define mmDP6_DP_SEC_CNTL2_BASE_IDX 2 10333#define mmDP6_DP_SEC_CNTL3 0x2754 10334#define mmDP6_DP_SEC_CNTL3_BASE_IDX 2 10335#define mmDP6_DP_SEC_CNTL4 0x2755 10336#define mmDP6_DP_SEC_CNTL4_BASE_IDX 2 10337#define mmDP6_DP_SEC_CNTL5 0x2756 10338#define mmDP6_DP_SEC_CNTL5_BASE_IDX 2 10339#define mmDP6_DP_SEC_CNTL6 0x2757 10340#define mmDP6_DP_SEC_CNTL6_BASE_IDX 2 10341#define mmDP6_DP_SEC_CNTL7 0x2758 10342#define mmDP6_DP_SEC_CNTL7_BASE_IDX 2 10343#define mmDP6_DP_DB_CNTL 0x2759 10344#define mmDP6_DP_DB_CNTL_BASE_IDX 2 10345#define mmDP6_DP_MSA_VBID_MISC 0x275a 10346#define mmDP6_DP_MSA_VBID_MISC_BASE_IDX 2 10347 10348 10349// addressBlock: dce_dc_dcio_dcio_dispdec 10350// base address: 0x0 10351#define mmDC_GENERICA 0x2868 10352#define mmDC_GENERICA_BASE_IDX 2 10353#define mmDC_GENERICB 0x2869 10354#define mmDC_GENERICB_BASE_IDX 2 10355#define mmDC_REF_CLK_CNTL 0x286b 10356#define mmDC_REF_CLK_CNTL_BASE_IDX 2 10357#define mmDC_GPIO_DEBUG 0x286c 10358#define mmDC_GPIO_DEBUG_BASE_IDX 2 10359#define mmUNIPHYA_LINK_CNTL 0x286d 10360#define mmUNIPHYA_LINK_CNTL_BASE_IDX 2 10361#define mmUNIPHYA_CHANNEL_XBAR_CNTL 0x286e 10362#define mmUNIPHYA_CHANNEL_XBAR_CNTL_BASE_IDX 2 10363#define mmUNIPHYB_LINK_CNTL 0x286f 10364#define mmUNIPHYB_LINK_CNTL_BASE_IDX 2 10365#define mmUNIPHYB_CHANNEL_XBAR_CNTL 0x2870 10366#define mmUNIPHYB_CHANNEL_XBAR_CNTL_BASE_IDX 2 10367#define mmUNIPHYC_LINK_CNTL 0x2871 10368#define mmUNIPHYC_LINK_CNTL_BASE_IDX 2 10369#define mmUNIPHYC_CHANNEL_XBAR_CNTL 0x2872 10370#define mmUNIPHYC_CHANNEL_XBAR_CNTL_BASE_IDX 2 10371#define mmUNIPHYD_LINK_CNTL 0x2873 10372#define mmUNIPHYD_LINK_CNTL_BASE_IDX 2 10373#define mmUNIPHYD_CHANNEL_XBAR_CNTL 0x2874 10374#define mmUNIPHYD_CHANNEL_XBAR_CNTL_BASE_IDX 2 10375#define mmUNIPHYE_LINK_CNTL 0x2875 10376#define mmUNIPHYE_LINK_CNTL_BASE_IDX 2 10377#define mmUNIPHYE_CHANNEL_XBAR_CNTL 0x2876 10378#define mmUNIPHYE_CHANNEL_XBAR_CNTL_BASE_IDX 2 10379#define mmUNIPHYF_LINK_CNTL 0x2877 10380#define mmUNIPHYF_LINK_CNTL_BASE_IDX 2 10381#define mmUNIPHYF_CHANNEL_XBAR_CNTL 0x2878 10382#define mmUNIPHYF_CHANNEL_XBAR_CNTL_BASE_IDX 2 10383#define mmUNIPHYG_LINK_CNTL 0x2879 10384#define mmUNIPHYG_LINK_CNTL_BASE_IDX 2 10385#define mmUNIPHYG_CHANNEL_XBAR_CNTL 0x287a 10386#define mmUNIPHYG_CHANNEL_XBAR_CNTL_BASE_IDX 2 10387#define mmDCIO_WRCMD_DELAY 0x287e 10388#define mmDCIO_WRCMD_DELAY_BASE_IDX 2 10389#define mmDC_PINSTRAPS 0x2880 10390#define mmDC_PINSTRAPS_BASE_IDX 2 10391#define mmDC_DVODATA_CONFIG 0x2882 10392#define mmDC_DVODATA_CONFIG_BASE_IDX 2 10393#define mmLVTMA_PWRSEQ_CNTL 0x2883 10394#define mmLVTMA_PWRSEQ_CNTL_BASE_IDX 2 10395#define mmLVTMA_PWRSEQ_STATE 0x2884 10396#define mmLVTMA_PWRSEQ_STATE_BASE_IDX 2 10397#define mmLVTMA_PWRSEQ_REF_DIV 0x2885 10398#define mmLVTMA_PWRSEQ_REF_DIV_BASE_IDX 2 10399#define mmLVTMA_PWRSEQ_DELAY1 0x2886 10400#define mmLVTMA_PWRSEQ_DELAY1_BASE_IDX 2 10401#define mmLVTMA_PWRSEQ_DELAY2 0x2887 10402#define mmLVTMA_PWRSEQ_DELAY2_BASE_IDX 2 10403#define mmBL_PWM_CNTL 0x2888 10404#define mmBL_PWM_CNTL_BASE_IDX 2 10405#define mmBL_PWM_CNTL2 0x2889 10406#define mmBL_PWM_CNTL2_BASE_IDX 2 10407#define mmBL_PWM_PERIOD_CNTL 0x288a 10408#define mmBL_PWM_PERIOD_CNTL_BASE_IDX 2 10409#define mmBL_PWM_GRP1_REG_LOCK 0x288b 10410#define mmBL_PWM_GRP1_REG_LOCK_BASE_IDX 2 10411#define mmDCIO_GSL_GENLK_PAD_CNTL 0x288c 10412#define mmDCIO_GSL_GENLK_PAD_CNTL_BASE_IDX 2 10413#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL 0x288d 10414#define mmDCIO_GSL_SWAPLOCK_PAD_CNTL_BASE_IDX 2 10415#define mmDCIO_CLOCK_CNTL 0x2895 10416#define mmDCIO_CLOCK_CNTL_BASE_IDX 2 10417#define mmDIO_OTG_EXT_VSYNC_CNTL 0x2898 10418#define mmDIO_OTG_EXT_VSYNC_CNTL_BASE_IDX 2 10419#define mmDCIO_SOFT_RESET 0x289e 10420#define mmDCIO_SOFT_RESET_BASE_IDX 2 10421#define mmDCIO_DPHY_SEL 0x289f 10422#define mmDCIO_DPHY_SEL_BASE_IDX 2 10423#define mmUNIPHY_IMPCAL_LINKA 0x28a0 10424#define mmUNIPHY_IMPCAL_LINKA_BASE_IDX 2 10425#define mmUNIPHY_IMPCAL_LINKB 0x28a1 10426#define mmUNIPHY_IMPCAL_LINKB_BASE_IDX 2 10427#define mmUNIPHY_IMPCAL_PERIOD 0x28a2 10428#define mmUNIPHY_IMPCAL_PERIOD_BASE_IDX 2 10429#define mmAUXP_IMPCAL 0x28a3 10430#define mmAUXP_IMPCAL_BASE_IDX 2 10431#define mmAUXN_IMPCAL 0x28a4 10432#define mmAUXN_IMPCAL_BASE_IDX 2 10433#define mmDCIO_IMPCAL_CNTL 0x28a5 10434#define mmDCIO_IMPCAL_CNTL_BASE_IDX 2 10435#define mmUNIPHY_IMPCAL_PSW_AB 0x28a6 10436#define mmUNIPHY_IMPCAL_PSW_AB_BASE_IDX 2 10437#define mmUNIPHY_IMPCAL_LINKC 0x28a7 10438#define mmUNIPHY_IMPCAL_LINKC_BASE_IDX 2 10439#define mmUNIPHY_IMPCAL_LINKD 0x28a8 10440#define mmUNIPHY_IMPCAL_LINKD_BASE_IDX 2 10441#define mmDCIO_IMPCAL_CNTL_CD 0x28a9 10442#define mmDCIO_IMPCAL_CNTL_CD_BASE_IDX 2 10443#define mmUNIPHY_IMPCAL_PSW_CD 0x28aa 10444#define mmUNIPHY_IMPCAL_PSW_CD_BASE_IDX 2 10445#define mmUNIPHY_IMPCAL_LINKE 0x28ab 10446#define mmUNIPHY_IMPCAL_LINKE_BASE_IDX 2 10447#define mmUNIPHY_IMPCAL_LINKF 0x28ac 10448#define mmUNIPHY_IMPCAL_LINKF_BASE_IDX 2 10449#define mmDCIO_IMPCAL_CNTL_EF 0x28ad 10450#define mmDCIO_IMPCAL_CNTL_EF_BASE_IDX 2 10451#define mmUNIPHY_IMPCAL_PSW_EF 0x28ae 10452#define mmUNIPHY_IMPCAL_PSW_EF_BASE_IDX 2 10453#define mmDCIO_DPCS_TX_INTERRUPT 0x28b3 10454#define mmDCIO_DPCS_TX_INTERRUPT_BASE_IDX 2 10455#define mmDCIO_DPCS_RX_INTERRUPT 0x28b4 10456#define mmDCIO_DPCS_RX_INTERRUPT_BASE_IDX 2 10457#define mmDCIO_SEMAPHORE0 0x28b5 10458#define mmDCIO_SEMAPHORE0_BASE_IDX 2 10459#define mmDCIO_SEMAPHORE1 0x28b6 10460#define mmDCIO_SEMAPHORE1_BASE_IDX 2 10461#define mmDCIO_SEMAPHORE2 0x28b7 10462#define mmDCIO_SEMAPHORE2_BASE_IDX 2 10463#define mmDCIO_SEMAPHORE3 0x28b8 10464#define mmDCIO_SEMAPHORE3_BASE_IDX 2 10465#define mmDCIO_SEMAPHORE4 0x28b9 10466#define mmDCIO_SEMAPHORE4_BASE_IDX 2 10467#define mmDCIO_SEMAPHORE5 0x28ba 10468#define mmDCIO_SEMAPHORE5_BASE_IDX 2 10469#define mmDCIO_SEMAPHORE6 0x28bb 10470#define mmDCIO_SEMAPHORE6_BASE_IDX 2 10471#define mmDCIO_SEMAPHORE7 0x28bc 10472#define mmDCIO_SEMAPHORE7_BASE_IDX 2 10473#define mmDCIO_USBC_FLIP_EN_SEL 0x28bd 10474#define mmDCIO_USBC_FLIP_EN_SEL_BASE_IDX 2 10475 10476 10477// addressBlock: dce_dc_dcio_dcio_chip_dispdec 10478// base address: 0x0 10479#define mmDC_GPIO_GENERIC_MASK 0x28c8 10480#define mmDC_GPIO_GENERIC_MASK_BASE_IDX 2 10481#define mmDC_GPIO_GENERIC_A 0x28c9 10482#define mmDC_GPIO_GENERIC_A_BASE_IDX 2 10483#define mmDC_GPIO_GENERIC_EN 0x28ca 10484#define mmDC_GPIO_GENERIC_EN_BASE_IDX 2 10485#define mmDC_GPIO_GENERIC_Y 0x28cb 10486#define mmDC_GPIO_GENERIC_Y_BASE_IDX 2 10487#define mmDC_GPIO_DVODATA_MASK 0x28cc 10488#define mmDC_GPIO_DVODATA_MASK_BASE_IDX 2 10489#define mmDC_GPIO_DVODATA_A 0x28cd 10490#define mmDC_GPIO_DVODATA_A_BASE_IDX 2 10491#define mmDC_GPIO_DVODATA_EN 0x28ce 10492#define mmDC_GPIO_DVODATA_EN_BASE_IDX 2 10493#define mmDC_GPIO_DVODATA_Y 0x28cf 10494#define mmDC_GPIO_DVODATA_Y_BASE_IDX 2 10495#define mmDC_GPIO_DDC1_MASK 0x28d0 10496#define mmDC_GPIO_DDC1_MASK_BASE_IDX 2 10497#define mmDC_GPIO_DDC1_A 0x28d1 10498#define mmDC_GPIO_DDC1_A_BASE_IDX 2 10499#define mmDC_GPIO_DDC1_EN 0x28d2 10500#define mmDC_GPIO_DDC1_EN_BASE_IDX 2 10501#define mmDC_GPIO_DDC1_Y 0x28d3 10502#define mmDC_GPIO_DDC1_Y_BASE_IDX 2 10503#define mmDC_GPIO_DDC2_MASK 0x28d4 10504#define mmDC_GPIO_DDC2_MASK_BASE_IDX 2 10505#define mmDC_GPIO_DDC2_A 0x28d5 10506#define mmDC_GPIO_DDC2_A_BASE_IDX 2 10507#define mmDC_GPIO_DDC2_EN 0x28d6 10508#define mmDC_GPIO_DDC2_EN_BASE_IDX 2 10509#define mmDC_GPIO_DDC2_Y 0x28d7 10510#define mmDC_GPIO_DDC2_Y_BASE_IDX 2 10511#define mmDC_GPIO_DDC3_MASK 0x28d8 10512#define mmDC_GPIO_DDC3_MASK_BASE_IDX 2 10513#define mmDC_GPIO_DDC3_A 0x28d9 10514#define mmDC_GPIO_DDC3_A_BASE_IDX 2 10515#define mmDC_GPIO_DDC3_EN 0x28da 10516#define mmDC_GPIO_DDC3_EN_BASE_IDX 2 10517#define mmDC_GPIO_DDC3_Y 0x28db 10518#define mmDC_GPIO_DDC3_Y_BASE_IDX 2 10519#define mmDC_GPIO_DDC4_MASK 0x28dc 10520#define mmDC_GPIO_DDC4_MASK_BASE_IDX 2 10521#define mmDC_GPIO_DDC4_A 0x28dd 10522#define mmDC_GPIO_DDC4_A_BASE_IDX 2 10523#define mmDC_GPIO_DDC4_EN 0x28de 10524#define mmDC_GPIO_DDC4_EN_BASE_IDX 2 10525#define mmDC_GPIO_DDC4_Y 0x28df 10526#define mmDC_GPIO_DDC4_Y_BASE_IDX 2 10527#define mmDC_GPIO_DDC5_MASK 0x28e0 10528#define mmDC_GPIO_DDC5_MASK_BASE_IDX 2 10529#define mmDC_GPIO_DDC5_A 0x28e1 10530#define mmDC_GPIO_DDC5_A_BASE_IDX 2 10531#define mmDC_GPIO_DDC5_EN 0x28e2 10532#define mmDC_GPIO_DDC5_EN_BASE_IDX 2 10533#define mmDC_GPIO_DDC5_Y 0x28e3 10534#define mmDC_GPIO_DDC5_Y_BASE_IDX 2 10535#define mmDC_GPIO_DDC6_MASK 0x28e4 10536#define mmDC_GPIO_DDC6_MASK_BASE_IDX 2 10537#define mmDC_GPIO_DDC6_A 0x28e5 10538#define mmDC_GPIO_DDC6_A_BASE_IDX 2 10539#define mmDC_GPIO_DDC6_EN 0x28e6 10540#define mmDC_GPIO_DDC6_EN_BASE_IDX 2 10541#define mmDC_GPIO_DDC6_Y 0x28e7 10542#define mmDC_GPIO_DDC6_Y_BASE_IDX 2 10543#define mmDC_GPIO_DDCVGA_MASK 0x28e8 10544#define mmDC_GPIO_DDCVGA_MASK_BASE_IDX 2 10545#define mmDC_GPIO_DDCVGA_A 0x28e9 10546#define mmDC_GPIO_DDCVGA_A_BASE_IDX 2 10547#define mmDC_GPIO_DDCVGA_EN 0x28ea 10548#define mmDC_GPIO_DDCVGA_EN_BASE_IDX 2 10549#define mmDC_GPIO_DDCVGA_Y 0x28eb 10550#define mmDC_GPIO_DDCVGA_Y_BASE_IDX 2 10551#define mmDC_GPIO_SYNCA_MASK 0x28ec 10552#define mmDC_GPIO_SYNCA_MASK_BASE_IDX 2 10553#define mmDC_GPIO_SYNCA_A 0x28ed 10554#define mmDC_GPIO_SYNCA_A_BASE_IDX 2 10555#define mmDC_GPIO_SYNCA_EN 0x28ee 10556#define mmDC_GPIO_SYNCA_EN_BASE_IDX 2 10557#define mmDC_GPIO_SYNCA_Y 0x28ef 10558#define mmDC_GPIO_SYNCA_Y_BASE_IDX 2 10559#define mmDC_GPIO_GENLK_MASK 0x28f0 10560#define mmDC_GPIO_GENLK_MASK_BASE_IDX 2 10561#define mmDC_GPIO_GENLK_A 0x28f1 10562#define mmDC_GPIO_GENLK_A_BASE_IDX 2 10563#define mmDC_GPIO_GENLK_EN 0x28f2 10564#define mmDC_GPIO_GENLK_EN_BASE_IDX 2 10565#define mmDC_GPIO_GENLK_Y 0x28f3 10566#define mmDC_GPIO_GENLK_Y_BASE_IDX 2 10567#define mmDC_GPIO_HPD_MASK 0x28f4 10568#define mmDC_GPIO_HPD_MASK_BASE_IDX 2 10569#define mmDC_GPIO_HPD_A 0x28f5 10570#define mmDC_GPIO_HPD_A_BASE_IDX 2 10571#define mmDC_GPIO_HPD_EN 0x28f6 10572#define mmDC_GPIO_HPD_EN_BASE_IDX 2 10573#define mmDC_GPIO_HPD_Y 0x28f7 10574#define mmDC_GPIO_HPD_Y_BASE_IDX 2 10575#define mmDC_GPIO_PWRSEQ_MASK 0x28f8 10576#define mmDC_GPIO_PWRSEQ_MASK_BASE_IDX 2 10577#define mmDC_GPIO_PWRSEQ_A 0x28f9 10578#define mmDC_GPIO_PWRSEQ_A_BASE_IDX 2 10579#define mmDC_GPIO_PWRSEQ_EN 0x28fa 10580#define mmDC_GPIO_PWRSEQ_EN_BASE_IDX 2 10581#define mmDC_GPIO_PWRSEQ_Y 0x28fb 10582#define mmDC_GPIO_PWRSEQ_Y_BASE_IDX 2 10583#define mmDC_GPIO_PAD_STRENGTH_1 0x28fc 10584#define mmDC_GPIO_PAD_STRENGTH_1_BASE_IDX 2 10585#define mmDC_GPIO_PAD_STRENGTH_2 0x28fd 10586#define mmDC_GPIO_PAD_STRENGTH_2_BASE_IDX 2 10587#define mmPHY_AUX_CNTL 0x28ff 10588#define mmPHY_AUX_CNTL_BASE_IDX 2 10589#define mmDC_GPIO_I2CPAD_MASK 0x2900 10590#define mmDC_GPIO_I2CPAD_MASK_BASE_IDX 2 10591#define mmDC_GPIO_I2CPAD_A 0x2901 10592#define mmDC_GPIO_I2CPAD_A_BASE_IDX 2 10593#define mmDC_GPIO_I2CPAD_EN 0x2902 10594#define mmDC_GPIO_I2CPAD_EN_BASE_IDX 2 10595#define mmDC_GPIO_I2CPAD_Y 0x2903 10596#define mmDC_GPIO_I2CPAD_Y_BASE_IDX 2 10597#define mmDC_GPIO_I2CPAD_STRENGTH 0x2904 10598#define mmDC_GPIO_I2CPAD_STRENGTH_BASE_IDX 2 10599#define mmDVO_STRENGTH_CONTROL 0x2905 10600#define mmDVO_STRENGTH_CONTROL_BASE_IDX 2 10601#define mmDVO_VREF_CONTROL 0x2906 10602#define mmDVO_VREF_CONTROL_BASE_IDX 2 10603#define mmDVO_SKEW_ADJUST 0x2907 10604#define mmDVO_SKEW_ADJUST_BASE_IDX 2 10605#define mmDC_GPIO_I2S_SPDIF_MASK 0x2910 10606#define mmDC_GPIO_I2S_SPDIF_MASK_BASE_IDX 2 10607#define mmDC_GPIO_I2S_SPDIF_A 0x2911 10608#define mmDC_GPIO_I2S_SPDIF_A_BASE_IDX 2 10609#define mmDC_GPIO_I2S_SPDIF_EN 0x2912 10610#define mmDC_GPIO_I2S_SPDIF_EN_BASE_IDX 2 10611#define mmDC_GPIO_I2S_SPDIF_Y 0x2913 10612#define mmDC_GPIO_I2S_SPDIF_Y_BASE_IDX 2 10613#define mmDC_GPIO_I2S_SPDIF_STRENGTH 0x2914 10614#define mmDC_GPIO_I2S_SPDIF_STRENGTH_BASE_IDX 2 10615#define mmDC_GPIO_TX12_EN 0x2915 10616#define mmDC_GPIO_TX12_EN_BASE_IDX 2 10617#define mmDC_GPIO_AUX_CTRL_0 0x2916 10618#define mmDC_GPIO_AUX_CTRL_0_BASE_IDX 2 10619#define mmDC_GPIO_AUX_CTRL_1 0x2917 10620#define mmDC_GPIO_AUX_CTRL_1_BASE_IDX 2 10621#define mmDC_GPIO_AUX_CTRL_2 0x2918 10622#define mmDC_GPIO_AUX_CTRL_2_BASE_IDX 2 10623#define mmDC_GPIO_RXEN 0x2919 10624#define mmDC_GPIO_RXEN_BASE_IDX 2 10625#define mmDC_GPIO_PULLUPEN 0x291a 10626#define mmDC_GPIO_PULLUPEN_BASE_IDX 2 10627 10628 10629// addressBlock: dce_dc_dcio_dcio_dac_dispdec 10630// base address: 0x0 10631#define mmDAC_MACRO_CNTL_RESERVED0 0x2920 10632#define mmDAC_MACRO_CNTL_RESERVED0_BASE_IDX 2 10633#define mmDAC_MACRO_CNTL_RESERVED1 0x2921 10634#define mmDAC_MACRO_CNTL_RESERVED1_BASE_IDX 2 10635#define mmDAC_MACRO_CNTL_RESERVED2 0x2922 10636#define mmDAC_MACRO_CNTL_RESERVED2_BASE_IDX 2 10637#define mmDAC_MACRO_CNTL_RESERVED3 0x2923 10638#define mmDAC_MACRO_CNTL_RESERVED3_BASE_IDX 2 10639 10640 10641// addressBlock: dce_dc_dcio_dcio_uniphy0_dispdec 10642// base address: 0x0 10643#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0 0x2928 10644#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 10645#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1 0x2929 10646#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 10647#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2 0x292a 10648#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 10649#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3 0x292b 10650#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 10651#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4 0x292c 10652#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 10653#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5 0x292d 10654#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 10655#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6 0x292e 10656#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 10657#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7 0x292f 10658#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 10659#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8 0x2930 10660#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 10661#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9 0x2931 10662#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 10663#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10 0x2932 10664#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 10665#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11 0x2933 10666#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 10667#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12 0x2934 10668#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 10669#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13 0x2935 10670#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 10671#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14 0x2936 10672#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 10673#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15 0x2937 10674#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 10675#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16 0x2938 10676#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 10677#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17 0x2939 10678#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 10679#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18 0x293a 10680#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 10681#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19 0x293b 10682#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 10683#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20 0x293c 10684#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 10685#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21 0x293d 10686#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 10687#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22 0x293e 10688#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 10689#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23 0x293f 10690#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 10691#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24 0x2940 10692#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 10693#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25 0x2941 10694#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 10695#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26 0x2942 10696#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 10697#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27 0x2943 10698#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 10699#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28 0x2944 10700#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 10701#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29 0x2945 10702#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 10703#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30 0x2946 10704#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 10705#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31 0x2947 10706#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 10707#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32 0x2948 10708#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 10709#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33 0x2949 10710#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 10711#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34 0x294a 10712#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 10713#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35 0x294b 10714#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 10715#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36 0x294c 10716#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 10717#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37 0x294d 10718#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 10719#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38 0x294e 10720#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 10721#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39 0x294f 10722#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 10723#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40 0x2950 10724#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 10725#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41 0x2951 10726#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 10727#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42 0x2952 10728#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 10729#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43 0x2953 10730#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 10731#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44 0x2954 10732#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 10733#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45 0x2955 10734#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 10735#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46 0x2956 10736#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 10737#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47 0x2957 10738#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 10739#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48 0x2958 10740#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 10741#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49 0x2959 10742#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 10743#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50 0x295a 10744#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 10745#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51 0x295b 10746#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 10747#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52 0x295c 10748#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 10749#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53 0x295d 10750#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 10751#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54 0x295e 10752#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 10753#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55 0x295f 10754#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 10755#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56 0x2960 10756#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 10757#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57 0x2961 10758#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 10759#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58 0x2962 10760#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 10761#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59 0x2963 10762#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 10763#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60 0x2964 10764#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 10765#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61 0x2965 10766#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 10767#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62 0x2966 10768#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 10769#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63 0x2967 10770#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 10771#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64 0x2968 10772#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 10773#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65 0x2969 10774#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 10775#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66 0x296a 10776#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 10777#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67 0x296b 10778#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 10779#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68 0x296c 10780#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 10781#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69 0x296d 10782#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 10783#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70 0x296e 10784#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 10785#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71 0x296f 10786#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 10787#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72 0x2970 10788#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 10789#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73 0x2971 10790#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 10791#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74 0x2972 10792#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 10793#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75 0x2973 10794#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 10795#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76 0x2974 10796#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 10797#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77 0x2975 10798#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 10799#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78 0x2976 10800#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 10801#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79 0x2977 10802#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 10803#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80 0x2978 10804#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 10805#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81 0x2979 10806#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 10807#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82 0x297a 10808#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 10809#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83 0x297b 10810#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 10811#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84 0x297c 10812#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 10813#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85 0x297d 10814#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 10815#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86 0x297e 10816#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 10817#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87 0x297f 10818#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 10819#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88 0x2980 10820#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 10821#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89 0x2981 10822#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 10823#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90 0x2982 10824#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 10825#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91 0x2983 10826#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 10827#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92 0x2984 10828#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 10829#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93 0x2985 10830#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 10831#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94 0x2986 10832#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 10833#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95 0x2987 10834#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 10835#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96 0x2988 10836#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 10837#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97 0x2989 10838#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 10839#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98 0x298a 10840#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 10841#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99 0x298b 10842#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 10843#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100 0x298c 10844#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 10845#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101 0x298d 10846#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 10847#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102 0x298e 10848#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 10849#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103 0x298f 10850#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 10851#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104 0x2990 10852#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 10853#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105 0x2991 10854#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 10855#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106 0x2992 10856#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 10857#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107 0x2993 10858#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 10859#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108 0x2994 10860#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 10861#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109 0x2995 10862#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 10863#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110 0x2996 10864#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 10865#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111 0x2997 10866#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 10867#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112 0x2998 10868#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 10869#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113 0x2999 10870#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 10871#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114 0x299a 10872#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 10873#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115 0x299b 10874#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 10875#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116 0x299c 10876#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 10877#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117 0x299d 10878#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 10879#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118 0x299e 10880#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 10881#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119 0x299f 10882#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 10883#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120 0x29a0 10884#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 10885#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121 0x29a1 10886#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 10887#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122 0x29a2 10888#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 10889#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123 0x29a3 10890#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 10891#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124 0x29a4 10892#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 10893#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125 0x29a5 10894#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 10895#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126 0x29a6 10896#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 10897#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127 0x29a7 10898#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 10899#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128 0x29a8 10900#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 10901#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129 0x29a9 10902#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 10903#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130 0x29aa 10904#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 10905#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131 0x29ab 10906#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 10907#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132 0x29ac 10908#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 10909#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133 0x29ad 10910#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 10911#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134 0x29ae 10912#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 10913#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135 0x29af 10914#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 10915#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136 0x29b0 10916#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 10917#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137 0x29b1 10918#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 10919#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138 0x29b2 10920#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 10921#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139 0x29b3 10922#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 10923#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140 0x29b4 10924#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 10925#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141 0x29b5 10926#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 10927#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142 0x29b6 10928#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 10929#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143 0x29b7 10930#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 10931#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144 0x29b8 10932#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 10933#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145 0x29b9 10934#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 10935#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146 0x29ba 10936#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 10937#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147 0x29bb 10938#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 10939#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148 0x29bc 10940#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 10941#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149 0x29bd 10942#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 10943#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150 0x29be 10944#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 10945#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151 0x29bf 10946#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 10947#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152 0x29c0 10948#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 10949#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153 0x29c1 10950#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 10951#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154 0x29c2 10952#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 10953#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155 0x29c3 10954#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 10955#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156 0x29c4 10956#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 10957#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157 0x29c5 10958#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 10959#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158 0x29c6 10960#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 10961#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159 0x29c7 10962#define mmDCIO_UNIPHY0_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 10963 10964 10965// addressBlock: dce_dc_combophy_dc_combophycmregs0_dispdec 10966// base address: 0x0 10967#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1 0x2928 10968#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE1_BASE_IDX 2 10969#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2 0x2929 10970#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE2_BASE_IDX 2 10971#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3 0x292a 10972#define mmDC_COMBOPHYCMREGS0_COMMON_FUSE3_BASE_IDX 2 10973#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM 0x292b 10974#define mmDC_COMBOPHYCMREGS0_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 10975#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT 0x292c 10976#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_PWRMGMT_BASE_IDX 2 10977#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL 0x292d 10978#define mmDC_COMBOPHYCMREGS0_COMMON_TXCNTRL_BASE_IDX 2 10979#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP 0x292e 10980#define mmDC_COMBOPHYCMREGS0_COMMON_TMDP_BASE_IDX 2 10981#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS 0x292f 10982#define mmDC_COMBOPHYCMREGS0_COMMON_LANE_RESETS_BASE_IDX 2 10983#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL 0x2930 10984#define mmDC_COMBOPHYCMREGS0_COMMON_ZCALCODE_CTRL_BASE_IDX 2 10985#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1 0x2931 10986#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU1_BASE_IDX 2 10987#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2 0x2932 10988#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU2_BASE_IDX 2 10989#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3 0x2933 10990#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU3_BASE_IDX 2 10991#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4 0x2934 10992#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU4_BASE_IDX 2 10993#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5 0x2935 10994#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU5_BASE_IDX 2 10995#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6 0x2936 10996#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU6_BASE_IDX 2 10997#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7 0x2937 10998#define mmDC_COMBOPHYCMREGS0_COMMON_DISP_RFU7_BASE_IDX 2 10999 11000
11001// addressBlock: dce_dc_combophy_dc_combophytxregs0_dispdec 11002// base address: 0x0 11003#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0 0x2948 11004#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 11005#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0 0x2949 11006#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE0_BASE_IDX 2 11007#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x294a 11008#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 11009#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0 0x294b 11010#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE0_BASE_IDX 2 11011#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0 0x294c 11012#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE0_BASE_IDX 2 11013#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0 0x294d 11014#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE0_BASE_IDX 2 11015#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0 0x294e 11016#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE0_BASE_IDX 2 11017#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0 0x294f 11018#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE0_BASE_IDX 2 11019#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0 0x2950 11020#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE0_BASE_IDX 2 11021#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0 0x2951 11022#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE0_BASE_IDX 2 11023#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0 0x2952 11024#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE0_BASE_IDX 2 11025#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0 0x2953 11026#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE0_BASE_IDX 2 11027#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0 0x2954 11028#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE0_BASE_IDX 2 11029#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0 0x2955 11030#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE0_BASE_IDX 2 11031#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0 0x2956 11032#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE0_BASE_IDX 2 11033#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0 0x2957 11034#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE0_BASE_IDX 2 11035#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1 0x2958 11036#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 11037#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1 0x2959 11038#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE1_BASE_IDX 2 11039#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x295a 11040#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 11041#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1 0x295b 11042#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE1_BASE_IDX 2 11043#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1 0x295c 11044#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE1_BASE_IDX 2 11045#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1 0x295d 11046#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE1_BASE_IDX 2 11047#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1 0x295e 11048#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE1_BASE_IDX 2 11049#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1 0x295f 11050#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE1_BASE_IDX 2 11051#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1 0x2960 11052#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE1_BASE_IDX 2 11053#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1 0x2961 11054#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE1_BASE_IDX 2 11055#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1 0x2962 11056#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE1_BASE_IDX 2 11057#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1 0x2963 11058#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE1_BASE_IDX 2 11059#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1 0x2964 11060#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE1_BASE_IDX 2 11061#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1 0x2965 11062#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE1_BASE_IDX 2 11063#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1 0x2966 11064#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE1_BASE_IDX 2 11065#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1 0x2967 11066#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE1_BASE_IDX 2 11067#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2 0x2968 11068#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 11069#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2 0x2969 11070#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE2_BASE_IDX 2 11071#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x296a 11072#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 11073#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2 0x296b 11074#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE2_BASE_IDX 2 11075#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2 0x296c 11076#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE2_BASE_IDX 2 11077#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2 0x296d 11078#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE2_BASE_IDX 2 11079#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2 0x296e 11080#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE2_BASE_IDX 2 11081#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2 0x296f 11082#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE2_BASE_IDX 2 11083#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2 0x2970 11084#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE2_BASE_IDX 2 11085#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2 0x2971 11086#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE2_BASE_IDX 2 11087#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2 0x2972 11088#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE2_BASE_IDX 2 11089#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2 0x2973 11090#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE2_BASE_IDX 2 11091#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2 0x2974 11092#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE2_BASE_IDX 2 11093#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2 0x2975 11094#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE2_BASE_IDX 2 11095#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2 0x2976 11096#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE2_BASE_IDX 2 11097#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2 0x2977 11098#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE2_BASE_IDX 2 11099#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3 0x2978 11100#define mmDC_COMBOPHYTXREGS0_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 11101#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3 0x2979 11102#define mmDC_COMBOPHYTXREGS0_MARGIN_DEEMPH_LANE3_BASE_IDX 2 11103#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x297a 11104#define mmDC_COMBOPHYTXREGS0_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 11105#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3 0x297b 11106#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU0_LANE3_BASE_IDX 2 11107#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3 0x297c 11108#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU1_LANE3_BASE_IDX 2 11109#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3 0x297d 11110#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU2_LANE3_BASE_IDX 2 11111#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3 0x297e 11112#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU3_LANE3_BASE_IDX 2 11113#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3 0x297f 11114#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU4_LANE3_BASE_IDX 2 11115#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3 0x2980 11116#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU5_LANE3_BASE_IDX 2 11117#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3 0x2981 11118#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU6_LANE3_BASE_IDX 2 11119#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3 0x2982 11120#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU7_LANE3_BASE_IDX 2 11121#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3 0x2983 11122#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU8_LANE3_BASE_IDX 2 11123#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3 0x2984 11124#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU9_LANE3_BASE_IDX 2 11125#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3 0x2985 11126#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU10_LANE3_BASE_IDX 2 11127#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3 0x2986 11128#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU11_LANE3_BASE_IDX 2 11129#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3 0x2987 11130#define mmDC_COMBOPHYTXREGS0_TX_DISP_RFU12_LANE3_BASE_IDX 2 11131 11132 11133// addressBlock: dce_dc_combophy_dc_combophypllregs0_dispdec 11134// base address: 0x0 11135#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0 0x2988 11136#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL0_BASE_IDX 2 11137#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1 0x2989 11138#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL1_BASE_IDX 2 11139#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2 0x298a 11140#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL2_BASE_IDX 2 11141#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3 0x298b 11142#define mmDC_COMBOPHYPLLREGS0_FREQ_CTRL3_BASE_IDX 2 11143#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE 0x298c 11144#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_COARSE_BASE_IDX 2 11145#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE 0x298d 11146#define mmDC_COMBOPHYPLLREGS0_BW_CTRL_FINE_BASE_IDX 2 11147#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL 0x298e 11148#define mmDC_COMBOPHYPLLREGS0_CAL_CTRL_BASE_IDX 2 11149#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL 0x298f 11150#define mmDC_COMBOPHYPLLREGS0_LOOP_CTRL_BASE_IDX 2 11151#define mmDC_COMBOPHYPLLREGS0_VREG_CFG 0x2991 11152#define mmDC_COMBOPHYPLLREGS0_VREG_CFG_BASE_IDX 2 11153#define mmDC_COMBOPHYPLLREGS0_OBSERVE0 0x2992 11154#define mmDC_COMBOPHYPLLREGS0_OBSERVE0_BASE_IDX 2 11155#define mmDC_COMBOPHYPLLREGS0_OBSERVE1 0x2993 11156#define mmDC_COMBOPHYPLLREGS0_OBSERVE1_BASE_IDX 2 11157#define mmDC_COMBOPHYPLLREGS0_DFT_OUT 0x2994 11158#define mmDC_COMBOPHYPLLREGS0_DFT_OUT_BASE_IDX 2 11159#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1 0x29c6 11160#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL1_BASE_IDX 2 11161#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL 0x29c7 11162#define mmDC_COMBOPHYPLLREGS0_PLL_WRAP_CNTRL_BASE_IDX 2 11163 11164 11165// addressBlock: dce_dc_dcio_dcio_uniphy1_dispdec 11166// base address: 0x360 11167#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0 0x2a00 11168#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11169#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1 0x2a01 11170#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11171#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2 0x2a02 11172#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11173#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3 0x2a03 11174#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11175#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4 0x2a04 11176#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11177#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5 0x2a05 11178#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11179#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6 0x2a06 11180#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11181#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7 0x2a07 11182#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11183#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8 0x2a08 11184#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11185#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9 0x2a09 11186#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11187#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10 0x2a0a 11188#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11189#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11 0x2a0b 11190#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11191#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12 0x2a0c 11192#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11193#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13 0x2a0d 11194#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11195#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14 0x2a0e 11196#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11197#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15 0x2a0f 11198#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11199#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16 0x2a10 11200#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11201#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17 0x2a11 11202#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11203#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18 0x2a12 11204#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11205#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19 0x2a13 11206#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11207#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20 0x2a14 11208#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11209#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21 0x2a15 11210#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11211#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22 0x2a16 11212#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11213#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23 0x2a17 11214#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11215#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24 0x2a18 11216#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11217#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25 0x2a19 11218#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11219#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26 0x2a1a 11220#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11221#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27 0x2a1b 11222#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11223#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28 0x2a1c 11224#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11225#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29 0x2a1d 11226#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11227#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30 0x2a1e 11228#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11229#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31 0x2a1f 11230#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11231#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32 0x2a20 11232#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11233#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33 0x2a21 11234#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11235#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34 0x2a22 11236#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11237#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35 0x2a23 11238#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11239#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36 0x2a24 11240#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11241#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37 0x2a25 11242#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11243#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38 0x2a26 11244#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11245#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39 0x2a27 11246#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11247#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40 0x2a28 11248#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11249#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41 0x2a29 11250#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11251#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42 0x2a2a 11252#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11253#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43 0x2a2b 11254#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11255#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44 0x2a2c 11256#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11257#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45 0x2a2d 11258#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11259#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46 0x2a2e 11260#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11261#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47 0x2a2f 11262#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11263#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48 0x2a30 11264#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11265#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49 0x2a31 11266#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11267#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50 0x2a32 11268#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11269#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51 0x2a33 11270#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11271#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52 0x2a34 11272#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11273#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53 0x2a35 11274#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11275#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54 0x2a36 11276#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11277#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55 0x2a37 11278#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11279#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56 0x2a38 11280#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11281#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57 0x2a39 11282#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11283#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58 0x2a3a 11284#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 11285#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59 0x2a3b 11286#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 11287#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60 0x2a3c 11288#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 11289#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61 0x2a3d 11290#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 11291#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62 0x2a3e 11292#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 11293#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63 0x2a3f 11294#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 11295#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64 0x2a40 11296#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 11297#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65 0x2a41 11298#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 11299#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66 0x2a42 11300#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 11301#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67 0x2a43 11302#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 11303#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68 0x2a44 11304#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 11305#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69 0x2a45 11306#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 11307#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70 0x2a46 11308#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 11309#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71 0x2a47 11310#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 11311#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72 0x2a48 11312#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 11313#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73 0x2a49 11314#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 11315#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74 0x2a4a 11316#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 11317#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75 0x2a4b 11318#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 11319#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76 0x2a4c 11320#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 11321#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77 0x2a4d 11322#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 11323#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78 0x2a4e 11324#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 11325#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79 0x2a4f 11326#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 11327#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80 0x2a50 11328#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 11329#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81 0x2a51 11330#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 11331#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82 0x2a52 11332#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 11333#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83 0x2a53 11334#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 11335#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84 0x2a54 11336#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 11337#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85 0x2a55 11338#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 11339#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86 0x2a56 11340#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 11341#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87 0x2a57 11342#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 11343#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88 0x2a58 11344#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 11345#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89 0x2a59 11346#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 11347#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90 0x2a5a 11348#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 11349#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91 0x2a5b 11350#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 11351#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92 0x2a5c 11352#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 11353#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93 0x2a5d 11354#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 11355#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94 0x2a5e 11356#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 11357#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95 0x2a5f 11358#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 11359#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96 0x2a60 11360#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 11361#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97 0x2a61 11362#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 11363#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98 0x2a62 11364#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 11365#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99 0x2a63 11366#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 11367#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100 0x2a64 11368#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 11369#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101 0x2a65 11370#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 11371#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102 0x2a66 11372#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 11373#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103 0x2a67 11374#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 11375#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104 0x2a68 11376#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 11377#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105 0x2a69 11378#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 11379#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106 0x2a6a 11380#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 11381#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107 0x2a6b 11382#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 11383#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108 0x2a6c 11384#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 11385#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109 0x2a6d 11386#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 11387#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110 0x2a6e 11388#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 11389#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111 0x2a6f 11390#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 11391#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112 0x2a70 11392#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 11393#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113 0x2a71 11394#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 11395#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114 0x2a72 11396#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 11397#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115 0x2a73 11398#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 11399#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116 0x2a74 11400#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 11401#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117 0x2a75 11402#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 11403#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118 0x2a76 11404#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 11405#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119 0x2a77 11406#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 11407#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120 0x2a78 11408#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 11409#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121 0x2a79 11410#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 11411#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122 0x2a7a 11412#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 11413#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123 0x2a7b 11414#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 11415#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124 0x2a7c 11416#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 11417#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125 0x2a7d 11418#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 11419#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126 0x2a7e 11420#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 11421#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127 0x2a7f 11422#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 11423#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128 0x2a80 11424#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 11425#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129 0x2a81 11426#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 11427#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130 0x2a82 11428#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 11429#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131 0x2a83 11430#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 11431#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132 0x2a84 11432#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 11433#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133 0x2a85 11434#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 11435#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134 0x2a86 11436#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 11437#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135 0x2a87 11438#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 11439#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136 0x2a88 11440#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 11441#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137 0x2a89 11442#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 11443#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138 0x2a8a 11444#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 11445#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139 0x2a8b 11446#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 11447#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140 0x2a8c 11448#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 11449#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141 0x2a8d 11450#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 11451#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142 0x2a8e 11452#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 11453#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143 0x2a8f 11454#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 11455#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144 0x2a90 11456#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 11457#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145 0x2a91 11458#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 11459#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146 0x2a92 11460#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 11461#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147 0x2a93 11462#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 11463#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148 0x2a94 11464#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 11465#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149 0x2a95 11466#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 11467#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150 0x2a96 11468#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 11469#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151 0x2a97 11470#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 11471#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152 0x2a98 11472#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 11473#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153 0x2a99 11474#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 11475#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154 0x2a9a 11476#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 11477#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155 0x2a9b 11478#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 11479#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156 0x2a9c 11480#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 11481#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157 0x2a9d 11482#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 11483#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158 0x2a9e 11484#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 11485#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159 0x2a9f 11486#define mmDCIO_UNIPHY1_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 11487 11488 11489// addressBlock: dce_dc_combophy_dc_combophycmregs1_dispdec 11490// base address: 0x360 11491#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1 0x2a00 11492#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE1_BASE_IDX 2 11493#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2 0x2a01 11494#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE2_BASE_IDX 2 11495#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3 0x2a02 11496#define mmDC_COMBOPHYCMREGS1_COMMON_FUSE3_BASE_IDX 2 11497#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM 0x2a03 11498#define mmDC_COMBOPHYCMREGS1_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 11499#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT 0x2a04 11500#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_PWRMGMT_BASE_IDX 2 11501#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL 0x2a05 11502#define mmDC_COMBOPHYCMREGS1_COMMON_TXCNTRL_BASE_IDX 2 11503#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP 0x2a06 11504#define mmDC_COMBOPHYCMREGS1_COMMON_TMDP_BASE_IDX 2 11505#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS 0x2a07 11506#define mmDC_COMBOPHYCMREGS1_COMMON_LANE_RESETS_BASE_IDX 2 11507#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL 0x2a08 11508#define mmDC_COMBOPHYCMREGS1_COMMON_ZCALCODE_CTRL_BASE_IDX 2 11509#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1 0x2a09 11510#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU1_BASE_IDX 2 11511#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2 0x2a0a 11512#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU2_BASE_IDX 2 11513#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3 0x2a0b 11514#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU3_BASE_IDX 2 11515#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4 0x2a0c 11516#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU4_BASE_IDX 2 11517#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5 0x2a0d 11518#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU5_BASE_IDX 2 11519#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6 0x2a0e 11520#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU6_BASE_IDX 2 11521#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7 0x2a0f 11522#define mmDC_COMBOPHYCMREGS1_COMMON_DISP_RFU7_BASE_IDX 2 11523 11524 11525// addressBlock: dce_dc_combophy_dc_combophytxregs1_dispdec 11526// base address: 0x360 11527#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0 0x2a20 11528#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 11529#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0 0x2a21 11530#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE0_BASE_IDX 2 11531#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2a22 11532#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 11533#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0 0x2a23 11534#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE0_BASE_IDX 2 11535#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0 0x2a24 11536#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE0_BASE_IDX 2 11537#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0 0x2a25 11538#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE0_BASE_IDX 2 11539#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0 0x2a26 11540#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE0_BASE_IDX 2 11541#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0 0x2a27 11542#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE0_BASE_IDX 2 11543#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0 0x2a28 11544#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE0_BASE_IDX 2 11545#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0 0x2a29 11546#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE0_BASE_IDX 2 11547#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0 0x2a2a 11548#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE0_BASE_IDX 2 11549#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0 0x2a2b 11550#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE0_BASE_IDX 2 11551#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0 0x2a2c 11552#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE0_BASE_IDX 2 11553#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0 0x2a2d 11554#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE0_BASE_IDX 2 11555#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0 0x2a2e 11556#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE0_BASE_IDX 2 11557#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0 0x2a2f 11558#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE0_BASE_IDX 2 11559#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1 0x2a30 11560#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 11561#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1 0x2a31 11562#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE1_BASE_IDX 2 11563#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2a32 11564#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 11565#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1 0x2a33 11566#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE1_BASE_IDX 2 11567#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1 0x2a34 11568#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE1_BASE_IDX 2 11569#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1 0x2a35 11570#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE1_BASE_IDX 2 11571#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1 0x2a36 11572#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE1_BASE_IDX 2 11573#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1 0x2a37 11574#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE1_BASE_IDX 2 11575#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1 0x2a38 11576#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE1_BASE_IDX 2 11577#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1 0x2a39 11578#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE1_BASE_IDX 2 11579#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1 0x2a3a 11580#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE1_BASE_IDX 2 11581#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1 0x2a3b 11582#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE1_BASE_IDX 2 11583#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1 0x2a3c 11584#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE1_BASE_IDX 2 11585#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1 0x2a3d 11586#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE1_BASE_IDX 2 11587#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1 0x2a3e 11588#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE1_BASE_IDX 2 11589#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1 0x2a3f 11590#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE1_BASE_IDX 2 11591#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2 0x2a40 11592#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 11593#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2 0x2a41 11594#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE2_BASE_IDX 2 11595#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2a42 11596#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 11597#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2 0x2a43 11598#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE2_BASE_IDX 2 11599#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2 0x2a44 11600#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE2_BASE_IDX 2 11601#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2 0x2a45 11602#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE2_BASE_IDX 2 11603#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2 0x2a46 11604#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE2_BASE_IDX 2 11605#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2 0x2a47 11606#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE2_BASE_IDX 2 11607#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2 0x2a48 11608#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE2_BASE_IDX 2 11609#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2 0x2a49 11610#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE2_BASE_IDX 2 11611#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2 0x2a4a 11612#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE2_BASE_IDX 2 11613#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2 0x2a4b 11614#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE2_BASE_IDX 2 11615#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2 0x2a4c 11616#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE2_BASE_IDX 2 11617#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2 0x2a4d 11618#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE2_BASE_IDX 2 11619#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2 0x2a4e 11620#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE2_BASE_IDX 2 11621#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2 0x2a4f 11622#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE2_BASE_IDX 2 11623#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3 0x2a50 11624#define mmDC_COMBOPHYTXREGS1_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 11625#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3 0x2a51 11626#define mmDC_COMBOPHYTXREGS1_MARGIN_DEEMPH_LANE3_BASE_IDX 2 11627#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2a52 11628#define mmDC_COMBOPHYTXREGS1_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 11629#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3 0x2a53 11630#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU0_LANE3_BASE_IDX 2 11631#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3 0x2a54 11632#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU1_LANE3_BASE_IDX 2 11633#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3 0x2a55 11634#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU2_LANE3_BASE_IDX 2 11635#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3 0x2a56 11636#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU3_LANE3_BASE_IDX 2 11637#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3 0x2a57 11638#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU4_LANE3_BASE_IDX 2 11639#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3 0x2a58 11640#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU5_LANE3_BASE_IDX 2 11641#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3 0x2a59 11642#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU6_LANE3_BASE_IDX 2 11643#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3 0x2a5a 11644#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU7_LANE3_BASE_IDX 2 11645#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3 0x2a5b 11646#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU8_LANE3_BASE_IDX 2 11647#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3 0x2a5c 11648#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU9_LANE3_BASE_IDX 2 11649#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3 0x2a5d 11650#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU10_LANE3_BASE_IDX 2 11651#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3 0x2a5e 11652#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU11_LANE3_BASE_IDX 2 11653#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3 0x2a5f 11654#define mmDC_COMBOPHYTXREGS1_TX_DISP_RFU12_LANE3_BASE_IDX 2 11655 11656 11657// addressBlock: dce_dc_combophy_dc_combophypllregs1_dispdec 11658// base address: 0x360 11659#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0 0x2a60 11660#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL0_BASE_IDX 2 11661#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1 0x2a61 11662#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL1_BASE_IDX 2 11663#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2 0x2a62 11664#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL2_BASE_IDX 2 11665#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3 0x2a63 11666#define mmDC_COMBOPHYPLLREGS1_FREQ_CTRL3_BASE_IDX 2 11667#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE 0x2a64 11668#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_COARSE_BASE_IDX 2 11669#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE 0x2a65 11670#define mmDC_COMBOPHYPLLREGS1_BW_CTRL_FINE_BASE_IDX 2 11671#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL 0x2a66 11672#define mmDC_COMBOPHYPLLREGS1_CAL_CTRL_BASE_IDX 2 11673#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL 0x2a67 11674#define mmDC_COMBOPHYPLLREGS1_LOOP_CTRL_BASE_IDX 2 11675#define mmDC_COMBOPHYPLLREGS1_VREG_CFG 0x2a69 11676#define mmDC_COMBOPHYPLLREGS1_VREG_CFG_BASE_IDX 2 11677#define mmDC_COMBOPHYPLLREGS1_OBSERVE0 0x2a6a 11678#define mmDC_COMBOPHYPLLREGS1_OBSERVE0_BASE_IDX 2 11679#define mmDC_COMBOPHYPLLREGS1_OBSERVE1 0x2a6b 11680#define mmDC_COMBOPHYPLLREGS1_OBSERVE1_BASE_IDX 2 11681#define mmDC_COMBOPHYPLLREGS1_DFT_OUT 0x2a6c 11682#define mmDC_COMBOPHYPLLREGS1_DFT_OUT_BASE_IDX 2 11683#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1 0x2a9e 11684#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL1_BASE_IDX 2 11685#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL 0x2a9f 11686#define mmDC_COMBOPHYPLLREGS1_PLL_WRAP_CNTRL_BASE_IDX 2 11687 11688 11689// addressBlock: dce_dc_dcio_dcio_uniphy2_dispdec 11690// base address: 0x6c0 11691#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0 0x2ad8 11692#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 11693#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1 0x2ad9 11694#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 11695#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2 0x2ada 11696#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 11697#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3 0x2adb 11698#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 11699#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4 0x2adc 11700#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 11701#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5 0x2add 11702#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 11703#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6 0x2ade 11704#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 11705#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7 0x2adf 11706#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 11707#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8 0x2ae0 11708#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 11709#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9 0x2ae1 11710#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 11711#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10 0x2ae2 11712#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 11713#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11 0x2ae3 11714#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 11715#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12 0x2ae4 11716#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 11717#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13 0x2ae5 11718#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 11719#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14 0x2ae6 11720#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 11721#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15 0x2ae7 11722#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 11723#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16 0x2ae8 11724#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 11725#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17 0x2ae9 11726#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 11727#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18 0x2aea 11728#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 11729#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19 0x2aeb 11730#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 11731#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20 0x2aec 11732#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 11733#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21 0x2aed 11734#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 11735#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22 0x2aee 11736#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 11737#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23 0x2aef 11738#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 11739#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24 0x2af0 11740#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 11741#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25 0x2af1 11742#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 11743#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26 0x2af2 11744#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 11745#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27 0x2af3 11746#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 11747#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28 0x2af4 11748#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 11749#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29 0x2af5 11750#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 11751#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30 0x2af6 11752#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 11753#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31 0x2af7 11754#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 11755#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32 0x2af8 11756#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 11757#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33 0x2af9 11758#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 11759#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34 0x2afa 11760#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 11761#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35 0x2afb 11762#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 11763#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36 0x2afc 11764#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 11765#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37 0x2afd 11766#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 11767#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38 0x2afe 11768#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 11769#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39 0x2aff 11770#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 11771#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40 0x2b00 11772#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 11773#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41 0x2b01 11774#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 11775#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42 0x2b02 11776#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 11777#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43 0x2b03 11778#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 11779#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44 0x2b04 11780#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 11781#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45 0x2b05 11782#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 11783#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46 0x2b06 11784#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 11785#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47 0x2b07 11786#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 11787#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48 0x2b08 11788#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 11789#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49 0x2b09 11790#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 11791#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50 0x2b0a 11792#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 11793#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51 0x2b0b 11794#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 11795#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52 0x2b0c 11796#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 11797#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53 0x2b0d 11798#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 11799#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54 0x2b0e 11800#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 11801#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55 0x2b0f 11802#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 11803#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56 0x2b10 11804#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 11805#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57 0x2b11 11806#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 11807#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58 0x2b12 11808#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 11809#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59 0x2b13 11810#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 11811#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60 0x2b14 11812#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 11813#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61 0x2b15 11814#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 11815#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62 0x2b16 11816#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 11817#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63 0x2b17 11818#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 11819#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64 0x2b18 11820#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 11821#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65 0x2b19 11822#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 11823#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66 0x2b1a 11824#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 11825#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67 0x2b1b 11826#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 11827#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68 0x2b1c 11828#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 11829#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69 0x2b1d 11830#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 11831#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70 0x2b1e 11832#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 11833#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71 0x2b1f 11834#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 11835#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72 0x2b20 11836#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 11837#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73 0x2b21 11838#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 11839#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74 0x2b22 11840#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 11841#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75 0x2b23 11842#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 11843#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76 0x2b24 11844#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 11845#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77 0x2b25 11846#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 11847#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78 0x2b26 11848#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 11849#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79 0x2b27 11850#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 11851#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80 0x2b28 11852#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 11853#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81 0x2b29 11854#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 11855#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82 0x2b2a 11856#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 11857#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83 0x2b2b 11858#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 11859#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84 0x2b2c 11860#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 11861#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85 0x2b2d 11862#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 11863#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86 0x2b2e 11864#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 11865#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87 0x2b2f 11866#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 11867#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88 0x2b30 11868#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 11869#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89 0x2b31 11870#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 11871#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90 0x2b32 11872#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 11873#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91 0x2b33 11874#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 11875#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92 0x2b34 11876#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 11877#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93 0x2b35 11878#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 11879#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94 0x2b36 11880#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 11881#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95 0x2b37 11882#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 11883#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96 0x2b38 11884#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 11885#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97 0x2b39 11886#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 11887#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98 0x2b3a 11888#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 11889#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99 0x2b3b 11890#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 11891#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100 0x2b3c 11892#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 11893#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101 0x2b3d 11894#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 11895#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102 0x2b3e 11896#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 11897#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103 0x2b3f 11898#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 11899#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104 0x2b40 11900#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 11901#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105 0x2b41 11902#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 11903#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106 0x2b42 11904#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 11905#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107 0x2b43 11906#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 11907#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108 0x2b44 11908#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 11909#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109 0x2b45 11910#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 11911#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110 0x2b46 11912#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 11913#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111 0x2b47 11914#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 11915#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112 0x2b48 11916#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 11917#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113 0x2b49 11918#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 11919#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114 0x2b4a 11920#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 11921#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115 0x2b4b 11922#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 11923#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116 0x2b4c 11924#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 11925#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117 0x2b4d 11926#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 11927#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118 0x2b4e 11928#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 11929#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119 0x2b4f 11930#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 11931#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120 0x2b50 11932#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 11933#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121 0x2b51 11934#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 11935#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122 0x2b52 11936#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 11937#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123 0x2b53 11938#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 11939#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124 0x2b54 11940#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 11941#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125 0x2b55 11942#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 11943#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126 0x2b56 11944#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 11945#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127 0x2b57 11946#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 11947#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128 0x2b58 11948#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 11949#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129 0x2b59 11950#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 11951#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130 0x2b5a 11952#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 11953#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131 0x2b5b 11954#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 11955#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132 0x2b5c 11956#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 11957#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133 0x2b5d 11958#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 11959#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134 0x2b5e 11960#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 11961#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135 0x2b5f 11962#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 11963#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136 0x2b60 11964#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 11965#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137 0x2b61 11966#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 11967#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138 0x2b62 11968#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 11969#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139 0x2b63 11970#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 11971#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140 0x2b64 11972#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 11973#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141 0x2b65 11974#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 11975#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142 0x2b66 11976#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 11977#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143 0x2b67 11978#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 11979#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144 0x2b68 11980#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 11981#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145 0x2b69 11982#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 11983#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146 0x2b6a 11984#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 11985#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147 0x2b6b 11986#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 11987#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148 0x2b6c 11988#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 11989#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149 0x2b6d 11990#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 11991#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150 0x2b6e 11992#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 11993#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151 0x2b6f 11994#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 11995#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152 0x2b70 11996#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 11997#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153 0x2b71 11998#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 11999#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154 0x2b72 12000#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2
12001#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155 0x2b73 12002#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 12003#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156 0x2b74 12004#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 12005#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157 0x2b75 12006#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 12007#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158 0x2b76 12008#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 12009#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159 0x2b77 12010#define mmDCIO_UNIPHY2_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 12011 12012 12013// addressBlock: dce_dc_combophy_dc_combophycmregs2_dispdec 12014// base address: 0x6c0 12015#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1 0x2ad8 12016#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE1_BASE_IDX 2 12017#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2 0x2ad9 12018#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE2_BASE_IDX 2 12019#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3 0x2ada 12020#define mmDC_COMBOPHYCMREGS2_COMMON_FUSE3_BASE_IDX 2 12021#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM 0x2adb 12022#define mmDC_COMBOPHYCMREGS2_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 12023#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT 0x2adc 12024#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_PWRMGMT_BASE_IDX 2 12025#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL 0x2add 12026#define mmDC_COMBOPHYCMREGS2_COMMON_TXCNTRL_BASE_IDX 2 12027#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP 0x2ade 12028#define mmDC_COMBOPHYCMREGS2_COMMON_TMDP_BASE_IDX 2 12029#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS 0x2adf 12030#define mmDC_COMBOPHYCMREGS2_COMMON_LANE_RESETS_BASE_IDX 2 12031#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL 0x2ae0 12032#define mmDC_COMBOPHYCMREGS2_COMMON_ZCALCODE_CTRL_BASE_IDX 2 12033#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1 0x2ae1 12034#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU1_BASE_IDX 2 12035#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2 0x2ae2 12036#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU2_BASE_IDX 2 12037#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3 0x2ae3 12038#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU3_BASE_IDX 2 12039#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4 0x2ae4 12040#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU4_BASE_IDX 2 12041#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5 0x2ae5 12042#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU5_BASE_IDX 2 12043#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6 0x2ae6 12044#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU6_BASE_IDX 2 12045#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7 0x2ae7 12046#define mmDC_COMBOPHYCMREGS2_COMMON_DISP_RFU7_BASE_IDX 2 12047 12048 12049// addressBlock: dce_dc_combophy_dc_combophytxregs2_dispdec 12050// base address: 0x6c0 12051#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0 0x2af8 12052#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 12053#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0 0x2af9 12054#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE0_BASE_IDX 2 12055#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2afa 12056#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 12057#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0 0x2afb 12058#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE0_BASE_IDX 2 12059#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0 0x2afc 12060#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE0_BASE_IDX 2 12061#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0 0x2afd 12062#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE0_BASE_IDX 2 12063#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0 0x2afe 12064#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE0_BASE_IDX 2 12065#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0 0x2aff 12066#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE0_BASE_IDX 2 12067#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0 0x2b00 12068#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE0_BASE_IDX 2 12069#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0 0x2b01 12070#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE0_BASE_IDX 2 12071#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0 0x2b02 12072#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE0_BASE_IDX 2 12073#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0 0x2b03 12074#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE0_BASE_IDX 2 12075#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0 0x2b04 12076#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE0_BASE_IDX 2 12077#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0 0x2b05 12078#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE0_BASE_IDX 2 12079#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0 0x2b06 12080#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE0_BASE_IDX 2 12081#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0 0x2b07 12082#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE0_BASE_IDX 2 12083#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1 0x2b08 12084#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 12085#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1 0x2b09 12086#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE1_BASE_IDX 2 12087#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2b0a 12088#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 12089#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1 0x2b0b 12090#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE1_BASE_IDX 2 12091#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1 0x2b0c 12092#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE1_BASE_IDX 2 12093#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1 0x2b0d 12094#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE1_BASE_IDX 2 12095#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1 0x2b0e 12096#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE1_BASE_IDX 2 12097#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1 0x2b0f 12098#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE1_BASE_IDX 2 12099#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1 0x2b10 12100#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE1_BASE_IDX 2 12101#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1 0x2b11 12102#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE1_BASE_IDX 2 12103#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1 0x2b12 12104#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE1_BASE_IDX 2 12105#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1 0x2b13 12106#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE1_BASE_IDX 2 12107#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1 0x2b14 12108#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE1_BASE_IDX 2 12109#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1 0x2b15 12110#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE1_BASE_IDX 2 12111#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1 0x2b16 12112#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE1_BASE_IDX 2 12113#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1 0x2b17 12114#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE1_BASE_IDX 2 12115#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2 0x2b18 12116#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 12117#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2 0x2b19 12118#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE2_BASE_IDX 2 12119#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2b1a 12120#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 12121#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2 0x2b1b 12122#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE2_BASE_IDX 2 12123#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2 0x2b1c 12124#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE2_BASE_IDX 2 12125#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2 0x2b1d 12126#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE2_BASE_IDX 2 12127#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2 0x2b1e 12128#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE2_BASE_IDX 2 12129#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2 0x2b1f 12130#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE2_BASE_IDX 2 12131#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2 0x2b20 12132#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE2_BASE_IDX 2 12133#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2 0x2b21 12134#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE2_BASE_IDX 2 12135#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2 0x2b22 12136#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE2_BASE_IDX 2 12137#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2 0x2b23 12138#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE2_BASE_IDX 2 12139#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2 0x2b24 12140#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE2_BASE_IDX 2 12141#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2 0x2b25 12142#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE2_BASE_IDX 2 12143#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2 0x2b26 12144#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE2_BASE_IDX 2 12145#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2 0x2b27 12146#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE2_BASE_IDX 2 12147#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3 0x2b28 12148#define mmDC_COMBOPHYTXREGS2_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 12149#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3 0x2b29 12150#define mmDC_COMBOPHYTXREGS2_MARGIN_DEEMPH_LANE3_BASE_IDX 2 12151#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2b2a 12152#define mmDC_COMBOPHYTXREGS2_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 12153#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3 0x2b2b 12154#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU0_LANE3_BASE_IDX 2 12155#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3 0x2b2c 12156#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU1_LANE3_BASE_IDX 2 12157#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3 0x2b2d 12158#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU2_LANE3_BASE_IDX 2 12159#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3 0x2b2e 12160#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU3_LANE3_BASE_IDX 2 12161#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3 0x2b2f 12162#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU4_LANE3_BASE_IDX 2 12163#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3 0x2b30 12164#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU5_LANE3_BASE_IDX 2 12165#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3 0x2b31 12166#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU6_LANE3_BASE_IDX 2 12167#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3 0x2b32 12168#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU7_LANE3_BASE_IDX 2 12169#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3 0x2b33 12170#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU8_LANE3_BASE_IDX 2 12171#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3 0x2b34 12172#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU9_LANE3_BASE_IDX 2 12173#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3 0x2b35 12174#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU10_LANE3_BASE_IDX 2 12175#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3 0x2b36 12176#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU11_LANE3_BASE_IDX 2 12177#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3 0x2b37 12178#define mmDC_COMBOPHYTXREGS2_TX_DISP_RFU12_LANE3_BASE_IDX 2 12179 12180 12181// addressBlock: dce_dc_combophy_dc_combophypllregs2_dispdec 12182// base address: 0x6c0 12183#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0 0x2b38 12184#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL0_BASE_IDX 2 12185#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1 0x2b39 12186#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL1_BASE_IDX 2 12187#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2 0x2b3a 12188#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL2_BASE_IDX 2 12189#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3 0x2b3b 12190#define mmDC_COMBOPHYPLLREGS2_FREQ_CTRL3_BASE_IDX 2 12191#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE 0x2b3c 12192#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_COARSE_BASE_IDX 2 12193#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE 0x2b3d 12194#define mmDC_COMBOPHYPLLREGS2_BW_CTRL_FINE_BASE_IDX 2 12195#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL 0x2b3e 12196#define mmDC_COMBOPHYPLLREGS2_CAL_CTRL_BASE_IDX 2 12197#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL 0x2b3f 12198#define mmDC_COMBOPHYPLLREGS2_LOOP_CTRL_BASE_IDX 2 12199#define mmDC_COMBOPHYPLLREGS2_VREG_CFG 0x2b41 12200#define mmDC_COMBOPHYPLLREGS2_VREG_CFG_BASE_IDX 2 12201#define mmDC_COMBOPHYPLLREGS2_OBSERVE0 0x2b42 12202#define mmDC_COMBOPHYPLLREGS2_OBSERVE0_BASE_IDX 2 12203#define mmDC_COMBOPHYPLLREGS2_OBSERVE1 0x2b43 12204#define mmDC_COMBOPHYPLLREGS2_OBSERVE1_BASE_IDX 2 12205#define mmDC_COMBOPHYPLLREGS2_DFT_OUT 0x2b44 12206#define mmDC_COMBOPHYPLLREGS2_DFT_OUT_BASE_IDX 2 12207#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1 0x2b76 12208#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL1_BASE_IDX 2 12209#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL 0x2b77 12210#define mmDC_COMBOPHYPLLREGS2_PLL_WRAP_CNTRL_BASE_IDX 2 12211 12212 12213// addressBlock: dce_dc_dcio_dcio_uniphy3_dispdec 12214// base address: 0xa20 12215#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0 0x2bb0 12216#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED0_BASE_IDX 2 12217#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1 0x2bb1 12218#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED1_BASE_IDX 2 12219#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2 0x2bb2 12220#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED2_BASE_IDX 2 12221#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3 0x2bb3 12222#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED3_BASE_IDX 2 12223#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4 0x2bb4 12224#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED4_BASE_IDX 2 12225#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5 0x2bb5 12226#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED5_BASE_IDX 2 12227#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6 0x2bb6 12228#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED6_BASE_IDX 2 12229#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7 0x2bb7 12230#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED7_BASE_IDX 2 12231#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8 0x2bb8 12232#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED8_BASE_IDX 2 12233#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9 0x2bb9 12234#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED9_BASE_IDX 2 12235#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10 0x2bba 12236#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED10_BASE_IDX 2 12237#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11 0x2bbb 12238#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED11_BASE_IDX 2 12239#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12 0x2bbc 12240#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED12_BASE_IDX 2 12241#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13 0x2bbd 12242#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED13_BASE_IDX 2 12243#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14 0x2bbe 12244#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED14_BASE_IDX 2 12245#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15 0x2bbf 12246#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED15_BASE_IDX 2 12247#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16 0x2bc0 12248#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED16_BASE_IDX 2 12249#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17 0x2bc1 12250#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED17_BASE_IDX 2 12251#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18 0x2bc2 12252#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED18_BASE_IDX 2 12253#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19 0x2bc3 12254#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED19_BASE_IDX 2 12255#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20 0x2bc4 12256#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED20_BASE_IDX 2 12257#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21 0x2bc5 12258#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED21_BASE_IDX 2 12259#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22 0x2bc6 12260#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED22_BASE_IDX 2 12261#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23 0x2bc7 12262#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED23_BASE_IDX 2 12263#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24 0x2bc8 12264#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED24_BASE_IDX 2 12265#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25 0x2bc9 12266#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED25_BASE_IDX 2 12267#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26 0x2bca 12268#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED26_BASE_IDX 2 12269#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27 0x2bcb 12270#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED27_BASE_IDX 2 12271#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28 0x2bcc 12272#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED28_BASE_IDX 2 12273#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29 0x2bcd 12274#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED29_BASE_IDX 2 12275#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30 0x2bce 12276#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED30_BASE_IDX 2 12277#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31 0x2bcf 12278#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED31_BASE_IDX 2 12279#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32 0x2bd0 12280#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED32_BASE_IDX 2 12281#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33 0x2bd1 12282#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED33_BASE_IDX 2 12283#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34 0x2bd2 12284#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED34_BASE_IDX 2 12285#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35 0x2bd3 12286#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED35_BASE_IDX 2 12287#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36 0x2bd4 12288#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED36_BASE_IDX 2 12289#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37 0x2bd5 12290#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED37_BASE_IDX 2 12291#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38 0x2bd6 12292#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED38_BASE_IDX 2 12293#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39 0x2bd7 12294#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED39_BASE_IDX 2 12295#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40 0x2bd8 12296#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED40_BASE_IDX 2 12297#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41 0x2bd9 12298#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED41_BASE_IDX 2 12299#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42 0x2bda 12300#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED42_BASE_IDX 2 12301#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43 0x2bdb 12302#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED43_BASE_IDX 2 12303#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44 0x2bdc 12304#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED44_BASE_IDX 2 12305#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45 0x2bdd 12306#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED45_BASE_IDX 2 12307#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46 0x2bde 12308#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED46_BASE_IDX 2 12309#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47 0x2bdf 12310#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED47_BASE_IDX 2 12311#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48 0x2be0 12312#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED48_BASE_IDX 2 12313#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49 0x2be1 12314#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED49_BASE_IDX 2 12315#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50 0x2be2 12316#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED50_BASE_IDX 2 12317#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51 0x2be3 12318#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED51_BASE_IDX 2 12319#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52 0x2be4 12320#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED52_BASE_IDX 2 12321#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53 0x2be5 12322#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED53_BASE_IDX 2 12323#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54 0x2be6 12324#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED54_BASE_IDX 2 12325#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55 0x2be7 12326#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED55_BASE_IDX 2 12327#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56 0x2be8 12328#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED56_BASE_IDX 2 12329#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57 0x2be9 12330#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED57_BASE_IDX 2 12331#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58 0x2bea 12332#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED58_BASE_IDX 2 12333#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59 0x2beb 12334#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED59_BASE_IDX 2 12335#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60 0x2bec 12336#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED60_BASE_IDX 2 12337#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61 0x2bed 12338#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED61_BASE_IDX 2 12339#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62 0x2bee 12340#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED62_BASE_IDX 2 12341#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63 0x2bef 12342#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED63_BASE_IDX 2 12343#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64 0x2bf0 12344#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED64_BASE_IDX 2 12345#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65 0x2bf1 12346#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED65_BASE_IDX 2 12347#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66 0x2bf2 12348#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED66_BASE_IDX 2 12349#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67 0x2bf3 12350#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED67_BASE_IDX 2 12351#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68 0x2bf4 12352#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED68_BASE_IDX 2 12353#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69 0x2bf5 12354#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED69_BASE_IDX 2 12355#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70 0x2bf6 12356#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED70_BASE_IDX 2 12357#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71 0x2bf7 12358#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED71_BASE_IDX 2 12359#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72 0x2bf8 12360#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED72_BASE_IDX 2 12361#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73 0x2bf9 12362#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED73_BASE_IDX 2 12363#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74 0x2bfa 12364#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED74_BASE_IDX 2 12365#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75 0x2bfb 12366#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED75_BASE_IDX 2 12367#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76 0x2bfc 12368#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED76_BASE_IDX 2 12369#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77 0x2bfd 12370#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED77_BASE_IDX 2 12371#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78 0x2bfe 12372#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED78_BASE_IDX 2 12373#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79 0x2bff 12374#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED79_BASE_IDX 2 12375#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80 0x2c00 12376#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED80_BASE_IDX 2 12377#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81 0x2c01 12378#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED81_BASE_IDX 2 12379#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82 0x2c02 12380#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED82_BASE_IDX 2 12381#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83 0x2c03 12382#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED83_BASE_IDX 2 12383#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84 0x2c04 12384#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED84_BASE_IDX 2 12385#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85 0x2c05 12386#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED85_BASE_IDX 2 12387#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86 0x2c06 12388#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED86_BASE_IDX 2 12389#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87 0x2c07 12390#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED87_BASE_IDX 2 12391#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88 0x2c08 12392#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED88_BASE_IDX 2 12393#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89 0x2c09 12394#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED89_BASE_IDX 2 12395#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90 0x2c0a 12396#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED90_BASE_IDX 2 12397#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91 0x2c0b 12398#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED91_BASE_IDX 2 12399#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92 0x2c0c 12400#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED92_BASE_IDX 2 12401#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93 0x2c0d 12402#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED93_BASE_IDX 2 12403#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94 0x2c0e 12404#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED94_BASE_IDX 2 12405#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95 0x2c0f 12406#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED95_BASE_IDX 2 12407#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96 0x2c10 12408#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED96_BASE_IDX 2 12409#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97 0x2c11 12410#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED97_BASE_IDX 2 12411#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98 0x2c12 12412#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED98_BASE_IDX 2 12413#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99 0x2c13 12414#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED99_BASE_IDX 2 12415#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100 0x2c14 12416#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED100_BASE_IDX 2 12417#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101 0x2c15 12418#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED101_BASE_IDX 2 12419#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102 0x2c16 12420#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED102_BASE_IDX 2 12421#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103 0x2c17 12422#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED103_BASE_IDX 2 12423#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104 0x2c18 12424#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED104_BASE_IDX 2 12425#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105 0x2c19 12426#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED105_BASE_IDX 2 12427#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106 0x2c1a 12428#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED106_BASE_IDX 2 12429#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107 0x2c1b 12430#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED107_BASE_IDX 2 12431#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108 0x2c1c 12432#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED108_BASE_IDX 2 12433#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109 0x2c1d 12434#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED109_BASE_IDX 2 12435#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110 0x2c1e 12436#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED110_BASE_IDX 2 12437#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111 0x2c1f 12438#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED111_BASE_IDX 2 12439#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112 0x2c20 12440#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED112_BASE_IDX 2 12441#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113 0x2c21 12442#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED113_BASE_IDX 2 12443#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114 0x2c22 12444#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED114_BASE_IDX 2 12445#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115 0x2c23 12446#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED115_BASE_IDX 2 12447#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116 0x2c24 12448#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED116_BASE_IDX 2 12449#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117 0x2c25 12450#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED117_BASE_IDX 2 12451#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118 0x2c26 12452#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED118_BASE_IDX 2 12453#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119 0x2c27 12454#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED119_BASE_IDX 2 12455#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120 0x2c28 12456#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED120_BASE_IDX 2 12457#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121 0x2c29 12458#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED121_BASE_IDX 2 12459#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122 0x2c2a 12460#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED122_BASE_IDX 2 12461#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123 0x2c2b 12462#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED123_BASE_IDX 2 12463#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124 0x2c2c 12464#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED124_BASE_IDX 2 12465#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125 0x2c2d 12466#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED125_BASE_IDX 2 12467#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126 0x2c2e 12468#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED126_BASE_IDX 2 12469#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127 0x2c2f 12470#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED127_BASE_IDX 2 12471#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128 0x2c30 12472#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED128_BASE_IDX 2 12473#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129 0x2c31 12474#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED129_BASE_IDX 2 12475#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130 0x2c32 12476#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED130_BASE_IDX 2 12477#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131 0x2c33 12478#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED131_BASE_IDX 2 12479#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132 0x2c34 12480#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED132_BASE_IDX 2 12481#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133 0x2c35 12482#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED133_BASE_IDX 2 12483#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134 0x2c36 12484#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED134_BASE_IDX 2 12485#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135 0x2c37 12486#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED135_BASE_IDX 2 12487#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136 0x2c38 12488#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED136_BASE_IDX 2 12489#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137 0x2c39 12490#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED137_BASE_IDX 2 12491#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138 0x2c3a 12492#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED138_BASE_IDX 2 12493#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139 0x2c3b 12494#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED139_BASE_IDX 2 12495#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140 0x2c3c 12496#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED140_BASE_IDX 2 12497#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141 0x2c3d 12498#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED141_BASE_IDX 2 12499#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142 0x2c3e 12500#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED142_BASE_IDX 2 12501#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143 0x2c3f 12502#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED143_BASE_IDX 2 12503#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144 0x2c40 12504#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED144_BASE_IDX 2 12505#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145 0x2c41 12506#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED145_BASE_IDX 2 12507#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146 0x2c42 12508#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED146_BASE_IDX 2 12509#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147 0x2c43 12510#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED147_BASE_IDX 2 12511#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148 0x2c44 12512#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED148_BASE_IDX 2 12513#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149 0x2c45 12514#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED149_BASE_IDX 2 12515#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150 0x2c46 12516#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED150_BASE_IDX 2 12517#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151 0x2c47 12518#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED151_BASE_IDX 2 12519#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152 0x2c48 12520#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED152_BASE_IDX 2 12521#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153 0x2c49 12522#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED153_BASE_IDX 2 12523#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154 0x2c4a 12524#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED154_BASE_IDX 2 12525#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155 0x2c4b 12526#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED155_BASE_IDX 2 12527#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156 0x2c4c 12528#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED156_BASE_IDX 2 12529#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157 0x2c4d 12530#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED157_BASE_IDX 2 12531#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158 0x2c4e 12532#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED158_BASE_IDX 2 12533#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159 0x2c4f 12534#define mmDCIO_UNIPHY3_UNIPHY_MACRO_CNTL_RESERVED159_BASE_IDX 2 12535 12536 12537// addressBlock: dce_dc_combophy_dc_combophycmregs3_dispdec 12538// base address: 0xa20 12539#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1 0x2bb0 12540#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE1_BASE_IDX 2 12541#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2 0x2bb1 12542#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE2_BASE_IDX 2 12543#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3 0x2bb2 12544#define mmDC_COMBOPHYCMREGS3_COMMON_FUSE3_BASE_IDX 2 12545#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM 0x2bb3 12546#define mmDC_COMBOPHYCMREGS3_COMMON_MAR_DEEMPH_NOM_BASE_IDX 2 12547#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT 0x2bb4 12548#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_PWRMGMT_BASE_IDX 2 12549#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL 0x2bb5 12550#define mmDC_COMBOPHYCMREGS3_COMMON_TXCNTRL_BASE_IDX 2 12551#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP 0x2bb6 12552#define mmDC_COMBOPHYCMREGS3_COMMON_TMDP_BASE_IDX 2 12553#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS 0x2bb7 12554#define mmDC_COMBOPHYCMREGS3_COMMON_LANE_RESETS_BASE_IDX 2 12555#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL 0x2bb8 12556#define mmDC_COMBOPHYCMREGS3_COMMON_ZCALCODE_CTRL_BASE_IDX 2 12557#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1 0x2bb9 12558#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU1_BASE_IDX 2 12559#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2 0x2bba 12560#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU2_BASE_IDX 2 12561#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3 0x2bbb 12562#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU3_BASE_IDX 2 12563#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4 0x2bbc 12564#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU4_BASE_IDX 2 12565#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5 0x2bbd 12566#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU5_BASE_IDX 2 12567#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6 0x2bbe 12568#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU6_BASE_IDX 2 12569#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7 0x2bbf 12570#define mmDC_COMBOPHYCMREGS3_COMMON_DISP_RFU7_BASE_IDX 2 12571 12572 12573// addressBlock: dce_dc_combophy_dc_combophytxregs3_dispdec 12574// base address: 0xa20 12575#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0 0x2bd0 12576#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE0_BASE_IDX 2 12577#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0 0x2bd1 12578#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE0_BASE_IDX 2 12579#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0 0x2bd2 12580#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE0_BASE_IDX 2 12581#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0 0x2bd3 12582#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE0_BASE_IDX 2 12583#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0 0x2bd4 12584#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE0_BASE_IDX 2 12585#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0 0x2bd5 12586#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE0_BASE_IDX 2 12587#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0 0x2bd6 12588#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE0_BASE_IDX 2 12589#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0 0x2bd7 12590#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE0_BASE_IDX 2 12591#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0 0x2bd8 12592#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE0_BASE_IDX 2 12593#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0 0x2bd9 12594#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE0_BASE_IDX 2 12595#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0 0x2bda 12596#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE0_BASE_IDX 2 12597#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0 0x2bdb 12598#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE0_BASE_IDX 2 12599#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0 0x2bdc 12600#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE0_BASE_IDX 2 12601#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0 0x2bdd 12602#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE0_BASE_IDX 2 12603#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0 0x2bde 12604#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE0_BASE_IDX 2 12605#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0 0x2bdf 12606#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE0_BASE_IDX 2 12607#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1 0x2be0 12608#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE1_BASE_IDX 2 12609#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1 0x2be1 12610#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE1_BASE_IDX 2 12611#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1 0x2be2 12612#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE1_BASE_IDX 2 12613#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1 0x2be3 12614#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE1_BASE_IDX 2 12615#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1 0x2be4 12616#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE1_BASE_IDX 2 12617#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1 0x2be5 12618#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE1_BASE_IDX 2 12619#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1 0x2be6 12620#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE1_BASE_IDX 2 12621#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1 0x2be7 12622#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE1_BASE_IDX 2 12623#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1 0x2be8 12624#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE1_BASE_IDX 2 12625#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1 0x2be9 12626#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE1_BASE_IDX 2 12627#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1 0x2bea 12628#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE1_BASE_IDX 2 12629#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1 0x2beb 12630#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE1_BASE_IDX 2 12631#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1 0x2bec 12632#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE1_BASE_IDX 2 12633#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1 0x2bed 12634#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE1_BASE_IDX 2 12635#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1 0x2bee 12636#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE1_BASE_IDX 2 12637#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1 0x2bef 12638#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE1_BASE_IDX 2 12639#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2 0x2bf0 12640#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE2_BASE_IDX 2 12641#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2 0x2bf1 12642#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE2_BASE_IDX 2 12643#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2 0x2bf2 12644#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE2_BASE_IDX 2 12645#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2 0x2bf3 12646#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE2_BASE_IDX 2 12647#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2 0x2bf4 12648#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE2_BASE_IDX 2 12649#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2 0x2bf5 12650#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE2_BASE_IDX 2 12651#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2 0x2bf6 12652#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE2_BASE_IDX 2 12653#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2 0x2bf7 12654#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE2_BASE_IDX 2 12655#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2 0x2bf8 12656#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE2_BASE_IDX 2 12657#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2 0x2bf9 12658#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE2_BASE_IDX 2 12659#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2 0x2bfa 12660#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE2_BASE_IDX 2 12661#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2 0x2bfb 12662#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE2_BASE_IDX 2 12663#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2 0x2bfc 12664#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE2_BASE_IDX 2 12665#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2 0x2bfd 12666#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE2_BASE_IDX 2 12667#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2 0x2bfe 12668#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE2_BASE_IDX 2 12669#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2 0x2bff 12670#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE2_BASE_IDX 2 12671#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3 0x2c00 12672#define mmDC_COMBOPHYTXREGS3_CMD_BUS_TX_CONTROL_LANE3_BASE_IDX 2 12673#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3 0x2c01 12674#define mmDC_COMBOPHYTXREGS3_MARGIN_DEEMPH_LANE3_BASE_IDX 2 12675#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3 0x2c02 12676#define mmDC_COMBOPHYTXREGS3_CMD_BUS_GLOBAL_FOR_TX_LANE3_BASE_IDX 2 12677#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3 0x2c03 12678#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU0_LANE3_BASE_IDX 2 12679#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3 0x2c04 12680#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU1_LANE3_BASE_IDX 2 12681#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3 0x2c05 12682#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU2_LANE3_BASE_IDX 2 12683#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3 0x2c06 12684#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU3_LANE3_BASE_IDX 2 12685#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3 0x2c07 12686#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU4_LANE3_BASE_IDX 2 12687#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3 0x2c08 12688#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU5_LANE3_BASE_IDX 2 12689#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3 0x2c09 12690#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU6_LANE3_BASE_IDX 2 12691#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3 0x2c0a 12692#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU7_LANE3_BASE_IDX 2 12693#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3 0x2c0b 12694#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU8_LANE3_BASE_IDX 2 12695#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3 0x2c0c 12696#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU9_LANE3_BASE_IDX 2 12697#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3 0x2c0d 12698#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU10_LANE3_BASE_IDX 2 12699#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3 0x2c0e 12700#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU11_LANE3_BASE_IDX 2 12701#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3 0x2c0f 12702#define mmDC_COMBOPHYTXREGS3_TX_DISP_RFU12_LANE3_BASE_IDX 2 12703 12704 12705// addressBlock: dce_dc_combophy_dc_combophypllregs3_dispdec 12706// base address: 0xa20 12707#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0 0x2c10 12708#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL0_BASE_IDX 2 12709#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1 0x2c11 12710#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL1_BASE_IDX 2 12711#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2 0x2c12 12712#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL2_BASE_IDX 2 12713#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3 0x2c13 12714#define mmDC_COMBOPHYPLLREGS3_FREQ_CTRL3_BASE_IDX 2 12715#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE 0x2c14 12716#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_COARSE_BASE_IDX 2 12717#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE 0x2c15 12718#define mmDC_COMBOPHYPLLREGS3_BW_CTRL_FINE_BASE_IDX 2 12719#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL 0x2c16 12720#define mmDC_COMBOPHYPLLREGS3_CAL_CTRL_BASE_IDX 2 12721#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL 0x2c17 12722#define mmDC_COMBOPHYPLLREGS3_LOOP_CTRL_BASE_IDX 2 12723#define mmDC_COMBOPHYPLLREGS3_VREG_CFG 0x2c19 12724#define mmDC_COMBOPHYPLLREGS3_VREG_CFG_BASE_IDX 2 12725#define mmDC_COMBOPHYPLLREGS3_OBSERVE0 0x2c1a 12726#define mmDC_COMBOPHYPLLREGS3_OBSERVE0_BASE_IDX 2 12727#define mmDC_COMBOPHYPLLREGS3_OBSERVE1 0x2c1b 12728#define mmDC_COMBOPHYPLLREGS3_OBSERVE1_BASE_IDX 2 12729#define mmDC_COMBOPHYPLLREGS3_DFT_OUT 0x2c1c 12730#define mmDC_COMBOPHYPLLREGS3_DFT_OUT_BASE_IDX 2 12731#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1 0x2c4e 12732#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL1_BASE_IDX 2 12733#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL 0x2c4f 12734#define mmDC_COMBOPHYPLLREGS3_PLL_WRAP_CNTRL_BASE_IDX 2 12735 12736 12737// addressBlock: dce_dc_dcio_dcio_zcal_dispdec 12738// base address: 0x0 12739#define mmZCAL_MACRO_CNTL_RESERVED0 0x2fe8 12740#define mmZCAL_MACRO_CNTL_RESERVED0_BASE_IDX 2 12741#define mmZCAL_MACRO_CNTL_RESERVED1 0x2fe9 12742#define mmZCAL_MACRO_CNTL_RESERVED1_BASE_IDX 2 12743#define mmZCAL_MACRO_CNTL_RESERVED2 0x2fea 12744#define mmZCAL_MACRO_CNTL_RESERVED2_BASE_IDX 2 12745#define mmZCAL_MACRO_CNTL_RESERVED3 0x2feb 12746#define mmZCAL_MACRO_CNTL_RESERVED3_BASE_IDX 2 12747#define mmZCAL_MACRO_CNTL_RESERVED4 0x2fec 12748#define mmZCAL_MACRO_CNTL_RESERVED4_BASE_IDX 2 12749 12750 12751// addressBlock: dce_dc_zcal_dc_zcalregs_dispdec 12752// base address: 0x0 12753#define mmCOMP_EN_CTL 0x2fe8 12754#define mmCOMP_EN_CTL_BASE_IDX 2 12755#define mmCOMP_EN_DFX 0x2fe9 12756#define mmCOMP_EN_DFX_BASE_IDX 2 12757#define mmZCAL_FUSES 0x2fea 12758#define mmZCAL_FUSES_BASE_IDX 2 12759 12760 12761// addressBlock: vga_vgaseqind 12762// base address: 0x0 12763#define ixSEQ00 0x0000 12764#define ixSEQ01 0x0001 12765#define ixSEQ02 0x0002 12766#define ixSEQ03 0x0003 12767#define ixSEQ04 0x0004 12768 12769 12770// addressBlock: vga_vgacrtind 12771// base address: 0x0 12772#define ixCRT00 0x0000 12773#define ixCRT01 0x0001 12774#define ixCRT02 0x0002 12775#define ixCRT03 0x0003 12776#define ixCRT04 0x0004 12777#define ixCRT05 0x0005 12778#define ixCRT06 0x0006 12779#define ixCRT07 0x0007 12780#define ixCRT08 0x0008 12781#define ixCRT09 0x0009 12782#define ixCRT0A 0x000a 12783#define ixCRT0B 0x000b 12784#define ixCRT0C 0x000c 12785#define ixCRT0D 0x000d 12786#define ixCRT0E 0x000e 12787#define ixCRT0F 0x000f 12788#define ixCRT10 0x0010 12789#define ixCRT11 0x0011 12790#define ixCRT12 0x0012 12791#define ixCRT13 0x0013 12792#define ixCRT14 0x0014 12793#define ixCRT15 0x0015 12794#define ixCRT16 0x0016 12795#define ixCRT17 0x0017 12796#define ixCRT18 0x0018 12797#define ixCRT1E 0x001e 12798#define ixCRT1F 0x001f 12799#define ixCRT22 0x0022 12800 12801 12802// addressBlock: vga_vgagrphind 12803// base address: 0x0 12804#define ixGRA00 0x0000 12805#define ixGRA01 0x0001 12806#define ixGRA02 0x0002 12807#define ixGRA03 0x0003 12808#define ixGRA04 0x0004 12809#define ixGRA05 0x0005 12810#define ixGRA06 0x0006 12811#define ixGRA07 0x0007 12812#define ixGRA08 0x0008 12813 12814 12815// addressBlock: vga_vgaattrind 12816// base address: 0x0 12817#define ixATTR00 0x0000 12818#define ixATTR01 0x0001 12819#define ixATTR02 0x0002 12820#define ixATTR03 0x0003 12821#define ixATTR04 0x0004 12822#define ixATTR05 0x0005 12823#define ixATTR06 0x0006 12824#define ixATTR07 0x0007 12825#define ixATTR08 0x0008 12826#define ixATTR09 0x0009 12827#define ixATTR0A 0x000a 12828#define ixATTR0B 0x000b 12829#define ixATTR0C 0x000c 12830#define ixATTR0D 0x000d 12831#define ixATTR0E 0x000e 12832#define ixATTR0F 0x000f 12833#define ixATTR10 0x0010 12834#define ixATTR11 0x0011 12835#define ixATTR12 0x0012 12836#define ixATTR13 0x0013 12837#define ixATTR14 0x0014 12838 12839 12840// base address: 0x0 12841 12842 12843// base address: 0x0 12844 12845 12846// base address: 0x0 12847 12848 12849// base address: 0x0 12850 12851 12852// base address: 0x0 12853 12854 12855// base address: 0x0 12856 12857 12858// base address: 0x0 12859 12860 12861// base address: 0x0 12862 12863 12864// base address: 0x0 12865 12866 12867// base address: 0x0 12868 12869 12870// base address: 0x0 12871 12872 12873// base address: 0x0 12874 12875 12876// base address: 0x0 12877 12878 12879// base address: 0x0 12880 12881 12882// base address: 0x0 12883 12884 12885// base address: 0x0 12886 12887 12888// base address: 0x0 12889 12890 12891// base address: 0x0 12892 12893 12894// base address: 0x0 12895 12896 12897// base address: 0x0 12898 12899 12900// base address: 0x0 12901 12902 12903// base address: 0x0 12904 12905 12906// base address: 0x0 12907 12908 12909// base address: 0x0 12910 12911 12912// base address: 0x0 12913 12914 12915// base address: 0x0 12916 12917 12918// base address: 0x0 12919 12920 12921// base address: 0x0 12922 12923 12924// base address: 0x0 12925 12926 12927// base address: 0x0 12928 12929 12930// base address: 0x0 12931 12932 12933// base address: 0x0 12934 12935 12936// base address: 0x0 12937 12938 12939// base address: 0x0 12940 12941 12942// base address: 0x0 12943 12944 12945// addressBlock: azendpoint_f2codecind 12946// base address: 0x0 12947#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x2200 12948#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x2706 12949#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x270d 12950#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_2 0x270e 12951#define ixAZALIA_F2_CODEC_CONVERTER_STRIPE_CONTROL 0x2724 12952#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER_3 0x273e 12953#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x2770 12954#define ixAZALIA_F2_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x2771 12955#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x2f09 12956#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x2f0a 12957#define ixAZALIA_F2_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x2f0b 12958#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONNECTION_LIST_ENTRY 0x3702 12959#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x3707 12960#define ixAZALIA_F2_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x3708 12961#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x3709 12962#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x371c 12963#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x371d 12964#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x371e 12965#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x371f 12966#define ixAZALIA_F2_CODEC_PIN_CONTROL_RESPONSE_SPEAKER_ALLOCATION 0x3770 12967#define ixAZALIA_F2_CODEC_PIN_CONTROL_CHANNEL_ALLOCATION 0x3771 12968#define ixAZALIA_F2_CODEC_PIN_CONTROL_DOWN_MIX_INFO 0x3772 12969#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR 0x3776 12970#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR_DATA 0x3776 12971#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL01_ENABLE 0x3777 12972#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL23_ENABLE 0x3778 12973#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL45_ENABLE 0x3779 12974#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL67_ENABLE 0x377a 12975#define ixAZALIA_F2_CODEC_PIN_CONTROL_LIPSYNC 0x377b 12976#define ixAZALIA_F2_CODEC_PIN_CONTROL_HBR 0x377c 12977#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_INDEX 0x3780 12978#define ixAZALIA_F2_CODEC_PIN_CONTROL_AUDIO_SINK_INFO_DATA 0x3781 12979#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x3785 12980#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x3786 12981#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x3787 12982#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x3788 12983#define ixAZALIA_F2_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x3789 12984#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x378a 12985#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x378b 12986#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x378c 12987#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x378d 12988#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x378e 12989#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x378f 12990#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x3790 12991#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x3791 12992#define ixAZALIA_F2_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x3792 12993#define ixAZALIA_F2_CODEC_PIN_ASSOCIATION_INFO 0x3793 12994#define ixAZALIA_F2_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x3797 12995#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x3798 12996#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB 0x3799 12997#define ixAZALIA_F2_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x379a 12998#define ixAZALIA_F2_CODEC_PIN_CONTROL_CODING_TYPE 0x379b 12999#define ixAZALIA_F2_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x379c 13000#define ixAZALIA_F2_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x379d
13001#define ixAZALIA_F2_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x379e 13002#define ixAZALIA_F2_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x3f09 13003#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CAPABILITIES 0x3f0c 13004#define ixAZALIA_F2_CODEC_PIN_PARAMETER_CONNECTION_LIST_LENGTH 0x3f0e 13005 13006 13007// addressBlock: azendpoint_descriptorind 13008// base address: 0x0 13009#define ixAUDIO_DESCRIPTOR0 0x0001 13010#define ixAUDIO_DESCRIPTOR1 0x0002 13011#define ixAUDIO_DESCRIPTOR2 0x0003 13012#define ixAUDIO_DESCRIPTOR3 0x0004 13013#define ixAUDIO_DESCRIPTOR4 0x0005 13014#define ixAUDIO_DESCRIPTOR5 0x0006 13015#define ixAUDIO_DESCRIPTOR6 0x0007 13016#define ixAUDIO_DESCRIPTOR7 0x0008 13017#define ixAUDIO_DESCRIPTOR8 0x0009 13018#define ixAUDIO_DESCRIPTOR9 0x000a 13019#define ixAUDIO_DESCRIPTOR10 0x000b 13020#define ixAUDIO_DESCRIPTOR11 0x000c 13021#define ixAUDIO_DESCRIPTOR12 0x000d 13022#define ixAUDIO_DESCRIPTOR13 0x000e 13023 13024 13025// addressBlock: azendpoint_sinkinfoind 13026// base address: 0x0 13027#define ixAZALIA_F2_CODEC_PIN_CONTROL_MANUFACTURER_ID 0x0000 13028#define ixAZALIA_F2_CODEC_PIN_CONTROL_PRODUCT_ID 0x0001 13029#define ixAZALIA_F2_CODEC_PIN_CONTROL_SINK_DESCRIPTION_LEN 0x0002 13030#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID0 0x0003 13031#define ixAZALIA_F2_CODEC_PIN_CONTROL_PORTID1 0x0004 13032#define ixSINK_DESCRIPTION0 0x0005 13033#define ixSINK_DESCRIPTION1 0x0006 13034#define ixSINK_DESCRIPTION2 0x0007 13035#define ixSINK_DESCRIPTION3 0x0008 13036#define ixSINK_DESCRIPTION4 0x0009 13037#define ixSINK_DESCRIPTION5 0x000a 13038#define ixSINK_DESCRIPTION6 0x000b 13039#define ixSINK_DESCRIPTION7 0x000c 13040#define ixSINK_DESCRIPTION8 0x000d 13041#define ixSINK_DESCRIPTION9 0x000e 13042#define ixSINK_DESCRIPTION10 0x000f 13043#define ixSINK_DESCRIPTION11 0x0010 13044#define ixSINK_DESCRIPTION12 0x0011 13045#define ixSINK_DESCRIPTION13 0x0012 13046#define ixSINK_DESCRIPTION14 0x0013 13047#define ixSINK_DESCRIPTION15 0x0014 13048#define ixSINK_DESCRIPTION16 0x0015 13049#define ixSINK_DESCRIPTION17 0x0016 13050 13051 13052// addressBlock: azf0controller_azinputcrc0resultind 13053// base address: 0x0 13054#define ixAZALIA_INPUT_CRC0_CHANNEL0 0x0000 13055#define ixAZALIA_INPUT_CRC0_CHANNEL1 0x0001 13056#define ixAZALIA_INPUT_CRC0_CHANNEL2 0x0002 13057#define ixAZALIA_INPUT_CRC0_CHANNEL3 0x0003 13058#define ixAZALIA_INPUT_CRC0_CHANNEL4 0x0004 13059#define ixAZALIA_INPUT_CRC0_CHANNEL5 0x0005 13060#define ixAZALIA_INPUT_CRC0_CHANNEL6 0x0006 13061#define ixAZALIA_INPUT_CRC0_CHANNEL7 0x0007 13062 13063 13064// addressBlock: azf0controller_azinputcrc1resultind 13065// base address: 0x0 13066#define ixAZALIA_INPUT_CRC1_CHANNEL0 0x0000 13067#define ixAZALIA_INPUT_CRC1_CHANNEL1 0x0001 13068#define ixAZALIA_INPUT_CRC1_CHANNEL2 0x0002 13069#define ixAZALIA_INPUT_CRC1_CHANNEL3 0x0003 13070#define ixAZALIA_INPUT_CRC1_CHANNEL4 0x0004 13071#define ixAZALIA_INPUT_CRC1_CHANNEL5 0x0005 13072#define ixAZALIA_INPUT_CRC1_CHANNEL6 0x0006 13073#define ixAZALIA_INPUT_CRC1_CHANNEL7 0x0007 13074 13075 13076// addressBlock: azf0controller_azcrc0resultind 13077// base address: 0x0 13078#define ixAZALIA_CRC0_CHANNEL0 0x0000 13079#define ixAZALIA_CRC0_CHANNEL1 0x0001 13080#define ixAZALIA_CRC0_CHANNEL2 0x0002 13081#define ixAZALIA_CRC0_CHANNEL3 0x0003 13082#define ixAZALIA_CRC0_CHANNEL4 0x0004 13083#define ixAZALIA_CRC0_CHANNEL5 0x0005 13084#define ixAZALIA_CRC0_CHANNEL6 0x0006 13085#define ixAZALIA_CRC0_CHANNEL7 0x0007 13086 13087 13088// addressBlock: azf0controller_azcrc1resultind 13089// base address: 0x0 13090#define ixAZALIA_CRC1_CHANNEL0 0x0000 13091#define ixAZALIA_CRC1_CHANNEL1 0x0001 13092#define ixAZALIA_CRC1_CHANNEL2 0x0002 13093#define ixAZALIA_CRC1_CHANNEL3 0x0003 13094#define ixAZALIA_CRC1_CHANNEL4 0x0004 13095#define ixAZALIA_CRC1_CHANNEL5 0x0005 13096#define ixAZALIA_CRC1_CHANNEL6 0x0006 13097#define ixAZALIA_CRC1_CHANNEL7 0x0007 13098 13099 13100// addressBlock: azinputendpoint_f2codecind 13101// base address: 0x0 13102#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x6200 13103#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x6706 13104#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x670d 13105#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x6f09 13106#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x6f0a 13107#define ixAZALIA_F2_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x6f0b 13108#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x7707 13109#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x7708 13110#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_PIN_SENSE 0x7709 13111#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x771c 13112#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_2 0x771d 13113#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_3 0x771e 13114#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT_4 0x771f 13115#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x7771 13116#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL0_ENABLE 0x7777 13117#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL2_ENABLE 0x7778 13118#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL4_ENABLE 0x7779 13119#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL6_ENABLE 0x777a 13120#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_HBR 0x777c 13121#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL1_ENABLE 0x7785 13122#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL3_ENABLE 0x7786 13123#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL5_ENABLE 0x7787 13124#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL7_ENABLE 0x7788 13125#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x7798 13126#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB 0x7799 13127#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x779a 13128#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x779b 13129#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x779c 13130#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_L 0x779d 13131#define ixAZALIA_F2_CODEC_INPUT_PIN_CONTROL_CHANNEL_STATUS_H 0x779e 13132#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x7f09 13133#define ixAZALIA_F2_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x7f0c 13134 13135 13136// addressBlock: azroot_f2codecind 13137// base address: 0x0 13138#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_VENDOR_AND_DEVICE_ID 0x0f00 13139#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_REVISION_ID 0x0f02 13140#define ixAZALIA_F2_CODEC_ROOT_PARAMETER_SUBORDINATE_NODE_COUNT 0x0f04 13141#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_POWER_STATE 0x1705 13142#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID 0x1720 13143#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_2 0x1721 13144#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_3 0x1722 13145#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESPONSE_SUBSYSTEM_ID_4 0x1723 13146#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_CONVERTER_SYNCHRONIZATION 0x1770 13147#define ixAZALIA_F2_CODEC_FUNCTION_CONTROL_RESET 0x17ff 13148#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUBORDINATE_NODE_COUNT 0x1f04 13149#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_GROUP_TYPE 0x1f05 13150#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_SUPPORTED_SIZE_RATES 0x1f0a 13151#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_STREAM_FORMATS 0x1f0b 13152#define ixAZALIA_F2_CODEC_FUNCTION_PARAMETER_POWER_STATES 0x1f0f 13153 13154 13155// addressBlock: azf0stream0_streamind 13156// base address: 0x0 13157#define ixAZF0STREAM0_AZALIA_FIFO_SIZE_CONTROL 0x0000 13158#define ixAZF0STREAM0_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13159#define ixAZF0STREAM0_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13160#define ixAZF0STREAM0_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13161#define ixAZF0STREAM0_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13162 13163 13164// addressBlock: azf0stream1_streamind 13165// base address: 0x0 13166#define ixAZF0STREAM1_AZALIA_FIFO_SIZE_CONTROL 0x0000 13167#define ixAZF0STREAM1_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13168#define ixAZF0STREAM1_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13169#define ixAZF0STREAM1_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13170#define ixAZF0STREAM1_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13171 13172 13173// addressBlock: azf0stream2_streamind 13174// base address: 0x0 13175#define ixAZF0STREAM2_AZALIA_FIFO_SIZE_CONTROL 0x0000 13176#define ixAZF0STREAM2_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13177#define ixAZF0STREAM2_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13178#define ixAZF0STREAM2_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13179#define ixAZF0STREAM2_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13180 13181 13182// addressBlock: azf0stream3_streamind 13183// base address: 0x0 13184#define ixAZF0STREAM3_AZALIA_FIFO_SIZE_CONTROL 0x0000 13185#define ixAZF0STREAM3_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13186#define ixAZF0STREAM3_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13187#define ixAZF0STREAM3_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13188#define ixAZF0STREAM3_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13189 13190 13191// addressBlock: azf0stream4_streamind 13192// base address: 0x0 13193#define ixAZF0STREAM4_AZALIA_FIFO_SIZE_CONTROL 0x0000 13194#define ixAZF0STREAM4_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13195#define ixAZF0STREAM4_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13196#define ixAZF0STREAM4_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13197#define ixAZF0STREAM4_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13198 13199 13200// addressBlock: azf0stream5_streamind 13201// base address: 0x0 13202#define ixAZF0STREAM5_AZALIA_FIFO_SIZE_CONTROL 0x0000 13203#define ixAZF0STREAM5_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13204#define ixAZF0STREAM5_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13205#define ixAZF0STREAM5_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13206#define ixAZF0STREAM5_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13207 13208 13209// addressBlock: azf0stream6_streamind 13210// base address: 0x0 13211#define ixAZF0STREAM6_AZALIA_FIFO_SIZE_CONTROL 0x0000 13212#define ixAZF0STREAM6_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13213#define ixAZF0STREAM6_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13214#define ixAZF0STREAM6_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13215#define ixAZF0STREAM6_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13216 13217 13218// addressBlock: azf0stream7_streamind 13219// base address: 0x0 13220#define ixAZF0STREAM7_AZALIA_FIFO_SIZE_CONTROL 0x0000 13221#define ixAZF0STREAM7_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13222#define ixAZF0STREAM7_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13223#define ixAZF0STREAM7_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13224#define ixAZF0STREAM7_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13225 13226 13227// addressBlock: azf0stream8_streamind 13228// base address: 0x0 13229#define ixAZF0STREAM8_AZALIA_FIFO_SIZE_CONTROL 0x0000 13230#define ixAZF0STREAM8_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13231#define ixAZF0STREAM8_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13232#define ixAZF0STREAM8_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13233#define ixAZF0STREAM8_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13234 13235 13236// addressBlock: azf0stream9_streamind 13237// base address: 0x0 13238#define ixAZF0STREAM9_AZALIA_FIFO_SIZE_CONTROL 0x0000 13239#define ixAZF0STREAM9_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13240#define ixAZF0STREAM9_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13241#define ixAZF0STREAM9_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13242#define ixAZF0STREAM9_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13243 13244 13245// addressBlock: azf0stream10_streamind 13246// base address: 0x0 13247#define ixAZF0STREAM10_AZALIA_FIFO_SIZE_CONTROL 0x0000 13248#define ixAZF0STREAM10_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13249#define ixAZF0STREAM10_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13250#define ixAZF0STREAM10_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13251#define ixAZF0STREAM10_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13252 13253 13254// addressBlock: azf0stream11_streamind 13255// base address: 0x0 13256#define ixAZF0STREAM11_AZALIA_FIFO_SIZE_CONTROL 0x0000 13257#define ixAZF0STREAM11_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13258#define ixAZF0STREAM11_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13259#define ixAZF0STREAM11_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13260#define ixAZF0STREAM11_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13261 13262 13263// addressBlock: azf0stream12_streamind 13264// base address: 0x0 13265#define ixAZF0STREAM12_AZALIA_FIFO_SIZE_CONTROL 0x0000 13266#define ixAZF0STREAM12_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13267#define ixAZF0STREAM12_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13268#define ixAZF0STREAM12_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13269#define ixAZF0STREAM12_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13270 13271 13272// addressBlock: azf0stream13_streamind 13273// base address: 0x0 13274#define ixAZF0STREAM13_AZALIA_FIFO_SIZE_CONTROL 0x0000 13275#define ixAZF0STREAM13_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13276#define ixAZF0STREAM13_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13277#define ixAZF0STREAM13_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13278#define ixAZF0STREAM13_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13279 13280 13281// addressBlock: azf0stream14_streamind 13282// base address: 0x0 13283#define ixAZF0STREAM14_AZALIA_FIFO_SIZE_CONTROL 0x0000 13284#define ixAZF0STREAM14_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13285#define ixAZF0STREAM14_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13286#define ixAZF0STREAM14_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13287#define ixAZF0STREAM14_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13288 13289 13290// addressBlock: azf0stream15_streamind 13291// base address: 0x0 13292#define ixAZF0STREAM15_AZALIA_FIFO_SIZE_CONTROL 0x0000 13293#define ixAZF0STREAM15_AZALIA_LATENCY_COUNTER_CONTROL 0x0001 13294#define ixAZF0STREAM15_AZALIA_WORSTCASE_LATENCY_COUNT 0x0002 13295#define ixAZF0STREAM15_AZALIA_CUMULATIVE_LATENCY_COUNT 0x0003 13296#define ixAZF0STREAM15_AZALIA_CUMULATIVE_REQUEST_COUNT 0x0004 13297 13298 13299// addressBlock: azf0endpoint0_endpointind 13300// base address: 0x0 13301#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13302#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13303#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13304#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13305#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13306#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13307#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13308#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13309#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13310#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13311#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13312#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13313#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13314#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13315#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13316#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13317#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13318#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13319#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13320#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13321#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13322#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13323#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13324#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13325#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13326#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13327#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13328#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13329#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13330#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13331#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13332#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13333#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13334#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13335#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13336#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13337#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13338#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13339#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13340#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13341#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13342#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13343#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13344#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13345#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13346#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13347#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13348#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13349#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13350#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13351#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13352#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13353#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13354#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13355#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13356#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13357#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13358#define ixAZF0ENDPOINT0_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13359#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13360#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13361#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13362#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13363#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13364#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13365#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13366#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13367#define ixAZF0ENDPOINT0_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13368#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13369#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13370#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13371#define ixAZF0ENDPOINT0_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13372 13373 13374// addressBlock: azf0endpoint1_endpointind 13375// base address: 0x0 13376#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13377#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13378#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13379#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13380#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13381#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13382#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13383#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13384#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13385#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13386#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13387#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13388#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13389#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13390#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13391#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13392#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13393#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13394#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13395#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13396#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13397#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13398#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13399#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13400#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13401#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13402#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13403#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13404#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13405#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13406#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13407#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13408#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13409#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13410#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13411#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13412#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13413#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13414#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13415#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13416#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13417#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13418#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13419#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13420#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13421#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13422#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13423#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13424#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13425#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13426#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13427#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13428#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13429#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13430#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13431#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13432#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13433#define ixAZF0ENDPOINT1_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13434#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13435#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13436#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13437#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13438#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13439#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13440#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13441#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13442#define ixAZF0ENDPOINT1_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13443#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13444#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13445#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13446#define ixAZF0ENDPOINT1_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13447 13448 13449// addressBlock: azf0endpoint2_endpointind 13450// base address: 0x0 13451#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13452#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13453#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13454#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13455#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13456#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13457#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13458#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13459#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13460#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13461#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13462#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13463#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13464#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13465#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13466#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13467#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13468#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13469#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13470#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13471#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13472#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13473#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13474#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13475#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13476#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13477#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13478#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13479#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13480#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13481#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13482#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13483#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13484#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13485#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13486#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13487#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13488#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13489#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13490#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13491#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13492#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13493#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13494#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13495#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13496#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13497#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13498#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13499#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13500#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13501#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13502#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13503#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13504#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13505#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13506#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13507#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13508#define ixAZF0ENDPOINT2_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13509#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13510#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13511#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13512#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13513#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13514#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13515#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13516#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13517#define ixAZF0ENDPOINT2_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13518#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13519#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13520#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13521#define ixAZF0ENDPOINT2_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13522 13523 13524// addressBlock: azf0endpoint3_endpointind 13525// base address: 0x0 13526#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13527#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13528#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13529#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13530#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13531#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13532#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13533#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13534#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13535#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13536#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13537#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13538#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13539#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13540#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13541#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13542#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13543#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13544#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13545#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13546#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13547#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13548#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13549#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13550#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13551#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13552#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13553#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13554#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13555#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13556#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13557#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13558#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13559#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13560#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13561#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13562#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13563#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13564#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13565#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13566#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13567#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13568#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13569#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13570#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13571#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13572#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13573#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13574#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13575#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13576#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13577#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13578#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13579#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13580#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13581#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13582#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13583#define ixAZF0ENDPOINT3_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13584#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13585#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13586#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13587#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13588#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13589#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13590#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13591#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13592#define ixAZF0ENDPOINT3_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13593#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13594#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13595#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13596#define ixAZF0ENDPOINT3_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13597 13598 13599// addressBlock: azf0endpoint4_endpointind 13600// base address: 0x0 13601#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13602#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13603#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13604#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13605#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13606#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13607#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13608#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13609#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13610#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13611#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13612#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13613#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13614#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13615#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13616#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13617#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13618#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13619#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13620#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13621#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13622#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13623#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13624#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13625#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13626#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13627#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13628#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13629#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13630#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13631#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13632#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13633#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13634#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13635#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13636#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13637#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13638#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13639#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13640#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13641#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13642#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13643#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13644#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13645#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13646#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13647#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13648#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13649#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13650#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13651#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13652#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13653#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13654#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13655#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13656#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13657#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13658#define ixAZF0ENDPOINT4_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13659#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13660#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13661#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13662#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13663#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13664#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13665#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13666#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13667#define ixAZF0ENDPOINT4_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13668#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13669#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13670#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13671#define ixAZF0ENDPOINT4_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13672 13673 13674// addressBlock: azf0endpoint5_endpointind 13675// base address: 0x0 13676#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13677#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13678#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13679#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13680#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13681#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13682#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13683#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13684#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13685#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13686#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13687#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13688#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13689#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13690#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13691#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13692#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13693#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13694#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13695#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13696#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13697#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13698#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13699#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13700#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13701#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13702#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13703#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13704#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13705#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13706#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13707#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13708#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13709#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13710#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13711#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13712#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13713#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13714#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13715#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13716#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13717#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13718#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13719#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13720#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13721#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13722#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13723#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13724#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13725#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13726#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13727#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13728#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13729#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13730#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13731#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13732#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13733#define ixAZF0ENDPOINT5_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13734#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13735#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13736#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13737#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13738#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13739#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13740#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13741#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13742#define ixAZF0ENDPOINT5_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13743#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13744#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13745#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13746#define ixAZF0ENDPOINT5_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13747 13748 13749// addressBlock: azf0endpoint6_endpointind 13750// base address: 0x0 13751#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13752#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13753#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13754#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13755#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13756#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13757#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13758#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13759#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13760#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13761#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13762#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13763#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13764#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13765#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13766#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13767#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13768#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13769#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13770#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13771#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13772#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13773#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13774#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13775#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13776#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13777#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13778#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13779#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13780#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13781#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13782#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13783#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13784#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13785#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13786#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13787#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13788#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13789#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13790#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13791#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13792#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13793#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13794#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13795#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13796#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13797#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13798#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13799#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13800#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13801#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13802#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13803#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13804#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13805#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13806#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13807#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13808#define ixAZF0ENDPOINT6_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13809#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13810#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13811#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13812#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13813#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13814#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13815#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13816#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13817#define ixAZF0ENDPOINT6_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13818#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13819#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13820#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13821#define ixAZF0ENDPOINT6_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13822 13823 13824// addressBlock: azf0endpoint7_endpointind 13825// base address: 0x0 13826#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13827#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13828#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13829#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13830#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13831#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13832#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_STRIPE_CONTROL 0x0007 13833#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_RAMP_RATE 0x0008 13834#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_CONTROL_GTC_EMBEDDING 0x0009 13835#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA 0x000c 13836#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MIN 0x000d 13837#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_CONVERTER_GTC_COUNTER_DELTA_MAX 0x000e 13838#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13839#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_PARAMETER_CAPABILITIES 0x0021 13840#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13841#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_PIN_SENSE 0x0023 13842#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIDGET_CONTROL 0x0024 13843#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x0025 13844#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x0028 13845#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x0029 13846#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x002a 13847#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x002b 13848#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x002c 13849#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x002d 13850#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x002e 13851#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x002f 13852#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x0030 13853#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x0031 13854#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x0032 13855#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x0033 13856#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x0034 13857#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x0035 13858#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13859#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x0037 13860#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x0038 13861#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x003a 13862#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x003b 13863#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x003c 13864#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x003d 13865#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x003e 13866#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x003f 13867#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x0040 13868#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x0041 13869#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x0042 13870#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13871#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13872#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13873#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0057 13874#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_MULTICHANNEL_MODE 0x0058 13875#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_0 0x0059 13876#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_1 0x005a 13877#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_2 0x005b 13878#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_3 0x005c 13879#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_4 0x005d 13880#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_5 0x005e 13881#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_6 0x005f 13882#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_7 0x0060 13883#define ixAZF0ENDPOINT7_AZALIA_F0_PIN_CONTROL_CODEC_CS_OVERRIDE_8 0x0061 13884#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_ASSOCIATION_INFO 0x0062 13885#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_DIGITAL_OUTPUT_STATUS 0x0063 13886#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13887#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB 0x0065 13888#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13889#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_CODING_TYPE 0x0067 13890#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_FORMAT_CHANGED 0x0068 13891#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_WIRELESS_DISPLAY_IDENTIFICATION 0x0069 13892#define ixAZF0ENDPOINT7_AZALIA_F0_CODEC_PIN_CONTROL_REMOTE_KEEPALIVE 0x006a 13893#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLE_STATUS 0x006b 13894#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_ENABLED_INT_STATUS 0x006c 13895#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_DISABLED_INT_STATUS 0x006d 13896#define ixAZF0ENDPOINT7_AZALIA_F0_AUDIO_FORMAT_CHANGED_INT_STATUS 0x006e 13897 13898 13899// addressBlock: azf0inputendpoint0_inputendpointind 13900// base address: 0x0 13901#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13902#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13903#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13904#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13905#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13906#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13907#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13908#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 13909#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13910#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 13911#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 13912#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13913#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 13914#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 13915#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 13916#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13917#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13918#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13919#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13920#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 13921#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13922#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 13923#define ixAZF0INPUTENDPOINT0_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 13924 13925 13926// addressBlock: azf0inputendpoint1_inputendpointind 13927// base address: 0x0 13928#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13929#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13930#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13931#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13932#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13933#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13934#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13935#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 13936#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13937#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 13938#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 13939#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13940#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 13941#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 13942#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 13943#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13944#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13945#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13946#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13947#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 13948#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13949#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 13950#define ixAZF0INPUTENDPOINT1_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 13951 13952 13953// addressBlock: azf0inputendpoint2_inputendpointind 13954// base address: 0x0 13955#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13956#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13957#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13958#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13959#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13960#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13961#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13962#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 13963#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13964#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 13965#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 13966#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13967#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 13968#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 13969#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 13970#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13971#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13972#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 13973#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 13974#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 13975#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 13976#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 13977#define ixAZF0INPUTENDPOINT2_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 13978 13979 13980// addressBlock: azf0inputendpoint3_inputendpointind 13981// base address: 0x0 13982#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 13983#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 13984#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 13985#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 13986#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 13987#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 13988#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 13989#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 13990#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 13991#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 13992#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 13993#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 13994#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 13995#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 13996#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 13997#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 13998#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 13999#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14000#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064
14001#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14002#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14003#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14004#define ixAZF0INPUTENDPOINT3_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14005 14006 14007// addressBlock: azf0inputendpoint4_inputendpointind 14008// base address: 0x0 14009#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14010#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14011#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14012#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14013#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14014#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14015#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14016#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14017#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14018#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14019#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14020#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14021#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14022#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14023#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14024#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14025#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14026#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14027#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14028#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14029#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14030#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14031#define ixAZF0INPUTENDPOINT4_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14032 14033 14034// addressBlock: azf0inputendpoint5_inputendpointind 14035// base address: 0x0 14036#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14037#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14038#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14039#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14040#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14041#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14042#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14043#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14044#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14045#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14046#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14047#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14048#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14049#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14050#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14051#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14052#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14053#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14054#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14055#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14056#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14057#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14058#define ixAZF0INPUTENDPOINT5_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14059 14060 14061// addressBlock: azf0inputendpoint6_inputendpointind 14062// base address: 0x0 14063#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14064#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14065#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14066#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14067#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14068#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14069#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14070#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14071#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14072#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14073#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14074#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14075#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14076#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14077#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14078#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14079#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14080#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14081#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14082#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14083#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14084#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14085#define ixAZF0INPUTENDPOINT6_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14086 14087 14088// addressBlock: azf0inputendpoint7_inputendpointind 14089// base address: 0x0 14090#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0001 14091#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CONVERTER_FORMAT 0x0002 14092#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_CHANNEL_STREAM_ID 0x0003 14093#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_CONTROL_DIGITAL_CONVERTER 0x0004 14094#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_STREAM_FORMATS 0x0005 14095#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_CONVERTER_PARAMETER_SUPPORTED_SIZE_RATES 0x0006 14096#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_AUDIO_WIDGET_CAPABILITIES 0x0020 14097#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_PARAMETER_CAPABILITIES 0x0021 14098#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE 0x0022 14099#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_INPUT_PIN_SENSE 0x0023 14100#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_WIDGET_CONTROL 0x0024 14101#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE 0x0036 14102#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_MULTICHANNEL_ENABLE2 0x0037 14103#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_HBR 0x0038 14104#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_CHANNEL_ALLOCATION 0x0053 14105#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_HOT_PLUG_CONTROL 0x0054 14106#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_UNSOLICITED_RESPONSE_FORCE 0x0055 14107#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x0056 14108#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_SNAPSHOT_CONTROL 0x0064 14109#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB 0x0065 14110#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_LPIB_TIMER_SNAPSHOT 0x0066 14111#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INPUT_STATUS_CONTROL 0x0067 14112#define ixAZF0INPUTENDPOINT7_AZALIA_F0_CODEC_INPUT_PIN_CONTROL_INFOFRAME 0x0068 14113 14114#endif 14115